Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with an improved breakdown voltage, and a method for manufacturing the same.SOLUTION: A semiconductor device includes; an active region ACT extending in a first direction and having a first width in a second direction crossing the first direction; a first gate structure 100 having a second width in the first direction, extending in the second direction, and including a first side and a second side respectively on the opposite sides on the active region; a first metal contact MC1 and a second metal contact MC2 arranged separated from each of the first and second sides of the first gate structure in the first direction; a first trench being formed in the active region and extending between the first side of the first gate structure and the first metal contact in the second direction; and a second trench extending between the second side of the first gate structure and the second metal contact in the second direction. A breakdown voltage of the semiconductor device can be increased by increasing an electric distance between the first gate structure, the first metal contact, and the second metal contact.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] As semiconductor device design rules shrink, the distance between the source and drain regions of transistors also becomes narrower. The doping concentration in the channel and source / drain regions increases, causing phenomena such as the short channel effect (SCE), hot carrier effect (HCE), and gate induced drain leakage (GIDL), which degrade the electrical characteristics of transistors.

[0003] Additionally, issues with low breakdown voltage (BV) in high-voltage transistors have arisen, creating a need to increase the electrical travel distance between the metal contact and the gate structure. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having improved breakdown voltage (BV) characteristics, more particularly, an increased breakdown voltage.

[0005] SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device having improved breakdown voltage (BV) characteristics, more particularly, an increased breakdown voltage.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the above technical objective, a semiconductor device according to some embodiments of the present invention includes an active region extending in a first direction and having a first width in a second direction intersecting the first direction; a first gate structure on the active region, the first gate structure having a second width in the first direction and extending in the second direction, the first gate structure having first and second sides opposite each other; first and second metal contacts disposed spaced apart in the first direction from the first and second sides of the first gate structure; a first trench formed in the active region, the first trench extending in the second direction between the first side of the first gate structure and the first metal contact; and a second trench extending in the second direction between the second side of the first gate structure and the second metal contact, the first trench being filled and having a starting point and a termination point spaced apart from the starting point along the second direction within the active region. The semiconductor device includes an insulating material forming a first active cut, the first active cut defining a first metal region within the active region in which a first metal contact is located, the first metal region being surrounded by a first virtual line extending from a starting point of the first active cut along a first direction, a second virtual line extending from an end point of the first active cut along the first direction, and the insulating material, wherein a first distance from the first metal contact to the first virtual line is smaller than a second distance from the first metal contact to the second virtual line, a length along the first direction of the region where the first gate structure and the active region overlap is longer than a length along which the first and second trenches extend in the first direction, and a length along the second direction of the region where the first gate structure and the active region overlap is longer than a length along which the first and second trenches extend in the second direction.

[0008] In order to achieve the above technical object, a semiconductor device according to some embodiments of the present invention includes an active region including a first region extending in a first direction and having a first width in a second direction intersecting the first direction, and a second region extending in the first direction and having a second width in the second direction, wherein the first region includes a first gate structure extending in the second direction on the active region and having a third width in the first direction, a first metal contact spaced apart in the first direction from the first gate structure, a first trench formed in the active region, and an insulating material filling the first trench to form a first active cut, wherein a first distance from the first metal contact to the first active cut and a second distance from the first metal contact to an end of the first region in the first direction are different from each other, and the second region includes a second gate structure extending in the second direction on the active region and having a fourth width in the first direction, and a second metal contact spaced apart in the first direction from the second gate structure.

[0009] To achieve the above technical objective, a semiconductor device according to some embodiments of the present invention includes an active area extending in a first direction and a second direction intersecting the first direction, a first gate structure disposed on the active area and extending in the second direction, a first active cut disposed on a first side of the first gate structure and extending from the first side of the active area in the second direction into the active area, a second active cut disposed on a second side of the first gate structure opposite the first side of the first gate structure and extending from the second side of the active area opposite the first side of the active area in the second direction into the active area, each of the first and second active cuts including a trench filled with an insulating material, and a first metal contact disposed spaced apart from the first active cut in the first direction, wherein a first distance from the first metal contact to the first active cut and a second distance from the first metal contact to an end of the active area opposite the first active cut are different from each other.

[0010] To achieve the above technical objective, a method for manufacturing a semiconductor device according to some embodiments of the present invention includes forming an active region extending in a first direction and having a first width in a second direction intersecting the first direction, forming a gate structure on the active region, forming a trench in the active region spaced apart from the gate structure in the first direction and extending in the second direction, filling the trench with an insulating material to form an active cut that defines a metal region, and disposing a metal contact in the metal region spaced apart from the active cut in the first direction, wherein the metal contact is asymmetrically disposed in the metal region.

[0011] Specific details of other embodiments are included in the detailed description and drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. [Figure 2] 2 is a layout diagram illustrating an example of the semiconductor device of FIG. 1 according to some embodiments. [Figure 3] 3 is an exemplary cross-sectional view taken along line AA' in FIG. 2. FIG. [Figure 4] 3 is an exemplary cross-sectional view taken along line BB' in FIG. 2. FIG. [Figure 5] 3 is an exemplary cross-sectional view taken along the line CC' in FIG. 2. FIG. [Figure 6] 3A-3C are exemplary diagrams illustrating intermediate stages in a method for manufacturing the semiconductor device of FIG. 2 according to some embodiments. [Figure 7] 3A-3C are exemplary diagrams illustrating intermediate stages in a method for manufacturing the semiconductor device of FIG. 2 according to some embodiments. [Figure 8] 3A-3C are exemplary diagrams illustrating intermediate stages in a method for manufacturing the semiconductor device of FIG. 2 according to some embodiments. [Figure 9] 3A-3C are exemplary diagrams illustrating intermediate stages in a method for manufacturing the semiconductor device of FIG. 2 according to some embodiments. [Figure 10]3 is an exemplary layout diagram illustrating a semiconductor device different from the metal contacts of FIG. 2 according to some embodiments. [Figure 11] 3 is an exemplary layout diagram illustrating a semiconductor device different from the metal contacts of FIG. 2 according to some embodiments. [Figure 12] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 13] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 14] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 15] FIG. 10 is a circuit diagram illustrating another semiconductor device according to some embodiments. [Figure 16] 16 is a layout diagram illustrating an example of the semiconductor device of FIG. 15 according to some embodiments. [Figure 17] 17A-17C are exemplary layout diagrams illustrating semiconductor devices different from the metal contacts of FIG. 16 according to some embodiments. [Figure 18] 17A-17C are exemplary layout diagrams illustrating semiconductor devices different from the metal contacts of FIG. 16 according to some embodiments. [Figure 19] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 20] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 21] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 22] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 23] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 24] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 25]FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 26] FIG. 10 is a circuit diagram illustrating another semiconductor device according to some embodiments. [Figure 27] FIG. 27 is a layout diagram illustrating an example of the semiconductor device of FIG. 26 according to some embodiments. [Figure 28] 28 is an exemplary layout diagram illustrating a semiconductor device different from the metal contact of FIG. 27 according to some embodiments. [Figure 29] 28 is an exemplary layout diagram illustrating a semiconductor device different from the metal contact of FIG. 27 according to some embodiments. [Figure 30] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 31] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 32] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 33] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 34] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 35] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. [Figure 36] FIG. 10 is a layout diagram illustrating another semiconductor device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] Although the following drawings relating to semiconductor devices according to some embodiments illustrate FinFETs, the semiconductor devices according to some embodiments are not limited thereto. For example, semiconductor devices according to some embodiments may include gate-all-around transistors (GAA FETs), tunneling transistors, bipolar junction transistors, lateral double-diffused transistors (LDMOS), and the like, each including a nanowire-shaped or nanosheet-shaped channel region.

[0014] FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to some embodiments.

[0015] Referring to FIG. 1, a semiconductor device 1 according to some embodiments may include a first transistor TR1.

[0016] The source of the first transistor TR1 may be coupled to the ground voltage, the drain of the first transistor TR1 may be coupled to the power supply voltage Vdd, and the gate of the first transistor TR1 may be coupled to the gate voltage Vg.

[0017] The breakdown voltage of the first transistor TR1 using a high voltage may decrease as the transistor TR1 is miniaturized. Therefore, the breakdown voltage of the first transistor TR1 using a high voltage can be increased by increasing the electrical distance between the metal contact (e.g., the drain terminal of the first transistor TR1 or the source terminal of the first transistor TR1) and the gate.

[0018] A structure for increasing the electrical distance between a metal contact (e.g., the drain end of the first transistor TR1 or the source end of the first transistor TR1) and the gate of the first transistor TR1 in the semiconductor device 1 according to some embodiments is examined in more detail in FIG.

[0019] FIG. 2 is a layout diagram illustrating an example of the semiconductor device of FIG. 1 according to some embodiments.

[0020] 1 and 2, a structure for increasing the electrical distance between a metal contact (e.g., the drain end of the first transistor TR1 or the source end of the first transistor TR1) and the gate of the first transistor TR1 will be described using a layout diagram for the first transistor TR1 of the semiconductor device 1 of FIG. 1 according to some embodiments.

[0021] The first transistor TR1 may receive a power supply voltage Vdd through a first metal contact MC1, a ground voltage through a second metal contact MC2, and a gate voltage Vg through a third metal contact MC3 connected to the gate structure 100.

[0022] The first metal contact MC1, the second metal contact MC2, and the third metal contact MC3 may include, for example, a conductive material.

[0023] The first transistor TR1 is formed on an active area ACT extending in a first direction DR1 and having a first width W1 in a second direction DR2. The gate structure 100 of the first transistor TR1 may have a second width W2 on the active area ACT and extend in the second direction DR2.

[0024] In this case, the first transistor TR1 may be surrounded by a shallow trench isolation (STI) 120 for electrical isolation from other elements. The shallow trench isolation 120 may be formed by filling an insulating material in a trench formed around the first transistor TR1. The insulating material forming the shallow trench isolation 120 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0025] The shallow trench isolation 120 surrounding the first transistor TR1 is formed to extend into the active region ACT. For example, the shallow trench isolation 120 surrounding the first transistor TR1 can form a first active cut AC1 and / or a second active cut AC2 into the active region ACT. The following FIGS. 3 and 4 will explain the structure in which the shallow trench isolation 120 surrounding the first transistor TR1 extends into the active region ACT to form the first active cut AC1 and / or the second active cut AC2, using cross-sectional views taken along the A-A' and B-B' cut lines.

[0026] FIG. 3 is an exemplary cross-sectional view taken along line AA' in FIG.

[0027] 1 to 3, a first transistor TR1 in a semiconductor device 1 according to some embodiments may have a FinFET structure.

[0028] According to some embodiments, the first transistor TR1 may include a gate structure 100, source / drain regions 122, a silicide layer 124, a first interlayer insulating film 120, a second interlayer insulating film 220, and a first metal contact MC1. According to some embodiments, the first transistor TR1 is formed on a substrate Sub and an active region ACT on the substrate Sub. The structure of the first transistor TR1 according to some embodiments is not limited thereto, and the first interlayer insulating film 120 may be formed of a different material from the first active cut AC1, thereby separating them.

[0029] The substrate Sub can be a silicon substrate or SOI (silicon-on-insulator). Alternatively, the substrate Sub can include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0030] The active area ACT is defined along a first direction DR1. The active area ACT may be a region in which an n-type transistor is formed. The active area ACT may include, for example, a well region doped with p-type impurities. The active area ACT may protrude from the substrate Sub. The active area ACT may include an epitaxial layer grown from the substrate Sub.

[0031] According to some embodiments, an active cut AC is formed between the first metal contact MC1 of the first transistor TR1 and the gate structure 100 in the semiconductor device 1. The active cut AC can be formed by filling an insulating material 120 into a trench formed between the first metal contact MC1 of the first transistor TR1 and the gate structure 100. The active cut AC formed between the first metal contact MC1 and the gate structure 100 increases the electrical travel length between the first metal contact MC1 and the gate structure 100, which can increase the breakdown voltage of the semiconductor device 1 according to some embodiments, more specifically, the breakdown voltage of the first transistor TR1.

[0032] The gate structure 100 according to some embodiments may include a gate spacer 100_1, a gate insulating film 100_2, a gate electrode 100_3, and a capping pattern 100_4. The structure of the gate structure 100 is not limited to the illustrated embodiment.

[0033] The gate spacer 100_1 may extend in the third direction DR3 along both sidewalls of the gate insulating film 100_2. The gate insulating film 100_2 is disposed between the gate electrode 100_3 and the gate spacer 100_1 and below the capping pattern 100_4. The capping pattern 100_4 is disposed on the gate electrode 100_3 and the gate insulating film 100_2, respectively. The gate spacer 100_1, the gate insulating film 100_2, and the capping pattern 100_4 may include an insulating material.

[0034] The source / drain regions 122 may be formed by removing a portion of the active region ACT to form a recess, and then filling the recess using an epitaxial process. The source / drain regions 122 are formed on the active region ACT. The source / drain regions 122 may be doped with impurities of a different conductivity type from that of the semiconductor pattern formed on the active region ACT.

[0035] A first metal contact MC1 is formed to apply an electrical signal to a first transistor TR1 in a semiconductor device 1 according to some embodiments. In this case, a silicide layer 124 may be disposed between the source / drain region 122 and the first metal contact MC1. That is, the first metal contact MC1 may be electrically connected to the source / drain region 122 via the silicide layer 124. The first metal contact MC1 may be formed in a third direction DR3 and extend in the second direction DR2.

[0036] The first interlayer insulating film 120 and the second interlayer insulating film 220 may surround the first metal contact MC1. The first interlayer insulating film 120 may also surround the gate structure 100. The first interlayer insulating film 120 and the second interlayer insulating film 220 may include an insulating material.

[0037] FIG. 4 is an exemplary cross-sectional view taken along line BB' in FIG.

[0038] Description of parts that overlap with those described with reference to FIGS. 1 to 3 will be omitted.

[0039] 1, 2, and 4, a first active cut AC1 and a second active cut AC2 are formed on both sides of a gate structure 100. That is, the first gate structure 100 may have a first side and a second side that are opposite to each other based on a first direction DR1. Also, based on the first direction DR1, the first side of the first gate structure 100 and a first metal contact MC1 are spaced apart, and the second side of the first gate structure and a second metal contact MC2 are spaced apart.

[0040] The first active cut AC1 and the second active cut AC2 are formed by forming trenches and then filling them with an insulating material. The first trench T1 formed by filling the first active cut AC1 with an insulating material may extend in the second direction DR2 between the first side of the first gate structure 100 and the first metal contact MC1. The second trench T2 formed by filling the second active cut AC2 with an insulating material may extend in the second direction DR2 between the second side of the first gate structure 100 and the second metal contact MC2.

[0041] Therefore, the electrical distance from the gate structure 100 to the first metal contact MC1 can be increased by the first active cut AC1, thereby increasing the breakdown voltage, and the electrical distance from the gate structure 100 to the second metal contact MC2 can be increased by the second active cut AC2, thereby increasing the breakdown voltage.

[0042] The gate electrode 100_3 of the gate structure 100 may be electrically connected to a third metal contact MC3 and may receive an external signal. The third metal contact MC3 may be formed in a third direction DR3 and extend in the second direction DR2.

[0043] 1 and 2, the first active cut AC1 may define a first metal region MCR1 in which the first metal contact MC1 is located within the active region ACT. As described above, the first active cut AC1 is formed by filling a trench formed within the active region ACT with an insulating material. The first active cut AC1 extends in the second direction DR2 from a start point SP1 of the shallow trench isolation 120 to an end point IP1. The length and thickness of the first active cut AC1 are not limited to those shown in the drawings.

[0044] 2, the length F2 of the first active cut AC1 extending in the first direction DR1 may be smaller than the length W2 of the region where the gate structure 100 and the active region ACT overlap along the first direction DR1. Also, the length F1 of the first active cut AC1 extending in the second direction DR2 may be smaller than the length W1 of the region where the gate structure 100 and the active region ACT overlap along the second direction DR2. In some embodiments, the descriptions regarding the first trench T1 and the first active cut AC1 may similarly apply to the second trench T2 and the second active cut AC2.

[0045] That is, by maximizing the length of the gate structure 100 in the region where the gate structure 100 and the active region ACT overlap, the electrical distance between the metal contacts MC1, MC2 and the gate structure 100 can be increased in a transistor structure that maximizes the driving current.

[0046] The first metal region MCR1 is defined by a region surrounded by a first imaginary line IL1 extending from a starting point SP1 along a first direction DR1, a second imaginary line IL2 extending from an ending point IP1 along the first direction DR1, a first active cut AC1, and a shallow trench isolation 120.

[0047] The first metal contacts MC1 are asymmetrically arranged in the first metal region MCR1. The manner in which the first metal contacts MC1 are asymmetrically arranged in the first metal region MCR1 will be examined in more detail.

[0048] The first metal contact MC1 may be spaced a first distance D1 from a termination EP1 of the first metal region MCR1 in the first direction DR1. The first metal contact MC1 may be spaced a second distance D2 from the first active cut AC1 in the first direction DR1. The first metal contact MC1 may be spaced a third distance D3 from the first virtual line IL1. The first metal contact MC1 may be spaced a fourth distance D4 from the second virtual line IL2. In this case, the first distance D1, the second distance D2, the third distance D3, and the fourth distance D4 may be different from each other.

[0049] Alternatively, the first distance D1 and the second distance D2 may be the same, and the third distance D3 and the fourth distance D4 may be different from each other. Alternatively, the third distance D3 and the fourth distance D4 may be the same, and the first distance D1 and the second distance D2 may be different from each other. Alternatively, at least one of the four distances (first distance D1, second distance D2, third distance D3, and fourth distance D4) may be different from the other three distances. The relationship between the first distance D1 to the fourth distance D4 is not limited to any relationship as long as they are the same as each other.

[0050] 2, a third distance D3 from the first metal contact MC1 to the first virtual line IL1 may be smaller than a fourth distance D4 from the first metal contact MC1 to the second virtual line IL2. That is, by increasing the electrical distance between the metal contacts MC1 and MC2 and the gate structure 100, the breakdown voltage can be increased.

[0051] The asymmetric arrangement of the first metal contacts MC1 in the first metal region MCR1 may be explained in a manner different from the above explanation.

[0052] The first metal contact MC1 may be spaced a first diagonal distance C1 from a point where an end EP1 of the first metal region MCR1 in the first direction DR1 meets the first virtual line IL1. The first metal contact MC1 may be spaced a second diagonal distance C2 from a point where an end EP1 of the first metal region MCR1 in the first direction meets the second virtual line IL2. The first metal contact MC1 may be spaced a third diagonal distance C3 from a point where the first virtual line IL1 meets the first active cut AC1. The first metal contact MC1 may be spaced a fourth diagonal distance C4 from a point where the second virtual line IL2 meets the first active cut AC1. The first diagonal distance C1, the second diagonal distance C2, the third diagonal distance C3, and the fourth diagonal distance C4 may be different from one another. Alternatively, the first diagonal distance C1 and the second diagonal distance C2 may be the same, and the third diagonal distance C3 and the fourth diagonal distance C4 may be different from each other. Alternatively, the third diagonal distance C3 and the fourth diagonal distance C4 may be the same, and the first diagonal distance C1 and the second diagonal distance C2 may be different from each other. Alternatively, at least one of the four diagonal distances (the first diagonal distance C1, the second diagonal distance C2, the third diagonal distance C3, and the fourth diagonal distance C4) may be different from the other three diagonal distances. The relationship between the first diagonal distance C1 to the fourth diagonal distance C4 is not limited to any particular relationship, as long as they are the same.

[0053] Also, for example, in order to more completely isolate the first transistor TR1 using a high voltage from other elements, a field region 110 may be formed surrounding the shallow trench isolation 120. The field region 110 is formed by implanting impurities into the bottom of a trench surrounding the shallow trench isolation 120 and filling the trench with an insulating material. The detailed structure of the field region 110 will be described below with reference to FIG. 5, which shows a cross section taken along line C-C'.

[0054] FIG. 5 is an exemplary cross-sectional view taken along the line CC' in FIG.

[0055] Referring to Figures 2 and 5, in order to more completely isolate the first transistor TR1 using a high voltage in the semiconductor device 1 according to some embodiments from other elements, impurities 110 can be implanted into the bottom of the trench to form a field region.

[0056] For example, when the first transistor TR1 in the semiconductor device 1 according to some embodiments is an n-type transistor, the impurity 110 forming the field region may be a trivalent element (e.g., boron) implanted to isolate the active region ACT in which the p-well is formed. As another example, when the first transistor TR1 in the semiconductor device 1 according to some embodiments is a p-type transistor, the impurity 110 forming the field region may be a pentavalent element (e.g., phosphorus) implanted to isolate the active region ACT in which the n-well is formed.

[0057] 1 and 2, the second active cut AC2 may define a second metal region MCR2 in which the second metal contact MC2 is located within the active region ACT. The second active cut AC2 is formed by filling a trench formed within the active region ACT with an insulating material. The second active cut AC2 extends in the second direction DR2 from a start point SP2 of the shallow trench isolation 120 to a termination point IP2. The length and thickness of the second active cut AC2 are not limited to those shown in the drawings. The second metal region MCR2 may be defined by a region surrounded by a third imaginary line IL3 extending from the start point SP2 along the first direction DR1, a fourth imaginary line IL4 extending from the termination point IP2 along the first direction DR1, the second active cut AC2, and the shallow trench isolation 120.

[0058] The second metal contacts MC2 are asymmetrically arranged in the second metal region MCR2. The explanation for the asymmetric arrangement of the second metal contacts MC2 in the second metal region MCR2 is similar to the explanation for the asymmetric arrangement of the first metal contacts MC1 in the first metal region MCR1, and therefore, a redundant explanation will be omitted.

[0059] 6 to 9, a method for manufacturing the semiconductor device of FIG. 2 according to some embodiments will be described starting from an intermediate stage. In the description of the semiconductor device manufacturing method, a description that overlaps with the description of the semiconductor device described above will be omitted.

[0060] 6-9 are exemplary diagrams illustrating intermediate stages in a method for fabricating the semiconductor device of FIG. 2 according to some embodiments.

[0061] 2 and 6, an active area ACT is formed on a substrate, and the active area ACT may extend in a first direction DR1 and have a first width W1 in a second direction DR2.

[0062] 2 and 7, a first trench T1 is formed to form a first active cut AC1, and a second trench T2 is formed to form a second active cut AC2.

[0063] 2 and 8, the first trench T1, the second trench T2, and the surrounding area of ​​the active region ACT are filled with an insulating material to form a first active cut AC1, a second active cut AC2, and a shallow trench isolation 120. In addition, a field region 110 surrounding the shallow trench isolation 120 is formed.

[0064] 2 and 9, a gate structure 100 is formed on the active region ACT, extending in the second direction DR2 and having a second width W2 in the first direction DR1. Then, a third metal contact MC3 is formed to enable the gate structure 100 to receive an external electrical signal.

[0065] Then, a first metal contact MC1 is asymmetrically formed in a first metal region MCR1 defined by a first active cut AC1, and a second metal contact MC2 is asymmetrically formed in a second metal region MCR2 defined by a second active cut AC2, thereby forming a transistor in the semiconductor device of FIG. 2 according to some embodiments.

[0066] In the following, explanations that overlap with the above explanation will be omitted, and differences will be mainly explained.

[0067] 10 and 11 are exemplary layout diagrams illustrating semiconductor devices with metal contacts different from those of FIG. 2 according to some embodiments.

[0068] Referring to FIG. 10, the semiconductor device of FIG. 10, according to some embodiments, includes metal contacts that are different in form than the metal contacts of the semiconductor device of FIG. 2, according to some embodiments.

[0069] More specifically, the first metal contact MC1 may include a plurality of sub-metal contacts (e.g., a first_1 metal contact MC1_1 and a first_2 metal contact MC1_2), and the second metal contact MC2 may include a plurality of sub-metal contacts (e.g., a second_1 metal contact MC2_1 and a second_2 metal contact MC2_2).

[0070] The number and arrangement of the plurality of sub-metal contacts in the first metal contact MC1 are not limited to this, and the number and arrangement of the plurality of sub-metal contacts in the second metal contact MC2 are not limited to this.

[0071] As another example, referring to FIG. 11, the semiconductor device of FIG. 11 according to some embodiments includes metal contacts that are different in form than the metal contacts of the semiconductor device of FIG. 2 according to some embodiments.

[0072] More specifically, the first metal contact MC1 may have a bar shape extending in the second direction DR2, and the second metal contact MC2 may also have a bar shape extending in the second direction DR2.

[0073] The length and shape of the bar-shaped first metal contact MC1 and second metal contact MC2 extending in the second direction DR2 are not limited thereto.

[0074] 12 to 14 are layout diagrams illustrating exemplary semiconductor devices according to some embodiments.

[0075] 12, unlike the semiconductor device of FIG. 2 according to some embodiments, the first active cut AC1 includes a first extension portion 130a and a first protrusion portion 135a. That is, the first extension portion 130a may be the same as the first active cut AC1 of FIG. 2, and the semiconductor device of FIG. 12 according to some embodiments may further include a first protrusion portion 135a.

[0076] By further including the first protrusion 135a, as in the semiconductor device of FIG. 12 according to some embodiments, the electrical travel distance between the first metal contact MC1 and the gate structure 100 may be further increased, which may increase the breakdown voltage of the semiconductor device of FIG. 12 according to some embodiments.

[0077] 12 according to some embodiments differs from the semiconductor device of FIG. 2 according to some embodiments in that the second active cut AC2 includes a second extension portion 130b and a second protrusion portion 135b. That is, the second extension portion 130b may be the same as the second active cut AC2 of FIG. 2, and the semiconductor device of FIG. 12 according to some embodiments may further include a second protrusion portion 135b.

[0078] By further including the second protrusion 135b, as in the semiconductor device of FIG. 12 according to some embodiments, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, which may increase the breakdown voltage of the semiconductor device of FIG. 12 according to some embodiments.

[0079] 13, unlike the semiconductor device of FIG. 2 according to some embodiments, the first active cut AC1 may be spaced apart from the gate structure 100 in the first direction DR1 by a first distance G1.

[0080] That is, as in the semiconductor device of FIG. 13 according to some embodiments, by arranging the first active cut AC1 at a first distance G1 from the gate structure 100 in the first direction DR1, the electrical travel distance between the first metal contact MC1 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 13 according to some embodiments.

[0081] Also, in some embodiments, the semiconductor device of FIG. 13 differs from the semiconductor device of FIG. 2 in that the second active cut AC2 may be spaced apart from the gate structure 100 in the first direction DR1 by a second distance G2.

[0082] That is, as in the semiconductor device of FIG. 13 according to some embodiments, by arranging the second active cut AC2 at a second distance G2 from the gate structure 100 in the first direction DR1, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 13 according to some embodiments.

[0083] The first interval G1 and the second interval G2 may be the same as each other or may be different from each other.

[0084] 14, unlike the semiconductor device of FIG. 12 according to some embodiments, the first active cut AC1 may be spaced apart from the gate structure 100 in the first direction DR1 by a first distance G1.

[0085] That is, as in the semiconductor device of FIG. 14 according to some embodiments, by arranging the first active cut AC1 at a first distance G1 from the gate structure 100 in the first direction DR1, the electrical travel distance between the first metal contact MC1 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 14 according to some embodiments.

[0086] Also, in some embodiments, the semiconductor device of FIG. 14 differs from the semiconductor device of FIG. 12 in that the second active cut AC2 may be spaced apart from the gate structure 100 in the first direction DR1 by a second distance G2.

[0087] That is, as in the semiconductor device of FIG. 14 according to some embodiments, by arranging the second active cut AC2 at a second distance G2 from the gate structure 100 in the first direction DR1, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 14 according to some embodiments.

[0088] FIG. 15 is a circuit diagram illustrating another semiconductor device according to some embodiments.

[0089] 15, another semiconductor device 2 according to some embodiments may include a first transistor TR1 and a second transistor TR2. For example, another semiconductor device 2 according to some embodiments may include a source follower circuit coupled to a current source load.

[0090] The source of the first transistor TR1 may be coupled to the drain of the second transistor TR2, the drain of the first transistor TR1 may be coupled to a power supply voltage Vdd, and the gate of the first transistor TR1 may be coupled to a gate voltage V1 (eg, an input voltage).

[0091] The drain of the second transistor TR2 may be connected to the source of the first transistor TR1, the source of the second transistor TR2 may be connected to the ground voltage, and the gate of the second transistor TR2 may be connected to another gate voltage V2.

[0092] Another semiconductor device 2 according to some embodiments may generate an output voltage Vout through a node where the source terminal of the first transistor TR1 and the drain terminal of the second transistor TR2 are connected.

[0093] The breakdown voltage of the first transistor TR1 and the second transistor TR2 using a high voltage may decrease as the transistors TR1 and TR2 are miniaturized. Therefore, the breakdown voltage of the first transistor TR1 and the second transistor TR2 using a high voltage can be increased by increasing the electrical distance between the metal contact (e.g., the drain terminal of the first transistor TR1, the source terminal of the first transistor TR1, the drain terminal of the second transistor TR2, or the source terminal of the second transistor TR2) and the gate.

[0094] A structure for increasing the electrical distance between a metal contact (e.g., a drain terminal or a source terminal of the first transistor TR1) and the gate of a first transistor TR1 in a semiconductor device 2 according to some embodiments will be examined in detail with reference to Figure 16. Also, a structure for increasing the electrical distance between a metal contact (e.g., a drain terminal or a source terminal of the second transistor TR2) and the gate of a second transistor TR2 in a semiconductor device 2 according to some embodiments will be examined in detail with reference to Figure 16. Descriptions that overlap with those described above will be omitted.

[0095] FIG. 16 is a layout diagram illustrating an example of the semiconductor device of FIG. 15 according to some embodiments.

[0096] 15 and 16, the semiconductor device of FIG. 16 according to some embodiments differs from the semiconductor device of FIG. 2 according to some embodiments in that it includes a first gate structure 102 and a second gate structure 104.

[0097] The first gate structure 102 may have a second width W2, and the second gate structure 104 may have a third width W3. The second width W2 and the third width W3 may be the same or different from each other.

[0098] The first metal contact MC1 may receive a power supply voltage Vdd applied to the drain terminal of the first transistor TR1, the fourth metal contact MC4 may receive a gate voltage V1 applied to the gate terminal of the first transistor TR1, the fifth metal contact MC5 may receive another gate voltage V2 applied to the gate terminal of the second transistor TR2, and the second metal contact MC2 may receive a ground voltage applied to the source terminal of the second transistor TR2. In addition, the third metal contact MC3 may be formed between the first gate structure 102 and the second gate structure 104 and may connect the source terminal of the first transistor TR1 to the drain terminal of the second transistor TR2. That is, an output voltage Vout may be generated and transmitted to the outside via the third metal contact MC3.

[0099] 17 and 18 are exemplary layout diagrams illustrating semiconductor devices with metal contacts different from that of FIG. 16 according to some embodiments.

[0100] 17 and 18, the semiconductor devices of FIGS. 17 and 18, according to some embodiments, include metal contacts that have a different configuration than the metal contacts of the semiconductor device of FIG. 16, according to some embodiments.

[0101] The description of various forms of metal contacts will be omitted as they overlap with the content described with reference to FIGS.

[0102] 19 to 25 are layout diagrams illustrating other semiconductor devices according to some embodiments.

[0103] 19, unlike the semiconductor device of FIG. 16 according to some embodiments, the first active cut AC1 includes a first extension portion 130a and a first protrusion portion 135a. That is, the first extension portion 130a may be the same as the first active cut AC1 of FIG. 16, and the semiconductor device of FIG. 19 according to some embodiments may further include a first protrusion portion 135a.

[0104] By further including the first protrusion 135a, as in the semiconductor device of FIG. 19 according to some embodiments, the electrical travel distance between the first metal contact MC1 and the gate structure 100 can be further increased, which can increase the breakdown voltage of the semiconductor device of FIG. 19 according to some embodiments.

[0105] 19 according to some embodiments differs from the semiconductor device of FIG. 16 according to some embodiments in that the second active cut AC2 includes a second extension portion 130b and a second protrusion portion 135b. That is, the second extension portion 130b may be the same as the second active cut AC2 of FIG. 16, and the semiconductor device of FIG. 19 according to some embodiments may further include a second protrusion portion 135b.

[0106] By further including the second protrusion 135b, as in the semiconductor device of FIG. 19 according to some embodiments, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, which may increase the breakdown voltage of the semiconductor device of FIG. 19 according to some embodiments.

[0107] 20, unlike the semiconductor device of FIG. 16 according to some embodiments, the first active cut AC1 may be disposed at a first distance G1 from the gate structure 100 in the first direction DR1.

[0108] That is, as in the semiconductor device of FIG. 20 according to some embodiments, by arranging the first active cut AC1 at a first distance G1 from the gate structure 100 in the first direction DR1, the electrical travel distance between the first metal contact MC1 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 20 according to some embodiments.

[0109] Also, in some embodiments, the semiconductor device of FIG. 20 differs from the semiconductor device of FIG. 16 in that the second active cut AC2 may be spaced apart from the gate structure 100 in the first direction DR1 by a second distance G2.

[0110] That is, as in the semiconductor device of FIG. 20 according to some embodiments, by arranging the second active cut AC2 at a second distance G2 from the gate structure 100 in the first direction DR1, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 20 according to some embodiments.

[0111] 21, unlike the semiconductor device of FIG. 16 according to some embodiments, a first active cut AC1 is disposed at a first distance G1 from the gate structure 100 in a first direction DR1.

[0112] That is, as in the semiconductor device of FIG. 21 according to some embodiments, by arranging the first active cut AC1 at a first distance G1 from the gate structure 100 in the first direction DR1, the electrical travel distance between the first metal contact MC1 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 21 according to some embodiments.

[0113] 21 according to some embodiments differs from the semiconductor device of FIG. 16 according to some embodiments in that the second active cut AC2 is spaced apart from the gate structure 100 in the first direction DR1 by a second distance G2.

[0114] That is, as in the semiconductor device of FIG. 21 according to some embodiments, by arranging the second active cut AC2 at a second distance G2 from the gate structure 100 in the first direction DR1, the electrical travel distance between the second metal contact MC2 and the gate structure 100 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of FIG. 21 according to some embodiments.

[0115] Referring to FIG. 22, the semiconductor device of FIG. 22 according to some embodiments differs from the semiconductor device of FIG. 16 according to some embodiments in that it may further include a third active cut AC3 and a fourth active cut AC4 between the first gate electrode 102 and the second gate electrode 104.

[0116] More specifically, the fourth active cut AC4 is disposed on a second side of the first gate electrode 102 opposite the first side where the second active cut AC2 is disposed in the first direction DR1. The second active cut AC2 may extend into the active region ACT from the first side of the active region ACT in the second direction DR2. The fourth active cut AC4 may extend into the active region ACT from the second side of the active region ACT opposite the first side of the active region ACT in the second direction DR2.

[0117] In addition, a third active cut AC3 may be disposed on a second side of the second gate electrode 104 opposite to the first side where the first active cut AC1 is disposed, based on the first direction DR1. The third active cut AC3 may extend into the active region ACT from the first side of the active region ACT in the second direction DR2. In addition, the first active cut AC1 may extend into the active region ACT from the second side of the active region ACT opposite to the first side of the active region ACT, based on the second direction DR2.

[0118] That is, by placing the third active cut AC3 in the semiconductor device of Figure 22 according to some embodiments, the electrical travel distance between the third metal contact MC3 and the second gate structure 104 may be further increased, which may increase the breakdown voltage of the semiconductor device of Figure 22 according to some embodiments. Also, by placing the fourth active cut AC4 in the semiconductor device of Figure 22 according to some embodiments, the electrical travel distance between the third metal contact MC3 and the first gate structure 102 may be further increased, which may increase the breakdown voltage of the semiconductor device of Figure 22 according to some embodiments.

[0119] Referring to FIG. 23, the semiconductor device of FIG. 23 according to some embodiments differs from the semiconductor device of FIG. 19 according to some embodiments in that it may further include a third active cut AC3 and a fourth active cut AC4 between the first gate electrode 102 and the second gate electrode 104.

[0120] More specifically, a fourth active cut AC4 is arranged on the opposite side of the first gate electrode 102 from the side where the second active cut AC2 is arranged. Also, a third active cut AC3 can be arranged on the opposite side of the second gate electrode 104 from the side where the first active cut AC1 is arranged.

[0121] In this case, each of the third active cut AC3 and the fourth active cut AC4 may include an extension and a protrusion.

[0122] That is, by arranging the third active cut AC3 including the extension and protrusion as in the semiconductor device of Figure 23 according to some embodiments, the electrical travel distance between the third metal contact MC3 and the second gate structure 104 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 23 according to some embodiments. Also, by arranging the fourth active cut AC4 including the extension and protrusion as in the semiconductor device of Figure 23 according to some embodiments, the electrical travel distance between the third metal contact MC3 and the first gate structure 102 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 23 according to some embodiments.

[0123] Referring to FIG. 24, the semiconductor device of FIG. 24 according to some embodiments differs from the semiconductor device of FIG. 20 according to some embodiments in that it may further include a third active cut AC3 and a fourth active cut AC4 between the first gate electrode 102 and the second gate electrode 104.

[0124] More specifically, a fourth active cut AC4 is arranged on the opposite side of the first gate electrode 102 from the side where the second active cut AC2 is arranged. Also, a third active cut AC3 can be arranged on the opposite side of the second gate electrode 104 from the side where the first active cut AC1 is arranged.

[0125] In this case, the third active cut AC3 may be spaced apart from the second gate electrode 104 by a third distance G3, and the fourth active cut AC4 may be spaced apart from the first gate electrode 102 by a fourth distance G4. The lengths of the first distance G1 to the fourth distance G4 may be the same or different from each other.

[0126] That is, as in the semiconductor device of Figure 24 according to some embodiments, by disposing the third active cut AC3 spaced apart from the second gate electrode 104 by the third spacing G3, the electrical travel distance between the third metal contact MC3 and the second gate structure 104 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 24 according to some embodiments. Also, as in the semiconductor device of Figure 24 according to some embodiments, by disposing the fourth active cut AC4 spaced apart from the first gate electrode 102 by the fourth spacing G4, the electrical travel distance between the third metal contact MC3 and the first gate structure 102 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 24 according to some embodiments.

[0127] Referring to FIG. 25, the semiconductor device of FIG. 25 according to some embodiments differs from the semiconductor device of FIG. 21 according to some embodiments in that it may further include a third active cut AC3 and a fourth active cut AC4 between the first gate electrode 102 and the second gate electrode 104.

[0128] More specifically, a fourth active cut AC4 is arranged on the opposite side of the first gate electrode 102 from the side where the second active cut AC2 is arranged. Also, a third active cut AC3 can be arranged on the opposite side of the second gate electrode 104 from the side where the first active cut AC1 is arranged.

[0129] In this case, the third active cut AC3 includes an extension and a protrusion and is spaced apart from the second gate electrode 104 by a third distance G3. The fourth active cut AC4 includes an extension and a protrusion and is spaced apart from the first gate electrode 102 by a fourth distance G4. The lengths of the first distance G1 to the fourth distance G4 may be the same or different from each other.

[0130] That is, as in the semiconductor device of Figure 25 according to some embodiments, by arranging the third active cut AC3, which is spaced apart from the second gate electrode 104 by the third spacing G3 and includes an extension and a protrusion, the electrical travel distance between the third metal contact MC3 and the second gate structure 104 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 25 according to some embodiments. Also, as in the semiconductor device of Figure 25 according to some embodiments, by arranging the fourth active cut AC4, which is spaced apart from the first gate electrode 102 by the fourth spacing G4 and includes an extension and a protrusion, the electrical travel distance between the third metal contact MC3 and the first gate structure 102 may be further increased, thereby increasing the breakdown voltage of the semiconductor device of Figure 25 according to some embodiments.

[0131] FIG. 26 is a circuit diagram illustrating another semiconductor device according to some embodiments.

[0132] 26, another semiconductor device 3 according to some embodiments may include an n-type transistor nTR and a p-type transistor pTR. For example, the semiconductor device 3 according to some embodiments may include multiple transistors (pTR and nTR) that configure an inverter.

[0133] The source of the n-type transistor nTR is connected to the ground voltage, the drain is connected to the drain of the p-type transistor pTR, and the gate is connected to the gate of the p-type transistor pTR to receive the input voltage Vin.

[0134] The source of the p-type transistor pTR is connected to the power supply voltage Vdd, the drain is connected to the drain of the n-type transistor nTR, and the gate is connected to the n-type transistor nTR to receive the input voltage Vin.

[0135] The input voltage Vin received through the gates of the n-type transistor nTR and the p-type transistor pTR is inverted, and an output voltage Vout is generated at a node where the drain of the n-type transistor nTR and the drain of the p-type transistor pTR are connected. That is, the output voltage Vout may be an inverted signal of the input voltage Vin.

[0136] The breakdown voltage of the high-voltage n-type transistor nTR and the p-type transistor pTR can be reduced by miniaturizing them. Therefore, the breakdown voltage of the high-voltage n-type transistor nTR and the p-type transistor pTR can be increased by increasing the electrical distance between the metal contact (e.g., the drain end of the n-type transistor nTR, the source end of the n-type transistor nTR, the drain end of the p-type transistor pTR, or the source end of the p-type transistor pTR) and the gate.

[0137] A structure for increasing the electrical distance between the gate and a metal contact (e.g., the drain end of the n-type transistor nTR or the source end of the n-type transistor nTR) of the n-type transistor nTR in the semiconductor device 3 according to some embodiments will be examined in detail with reference to Figure 27. Also, a structure for increasing the electrical distance between the gate and a metal contact (e.g., the drain end of the p-type transistor pTR or the source end of the p-type transistor pTR) of the p-type transistor pTR in the semiconductor device 3 according to some embodiments will be examined in detail with reference to Figure 27. In the following, descriptions that overlap with those described above will be omitted.

[0138] FIG. 27 is a layout diagram illustrating an example of the semiconductor device of FIG. 26 according to some embodiments.

[0139] 26 and 27, the semiconductor device of FIG. 27 according to some embodiments differs from the semiconductor device of FIG. 16 according to some embodiments in that it further includes a metal line ML. The metal line ML extends in a first direction DR1 and can electrically connect the fourth metal contact MC4 and the fifth metal contact MC5. Although not shown in the drawings, a metal contact formed in a third direction DR3 on the metal line ML can be formed to receive an external voltage (e.g., an input voltage Vin).

[0140] 27 according to some embodiments may include different active regions, such as a first active region ACT1 in which an n-type transistor is formed and a second active region ACT2 in which a p-type transistor is formed, unlike the semiconductor device of FIG.

[0141] More specifically, a first active region ACT1 in which an n-type transistor nTR is formed may form a p-well on a substrate, and a second active region ACT2 in which a p-type transistor pTR is formed may form an n-well on a substrate. The first active region ACT1 may be isolated from the second active region ACT2 in the first direction by a shallow trench isolation 120 extending in the second direction between the first active region ACT1 and the second active region ACT2.

[0142] That is, the first metal contact MC1 may be connected to a ground voltage, the fourth metal contact MC4 may receive an input voltage Vin through a metal line ML and may be connected to a p-type transistor pTR through a third metal contact MC3, the second metal contact MC2 may be connected to a power supply voltage Vdd, and the fifth metal contact MC5 may receive an input voltage Vin through a metal line ML and may be connected to an n-type transistor nTR through the third metal contact MC3.

[0143] In this case, a trivalent element (e.g., boron) may be implanted into the field region 110 surrounding the first active region ACT1 forming the p-well, and a pentavalent element (e.g., phosphorous) may be implanted into the field region 112 surrounding the second active region ACT2 forming the n-well.

[0144] 28 and 29 are exemplary layout diagrams illustrating semiconductor devices different from the metal contacts of FIG. 27 according to some embodiments.

[0145] 28 and 29, the semiconductor devices of FIGS. 28 and 29, according to some embodiments, include metal contacts that are different in form than the metal contacts of the semiconductor device of FIG. 27, according to some embodiments.

[0146] The description of various forms of metal contacts will be omitted as they overlap with the content described with reference to FIGS.

[0147] 30 to 36 are layout diagrams illustrating other semiconductor devices according to some embodiments.

[0148] Referring to Figures 30 to 36, the semiconductor devices of Figures 30 to 36 according to some embodiments have the same structure as the semiconductor devices of Figures 19 to 25 according to some embodiments, except that they include a first active region ACT1 and a second active region, the field regions are composed of different field regions (110 and 112), and include a metal line ML, and therefore description thereof will be omitted.

[0149] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and may be manufactured in various different forms, and that those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the above-described embodiment should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]

[0150] 100: Gate structure 110, 112: Field area 120: Shallow trench isolation

Claims

1. an active area extending in a first direction and having a first width in a second direction intersecting the first direction; a first gate structure over the active region, the first gate structure having a second width in the first direction and extending in the second direction, the first gate structure having opposite first and second sides; first and second metal contacts spaced apart from the first and second sides of the first gate structure in the first direction; a first trench formed in the active area and extending in the second direction between a first side of the first gate structure and the first metal contact, and a second trench extending in the second direction between a second side of the first gate structure and the second metal contact; an insulating material filling the first trench to form a first active cut in the active region, the first active cut having a starting point and a termination point spaced apart from the starting point along the second direction; the first active cut defines a first metal region in the active region in which the first metal contact is located, the first metal region being surrounded by a first virtual line extending from a starting point of the first active cut along the first direction, a second virtual line extending from an end point of the first active cut along the first direction, and the insulating material, and a first distance from the first metal contact to the first virtual line is smaller than a second distance from the first metal contact to the second virtual line; a length along the first direction of a region where the first gate structure and the active region overlap is longer than a length along which the first and second trenches extend in the first direction, and a length along the second direction of a region where the first gate structure and the active region overlap is longer than a length along which the first and second trenches extend in the second direction.

2. 2. The semiconductor device of claim 1, wherein the first active cut is spaced apart from the first gate structure by a first distance in the first direction.

3. The semiconductor device according to claim 1 , wherein the first active cut is disposed between the first metal contact and the first gate structure.

4. 4. The semiconductor device according to claim 1, wherein the first metal contact is a bar contact.

5. 4. The semiconductor device according to claim 1, wherein the first metal contacts are two pairs of contacts.

6. The semiconductor device according to claim 1 , wherein the first active cut includes a protrusion extending in the first direction and an extension extending in the second direction.

7. The semiconductor device according to claim 6 , wherein the first metal contact is located between the protrusion and the extension.

8. a second active cut formed by filling the second trench with the insulating material; The semiconductor device according to claim 1 , wherein the first gate structure is disposed between the first active cut and the second active cut.

9. the second metal contact is spaced apart from the second active cut in the first direction; 9. The semiconductor device of claim 8, wherein the second active cut defines a second metal region within the active region, and the second metal contacts are asymmetrically disposed within the second metal region.

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