Page buffer circuit and memory device including the same

Abstract

To provide a page buffer circuit and a memory device having the page buffer circuit.SOLUTION: A memory device 10 includes: a memory array including a plurality of memory cells; and a peripheral circuit 200 arranged in a page buffer region including a main region and a cache region arranged in a first horizontal direction, the peripheral circuit having a page buffer circuit 210 including a first page buffer unit and a second page buffer unit next to each other in the main region in a second horizontal direction. The first page buffer unit includes a first sensing node and the second page buffer unit includes a second sensing node. The first sensing node includes a first lower metal pattern and a first upper metal pattern electrically connected to the first lower metal pattern. The sensing node has a second lower metal pattern provided in the lower metal layer and a second upper metal pattern provided in the upper metal layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device, and more particularly to a page buffer circuit and a memory device including the page buffer circuit. [Background technology]

[0002] Recently, the increasing functionality of information and communication devices has led to a demand for larger capacity and higher integration of memory devices. Memory devices include a page buffer for storing data in memory cells or outputting data from memory cells, and the page buffer may include semiconductor elements such as transistors. Due to the increasing integration of memory devices and the advancement of process technology, the size of the semiconductor elements included in the page buffer has been reduced, which has resulted in a more complex layout of wiring connected to the semiconductor elements. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical concept of the present invention provides a memory device that can improve the read reliability of the memory device while reducing the size of the page buffer circuit. [Means for solving the problem]

[0004] A memory device according to the technical idea of ​​the present invention includes a memory cell array including a plurality of memory cells, and a page buffer circuit connected to the memory cell array, arranged in a page buffer region including a main region and a cache region arranged in a first horizontal direction, the page buffer circuit including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region, the first page buffer unit including a first sensing node, the second page buffer unit including a second sensing node, the first sensing node including a first lower metal pattern provided in a lower metal layer and a first upper metal pattern provided in an upper metal layer arranged vertically above the lower metal layer and electrically connected to the first lower metal pattern, the second sensing node including a second lower metal pattern provided in the lower metal layer and a second upper metal pattern provided in the upper metal layer and electrically connected to the second lower metal pattern, the second sensing node including a second lower metal pattern provided in the lower metal layer and a second upper metal pattern provided in the upper metal layer and not adjacent to the first upper metal pattern in the second horizontal direction.

[0005] Also, a memory device according to the technical idea of ​​the present invention includes a first semiconductor layer including a plurality of memory cells respectively connected to a plurality of bit lines extending in a first horizontal direction, and a second semiconductor layer disposed vertically relative to the first semiconductor layer and including a plurality of page buffers, the plurality of page buffers including a first page buffer unit including a first sensing node and a second page buffer unit including a second sensing node, the first sensing node including a first lower metal pattern provided on a lower metal layer; and a first upper metal pattern provided on an upper metal layer disposed vertically above the lower metal layer and electrically connected to the first lower metal pattern, the second sensing node including a second lower metal pattern provided on the lower metal layer; and a second upper metal pattern provided on the upper metal layer, the second page buffer unit being adjacent to the first page buffer unit in a second horizontal direction, and the first upper metal pattern not being adjacent to the second upper metal pattern in the second horizontal direction.

[0006] In addition, a memory device according to the technical idea of ​​the present invention includes a memory cell region including a plurality of memory cells and first metal pads, and a peripheral circuit region including second metal pads, the peripheral circuit region being vertically connected to the memory cell region via the first metal pads and the second metal pads, the peripheral circuit region including a plurality of page buffers, the plurality of page buffers including a first page buffer unit including a first sensing node and a second page buffer unit including a second sensing node, the first sensing node including a first lower metal pattern provided on a lower metal layer; and a first upper metal pattern provided on an upper metal layer disposed vertically above the lower metal layer and electrically connected to the first lower metal pattern, the second sensing node including a second lower metal pattern provided on the lower metal layer; and a second upper metal pattern provided on the upper metal layer, the second page buffer unit being adjacent to the first page buffer unit in a second horizontal direction, and the first upper metal pattern not adjacent to the second upper metal pattern in the second horizontal direction.

[0007] In addition, a page buffer according to the technical idea of ​​the present invention is a page buffer arranged in a page buffer area including a main area and a cache area adjacent to each other in a first horizontal direction, and includes: a first sensing latch and a second sensing latch adjacent to each other in a second horizontal direction on the main area; a first cache latch and a second cache latch adjacent to each other in the second horizontal direction on the cache area and connected to the first sensing latch and the second sensing latch, respectively; a lower metal layer arranged vertically above the first and second sensing latches and including a first lower metal pattern corresponding to a first sensing node connected to the first sensing latch and a second lower metal pattern corresponding to a second sensing node connected to the second sensing latch; and an upper metal layer arranged vertically above the lower metal layer and including a first upper metal pattern connected to the first lower metal pattern and a second upper metal pattern connected to the second lower metal pattern, wherein the first and second upper metal patterns are not adjacent to each other in the second horizontal direction. [Effects of the Invention]

[0008] According to the technical concept of the present invention, the sensing node of each page buffer unit of the page buffer circuit is implemented using multiple metal layers arranged in a vertical direction, thereby increasing the capacitance of the sensing node. In addition, shielding metal patterns to which a power supply voltage or a ground voltage is applied are arranged on both sides of the metal pattern on which the sensing node is implemented, thereby preventing coupling with adjacent sensing nodes. Therefore, during a read operation on the memory device, voltage fluctuations at the sensing node can be reduced, thereby improving the read reliability of the memory device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a memory device according to an embodiment of the present invention; [Figure 2]2 is a diagram illustrating a schematic structure of the memory device of FIG. 1 according to an embodiment of the present invention; [Figure 3] 2 is a diagram illustrating an example of a memory cell array of FIG. 1 according to an embodiment of the present invention. [Figure 4] FIG. 4 is a perspective view of the memory block of FIG. 3 according to one embodiment of the present invention. [Figure 5] 2 is a detailed diagram of a page buffer according to an embodiment of the present invention; [Figure 6] FIG. 2 is a circuit diagram showing a page buffer circuit according to an embodiment of the present invention. [Figure 7] FIG. 2 is a circuit diagram illustrating a cache unit according to an embodiment of the present invention. [Figure 8] 2 is a detailed diagram of a page buffer according to an embodiment of the present invention; [Figure 9] 1 is a diagram illustrating a page buffer circuit and a page buffer decoder according to an embodiment of the present invention; [Figure 10] 10 is a diagram illustrating in more detail the page buffer circuit of FIG. 9 according to an embodiment of the present invention. [Figure 11] 1 is a diagram illustrating a page buffer circuit according to an embodiment of the present invention. [Figure 12] 12 is a perspective view exemplarily illustrating first to third metal layers of FIG. 11 according to an embodiment of the present invention. [Figure 13] 1 is a cross-sectional view illustrating a page buffer circuit according to an embodiment of the present invention; [Figure 14] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 15] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 16] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 17] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 18] 1 is a diagram illustrating an example of a page buffer circuit according to an embodiment of the present invention. [Figure 19] 10 is a diagram illustrating an example of a layout of first and third metal layers according to some embodiments of the present invention. [Figure 20] 10 is a diagram illustrating an example of a layout of first and third metal layers according to some embodiments of the present invention. [Figure 21] 10 is a diagram illustrating an example of a layout of first and third metal layers according to some embodiments of the present invention. [Figure 22] 10 is a diagram illustrating an example of a layout of first and third metal layers according to some embodiments of the present invention. [Figure 23] 2 is a detailed diagram of a page buffer according to some embodiments of the present invention; [Figure 24] 2 is a detailed diagram of a page buffer according to some embodiments of the present invention; [Figure 25] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 26] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 27] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 28] 10 is a diagram illustrating an example layout of a third metal layer according to some embodiments of the present invention. [Figure 29] 1 is a cross-sectional view illustrating a memory device according to an embodiment of the present invention; [Figure 30] 1 is a block diagram illustrating an example in which a memory device according to some embodiments of the present invention is applied to an SSD system. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram illustrating a memory device 10 according to one embodiment of the present invention.

[0012] 1, the memory device 10 includes a memory cell array 100 and a peripheral circuit 200, which includes a page buffer circuit 210, a control circuit 220, a voltage generator 230, and a row decoder 240. Although not shown in FIG. 1, the peripheral circuit 200 may further include a data input / output circuit or an input / output interface.

[0013] The memory cell array 100 may be connected to a page buffer circuit 210 through bit lines BL and to a row decoder 240 through word lines WL, string select lines SSL, and ground select lines GSL. The memory cell array 100 may include a plurality of memory cells, which may be flash memory cells, for example. In the following, an embodiment of the present invention will be described in detail, taking as an example a case where the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as ReRAM (resistive RAM), PRAM (phase change RAM), or MRAM (magnetic RAM).

[0014] In one embodiment, memory cell array 100 includes a three-dimensional memory cell array including multiple NAND strings, each including a memory cell coupled to a word line stacked vertically on a substrate, as described below with reference to FIGS. 3 and 4. U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference for details of suitable configurations for three-dimensional memory arrays in which the three-dimensional memory array is configured with multiple levels and word lines and / or bit lines are shared between the levels. However, the present invention is not so limited. In some embodiments, memory cell array 100 may include a two-dimensional memory cell array including multiple NAND strings arranged along rows and columns.

[0015] The control circuit 220 can output various control signals, such as a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR, for programming data to the memory cell array 100, reading data from the memory cell array 100, or erasing data stored in the memory cell array 100, based on the command CMD, the address ADDR, and the control signal CTRL. As a result, the control circuit 220 can generally control various operations within the memory device 10.

[0016] The voltage generator 230 may generate various types of voltages based on the voltage control signal CTRL_vol to perform program, read, and erase operations on the memory cell array 100. Specifically, the voltage generator 230 may generate a word line voltage VWL, such as a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage. The voltage generator 230 may also generate a string select line voltage and a ground select line voltage based on the voltage control signal CTRL_vol.

[0017] The row decoder 240 can select one of a plurality of memory blocks, one of a plurality of word lines WL of the selected memory block, and one of a plurality of string select lines SSL in response to a row address X-ADDR. The page buffer circuit 210 can select some of the bit lines BL in response to a column address Y-ADDR. Specifically, the page buffer circuit 210 operates as a write driver or a sense amplifier depending on the operation mode.

[0018] The page buffer circuit 210 may include a plurality of page buffers PB, each connected to a plurality of bit lines BL. In this embodiment, the page buffer units (e.g., PBU0 to PBU7 in FIG. 6) included in each of the plurality of page buffers PB and the cache units (e.g., CU0 to CU7 in FIG. 6) included in each of the plurality of page buffers PB are spaced apart and separated from each other. This improves the flexibility of wiring arrangement above the page buffer units and reduces layout complexity. In addition, the cache units are arranged adjacent to data input / output lines, thereby reducing the distance between the cache units and the data input / output lines and improving data input / output speed.

[0019] In one embodiment, the sensing node of each page buffer unit is implemented using multiple metal layers arranged vertically, thereby increasing the capacitance of the sensing node. In this specification, the term "metal layer" refers to a "conductive layer" and is not limited to a metal material. In addition, shielding metal patterns to which a power supply voltage or a ground voltage is applied are arranged on both sides of the metal pattern in which the sensing node is implemented, thereby preventing coupling with adjacent sensing nodes. Therefore, during a read operation on the memory device 10, voltage fluctuations of the sensing node can be reduced, thereby improving the read reliability of the memory device 10.

[0020] FIG. 2 illustrates a schematic structure of memory device 10 of FIG. 1 according to one embodiment of the present invention.

[0021] 2, the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, where the first semiconductor layer L1 may be stacked in a vertical direction VD relative to the second semiconductor layer L2. Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD, such that the second semiconductor layer L2 may be disposed close to the substrate.

[0022] In one embodiment, the memory cell array 100 of FIG. 1 may be formed on a first semiconductor layer L1, and the peripheral circuit 200 of FIG. 1 may be formed on a second semiconductor layer L2. As a result, the memory device 10 may have a structure in which the memory cell array 100 is disposed above the peripheral circuit 200, i.e., a cell over periphery (COP) structure. The COP structure may effectively reduce the horizontal area and improve the integration density of the memory device 10.

[0023] In one embodiment, the second semiconductor layer L2 may include a substrate, and a metal pattern (e.g., first to third metal layers LM0, LM2, and LM3 in FIG. 11 ) for wiring transistors and the transistors may be formed on the substrate to form the peripheral circuit 200 in the second semiconductor layer L2. After the peripheral circuit 200 is formed in the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 100 may be formed, and a metal pattern may be formed to electrically connect the word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuit 200 formed in the second semiconductor layer L2. For example, the bit lines BL may extend in a first horizontal direction HD1, and the word lines WL may extend in a second horizontal direction HD2.

[0024] With the development of semiconductor processes, the higher the number of memory cell levels arranged in the memory cell array 100, i.e., the more the number of stacked word lines WL, the smaller the area of ​​the memory cell array 100, and therefore the area of ​​the peripheral circuit 200. According to this embodiment, in order to reduce the area occupied by the page buffer circuit 210, the page buffer circuit 210 has a structure in which the page buffer unit and the cache latch are separated, and the sensing nodes included in each page buffer unit may be commonly connected to a combined sensing node. This will be described in detail with reference to FIG. 6.

[0025] FIG. 3 illustrates an exemplary memory cell array 100 of FIG. 1 according to one embodiment of the present invention.

[0026] Referring to FIG. 3, the memory cell array 100 includes a plurality of memory blocks BLK0 through BLKi, where i is a positive integer. Each of the memory blocks BLK0 through BLKi may have a three-dimensional structure (or a vertical structure). Specifically, each of the memory blocks BLK0 through BLKi may include a plurality of NAND strings extending along a vertical direction VD. In this case, the NAND strings may be spaced apart by a specific distance along first and second horizontal directions HD1 and HD2. The memory blocks BLK0 through BLKi may be selected by a row decoder (240 of FIG. 1). For example, the row decoder 240 may select a memory block corresponding to a block address from among the memory blocks BLK0 through BLKi.

[0027] FIG. 4 is a perspective view showing memory block BLK0 of FIG. 3 according to one embodiment of the present invention.

[0028] 4, the memory block BLK0 is formed in a direction perpendicular to a substrate (sub). The substrate (sub) has a first conductivity type (e.g., p-type), and a common source line CSL is provided on the substrate (sub) extending along a second horizontal direction HD2 and doped with impurities of a second conductivity type (e.g., n-type). However, the present invention is not limited to a substrate (sub) having p-type conductivity. In other embodiments, the substrate (sub) may have n-type conductivity, and a common source line CSL is provided on the substrate (sub) extending along the second horizontal direction HD2 and doped with p-type impurities.

[0029] A plurality of insulating layers IL extending along the second horizontal direction HD2 are sequentially provided along the vertical direction VD on a region of the substrate (sub) between two adjacent common source lines CSL, and the insulating layers IL are spaced apart by a specific distance along the vertical direction VD. For example, the insulating layers IL may include an insulating material such as silicon oxide.

[0030] A plurality of pillars P are provided on a region of a substrate (sub) between two adjacent common source lines CSL, sequentially arranged along a first horizontal direction HD1 and penetrating a plurality of insulating films IL along a vertical direction VD. For example, the plurality of pillars P contact the substrate (sub) by penetrating the plurality of insulating films IL. Specifically, a surface layer S of each pillar P may include a silicon material having a first type and also function as a channel region. Meanwhile, an inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0031] A charge storage layer (CS) is provided along the insulating film IL, the pillar P, and the exposed surfaces of the substrate (sub) in a region between two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (or a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, gate electrodes GE, such as select lines GSL, SSL, and word lines WL0 to WL7, are provided on the exposed surface of the charge storage layer CS in a region between two adjacent common source lines CSL. According to an embodiment, a string select transistor SST may be provided corresponding to the string select line SSL, and a ground select transistor GST may be provided corresponding to the ground select line GSL.

[0032] Drains or drain contacts DR are provided on the pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 are provided on the drains DR, extending in a first horizontal direction HD1 and spaced apart from each other along a second horizontal direction HD2.

[0033] FIG. 5 shows in detail the page buffer PB according to one embodiment of the present invention.

[0034] 5, the page buffer PB may correspond to an example of the page buffer PB of FIG. 1. The page buffer PB may include a page buffer unit PBU and a cache unit CU. The cache unit CU may include a cache latch (C-LATCH) CL. In one embodiment, the cache latch CL is connected to a data input / output line, and thus the cache unit CU may be disposed adjacent to the data input / output line. As a result, the page buffer unit PBU and the cache unit CU are disposed spaced apart from each other, and the page buffer PB may have a separated structure of the page buffer unit PBU and the cache unit CU.

[0035] The page buffer unit PBU may include a main unit MU. The main unit MU may include a main transistor in the page buffer PB. The page buffer unit PBU may further include a bit line selection transistor TR_hv connected to the bit line BL and driven by a bit line selection signal BLSLT. The bit line selection transistor TR_hv may be implemented using a high voltage transistor, and thus the bit line selection transistor TR_hv may be disposed in a well region different from the main unit MU, i.e., a high voltage unit HVU.

[0036] The main unit MU may include a sensing latch (S-LATCH) SL, a force latch (F-LATCH) FL, a most significant bit latch (M-LATCH) ML, and a least significant bit latch (L-LATCH) LL. Depending on the embodiment, the sensing latch SL, the force latch FL, the most significant bit latch ML, or the least significant bit latch LL may be referred to as a "main latch." The main unit MU may further include a precharge circuit PC that can control a precharge operation for the bit line BL or the sensing node SO based on a bit line clamping control signal BLCLAMP, and may further include a transistor PM' driven by a bit line setup signal BLSETUP.

[0037] The sensing latch SL can store data stored in a memory cell or a sensing result of the threshold voltage of the memory cell during a read or program verify operation. The sensing latch SL can also be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL can also be used to improve threshold voltage distribution during a program operation. The upper bit latch ML, lower bit latch LL, and cache latch CL are used to store data input from the outside during a program operation and are also referred to as "data latches." When programming 3-bit data into one memory cell, the 3-bit data can be stored in the upper bit latch ML, lower bit latch LL, and cache latch CL, respectively. During a read operation, the cache latch CL can transmit data read from the memory cell from the sensing latch SL and output it to the outside via a data input / output line.

[0038] The main unit MU may further include first through fourth transistors NM1 through NM4. The first transistor NM1 is connected between the sensing node SO and the sensing latch SL and may be driven by a ground control signal SOGND. The second transistor NM2 is connected between the sensing node SO and the forcing latch FL and may be driven by a forcing monitoring signal MON_F. The third transistor NM3 is connected between the sensing node SO and the most significant bit latch ML and may be driven by a most significant bit monitoring signal MON_M. The fourth transistor NM4 is connected between the sensing node SO and the least significant bit latch LL and may be driven by a least significant bit monitoring signal MON_L.

[0039] The main unit MU may further include fifth and sixth transistors NM5 and NM6 connected in series between the bit line selection transistor TV_hv and the sensing node SO. The fifth transistor NM5 may be driven by a bit line shut-off signal BLSHF, and the sixth transistor NM6 may be driven by a bit line connection control signal CLBLK. The main unit MU may further include a precharge transistor PM. The precharge transistor PM is connected to the sensing node SO and driven by a load signal LOAD to precharge the sensing node SO to a precharge level during a precharge period.

[0040] In this embodiment, the main unit MU may further include a pair of pass transistors, i.e., first and second pass transistors TR and TR', coupled to the sensing node SO. Depending on the embodiment, the first and second pass transistors TR and TR' may also be referred to as "first and second sensing node-connected transistors." The first and second pass transistors TR and TR' may be driven by a pass control signal SO_PASS. Depending on the embodiment, the pass control signal SO_PASS may also be referred to as "sensing node-connected control signal." The first pass transistor TR may be coupled between the first terminal SOC_U and the sensing node SO, and the second pass transistor TR' may be coupled between the sensing node SO and the second terminal SOC_D.

[0041] The page buffer PB verifies whether a selected memory cell among memory cells included in a NAND string connected to a bit line BL has been programmed during a program operation. Specifically, the page buffer PB stores data sensed through the bit line BL in the sensing latch SL during a program verify operation. The upper bit latch ML and the lower bit latch LL, in which target data is stored, are set according to the sensed data stored in the sensing latch SL. For example, if the sensed data indicates that programming has been completed, the upper bit latch ML and the lower bit latch LL are changed to a program inhibit setting for the selected memory cell in the subsequent program loop. The cache latch CL can temporarily store input data provided from the outside. During a program operation, target data to be stored in the cache latch CL can be stored in the upper bit latch ML and the lower bit latch LL.

[0042] According to one embodiment, the cache unit CU may include a monitor transistor NM7. A source S of the monitor transistor NM7 may be coupled to the coupled sensing node SOC, and a cache monitoring signal MON_C may be applied to a gate of the monitor transistor NM7. The cache unit CU may also include a cache latch CL.

[0043] FIG. 6 is a circuit diagram illustrating a page buffer circuit 210a according to one embodiment of the present invention.

[0044] 6, the page buffer circuit 210a may include first through eighth page buffer units PBU0 through PBU7 arranged along a first horizontal direction HD1 and first through eighth cache units CU0 through CU7 arranged along the first horizontal direction HD1. For example, each of the first through eighth page buffer units PBU0 through PBU7 may be implemented substantially similarly to the page buffer unit PBU of FIG. 5, and each of the first through eighth cache units CU0 through CU7 may be implemented substantially similarly to the cache unit CU of FIG. 5, and the content described above with reference to FIG. 5 may be applied to this embodiment.

[0045] The first page buffer unit PBU0 may include first and second pass transistors TR0 and TR0' connected in series, and the second page buffer unit PBU1 may include first and second pass transistors TR1 and TR1' connected in series. A pass control signal SO_PASS[7:0] may be applied to the gates of the first and second pass transistors TR0, TR0', TR1, and TR1'. According to this embodiment, when the pass control signal SO_PASS is activated, the first and second pass transistors TR0 through TR7 and TR0 through TR7' are turned on. As a result, the first and second pass transistors TR0 through TR7' included in the first through eighth page buffer units PBU0 through PBU7 are connected in series, and the first through eighth sensing nodes SO0 through SO7 are all connected to the combined sensing node SOC.

[0046] The first through eighth page buffer units PBU0 through PBU7 may further include precharge transistors PM0 through PM7, respectively. In the first page buffer unit PBU0, the precharge transistor PM0 may be connected between the first sensing node SO0 and a voltage terminal to which a precharge level is applied, and may have a gate to which a load signal LOAD is applied. The precharge transistor PM0 may precharge the first sensing node SO0 to the precharge level in response to the load signal LOAD.

[0047] The first cache unit CU0 may include a monitor transistor NM7a. For example, the monitor transistor NM7a may correspond to transistor NM7 of FIG. 5. The source S of the monitor transistor NM7a may be connected to a coupled sensing node SOC, and a cache monitoring signal MON_C[7:0] may be applied to the gate of the monitor transistor NM7a. The monitor transistors NM7a through NM7h included in the first through eighth cache units CU0 through CU7, respectively, may be commonly connected in parallel to the coupled sensing node SOC. Specifically, the sources of the monitor transistors NM7a through NM7h may be commonly connected to the coupled sensing node SOC.

[0048] The page buffer circuit 210a may further include a precharge circuit SOC_PRE between the eighth page buffer unit PBU7 and the first cache unit CU0. The precharge circuit SOC_PRE may include a precharge transistor PMa and a shield transistor NMa for precharging the coupled sensing node SOC. The precharge transistor PMa is driven by a coupled sensing node load signal SOC_LOAD, and when the precharge transistor PMa is turned on, the coupled sensing node SOC may be precharged to a precharge level. The shield transistor NMa is driven by a coupled sensing node shield signal SOC_SHLD, and when the shield transistor NMa is turned on, the coupled sensing node SOC may be discharged to the ground level.

[0049] In a structure in which the first through eighth page buffer units PBU0 through PBU7 are separated from the first through eighth cache units CU0 through CU7, providing eight signal lines to connect the first through eighth page buffer units PBU0 through PBU7 to the first through eighth cache units CU0 through CU7 would increase the size of the page buffer circuit 210a along the second horizontal direction HD2. However, according to this embodiment, the first through eighth sensing nodes SO0 through SO7 are connected to each other using first and second pass transistors TR0 through TR7 and TR0 through TR7' included in the first through eighth page buffer units PBU0 through PBU7, respectively, and the first through eighth sensing nodes SO0 through SO7 are connected to the first through eighth cache units CU0 through CU7 through the combined sensing node SOC. This prevents the size of the page buffer circuit 210a from increasing along the second horizontal direction HD2.

[0050] FIG. 7 is a circuit diagram showing a cache unit CU according to one embodiment of the present invention.

[0051] 7, the cache unit CU includes a monitor transistor NM7 and a cache latch CL, and the cache latch CL includes first and second inverters INV1 and INV2, a dump transistor 132, and transistors 131, 133, and 135. The monitor transistor NM7 is driven by a cache monitoring signal MON_C and can control the connection between the coupled sensing node SOC and the cache latch CL.

[0052] The first inverter INV1 is connected between the first node ND1 and the second node ND2, and the second inverter INV2 is connected between the second node ND2 and the first node ND1. The first and second inverters INV1 and INV2 may form a latch. The transistor 131 has a gate connected to a coupled sensing node SOC. The dump transistor 132 is driven by a dump signal Dump_C to transfer data stored in the cache latch CL to one of the main latches, e.g., the sensing latch SL, the force latch FL, the most significant bit latch ML, or the least significant bit latch LL, in the page buffer unit PBU. The transistor 133 is driven by a data signal DI, the transistor 134 is driven by a data inversion signal nDI, and the transistor 135 is driven by a write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first and second nodes ND1 and ND2 may be determined by the data signal DI and the data inversion signal nDI.

[0053] The cache unit CU may be connected to the input / output terminal RDi through transistors 136 and 137. The transistor 136 has a gate connected to a second node ND and may be turned on or off depending on the voltage level of the second node ND2. The transistor 137 may be driven by a read control signal DIO_R. When the control signal DIO_R is activated and the transistor 137 is turned on, the voltage level of the input / output terminal RDi may be determined to be “1” or “0” depending on the state of the cache latch CL.

[0054] FIG. 8 shows in detail a page buffer PB' according to one embodiment of the present invention.

[0055] 8, the page buffer PB' includes a page buffer unit PBU' and a cache unit CU, and the page buffer unit PBU' includes a main unit MU' and a high-voltage unit HVU. The page buffer PB' corresponds to a modified version of the page buffer PB of FIG. 5, and the contents described above with reference to FIGS. 5 to 7 may be applied to this embodiment. The page buffer unit PBU of FIG. 5 includes first and second pass transistors TR, TR', while the page buffer unit PBU' according to this embodiment includes one pass transistor TR". The pass transistor TR" may be driven by a pass control signal SO_PASS and may be connected between a first terminal SOC_U and a second terminal SOC_D.

[0056] FIG. 9 illustrates a page buffer circuit 210 and a page buffer decoder 250 according to one embodiment of the present invention.

[0057] 9, the page buffer circuit 210 may include first through fourth page buffer circuits PGBUFa through PGBUFd arranged along a second horizontal direction HD2. For example, each of the first through fourth page buffer circuits PGBUFa through PGBUFd may be implemented as the page buffer circuit 210 of FIG. 6. In this manner, the page buffer circuit 210 may be implemented in the form of a page buffer array. However, the present invention is not limited thereto. Each of the first through fourth page buffer circuits PGBUFa through PGBUFd may include a plurality of page buffers, each of which may be implemented as the page buffer PB' of FIG. 8.

[0058] The page buffer decoder 250 may include first through fourth page buffer decoders PBDECa through PBDECd arranged adjacent to the page buffer circuit 210 in a first horizontal direction HD1 and along a second horizontal direction HD2. The first through fourth page buffer decoders PBDECa through PBDECd may be connected to the first through fourth page buffer circuits PGBUFa through PGBUFd, respectively. For example, the first page buffer decoder PBDECa may generate a decoder output signal corresponding to the number of fail bits from a page buffer signal received from the first page buffer circuit PGBUFa. For example, if the page buffer signal is logic low, it may be determined that programming for the corresponding memory cell has failed and be determined as a fail bit.

[0059] FIG. 10 illustrates in more detail the page buffer circuit 210 of FIG. 9 according to one embodiment of the present invention.

[0060] 10, the first page buffer circuit PGBUFa includes page buffer units PBU0a through PBU7a and cache units CU0a through CU7a, where the sensing nodes of the page buffer units PBU0a through PBU7a are commonly connected to a first coupled sensing node SOC1, and the cache units CU0a through CU7a are commonly connected to the first coupled sensing node SOC1. The second page buffer circuit PGBUFb includes page buffer units PBU0b through PBU7b and cache units CU0b through CU7b, where the sensing nodes of the page buffer units PBU0b through PBU7b are commonly connected to a second coupled sensing node SOC2, and the cache units CU0b through CU7b are commonly connected to the second coupled sensing node SOC2. The third page buffer circuit PGBUFc includes page buffer units PBU0c through PBU7c and cache units CU0c through CU7c, where the sensing nodes of the page buffer units PBU0c through PBU7c are commonly connected to a third coupled sensing node SOC3, and the cache units CU0c through CU7c may be commonly connected to the third coupled sensing node SOC3. The fourth page buffer circuit PGBUFd includes page buffer units PBU0d through PBU7d and cache units CU0d through CU7d, where the sensing nodes of the page buffer units PBU0d through PBU7d are commonly connected to a fourth coupled sensing node SOC4, and the cache units CU0d through CU7d may be commonly connected to the fourth coupled sensing node SOC4.

[0061] Figure 11 shows a page buffer circuit 20 according to an embodiment of the present invention. Figure 12 is a perspective view exemplarily showing the first to third metal layers LM0 to LM2 of Figure 11 according to an embodiment of the present invention.

[0062] 11 and 12, the page buffer circuit 20 may include first and second page buffer units PBU0a and PBU0b adjacent to each other in a second horizontal direction HD2. The first page buffer unit PBU0a may include a transistor TRa, which may include a source S0a, a gate G0a, and a drain D0a. The second page buffer unit PBU0b may include a transistor TRb, which may include a source S0b, a gate G0b, and a drain D0b. For example, the transistors TRa and TRb may correspond to the pass transistor TR illustrated in FIG. 5 or the pass transistor TR″ of FIG. 8, but the present invention is not limited thereto.

[0063] A first metal layer LM0, a second metal layer LM1, and a third metal layer LM2 may be disposed above the page buffer circuit 20 in the vertical direction VD. For example, the first and third metal layers LM0 and LM2 extend in a first horizontal direction HD1, and the second metal layer LM1 extends in a second horizontal direction HD2. The first metal layer LM0 may include first metal patterns LM0a and LM0b, the second metal layer LM1 may include second metal patterns LM1a and LM1b, and the third metal layer LM2 may include third metal patterns LM2a and LM2b. For example, the pitch of the first metal patterns LM0a and LM0b is smaller than the pitch of the third metal patterns LM2a and LM2b. For example, the thickness of the first metal patterns LM0a and LM0b along the vertical direction VD is thinner than the thickness of the third metal patterns LM2a and LM2b along the vertical direction VD. In this specification, the "first metal layer" is also referred to as the "lower metal layer," the "third metal layer" is also referred to as the "upper metal layer," the "first metal pattern" is also referred to as the "lower metal pattern," and the "second metal pattern" is also referred to as the "second upper metal pattern."

[0064] The first, second, and third metal patterns LM0a, LM1a, and LM2a disposed on the first page buffer unit PBU0a may be connected to each other to implement a first sensing node SO0. For example, the first metal pattern LM0a may be connected to the drain D0a of the transistor TRa through a contact CT0a, the second metal pattern LM1a may be connected to the first metal pattern LM0a through a contact CT1a, and the third metal pattern LM2a may be connected to the second metal pattern LM1a through a contact CT2a. In this case, the third metal pattern LM2a may also be referred to as the first sensing node SO0 or the first sensing plus node SO0+. By implementing the first sensing node SO0 using multiple metal layers in this manner, the overall capacitance of the first sensing node SO0 may be increased to a sufficiently large value relative to the sensing current to provide robustness against variations in sensing conditions. Therefore, during reading, the voltage fluctuation of the first sensing node SO0 is reduced, and the read reliability for the first sensing node SO0 can be improved.

[0065] The first, second, and third metal patterns LM0b, LM1b, and LM2b arranged on the second page buffer unit PBU0b are connected to each other, thereby implementing a second sensing node SO1. For example, the first metal pattern LM0b may be connected to the drain D0b of the transistor TRb through a contact CT0b, the second metal pattern LM1b may be connected to the first metal pattern LM0b through a contact CT1b, and the third metal pattern LM2b may be connected to the second metal pattern LM1b through a contact CT2b. In this case, the third metal pattern LM2b may also be referred to as the second sensing node SO1 or the second sensing plus node SO1+. By implementing the second sensing node SO1 using multiple metal layers in this manner, the overall capacitance of the second sensing node SO1 may be increased to a sufficiently large value relative to the sensing current to provide robustness against changes in sensing conditions. Therefore, during reading, the voltage fluctuation of the second sensing node SO1 is reduced, and the read reliability for the second sensing node SO1 can be improved.

[0066] In one embodiment, the third metal patterns LM2a and LM2b may be arranged so as not to be adjacent to each other in the second horizontal direction HD2. For example, the third metal patterns LM2a and LM2b may be spaced apart by a first distance SP in the first horizontal direction HD1. This may reduce coupling between the third metal patterns LM2a and LM2b, so that fluctuations in the voltage of the second sensing node SO1 do not affect the voltage of the first sensing node SO0, thereby improving read reliability of the memory device.

[0067] In one embodiment, the first metal layer LM0 may further include first metal patterns LM0c, LM0d, and LM0e disposed between the first metal patterns LM0a and LM0b. Each of the first metal patterns LM0c, LM0d, and LM0e may include a plurality of patterns spaced apart from one another, and for example, the plurality of patterns may be connected to a plurality of transistors. For example, an internal power supply voltage or a ground voltage may be applied to the first metal pattern LM0c, thereby shielding the first metal pattern LM0a corresponding to the first sensing node SO0. In this specification, a metal pattern to which an internal power supply voltage or a ground voltage is applied is also referred to as a "power supply pattern." For example, an internal power supply voltage or a ground voltage may be applied to the first metal pattern LM0e, thereby shielding the second metal pattern LM0b corresponding to the second sensing node SO1. As described above, according to this embodiment, by arranging first metal patterns LM0c and LM0e having fixed bias voltages on both sides of the first metal patterns LM0a and LM0b corresponding to the first and second sensing nodes SO0 and SO1, respectively, it is possible to minimize voltage fluctuations at the first and second sensing nodes SO0 and SO1.

[0068] The area occupied by the page buffer circuit 20 may be determined based on the transistor width WD. For example, as the transistor width WD decreases due to process miniaturization, the area occupied by the page buffer circuit 20 decreases. For example, the transistor width WD corresponds to the size of the gate G0a of the transistor TRa along the second horizontal direction HD2. Specifically, as the transistor width WD decreases, the size of the first page buffer unit PBU0a along the second horizontal direction HD2 decreases. However, despite the decrease in the transistor width WD, the pitch of the first metal layer LM0 does not decrease. As a result, the number of wirings, i.e., the number of metal patterns, in the first metal layer LM0 disposed above the first page buffer unit PBU0a, whose size in the second horizontal direction HD2 has decreased, also decreases. For example, the number of metal patterns in the first metal layer LM0 corresponding to the first page buffer unit PBU0a is reduced from six to four.

[0069] If the number of metal patterns in the first metal layer LM0 corresponding to the first page buffer unit PBU0a is reduced, the sensing reliability of the first page buffer unit PBU0a may be reduced. For example, to prevent coupling between the first sensing node S00 and adjacent nodes during sensing, the metal pattern adjacent to the first sensing node S00 can be used as a shield line to which a fixed bias is applied. However, if the metal pattern corresponding to the shield line is removed due to the reduction in the number of metal patterns, a problem occurs in which voltage fluctuations at the first sensing node S00 increase due to coupling between the first sensing node S00 and adjacent nodes, which may reduce the sensing reliability of the first page buffer unit PBU0a.

[0070] However, according to this embodiment, by using a page buffer unit-cache unit separation structure, the degree of freedom for the metal patterns included in the third metal layer LM2 arranged on the first page buffer unit PBU0 increases, and one of the metal patterns included in the third metal layer LM2 can be used as the first sensing plus node SO0+. By connecting the first sensing node SO0 and the first sensing plus node SO+, an increase in voltage fluctuation at the first sensing node SO0 can be prevented, and therefore, a decrease in the sensing reliability of the first page buffer unit PBU0 can be prevented.

[0071] FIG. 13 is a cross-sectional view illustrating an exemplary page buffer circuit 20a according to one embodiment of the present invention.

[0072] Referring to FIG. 13, the page buffer circuit 20a corresponds to a modification of the page buffer circuit 20 illustrated in FIG. 11, and the contents described above with reference to FIGS. 11 and 12 may also apply to this embodiment. The page buffer circuit 20a may include a transistor TR disposed on a substrate (sub). For example, the transistor TR may correspond to the pass transistor TR illustrated in FIG. 5 or the pass transistor TR″ of FIG. 8, but the present invention is not limited thereto. The first metal layer LM0 may extend in a first horizontal direction HD1 and be connected to the source / drain region S / D of the transistor TR through a contact CT0. The second metal layer LM1 may extend in a second horizontal direction HD2 and be connected to the first metal layer LM0 through a contact CT1. The third metal layer LM2 may extend in the first horizontal direction HD1 and be connected to the second metal layer LM1 through a contact CT2. Thus, according to this embodiment, the third metal layer LM2 and the first metal layer LM0 may partially overlap in the vertical direction VD.

[0073] FIG. 14 exemplarily illustrates a layout 30 of a third metal layer disposed on top of the page buffer circuit 210 and the page buffer decoder 250, according to one embodiment of the present invention.

[0074] 14, a page buffer circuit 210 and a page buffer decoder 250 may be arranged along a first horizontal direction HD1. The page buffer circuit 210 may be arranged in a page buffer region including a main region MR and a cache region CR. A page buffer unit array including page buffer units PBU0a to PBU0d may be arranged in the main region MR, and a cache unit array including cache units CU0a to CU0d may be arranged in the cache region CR.

[0075] The third metal layer LM2 may include metal patterns 311 to 318 and 321 to 328 extending in a first horizontal direction HD1 and may be arranged above the page buffer circuit 210 and the page buffer decoder 250 in the vertical direction VD. For example, the third metal layer LM2 corresponds to the third metal layer LM2 in FIGS. 11 to 13. The metal patterns 311, 314, and 316 may be arranged across the main region MR, the cache region CR, and the page buffer decoder 250, and the metal pattern 315 may be arranged across the main region MR and the cache region CR. For example, the internal power supply voltage IVC may be applied to the metal patterns 311 and 316, the ground voltage GND may be applied to the metal pattern 314, and the page buffer driver signal PBDRV may be applied to the metal pattern 315.

[0076] The metal patterns 312, 313, 317, and 318 may be disposed across the cache region CR and the page buffer decoder 250. The metal patterns 312, 313, 317, and 318 may be electrically connected to the cache units CU0a to CU0d and the page buffer decoder 250 through contacts CT. The metal patterns 321 to 328 may be disposed across the main region MR.

[0077] 10, the page buffer circuit 210 may have a page buffer unit-cache unit separation structure. For example, in the page buffer circuit 210, metal patterns 312, 313, 317, and 318, to which signals related to the cache units CU0a through CU0d are applied, are disposed across the cache region CR and the top of the page buffer decoder 250 and do not extend to the main region MR. For example, the metal patterns 312 and 318 correspond to the input / output terminal RDi and the inverted input / output terminal nRDi, and the data inverted signal nDI and the data signal DI may be applied to the metal patterns 313 and 317, respectively.

[0078] This page buffer unit-cache unit separation structure increases the wiring flexibility of the third metal layer LM2 above the main region MR where the page buffer units PBU0a-PBU0d are arranged. As a result, some metal patterns 321-324 of the third metal layer LM2 arranged above the main region MR can be used for the first through fourth sensing nodes SO0-SO3 of the page buffer units PBU0a-PBU0d, respectively. Specifically, the first through fourth sensing nodes SO0-SO3 are implemented by metal patterns included in the first metal layer LM0, and the metal patterns included in the first metal layer LM0 are electrically connected to the metal patterns 321-324 included in the third metal layer LM2, respectively, thereby increasing the capacitance of the first through fourth sensing nodes SO0-SO3.

[0079] FIG. 15 exemplarily shows a layout 30a of the third metal layer LM2 according to one embodiment of the present invention.

[0080] 15, layout 30a corresponds to a modified example of layout 30 of FIG. 14, and therefore a redundant description will be omitted. For example, first through eighth cache units CU0 through CU7 of FIG. 6 may be arranged in cache region CR. Main region MR may include a low voltage region LV and a high voltage region HV. For example, main unit MU of FIG. 5 or main unit MU' of FIG. 8 may be arranged in low voltage region LV, and high voltage unit HVU of FIG. 5 or 8 may be arranged in high voltage region HV. While FIG. 15 illustrates one low voltage region LV and one high voltage region HV for convenience, the present invention is not limited thereto. For example, a plurality of low voltage regions and a plurality of high voltage regions corresponding to, for example, first through eighth page buffer units PBU0 through PBU7 of FIG. 6 may be arranged along a first horizontal direction HD1. The page buffer units arranged in main region MR are connected to a column driver, and the column driver may provide a gate driving voltage applied to the gates of the transistors included in the page buffer units.

[0081] The third metal layer LM2 may include metal patterns 311-318, 321-328, and 331-334 extending in a first horizontal direction HD1. The metal patterns 311, 314, and 316 may be disposed across the main region MR, the cache region CR, and the page buffer decoder 250, and the metal pattern 315 may be disposed across the main region MR and the cache region CR. For example, the first page buffer driver signal PBDRV may be applied to the metal pattern 315 and may be connected to a column driver. The metal patterns 331-334 may be disposed above the high voltage region HV of the page buffer circuit 210 in the vertical direction VD. For example, the metal patterns 331-334 correspond to first through fourth nodes SOC_U0-SOC_U3, respectively. For example, one of the first through fourth nodes SOC_U0-SOC_U3 corresponds to the first terminal SOC_U of FIG. 5 or FIG. 8.

[0082] FIG. 16 exemplarily shows a layout 30b of the third metal layer LM2 according to one embodiment of the present invention.

[0083] 16, layout 30b corresponds to a modified example of layout 30a of FIG. 15, and therefore, a redundant description will be omitted. The third metal layer LM2 may include metal patterns 311, 312a through 316a, 321a through 324a, 326a, 331a, 333a, and 335 extending in a first horizontal direction HD1. The metal patterns 311 and 315a may be disposed across the main region MR, the cache region CR, and the top of the page buffer decoder 250. For example, an internal power supply voltage IVC and a ground voltage GND may be applied to the metal patterns 311 and 315a, respectively.

[0084] The metal patterns 321a through 324a may be disposed above the low voltage region LV in the vertical direction VD and correspond to, for example, first through fourth sensing nodes SO0 through SO3, respectively. The metal patterns 321a and 322a may be disposed in a row along a first horizontal direction HD1, and the metal patterns 323a and 324a may be disposed in a row along the first horizontal direction HD1. The metal pattern 326a may be disposed above the main region MR in the vertical direction VD and may receive, for example, a ground voltage GND. The metal pattern 335 may be disposed above the main region MR in the vertical direction VD and may receive, for example, a first page buffer driver signal PBDRV and be connected to a first column driver. The metal pattern 316b may be disposed above the cache region CR and the page buffer decoder 250 and may receive, for example, a second page buffer driver signal PBDRVa and be connected to a second column driver. The metal patterns 331a and 333a may be disposed above the high voltage region HV in the vertical direction VD. For example, the metal pattern 331a corresponds to the first and second nodes SOC_U0 and SOC_U1, and the metal pattern 333a corresponds to the third and fourth nodes SOC_U2 and SOC_U4.

[0085] FIG. 17 exemplarily shows a layout 30c of the third metal layer LM2 according to one embodiment of the present invention.

[0086] 17, layout 30c corresponds to a modification of layout 30b of FIG. 16, and therefore redundant description will be omitted. Third metal layer LM2 may include metal patterns 311, 312a through 316a, 321a through 324a, 326b, 327a, and 331b through 334b ​​extending in a first horizontal direction HD1. Metal pattern 315b is disposed in the vertical direction VD above cache region CR and page buffer decoder 250, and may receive, for example, ground voltage GND. Metal patterns 326b and 327a are disposed in the vertical direction VD above low voltage region LV, and may receive, for example, ground voltage GND and internal power supply voltage IVC, respectively. Metal patterns 331b through 334b ​​are disposed in the vertical direction VD above high voltage region HV, and may receive, for example, first through fourth nodes SOC_U0 through SOC_U3, respectively.

[0087] FIG. 18 illustrates an exemplary page buffer circuit 40 according to one embodiment of the present invention.

[0088] 18, the page buffer circuit 40 may include a lower metal layer 410 including lower metal patterns 411a, 411b, 412, 413a, 413b, 414, 415a, 415b, 416, 417a, 417b, and 418, an upper metal layer 420 including upper metal patterns 421 through 429, and a plurality of active areas 430. For example, the plurality of active areas 430 may include source / drain regions of transistors included in the page buffer unit. As shown in FIG. 18, the pitch of the lower metal patterns is smaller than the pitch of the upper metal patterns. For example, in one embodiment, the distance between adjacent patterns of the lower metal patterns is shorter than the distance between adjacent patterns of the upper metal patterns.

[0089] The lower metal patterns 411a through 418 are disposed above the active areas 430 in the vertical direction VD and extend in a first horizontal direction HD1. For example, the lower metal patterns 412, 414, 416, and 418 correspond to the first through fourth sensing nodes SO0 through SO3, respectively. The upper metal patterns 421 through 429 are disposed above the lower metal layer 410 in the vertical direction VD and extend in the first horizontal direction HD1. For example, the upper metal patterns 422, 424, 426, and 428 are connected to the lower metal patterns 412, 414, 416, and 418, respectively, through contacts CT, thereby corresponding to the first through fourth sensing nodes SO0 through SO3, respectively.

[0090] Lower metal patterns 411a and 411b arranged on both sides of the lower metal pattern 412 corresponding to the first sensing node SO0 may be applied with, for example, an internal power supply voltage or a ground voltage, and may therefore be used as shielding lines for the lower metal pattern 412. Similarly, lower metal patterns 413a and 413b may be used as shielding lines for the lower metal pattern 414, lower metal patterns 415a and 415b may be used as shielding lines for the lower metal pattern 416, and lower metal patterns 417a and 417b may be used as shielding lines for the lower metal pattern 418. Furthermore, upper metal patterns 421, 423, 425, and 427 may be applied with, for example, an internal power supply voltage or a ground voltage, and may therefore be used as shielding lines for the upper metal patterns 422, 424, 426, and 428.

[0091] FIG. 19 exemplarily shows a layout 50a of the first and third metal layers LM0 and LM2 according to one embodiment of the present invention.

[0092] 19, first and third metal layers LM0 and LM2 extend in a first horizontal direction HD1, and the third metal layer LM2 is disposed above the first metal layer LM0 in a vertical direction VD and may be connected to each other through contacts CT. The third metal layer LM2 may include first through fourth sensing node patterns SOa through SOd and first through fourth internal signal patterns ISa through ISd. For example, signals connected to the sensing latches may be applied to the internal signal patterns ISa through ISd, respectively. The first through fourth sensing node patterns SOa through SOd are not adjacent to each other in a second horizontal direction HD2. For example, the first through fourth sensing node patterns SOa through SOd and the first through fourth internal signal patterns ISa through ISd may be alternately arranged along the second horizontal direction HD2.

[0093] The following describes patterns arranged on multiple tracks of the third metal layer LM3. For example, a first internal signal pattern ISa may be arranged on the first track, first and second sensing node patterns SOa and SOb may be arranged on the second track, a second internal signal pattern ISb may be arranged on the third track, a third internal signal pattern ISc may be arranged on the fourth track, third and fourth sensing node patterns SOc and SOd may be arranged on the fifth track, and a fourth internal signal pattern ISd may be arranged on the sixth track.

[0094] FIG. 20 exemplarily shows a layout 50b of the first and third metal layers LM0 and LM2 according to one embodiment of the present invention.

[0095] 20, layout 50b corresponds to a modified example of layout 50 of FIG. 19, and therefore a redundant description will be omitted. Third metal layer LM2 may further include metal patterns 511 and 512 to which a ground voltage GND or an internal power supply voltage IVC is applied, respectively. Metal patterns 511 and 512 may be used as shielding lines for first through fourth sensing node patterns SOa through SOd. For example, metal pattern 511 may include vertical patterns on the first, third, fourth, and sixth tracks and horizontal patterns connecting them, and is used as a shielding pattern for first and third sensing node patterns SOa and SOc. For example, metal pattern 512 may include vertical patterns on the first, third, fourth, and sixth tracks and horizontal patterns connecting them, and is used as a shielding line for second and fourth sensing node patterns SOb and SOd.

[0096] 21 illustrates a layout 50c of first and third metal layers LM0 and LM2 according to an embodiment of the present invention. Referring to FIG. 21, layout 50c corresponds to a modification of layout 50a of FIG. 20, and therefore, a redundant description will be omitted. Third metal layer LM2 may further include patterns 513 and 514 to which a ground voltage GND or an internal power supply voltage IVC is applied, respectively. Metal patterns 513 and 514 may be used as shield lines for first through fourth sensing node patterns SOa through SOd. Metal pattern 513 may also be used as a shield line for first through fourth internal signal patterns ISa through ISd.

[0097] FIG. 22 exemplarily illustrates a layout 50d of the first and third metal layers LM0 and LM2 according to one embodiment of the present invention.

[0098] 22, layout 50d corresponds to a modification of layout 50a of FIG. 19, and therefore a redundant description will be omitted. The third metal layer LM2 may include first and second sensing node patterns SOa and SOb and first through fourth internal signal patterns ISa through ISd. The first and second sensing node patterns SOa and SOb and the first through fourth internal signal patterns ISa through ISd may be alternately arranged. The following describes patterns arranged on multiple tracks of the third metal layer LM3. For example, the first internal signal pattern ISa may be arranged on the first track, the first sensing node pattern SOa may be arranged on the second track, the second internal signal pattern ISb may be arranged on the second and third tracks, the third internal signal pattern ISc may be arranged on the fourth track, the second sensing node pattern SOb may be arranged on the fifth track, and the fourth internal signal pattern ISd may be arranged on the sixth track.

[0099] FIG. 23 shows in detail the page buffer PB″ according to one embodiment of the present invention.

[0100] Referring to FIG. 23, a page buffer PB″ corresponds to a modified version of the page buffer PB illustrated in FIG. 5, and the contents described above regarding the page buffer PB may also be applied to this embodiment. The page buffer PB″ may further include a dynamic latch DL compared to the page buffer PB. Also, in some embodiments, the page buffer PB″ may include one pass transistor TR″ instead of the pass transistors TR and TR′ as illustrated in FIG. 8.

[0101] The dynamic latch DL may include first to third transistors NM11, NM12, and NM13. The first transistor NM11 may be arranged between the sensing node SO and a dynamic node D, the second transistor NM12 may be arranged between the dynamic node D and a ground terminal, and the third transistor NM13 may be arranged between the sensing latch SL and a gate of the second transistor NM12. The first transistor NM11 may be driven by a monitor signal MON_D, and the third transistor NM13 may be driven by a set signal SET_D.

[0102] FIG. 24 shows in detail the page buffer PB"_1 according to one embodiment of the present invention.

[0103] Referring to FIG. 24, the page buffer PB″_1 corresponds to a modified example of the page buffer PB″ illustrated in FIG. 23, and the content described above regarding the page buffer PB″ may also be applied to this embodiment. The page buffer PB″_1 may include a dynamic latch DL′, and the dynamic latch DL′ may include first to third transistors NM11, NM12, and NM13′. In this case, the third transistor NM13′ may be disposed between the sensing node SO and the gate of the second transistor NM12.

[0104] FIG. 25 exemplarily shows a layout 60 of the third metal layer LM3 according to one embodiment of the present invention.

[0105] 25, first to fourth page buffer units 610 to 640 are arranged along a second horizontal direction HD2. For example, each of the first to fourth page buffer units 610 to 640 corresponds to page buffer unit PBU" in FIG. 23 or page buffer unit PBU"_1 in FIG. 24. A third metal layer LM2 may include metal patterns 611, 612, 613, 614, 621, 622, 623, 624, 631, 632, 633, 634, and 635, and may be arranged above the first to fourth page buffer units 610 to 640 in the vertical direction VD.

[0106] Metal patterns 611 through 614 correspond to first through fourth sensing nodes SO0 through SO3, respectively, and metal patterns 621 through 624 correspond to first through fourth dynamic nodes D_0 through D_3, respectively. In this case, first sensing node SO0 and first dynamic node D_0 may be coupled to a transistor included in first page buffer unit 610, for example, first transistor NM11 of FIG. 23 or 24. Similarly, second sensing node SO1 and second dynamic node D_1 may be coupled to a transistor included in second page buffer unit 620, third sensing node SO2 and third dynamic node D_2 may be coupled to a transistor included in third page buffer unit 630, and fourth sensing node SO3 and fourth dynamic node D_3 may be coupled to a transistor included in fourth page buffer unit 640.

[0107] For example, metal patterns 611 and 621 may be arranged in a line along a first horizontal direction HD1, metal patterns 612 and 622 may be arranged in a line along the first horizontal direction HD1, metal patterns 613 and 623 may be arranged in a line along the first horizontal direction HD1, and metal patterns 614 and 624 may be arranged in a line along the first horizontal direction HD1. An internal power supply voltage IVC may be applied to metal patterns 631 and 634, and a ground voltage GND may be applied to metal patterns 632 and 635. A first page buffer driver signal PBDRV may be applied to metal pattern 633 and may be connected to, for example, a column driver.

[0108] FIG. 26 exemplarily shows a layout 60a of the third metal layer LM3 according to one embodiment of the present invention.

[0109] 26, first to fourth page buffer units 610a to 640a are arranged along a second horizontal direction HD2. For example, the first to fourth page buffer units 610a to 640a correspond to page buffer unit PBU" in FIG. 23 or page buffer unit PBU"_1 in FIG. 24, respectively. The third metal layer LM2 may include metal patterns 611a, 612a, 613a, 614a, 621a, 622a, 623a, 624a, 631a, 632a, 633a, and 634a, and may be arranged above the first to fourth page buffer units 610a to 640a in the vertical direction VD.

[0110] Metal patterns 611a through 614a correspond to first through fourth sensing nodes SO0 through SO3, respectively, and metal patterns 621a through 624a correspond to first through fourth dynamic nodes D_0 through D_3, respectively. For example, metal patterns 611a, 612a, 621a, and 622a may be arranged in a row along a first horizontal direction HD1, and metal patterns 613a, 614a, 623a, and 624a may be arranged in a row along the first horizontal direction HD1. An internal power supply voltage IVC may be applied to metal patterns 631a and 634a, and a ground voltage GND may be applied to metal pattern 632a. A first page buffer driver signal PBDRV may be applied to metal pattern 633a and may be connected to, for example, a column driver.

[0111] FIG. 27 exemplarily shows a layout 60b of the third metal layer LM3 according to one embodiment of the present invention.

[0112] 27, first through fourth page buffer units 610b through 640b are arranged along a second horizontal direction HD2. For example, the first through fourth page buffer units 610b through 640b correspond to page buffer unit PBU" in FIG. 23 or page buffer unit PBU"_1 in FIG. 24. The third metal layer LM2 may include metal patterns 611b, 612b, 613b, 614b, 621b, 622b, 623b, 624b, 631b, 632b, 633b, 634b, and 635b, and may be arranged above the first through fourth page buffer units 610b through 640b in the vertical direction VD.

[0113] Metal patterns 611b through 614b correspond to first through fourth sensing nodes SO0 through SO3, respectively, and metal patterns 621b through 624b correspond to first through fourth dynamic nodes D_0 through D_3, respectively. For example, metal patterns 611b and 621b may be arranged in a row along a first horizontal direction HD1, metal patterns 612b and 622b may be arranged in a row along the first horizontal direction HD1, metal patterns 613b and 623b may be arranged in a row along the first horizontal direction HD1, and metal patterns 614b and 624b may be arranged in a row along the first horizontal direction HD1. An internal power supply voltage IVC may be applied to metal patterns 631b and 634b, and a ground voltage GND may be applied to metal patterns 632b and 635b. A first page buffer driver signal PBDRV may be applied to metal pattern 633b and may be connected to, for example, a column driver.

[0114] FIG. 28 exemplarily illustrates a layout 60c of the third metal layer LM3 according to one embodiment of the present invention.

[0115] Referring to FIG. 28, first through fourth page buffer units 610c through 640c are arranged along a second horizontal direction HD2. For example, the first through fourth page buffer units 610c through 640c correspond to page buffer unit PBU″ in FIG. 23 or page buffer unit PBU″_1 in FIG. 24, respectively. The third metal layer LM3 may include metal patterns 611a through 634a and may be arranged above the first through fourth page buffer units 610c through 640c in the vertical direction VD.

[0116] Metal patterns 611a through 614a correspond to first through fourth sensing nodes SO0 through SO3, respectively, and metal patterns 621c through 624c correspond to first through fourth dynamic nodes D_0 through D_3, respectively. For example, metal patterns 611a, 612a, 621c, and 622c may be arranged in a row along a first horizontal direction HD1, and metal patterns 613a, 614a, 623c, and 624c may be arranged in a row along the first horizontal direction HD1. An internal power supply voltage IVC may be applied to metal patterns 631a and 634a, and a ground voltage GND may be applied to metal pattern 632a. A first page buffer driver signal PBDRV may be applied to metal pattern 633a and may be connected to, for example, a column driver.

[0117] FIG. 29 is a cross-sectional view of a memory device 900 according to one embodiment of the present invention.

[0118] Referring to FIG. 29, the memory device 900 may also have a C2C (Chip-to-Chip) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method refers to electrically connecting a bonding metal formed on a top metal layer of the upper chip to a bonding metal formed on a top metal layer of the lower chip. For example, if the bonding metal is formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten. The embodiments illustrated in FIGS. 1 through 27 may be implemented in the memory device 900. For example, the page buffer circuit described above with reference to FIGS. 1 through 27 may be disposed in the peripheral circuit region PERI.

[0119] The peripheral circuit region PERI and the cell region CELL of the memory device 900 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA. The peripheral circuit region PERI may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c connected to the plurality of circuit elements 720a, 720b, and 720c, respectively, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In one embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, which has a relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper, which has a relatively low resistance.

[0120] Although only first metal layers 730a, 730b, and 730c and second metal layers 740a, 740b, and 740c are illustrated and described herein, the present invention is not limited thereto, and at least one more metal layer may be formed on the second metal layers 740a, 740b, and 740c. At least some of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum, which has a lower resistance than copper, which forms the second metal layers 740a, 740b, and 740c.

[0121] The interlayer insulating layer 715 is disposed on the first substrate 710 to cover the plurality of circuit elements 720a, 720b, 720c, the first metal layers 730a, 730b, 730c, and the second metal layers 740a, 740b, 740c, and may include an insulating material such as silicon oxide or silicon nitride.

[0122] Lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region PERI are electrically connected to the upper bonding metals 871b and 872b in the cell region CELL by bonding, and the lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b may be formed of aluminum, copper, or tungsten. The upper bonding metals 871b and 872b in the cell region CELL are referred to as first metal pads, and the lower bonding metals 771b and 772b in the peripheral circuit region PERI are referred to as second metal pads.

[0123] The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 810 and a common source line 820. A plurality of word lines 831 to 838 (830) may be stacked on the second substrate 810 along a vertical direction VD on the upper surface of the second substrate 810. A string select line and a ground select line may be disposed above and below the word lines 830, respectively, and a plurality of word lines 830 may be disposed between the string select line and the ground select line.

[0124] In the bit line bonding region BLBA, the channel structure CH may extend vertically above the top surface of the second substrate 810 and penetrate the word lines 830, the string select lines, and the ground select lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may also serve as a bit line contact, and the second metal layer 860c may also serve as a bit line. In one embodiment, the bit line 860c extends along a first horizontal direction HD1 parallel to the top surface of the second substrate 810.

[0125] 29, a region in which the channel structure CH and the bit line 860c are disposed may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 860c may be electrically connected to a circuit element 720c that provides a page buffer 893 in the peripheral circuit region PERI. For example, the bit line 860c may be connected to upper bonding metals 871c and 872c in the peripheral circuit region PERI, and the upper bonding metals 871c and 872c may be connected to lower bonding metals 771c and 772c that are connected to the circuit element 720c of the page buffer 893.

[0126] In the word line bonding region WLBA, the word lines 830 may extend along a second horizontal direction HD2 parallel to the top surface of the second substrate 810 and may be connected to a plurality of cell contact plugs 841-847 (840). The word lines 830 and the cell contact plugs 840 may be connected to each other at pads, at least some of which extend to different lengths along the second horizontal direction. A first metal layer 850b and a second metal layer 860b may be sequentially connected to the top of the cell contact plug 840 connected to the word line 830. The cell contact plug 840 may be connected to the peripheral circuit region PERI in the word line bonding region WLBA through upper bonding metals 871b and 872b of the cell region CELL and lower bonding metals 771b and 772b of the peripheral circuit region PERI.

[0127] The cell contact plug 840 may be electrically coupled to a circuit element 720b that provides a row decoder 894 in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 720b that provides the row decoder 894 is also different from the operating voltage of the circuit element 720c that provides the page buffer 893. For example, the operating voltage of the circuit element 720c that provides the page buffer 893 is higher than the operating voltage of the circuit element 720b that provides the row decoder 894.

[0128] A common source line contact plug 880 may be disposed in the external pad bonding region PA. The common source line contact plug 880 may be formed of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to the common source line 820. A first metal layer 850a and a second metal layer 860a may be sequentially stacked on the common source line contact plug 880. For example, the region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed may be defined as the external pad bonding region PA.

[0129] 29, a lower insulating film 701 covering the lower surface of the first substrate 710 may be formed under the first substrate 710, and a first I / O pad 705 may be formed on the lower insulating film 701. The first I / O pad 705 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a first I / O contact plug 703 and may be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film may be disposed between the first I / O contact plug 703 and the first substrate 710 to electrically separate the first I / O contact plug 703 from the first substrate 710.

[0130] 29, an upper insulating film 801 covering the upper surface of the second substrate 810 may be formed on the upper surface of the second substrate 810, and a second I / O pad 805 may be disposed on the upper insulating film 801. The second I / O pad 805 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a second I / O contact plug 803.

[0131] According to the embodiment, the second substrate 810 and the common source line 820 are not disposed in the region where the second I / O contact plug 803 is disposed. In addition, the second I / O pad 805 does not overlap with the word line 830 in the third direction (Z-axis direction). Referring to FIG. 29, the second I / O contact plug 803 is separated from the second substrate 810 in a direction parallel to the top surface of the second substrate 810 and may be connected to the second I / O pad 805 by penetrating the interlayer insulating layer 815 of the cell region CELL.

[0132] Depending on the embodiment, the first I / O pad 705 and the second I / O pad 805 may be selectively formed. For example, the memory device 800 may include only the first I / O pad 705 disposed on the top of the first substrate 710, or only the second I / O pad 805 disposed on the top of the second substrate 810. Alternatively, the memory device 800 may include both the first I / O pad 705 and the second I / O pad 805.

[0133] In the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, respectively, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0134] In the memory device 800, a lower metal pattern 773a having the same shape as the upper metal pattern 872a of the cell region CELL may be formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the upper metal layer of the cell region CELL in the external pad bonding region PA, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0135] Lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region PERI may be electrically connected to the upper bonding metals 871b and 872b in the cell region CELL by bonding.

[0136] In addition, in the bit line bonding region BLBA, an upper metal pattern 892 having the same shape as the lower metal pattern 752 in the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL in correspondence with the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0137] FIG. 30 is a block diagram illustrating an example in which a memory device according to some embodiments of the present invention is applied to an SSD system.

[0138] 30, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 transmits and receives signals to and from the host 1100 through a signal connector and receives power through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may also be vertically stacked NAND flash memory devices. In this case, the SSD 1200 may be implemented using the embodiments described above with reference to FIGS. 1 to 29.

[0139] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, these terms are merely used to describe the technical spirit of the present invention and are not intended to limit the meaning or scope of the present invention as described in the claims. Therefore, a person skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims.

Claims

1. a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array, arranged in a page buffer area including a main area and a cache area arranged in a first horizontal direction, the page buffer circuit including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main area; The first page buffer unit a first bit line selection transistor connected to the first bit line; a first sensing node configured to be connected to the first bit line selection transistor; a first pass transistor connected to the first sensing node; a second bit line selection transistor connected to the second bit line; a second sensing node configured to be connected to the second bit line selection transistor, the second page buffer unit including the second sensing node; a second pass transistor coupled to the second sensing node; The first sensing node a first lower metal pattern provided in a lower metal layer and electrically connected to the first pass transistor; a first upper metal pattern provided in an upper metal layer disposed vertically above the lower metal layer and electrically connected to the first lower metal pattern; The second sensing node a second lower metal pattern provided in the lower metal layer and electrically connected to the second pass transistor; a second upper metal pattern provided in the upper metal layer, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction;

2. The page buffer circuit includes:

2. The memory device of claim 1, further comprising: a first cache latch and a second cache latch provided in the cache area, connected to the first page buffer unit and the second page buffer unit, respectively, and adjacent to each other in the second horizontal direction.

3. 3. The memory device of claim 1, wherein the first and second lower metal patterns extend in the same direction as the first and second upper metal patterns.

4. A memory device as described in Claim 3, characterized in that the extension direction of the first and second bit lines is the same as the extension direction of the first and second lower metal patterns and the first and second upper metal patterns.

5. The upper metal layer is a first power supply pattern provided on an upper portion of the first page buffer unit; the first upper metal pattern provided on the first page buffer unit and adjacent to the first power supply pattern in the second horizontal direction; the second upper metal pattern provided on an upper portion of the second page buffer unit; 5. The memory device of claim 1, further comprising: a second power supply pattern provided above the second page buffer unit and adjacent to the second upper metal pattern in the second horizontal direction.

6. The upper metal layer is an internal signal pattern provided on an upper portion of the first page buffer unit; a first power supply pattern provided above the first page buffer unit and adjacent to the internal signal pattern in the second horizontal direction; 5. The memory device of claim 1, further comprising: the first upper metal pattern and the second upper metal pattern provided on an upper portion of the second page buffer unit.

7. The upper metal layer is a first power supply pattern provided on an upper portion of the first page buffer unit; a second power supply pattern provided on an upper portion of the second page buffer unit; 5. The memory device of claim 1, further comprising: the first upper metal pattern and the second upper metal pattern arranged in the first horizontal direction between the first power supply pattern and the second power supply pattern.

8. The upper metal layer is an internal signal pattern provided on an upper portion of the first page buffer unit; the first upper metal pattern and the second upper metal pattern arranged in the first horizontal direction above the second page buffer unit; 5. The memory device of claim 1, further comprising: a power supply pattern provided between the internal signal pattern and the first and second upper metal patterns.

9. The upper metal layer is a first power supply pattern; the first upper metal pattern adjacent to the first power supply pattern in the second horizontal direction; a second power supply pattern adjacent to the first upper metal pattern in the second horizontal direction; the second upper metal pattern adjacent to the second power supply pattern in the second horizontal direction; a third power supply pattern adjacent to the second upper metal pattern in the second horizontal direction, 5. The memory device of claim 1, wherein the first, second, and third power supply patterns and the first and second upper metal patterns extend in the first horizontal direction.

10. The upper metal layer is a first internal signal pattern on a first track; the first upper metal pattern on a second track; a second internal signal pattern on a third track; and a third internal signal pattern on a fourth track; and the second upper metal pattern on a fifth track; 5. The memory device of claim 1, wherein the first to third internal signal patterns and the first and second upper metal patterns extend in the first horizontal direction, and the first to fifth tracks are positioned in this order spaced apart in the second horizontal direction.

11. The upper metal layer is a first power supply pattern on the first track; a second power supply pattern on the third track; 11. The memory device of claim 10, wherein the first power supply pattern, the first upper metal pattern, and the second power supply pattern are adjacent to each other in the second horizontal direction.

12. The first and second lower metal patterns are 12. The memory device of claim 1, wherein the cells are not adjacent to each other in the second horizontal direction.

13. The lower metal layer is a first power supply pattern; the first lower metal pattern adjacent to the first power supply pattern in the second horizontal direction; the second lower metal pattern; a second power supply pattern between the first lower metal pattern and the second lower metal pattern, 2. The memory device of claim 1, wherein the first and second power supply patterns and the first and second lower metal patterns extend in the first horizontal direction.

14. the first page buffer unit includes a first dynamic latch connected to the first sensing node; the second page buffer unit includes a second dynamic latch connected to the second sensing node; The first dynamic latch includes a first dynamic node, and the second dynamic latch includes a second dynamic node, the first dynamic node being: a third lower metal pattern provided in the lower metal layer; a third upper metal pattern provided in the upper metal layer and electrically connected to the third lower metal pattern; The second dynamic node a fourth lower metal pattern provided in the lower metal layer; 10. The memory device of claim 1, further comprising: a fourth upper metal pattern provided in the upper metal layer and electrically connected to the fourth lower metal pattern.

15. the first upper metal pattern and the third upper metal pattern are arranged in the first horizontal direction, the second upper metal pattern and the fourth upper metal pattern are arranged in the first horizontal direction, 15. The memory device of claim 14, wherein the third upper metal pattern and the fourth upper metal pattern are not adjacent to each other in the second horizontal direction.

16. 15. The memory device of claim 14, wherein the first through fourth upper metal patterns are arranged in the first horizontal direction.

17. the first upper metal pattern and the third upper metal pattern are arranged in the first horizontal direction, the second upper metal pattern and the fourth upper metal pattern are arranged in the first horizontal direction, 15. The memory device of claim 14, wherein the third upper metal pattern and the fourth upper metal pattern are adjacent to each other in the second horizontal direction.

18. a first semiconductor layer including a plurality of memory cells respectively connected to a plurality of bit lines extending in a first horizontal direction; a second semiconductor layer provided perpendicular to the first semiconductor layer and including a plurality of page buffers; the plurality of page buffers include a first page buffer unit and a second page buffer unit; The first page buffer unit a first bit line selection transistor connected to the first bit line; a first sensing node configured to be connected to the first bit line selection transistor; a first pass transistor connected to the first sensing node; a second bit line selection transistor connected to the second bit line; a second sensing node configured to be connected to the second bit line selection transistor, the second page buffer unit including the second sensing node; a second pass transistor coupled to the second sensing node; The first sensing node a first lower metal pattern provided in a lower metal layer and electrically connected to the first pass transistor; a first upper metal pattern provided in an upper metal layer disposed above the lower metal layer in the vertical direction and electrically connected to the first lower metal pattern; The second sensing node a second lower metal pattern provided in the lower metal layer and electrically connected to the second pass transistor; a second upper metal pattern provided on the upper metal layer, the second page buffer unit is provided adjacent to the first page buffer unit in a second horizontal direction, The memory device, wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

19. The plurality of page buffers include: a first page buffer unit provided along the first horizontal direction in the main region of the second semiconductor layer; a second page buffer unit provided in the main region of the second semiconductor layer along the first horizontal direction and adjacent to the first page buffer unit in the second horizontal direction; first cache latches provided in the cache region of the second semiconductor layer along the first horizontal direction and corresponding to the first page buffer units, respectively; second cache latches provided along the first horizontal direction in the cache region of the second semiconductor layer, adjacent to the first cache latches in the second horizontal direction, and corresponding to the second page buffer units, respectively; 20. The memory device of claim 18, wherein the main area and the cache area are adjacent to each other in the first horizontal direction.

20. a memory cell region including a plurality of memory cells and a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region through the first metal pad and the second metal pad; the peripheral circuit region includes a plurality of page buffers; the plurality of page buffers include a first page buffer unit and a second page buffer unit; The first page buffer unit a first bit line selection transistor connected to the first bit line; a first sensing node configured to be connected to the first bit line selection transistor; a first pass transistor connected to the first sensing node; a second bit line selection transistor connected to the second bit line; a second sensing node configured to be connected to the second bit line selection transistor, the second page buffer unit including the second sensing node; a second pass transistor coupled to the second sensing node; The first sensing node a first lower metal pattern provided in a lower metal layer and electrically connected to the first pass transistor; a first upper metal pattern provided in an upper metal layer disposed above the lower metal layer in the vertical direction and electrically connected to the first lower metal pattern; The second sensing node a second lower metal pattern provided in the lower metal layer and electrically connected to the second pass transistor; a second upper metal pattern provided on the upper metal layer, the second page buffer unit is provided adjacent to the first page buffer unit in a second horizontal direction, The memory device, wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

Images