P-type laterally diffused metal oxide semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a P-type laterally diffused metal oxide semiconductor device includes the steps of forming an N-type buried layer (220) in a substrate (210), forming a P-type region (230) overlying the N-type buried layer (220), forming a mask layer (240) overlying the P-type region (230), patterning the mask layer (240) to form at least two implantation windows (241, 243, 245), performing N-type ion implantation through the at least two implantation windows (241, 243, 245) to form a high pressure N-well doped region (231) and a low pressure N-well doped region (233), forming an oxide layer (244), and at least one of the steps of: The method includes the steps of removing at least a portion of the mask layer (240), performing P-type ion implantation into the P-type region (230) to form a P-type doped region (234), diffusing the P-type doped region (234) by thermal annealing to form a drift region (236) and two P-type well regions (238), diffusing the high voltage N-well doped region (231) to form a high voltage N-type well region (235), diffusing the low voltage N-well doped region (233) to form a low voltage N-type well region (237), and forming a source doped region (252), a drain doped region (254), and a gate (260).

Description

[Technical Field]

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and more particularly to P-type laterally diffused metal oxide semiconductor devices, and further to a method for fabricating P-type laterally diffused metal oxide semiconductor devices. [Background technology]

[0002] This application claims priority to a Chinese patent application bearing application number 2022101816543 and entitled "P-type laterally diffused metal oxide semiconductor device and method for manufacturing the same," filed on February 25, 2022, the entire text of which is hereby incorporated by reference into this application.

[0003] High-voltage integrated circuits are an important field in power electronics. By integrating high-voltage power devices, signal processing systems, peripheral interface circuits, protection circuits, and detection circuits onto a single chip, they not only improve system reliability and stability but also reduce system power consumption, volume, weight, and cost. When the high-side circuit in a high-voltage integrated circuit is at a high potential, level shift technology is required to transmit low-voltage signals to the high-voltage section to drive the high-side power devices. A level shift circuit acts as a bridge connecting high-voltage and low-voltage circuits, boosting the low-voltage signal output by the upstream dead zone generation circuit to a high-voltage signal for use by the downstream high-voltage circuit, preventing crosstalk between the high-voltage and low-voltage signals. The LDMOS high-voltage power conversion device is a key component in level shift circuits. Its gate receives the signal from the low-side circuit and outputs the high-voltage signal through its drain, so the LDMOS must be able to withstand the voltage of the high-side circuit. Breakdown voltage is one of the important parameters for evaluating LDMOS devices. Breakdown voltage is the maximum voltage that the drain end of an LDMOS can withstand when a high voltage is applied to the drain end and the gate and source are at zero potential. If the voltage at the drain end exceeds the breakdown voltage of the device, the device will experience avalanche breakdown, and if the device remains in avalanche breakdown state for a long time, it will be burned. LDMOS has excellent switching characteristics and a high breakdown voltage, so it is widely used in high-voltage power integrated circuits.

[0004] PLDMOS is a type of LDMOS, and has the superior performance of LDMOS. PLDMOS can simplify the complexity of power integrated circuits as a high-side driver and reduce the chip area. However, unlike the manufacturing process of a typical NLDMOS, the manufacturing process flow of an exemplary PLDMOS is more complicated. Summary of the Invention [Problem to be solved by the invention]

[0005] According to some embodiments, a method for fabricating a P-type laterally diffused metal oxide semiconductor device is provided. [Means for solving the problem]

[0006] A method for fabricating a P-type laterally diffused metal oxide semiconductor device includes: forming an N-type buried layer in a substrate, forming a P-type region overlying the N-type buried layer, and forming a mask layer overlying the P-type region; patterning the mask layer to form at least two implantation windows; performing N-type ion implantation through the at least two implantation windows to form a high-voltage N-well doped region and a low-voltage N-well doped region in the P-type region, wherein a doping concentration of the low-voltage N-well doped region is higher than a doping concentration of the high-voltage N-well doped region; forming an oxide layer on a surface of the P-type region at each implantation window; removing at least a portion of the mask layer; performing P-type ion implantation into the P-type region to form a P-type doped region; diffusing the P-type doping region to form a drift region and two P-type well regions, diffusing the high-pressure N-well doping region to form a high-pressure N-type well region, and diffusing the low-pressure N-well doping region to form a low-pressure N-type well region by thermal annealing, wherein the drift region is located between the high-pressure N-type well region and the low-pressure N-type well region, and the two P-type well regions are located on both sides of the high-pressure N-type well region, respectively, and one of the P-type well regions is located between the high-pressure N-type well region and the drift region; forming a source doping region, a drain doping region, and a gate, wherein the source doping region is located in the low-voltage N-type well region, the drain doping region is located in the P-type well region and is located between the high-voltage N-type well region and the drift region, the gate is located between the source doping region and the drain doping region, and the source doping region and the drain doping region have P-type doping.

[0007] The P-type laterally diffused metal oxide semiconductor device includes a substrate, an N-type buried layer, a P-type region, a high-voltage N-type well region, a low-voltage N-type well region, a drift region and two P-type well regions, a field-effect oxide layer, a gate, a body region and a source doping region, a substrate pull-out region, and a drain doping region; the N-type buried layer is provided in the substrate, the P-type region is provided on the N-type buried layer and the substrate, the high-voltage N-type well region, the low-voltage N-type well region, the drift region, and the two P-type well regions are provided within the P-type region; the field effect oxide layer is provided on the P-type region; the gate is located on the low-voltage N-type well region and the field effect oxide layer; the body region and the source doping region are disposed within the low-voltage N-type well region, the body region is connected to a body region metal electrode, and the source doping region is located between the gate and the body region and is connected to a source metal electrode; the substrate lead-out region is provided in one of the P-type well regions and is connected to a metal electrode of the substrate lead-out region; The drain doping region is provided in the other of the P-type well regions, and is located between the high-voltage N-type well region and the drift region, and is connected to a drain metal electrode.

[0008] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0009] To better describe and explain the embodiments and / or examples of the invention disclosed herein, reference may be made to one or more drawings. Any additional details or examples used to illustrate the drawings should not be construed as limiting the scope of either the disclosed invention, the presently described embodiments and / or examples, and the currently understood best mode of such invention. [Figure 1] 1 is a flowchart illustrating a method for manufacturing a P-type laterally diffused metal oxide semiconductor device in accordance with one embodiment. [Figure 2a] FIG. 10 is a cross-sectional view showing the configuration of the device after step S120 is completed in one embodiment. [Figure 2b] FIG. 10 is a cross-sectional view showing the configuration of the device after the first step of injection in step S130 is completed in one embodiment. [Figure 2c] FIG. 10 is a cross-sectional view showing the configuration of the device after the second step of injection in step S130 is completed in one embodiment. [Figure 2d] FIG. 10 is a cross-sectional view showing the configuration of the device after step S140 is completed in one embodiment. [Figure 2e] FIG. 10 is a cross-sectional view showing the configuration of the device after step S160 is completed in one embodiment. [Figure 2f] FIG. 10 is a schematic diagram showing the configuration of a drift region, a P-type well region, a high-voltage N-type well region, and a low-voltage N-type well region after a second thermal annealing in one example. [Figure 3] 1 is a cross-sectional schematic diagram of a P-type laterally diffused metal oxide semiconductor device according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate an understanding of the present invention, the present invention will now be more fully described with reference to the accompanying drawings, in which preferred embodiments of the present invention are illustrated. However, the present invention may be embodied in many different forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein are for the purpose of describing specific examples only and are not intended to be limiting of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0012] When an element or layer is referred to as "located on," "adjacent to," "connected to," or "coupled" to another element or layer, it is understood that it may be directly located on, adjacent to, connected to, or coupled to the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is referred to as "located directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. While terms such as first, second, and third may be used to describe various elements, members, regions, layers, and / or portions, it is understood that these elements, members, regions, layers, and / or portions are not limited by these terms. These terms are used only to distinguish one element, member, region, layer, or portion from another element, member, region, layer, or portion. Thus, a first element, member, region, layer, or portion described below could be referred to as a second element, member, region, layer, or portion without departing from the teachings of the present invention.

[0013] Spatial relationship terms such as "below," "below," "below," "below," "above," "above" and the like may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures for ease of description. It should be understood that the spatial relationship terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if a device in the figures were turned over, elements or features described as "below" or "below" or "below" other elements would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both an above and below orientation. A device may be oriented differently (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "one," and "said" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the terms "consisting of" and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0015] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. Therefore, variations from the illustrated shapes due, for example, to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein and should include, for example, deviations in shape due to manufacturing. For example, an implanted region illustrated as a rectangle typically has rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary transition from implanted to non-implanted region. Similarly, buried regions formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs. Accordingly, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the present invention.

[0016] The terms used in the semiconductor field in this specification are technical terms commonly used by those skilled in the art. For example, to distinguish the doping concentration of P-type and N-type impurities, P+ type represents P-type with a high doping concentration, P-type represents P-type with a medium doping concentration, P-type represents P-type with a low doping concentration, N+ type represents N-type with a high doping concentration, N-type represents N-type with a medium doping concentration, and N-type represents N-type with a low doping concentration.

[0017] In order to simplify the manufacturing process of PLDMOS and make it compatible with the manufacturing process of NLDMOS, according to one embodiment, a method for manufacturing a P-type laterally diffused metal oxide semiconductor device is proposed. Referring to Figure 1, the method includes the following steps:

[0018] In step S110, an N-type buried layer is formed in a substrate, a P-type region located in the N-type buried layer is formed, and a mask layer located in the P-type region is formed.

[0019] Referring to FIG. 2A, in one embodiment of the present application, the substrate 210 is a semiconductor substrate, and its material can be undoped single crystal silicon, doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In the embodiment shown in FIG. 2A, the material of the substrate 210 is single crystal silicon, i.e., a P-type silicon substrate. An N-type buried layer 220 is provided in the substrate 210. A P-type region 230 is located on the N-type buried layer 220. The P-type region 230 can be formed epitaxially or non-epitaxially (for a complete substrate, a buried layer DN is implanted, and then P is implanted to form a P-doped region). The mask layer 240 is located on the P-type region 230 and includes a silicon oxide layer 246 and a silicon nitride layer 248 on the silicon oxide layer 246. Specifically, the material of the silicon oxide layer 246 may be silicon dioxide, and the material of the silicon nitride layer 248 may be silicon nitride.

[0020] In one embodiment, an N-type buried layer 220 may first be formed in a substrate 210, a P-type region 230 may then be formed on the N-type buried layer 220, and a silicon oxide layer 246 and a silicon nitride layer 248 may then be deposited on the P-type region 230 to form a mask layer 240.

[0021] In step S120, the mask layer is patterned to form at least two implantation windows.

[0022] In one embodiment, photoresist is applied to mask layer 240, and the photoresist is exposed and developed using an N-well photomask, resulting in photoresist layer 292 as shown in FIG. 2a. Next, mask layer 240 is etched using photoresist layer 292 as an etching barrier layer to remove excess mask layer 240 and form a plurality of implantation windows as shown in FIG. 2a. These implantation windows include high-voltage N-well implantation window 241 and low-voltage N-well implantation window 243, and may further include a plurality of N-type ion implantation windows 245 located between high-voltage N-well implantation window 241 and low-voltage N-well implantation window 243. Referring to FIG. 2a, in one embodiment, the spacing d between adjacent N-type ion implantation windows 245 is 1.0 to 2.0 μm, and the width w of each N-type ion implantation window 245 is 2.0 to 4.0 μm.

[0023] In one embodiment, a thin oxide layer 242 is further formed on the surface of P-type region 230 at each implantation window.

[0024] In step S130, N-type ion implantation is performed through the plurality of implantation windows to form high-voltage N-well doped regions and low-voltage N-well doped regions in the P-type region.

[0025] In one embodiment, the N-type ion implantation in step S130 is a two-step implantation. Referring to FIG. 2b, the first N-type ion implantation forms high-pressure N-well doping regions 231 in the P-type region 230 below each implantation window. Then, photoresist layer 292 is removed, photoresist is applied again, and the photoresist is exposed using a low-pressure N-well photomask. The exposed photoresist layer covers the high-pressure N-well implantation window 241 and each N-type ion implantation window, but exposes the low-pressure N-well implantation window 243. As shown in FIG. 2c, the second N-type ion implantation is performed through the low-pressure N-well implantation window 243 into the lower P-type region 230, overlapping the N-type ions implanted in the first step to form low-pressure N-well doping regions 233. In one embodiment, the dose of the N-type ion implantation in the second implantation is higher than the dose of the N-type ion implantation in the first implantation, so that the doping concentration of the low-pressure N-well doped region 233 is higher than the doping concentration of the high-pressure N-well doped region 231.

[0026] 2b, in this embodiment, the first implantation forms drift region doping adjustment regions 232 below each N-type ion implantation window 245. The N-type doped drift region doping adjustment regions 232 can adjust the doping concentration of the drift region formed in subsequent steps.

[0027] In one embodiment, the ion source for the two N-type ion implants in step S130 is phosphorus.

[0028] In step S140, an oxide layer is formed on the surface of the P-type region in each implantation window.

[0029] 2d, in one embodiment, the thin oxide layer 242 on the surface of the P-type region 230 located in each implantation window is thickened by high-temperature oxidation to form oxide layer 244. The high-temperature oxidation may be an oxygen-permeable thermal anneal or other high-temperature oxygen-permeable process. The N-type ions implanted in step S130 diffuse during the annealing process.

[0030] In step S150, at least a portion of the mask layer is removed.

[0031] In this step, a portion of the mask layer 240 is removed because subsequent P-type ion implantation will be performed at the location of the mask layer 240. In one embodiment, in step S150, the silicon nitride layer 248 in the mask layer 240 is removed, leaving the silicon oxide layer 246.

[0032] In step S160, P-type ion implantation is performed into the P-type region to form a P-type doped region.

[0033] 2e, when P-type ions are implanted into P-type region 230, oxide layer 244 blocks the P-type ions from being implanted. The P-type ions are implanted at locations covered by silicon oxide layer 246 in the previous step, forming P-type doped region 234. When the P-type ions diffuse into the areas of P-type region 230 where N-type ions were implanted, they are neutralized by the N-type ions.

[0034] In one embodiment, the ion source for the P-type ion implantation in step S160 is boron.

[0035] In step S170, thermal annealing is performed.

[0036] 2f, thermal annealing is again performed to promote diffusion of high-pressure N-well doping region 231, low-pressure N-well doping region 233, and P-type doping region 234, causing their bottoms to reach N-type buried layer 220. High-pressure N-well doping region 231 forms high-pressure N-type well region 235 after thermal annealing, and low-pressure N-well doping region 233 forms low-pressure N-type well region 237 after thermal annealing. High-pressure N-type well region 235 and low-pressure N-type well region 233 both contact N-type buried layer 220. P-type doping region 234 forms drift region 236 and two P-type well regions 238 after thermal annealing. The two P-type well regions 238 are formed on either side of high-pressure N-type well region 235, and drift region 236 is formed between P-type well region 238 and low-pressure N-type well region 237, adjacent to low-pressure N-type well region 237. Because the N-type drift region doping adjustment region 232 has been previously formed in the region where the drift region 236 is located, in the process of forming the drift region 236 after the P-type doping region 234 is thermally annealed in step S170, the N-type drift region doping adjustment region 232 neutralizes some of the P-type ions in the drift region 236, so that the doping concentration of the drift region 236 is lower than that of the P-type well region 238. Note that by making the dose of the P-type ion implantation in step S160 larger than the dose of the first N-type ion implantation in step S130, it is possible to effectively ensure that the P-type doping region 234 forms the P-type drift region 236 after the thermal annealing in step S170.

[0037] In one embodiment, the doping concentration of high-voltage N-well region 235 is lower than the doping concentration of low-voltage N-well region 237. The doping concentrations of high-voltage N-well region 235 and low-voltage N-well region 237 range from 1e 11 cm -2 ~1e 13 cm -2 is.

[0038] In one embodiment, the doping concentration range of the drift region 236 and the P-well region 238 is 1e11 cm -2 ~1e 13 cm -2 is.

[0039] In step S180, a source doping region, a drain doping region and a gate are formed.

[0040] 3, in one embodiment, a source doping region 252 is formed in the low-voltage N-type well region 237 by photolithography and ion implantation processes. A drain doping region 254 is formed in the P-type well region 238 between the high-voltage N-type well region 235 and the drift region 236 by photolithography and ion implantation processes. The source doping region 252 and the drain doping region 254 have P-type doping. Specifically, the source doping region 252 and the drain doping region 254 are P+ regions. A gate 260 is formed between the source doping region 252 and the drain doping region 254 by deposition, photolithography, and etching processes.

[0041] In one embodiment, before forming gate 260, the method further includes forming a field effect oxide layer 250 in drift region 236. Gate 260, formed of polysilicon, extends above field effect oxide layer 250 from the edge of source doping region 252 toward drain doping region 254.

[0042] In one embodiment, after step S180, the method further includes forming a source metal electrode S, a drain metal electrode D, and a gate metal electrode G. The source metal electrode S is located in the source doping region 252 and is electrically connected to the source doping region 252. The drain metal electrode D is located in the drain doping region 254 and is electrically connected to the drain doping region 254. The gate metal electrode G is located in the gate 260 and is electrically connected to the gate 260. A portion of the drain metal electrode D located above the field effect oxide layer 250 serves as a drain metal field plate, and a portion of the gate metal electrode G located above the field effect oxide layer 250 serves as a gate metal field plate.

[0043] In one embodiment, the method further includes forming a substrate pull-out region 256 and a body region 258. The substrate pull-out region 256 is formed in the P-type well region 238 on a side of the high-voltage N-type well region 235 away from the drift region 236, and the substrate pull-out region 256 has a P-type doping. The body region 258 is formed in the low-voltage N-type well region 237, and the body region 258 has an N-type doping. The source doping region 252 is located between the body region 258 and the drift region 236. In one embodiment of the present application, the substrate pull-out region 256 is a P+ region and the body region 258 is an N+ region.

[0044] In one embodiment, simultaneously with the step of forming the field effect oxide layer 250 described above, a field effect oxide layer 250 is formed on the surface of the drift region 236 between the substrate pull-out region 256 and the drain doping region 254, and a field effect oxide layer 250 is formed on the surface of the drift region 236 on both sides of the body region 258.

[0045] According to the above-mentioned method for manufacturing a P-type laterally diffused metal oxide semiconductor device, the patterned mask layer forms segmented implantation windows 245, and after N-type ion implantation, the surface of the implantation windows is covered with an oxide layer 244, so that the oxide layer 244 can serve as a barrier layer during the subsequent P-type ion implantation. Therefore, the P-type ion implantation does not require a separate photomask, and the manufacturing process of a PLDMOS device can be effectively simplified and made compatible with the manufacturing process of an NLDMOS.

[0046] According to one embodiment, there is further provided a P-type laterally diffused metal oxide semiconductor device (PLDMOS) applicable to high-voltage integrated circuits with a breakdown voltage of 600V. The PLDMOS can be manufactured by the method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to any of the above embodiments. Referring to FIG. 3 , the PLDMOS includes a P-type substrate 210, an N-type buried layer 220 provided within the substrate 210, and a P-type region provided on the N-type buried layer 220 and the substrate 210. A high-voltage N-type well region 235, a low-voltage N-type well region 237, a P-type doped drift region 236, and a P-type well region 238 are provided within the P-type region. A field-effect oxide layer 250 is provided on the P-type region, and a gate 260, specifically a polysilicon gate, is provided on the field-effect oxide layer 250, and the gate 260 is located above the low-voltage N-type well region 237 and the field-effect oxide layer 250. The low-voltage N-type well region 237 is provided with a cathode N-type heavily doped region (referred to as body region 258) and a cathode P-type heavily doped region (referred to as source doped region 252), with the body region 258 connected to the body region's metal electrode Bulk. The source doped region 252 is located between the gate 260 and the body region 258 and connected to the source metal electrode S. The P-type well region 238 is provided with an anode P-type heavily doped region (referred to as substrate pull-out region 256), with the substrate pull-out region 256 connected to the substrate pull-out region's metal electrode Sub. The P-type well region 238 is provided with an anode P-type heavily doped region (referred to as drain doped region 254), with the drain doped region 254 located between the high-voltage N-type well region 235 and the drift region 236 and connected to the drain metal electrode D.

[0047] 3, a first side of the drain front metal layer (i.e., drain metal electrode D) is located above the field-effect oxide layer 250 between the drain doping region 254 and the substrate pull-out region 256, and a second side is located above the field-effect oxide layer 250 on the drift region 236 and extends toward the drift region 236 to form a drain metal field plate. A first side of the gate front metal layer (i.e., gate metal electrode G) is located above the field-effect oxide layer 250 on the drift region 236, and a second side is located above the gate 260, and a first side is extended above the drift region 236 to form a gate metal field plate.

[0048] Although the various steps in the flowcharts of the present application are shown sequentially, as indicated by the arrows, it should be understood that these steps are not necessarily performed sequentially in the order indicated by the arrows. Unless explicitly stated herein, these steps do not have a strict order of execution and may be performed in other orders. Furthermore, at least some of the steps in the flowcharts of the present application may include multiple steps or multiple stages, which are not necessarily performed simultaneously but may be performed at different times, and which are not necessarily performed sequentially but may be performed in order or alternating with other steps or at least some of the steps or stages in other steps.

[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described, but as long as there is no contradiction between the combinations of these technical features, they should all be considered within the scope of the present specification.

[0050] The above examples only show some embodiments of the present application, and the descriptions are more specific and detailed, but this should not be understood as limiting the scope of protection of the patent. It should be noted that a person skilled in the art can make many modifications and improvements without departing from the concept of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application should be determined based on the scope of the appended claims.

Claims

1. forming an N-type buried layer in a substrate, forming a P-type region overlying the N-type buried layer, and forming a mask layer overlying the P-type region; patterning the mask layer to form at least two implantation windows; performing N-type ion implantation through the at least two implantation windows to form a high-voltage N-well doped region and a low-voltage N-well doped region in the P-type region, the low-voltage N-well doped region having a higher doping concentration than the high-voltage N-well doped region; forming an oxide layer on a surface of the P-type region at each of the implantation windows; removing at least a portion of the mask layer; performing P-type ion implantation into the P-type region to form a P-type doped region; diffusing the P-type doping region to form a drift region and two P-type well regions, diffusing the high-pressure N-well doping region to form a high-pressure N-type well region, and diffusing the low-pressure N-well doping region to form a low-pressure N-type well region by thermal annealing, wherein the drift region is located between the high-pressure N-type well region and the low-pressure N-type well region, and the two P-type well regions are located on both sides of the high-pressure N-type well region, and one of the P-type well regions is located between the high-pressure N-type well region and the drift region; forming a source doped region, a drain doped region, and a gate, wherein the source doped region is located in the low-voltage N-type well region, the drain doped region is located in the P-type well region and is located between the high-voltage N-type well region and the drift region, and the gate is located between the source doped region and the drain doped region, and the source doped region and the drain doped region have P-type doping.

2. the at least two implant windows include a high-pressure N-well implant window and a low-pressure N-well implant window; performing N-type ion implantation through each of the implantation windows to form the high-voltage N-well doped region and the low-voltage N-well doped region within the P-type region; performing a first N-type ion implantation through the high-voltage N-well implantation window and the low-voltage N-well implantation window to form the high-voltage N-well doping region; forming a photoresist layer over the P-type region, covering the high-voltage N-well implant window and exposing the low-voltage N-well implant window; 2. The method of claim 1, further comprising: performing a second N-type ion implant through said low-pressure N-well implant window to form said low-pressure N-well doped region within said P-type region.

3. the at least two implantation windows further include a plurality of N-type ion implantation windows located between the high-pressure N-well implantation window and the low-pressure N-well implantation window; the first N-type ion implantation includes forming a corresponding number of N-type drift region doping adjustment regions in the P-type region through the plurality of N-type ion implantation windows; 3. The method of claim 2, wherein the photoresist layer covers the plurality of N-type ion implantation windows.

4. 4. The method of claim 3, wherein the spacing between adjacent windows of the plurality of N-type ion implantation windows is 1.0 to 2.0 μm.

5. 4. The method of claim 3, wherein the width of each N-type ion implantation window is between 2.0 and 4.0 μm.

6. 4. The method of claim 3, wherein the dose of the P-type ion implant is greater than the dose of the first N-type ion implant.

7. 2. The method of claim 1, wherein the mask layer comprises a silicon dioxide layer and a silicon nitride layer overlying the silicon dioxide layer, and wherein removing at least a portion of the mask layer comprises removing the silicon nitride layer.

8. Before forming the gate, further 2. The method of claim 1, comprising forming a field effect oxide layer on the drift region, the field effect oxide layer being located between the source doped region and the drain doped region, the gate being a polysilicon gate, and the polysilicon gate extending onto the field effect oxide layer.

9. forming a source metal electrode, a drain metal electrode, and a gate metal electrode; 9. The method of claim 8, wherein the source metal electrode is located on and electrically connected to the source doping region, the drain metal electrode is located on and electrically connected to the drain doping region, the gate metal electrode is located on and electrically connected to the gate, a portion of the drain metal electrode located above a field effect oxide layer is a drain metal field plate, and a portion of the gate metal electrode located above the field effect oxide layer is a gate metal field plate.

10. forming a substrate pull-out region, the substrate pull-out region being formed in a P-type well region on a side of the high-voltage N-type well region away from the drift region, the substrate pull-out region having P-type doping; 10. The method of claim 1, further comprising: forming a body region, the body region formed in the low-voltage N-type well region, the body region having N-type doping, and the source doped region located between the body region and the drift region.

11. The N-type ion source for the N-type ion implantation is phosphorus, and the doping concentration is 1e １１ cm －２ ~1e １３ cm －２ The P-type ion source for the P-type ion implantation is boron, and the doping concentration is 1e １１ cm －２ ~1e １３ cm －２ 2. The method of claim 1, wherein:

12. 2. The method of claim 1, wherein the doping concentration of the drift region is lower than the doping concentration of the P-type well region.

13. 2. The method of claim 1, wherein the high-voltage N-well region and the low-voltage N-well region both contact the N-type buried layer.

14. 1. A P-type laterally diffused metal oxide semiconductor device, comprising: a substrate, an N-type buried layer, a P-type region, a high-voltage N-type well region, a low-voltage N-type well region, a drift region and two P-type well regions, a field-effect oxide layer, a gate, a body region and a source doping region, a substrate pull-out region, and a drain doping region; the N-type buried layer is provided in the substrate, the P-type region is provided on the N-type buried layer and the substrate, the high-voltage N-type well region, the low-voltage N-type well region, the drift region, and the two P-type well regions are provided within the P-type region; the field effect oxide layer is provided on the P-type region; the gate is located on the low-voltage N-type well region and the field effect oxide layer; the body region and the source doping region are provided in the low-voltage N-type well region, the body region is connected to a metal electrode of the body region, the source doping region is located between the gate and the body region and is connected to a source metal electrode; the substrate lead-out region is provided in one of the P-type well regions and is connected to a metal electrode of the substrate lead-out region; a drain doping region provided in the other of the P-type well regions, the drain doping region being located between the high-voltage N-type well region and the drift region and connected to a drain metal electrode.

15. 15. The P-type laterally diffused metal oxide semiconductor device of claim 14, wherein the doping concentration of the drift region is lower than the doping concentration of the P-type well region.

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