Semiconductor device and wafer

Abstract

To provide a semiconductor device capable of being downsized.SOLUTION: A semiconductor device comprises: a substrate 10; a metal layer provided below the substrate; a semiconductor element that comprises a plurality of first electrodes provided on the substrate, respectively connected with the metal layer via through-holes 20 penetrating through the substrate, and electrically isolated from each other on the substrate, a plurality of second electrodes provided on the substrate so as to alternate with the plurality of first electrodes, and a first pad provided on the substrate and connected with the plurality of second electrodes; and a protection film provided on the substrate so as to cover the plurality of first electrodes and the plurality of second electrodes, having a first opening that exposes at least a part of the first pad and not having an opening overlapped with the plurality of first electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and wafers, for example, semiconductor devices and wafers having semiconductor elements. [Background technology]

[0002] A technique is known in which a through hole is formed in a substrate and one of the electrodes of a semiconductor element formed on the substrate is connected to a metal layer on the underside of the substrate via the through hole in the substrate (for example, Patent Document 1).It is also known to measure the characteristics of a semiconductor element formed on a wafer by contacting a needle from above with the semiconductor element (for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2020-17647 [Patent Document 2] Patent Publication No. 2018-146444 Summary of the Invention [Problem to be solved by the invention]

[0004] When measuring the characteristics of semiconductor elements in wafer form, needles for applying bias or signals are placed in contact with pads on the wafer surface that are connected to multiple electrodes of the semiconductor element. This requires providing pads on the wafer surface for contacting the needles with the electrodes, as well as pads for applying bias or signals that are connected to the metal layer on the underside of the substrate via through-holes. This results in larger chips.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device and wafer that can be miniaturized. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a semiconductor element including a substrate; a metal layer provided below the substrate; a plurality of first electrodes provided on the substrate, each connected to the metal layer via a through hole penetrating the substrate and electrically isolated from each other on the substrate; a plurality of second electrodes provided on the substrate and arranged alternately with the plurality of first electrodes; and a first pad provided on the substrate to which the plurality of second electrodes are connected; and a protective film provided on the substrate to cover the plurality of first electrodes and the plurality of second electrodes, having a first opening exposing at least a portion of the first pad, and having no openings overlapping the plurality of first electrodes.

[0007] One embodiment of the present disclosure is a wafer comprising: a substrate having a plurality of regions in which a plurality of chips are to be formed, a first metal layer provided below the substrate, a plurality of first electrodes each connected to the first metal layer via a first through hole penetrating the substrate and electrically isolated from one another on the substrate, a plurality of second electrodes provided alternately with the plurality of first electrodes, and pads to which the plurality of second electrodes are connected; a plurality of semiconductor elements provided on the substrate in the plurality of regions corresponding to each other; a second metal layer provided on the substrate outside the plurality of regions and electrically connected to the first metal layer via a second through hole penetrating the substrate; and a protective film covering the plurality of first electrodes and the plurality of second electrodes and not covering at least a portion of the pads and at least a portion of the second metal layer. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a semiconductor device and a wafer that can be miniaturized. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line BB in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along CC in FIG. [Figure 5] FIG. 5 is a plan view of a wafer according to the first embodiment. [Figure 6] FIG. 6 is an enlarged plan view of the vicinity of the metal layer 34 of the wafer in Example 1. As shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view of a wafer in Example 1. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8C] FIG. 8C is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8D] FIG. 8D is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a plan view illustrating a method for measuring the semiconductor device in the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line AA in FIG. [Figure 11] FIG. 11 is an enlarged plan view of the vicinity of the wafer in FIG. [Figure 12] FIG. 12 is a plan view of a semiconductor device according to a first comparative example. [Figure 13] FIG. 13 is a plan view of a semiconductor device according to a second comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] [Details of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including: a substrate; a metal layer provided below the substrate; a plurality of first electrodes provided on the substrate, each connected to the metal layer via a through-hole penetrating the substrate and electrically isolated from one another on the substrate; a plurality of second electrodes provided on the substrate and arranged alternately with the plurality of first electrodes; and a first pad provided on the substrate and connected to the plurality of second electrodes; and a protective film provided on the substrate to cover the plurality of first electrodes and the plurality of second electrodes, the protective film having first openings exposing at least a portion of the first pads but no openings overlapping the plurality of first electrodes, which enables miniaturization. (2) It is preferable that a needle mark is provided on the upper surface of the first pad within the first opening, and that no needle mark is provided on the upper surface of the first electrode. (3) Preferably, the semiconductor element comprises a plurality of gate fingers provided on the substrate and a second pad to which the plurality of gate fingers are connected, the plurality of first electrodes being a plurality of source fingers, the plurality of second electrodes being a plurality of drain fingers, the plurality of gate fingers being sandwiched between one of the plurality of source fingers and one of the plurality of drain fingers, and the protective film covering the plurality of gate fingers and having a second opening exposing at least a portion of the second pad. (4) It is preferable that a needle mark is provided on the upper surface of the second pad within the second opening. (5) The plurality of first electrodes preferably includes three or more first electrodes. (6) One embodiment of the present disclosure is a wafer comprising: a substrate having a plurality of regions in which a plurality of chips are to be formed, a first metal layer provided under the substrate, a plurality of first electrodes connected to the first metal layer via first through-holes penetrating the substrate and electrically isolated from one another on the substrate, a plurality of second electrodes provided alternately with the first electrodes, and pads to which the second electrodes are connected, a plurality of semiconductor elements provided on the substrate in the plurality of regions corresponding to each other, a second metal layer provided on the substrate outside the plurality of regions and electrically connected to the first metal layer via second through-holes penetrating the substrate, and a protective film covering the plurality of first electrodes and the plurality of second electrodes but not covering at least a portion of the pads and at least a portion of the second metal layer, thereby enabling miniaturization. (7) The second metal layer is preferably provided in the peripheral region of the wafer.

[0012] Specific examples of semiconductor devices and wafers according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] [Example 1] Fig. 1 is a plan view of a semiconductor device according to Example 1. Fig. 2 to Fig. 4 are cross-sectional views taken along lines AA to CC in Fig. 1, respectively. The normal direction to the top surface of substrate 10 is defined as the Z direction, the extension direction of each finger as the Y direction, and the width direction of each finger as the X direction.

[0014] 1 to 4, in the semiconductor device 100, a transistor 40 is provided on a substrate 10. The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. A region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region, and a region that has not been inactivated is an active region 11. A metal layer 22 is provided on the lower surface of the substrate 10.

[0015] The transistor 40 is a multi-finger FET (Field Effect Transistor) and mainly includes a plurality of source fingers 12, a plurality of drain fingers 14, a plurality of gate fingers 16, a drain pad 15, and a gate pad 17 provided on a substrate 10. The source fingers 12 and the drain fingers 14 are arranged alternately in the X direction on the substrate 10. The gate fingers 16 are provided between the source fingers 12 and the drain fingers 14 in the X direction. The source fingers 12 are electrically connected to and short-circuited by a metal layer 22 via through-holes 20 that penetrate the substrate 10. The plurality of drain fingers 14 are commonly connected to a drain pad 15 at the +Y end. The plurality of gate fingers 16 are commonly connected to a gate pad 17 at the -Y end.

[0016] A protective film 18 is provided on the substrate 10 to cover the source fingers 12, the drain fingers 14, and the gate fingers 16. The protective film 18 has openings 19a and 19b that expose at least a portion of the drain pad 15 and at least a portion of the gate pad 17, respectively. In the measured transistor 40 in the semiconductor device 100, needle marks 25a and 25b are formed on the drain pad 15 and the gate pad 17 in the openings 19a and 19b, respectively. The needle marks 25a and 25b are marks where a needle used to measure the characteristics of the transistor came into contact with the drain pad 15 and the gate pad 17.

[0017] When the semiconductor device 100 is a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. When the semiconductor device is a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The source finger 12 and the drain finger 14 are metal films, for example, an adhesion film (e.g., a titanium film) and an aluminum film from the substrate 10 side. The gate finger 16 is metal films, for example, an adhesion film (e.g., a nickel film) and a gold film from the substrate 10 side. The drain pad 15 and the gate pad 17 each include the same metal film as the drain finger 14 and the gate finger 16, and a wiring layer (e.g., a gold layer) on the metal film. The metal layer 22 is, for example, an adhesion layer and a gold layer from the substrate 10 side. The protective film 18 is, for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film, or an organic insulating film such as a polyimide film.

[0018] FIG. 5 is a plan view of a wafer according to the first embodiment. As shown in FIG. 5, the planar shape of the wafer 30 is circular, and an orientation flat is provided in a part of the wafer. The size of the wafer 30 is 3 inches, 4 inches, 6 inches, or the like. The area within a predetermined distance from the outer periphery of the wafer 30 is a non-effective area 33. 。 The width of the non-effective area 33 is, for example, 1 mm to 5 mm. The area inside the non-effective area 33 is the effective area 31. The effective area 31 is the area where transistors 40 are formed. The characteristics of transistors 40 formed in the non-effective area 33 cannot be guaranteed and therefore are not shipped. A plurality of chip areas 32, in which a plurality of transistors 40 should be formed respectively, are arranged in a matrix in the X and Y directions. The size of the chip areas 32 is, for example, 0.5 mm to 10 mm. A metal layer 34 is provided in the non-effective area 33 on the periphery of the wafer 30. Three metal layers 34 are provided at approximately equal intervals along the circumference of the wafer. The number of metal layers 34 may be one or more.

[0019] FIG. 6 is an enlarged plan view of the vicinity of the metal layer 34 of the wafer in Example 1. FIG. 7 is a cross-sectional view of the wafer in Example 1. FIG. 7 shows the chip region 32 and the non-effective region 33 in which the metal layer 34 is provided. As shown in FIGS. 6 and 7, through-holes 21 penetrating the substrate 10 are provided in the non-effective region 33. A plurality of through-holes 21 are provided. The number of through-holes 21 is appropriately set depending on the magnitude of the current that flows when measuring the characteristics of the transistor 40, which will be described later. The metal layer 34 is electrically connected to and short-circuited with the metal layer 22 via the through-holes 21. The metal layer 34 and the source fingers 12 of the transistor 40 are electrically connected to and short-circuited with each other via the metal layer 22. The protective film 18 has an opening 19c, and the metal layer 34 is exposed through the opening 19c. The metal layer 34 is, for example, a gold layer.

[0020] [Manufacturing method of Example 1] 8A to 8D are cross-sectional views showing a manufacturing method of the semiconductor device according to the first embodiment. As shown in FIG. 8A, in the chip region 32, the source fingers 12, the drain fingers 14, and the gate fingers 16 are formed on the substrate 10 by, for example, vacuum deposition and lift-off. At this time, a metal layer may be formed partially for the drain pad 15 and the gate pad 17. This completes the transistor 40. The thickness of the substrate 10 is, for example, 500 μm.

[0021] As shown in FIG. 8B , a metal layer 34 is formed in the non-effective region 33 by, for example, electrolytic plating. The metal layer 34 functions as an electrode that supplies current when forming wiring layers (e.g., drain pads 15 and gate pads 17) in the chip region 32 by electrolytic plating. The metal layer 34 and wiring layers are formed as follows: First, a seed metal layer is formed over the entire surface of the wafer 30. The seed metal layer is, for example, an adhesion layer and a low-resistance layer (e.g., a gold layer) from the substrate 10 side. A patterned mask layer (e.g., a photoresist layer) is formed on the seed metal layer. At this time, the mask layer is not formed in the region where the metal layer 34 and wiring layer are to be formed. A current is supplied to the seed metal layer from the region where the metal layer 34 is to be formed, thereby forming a plating layer on the seed metal layer where the mask layer is not formed. The seed metal layer is etched using the plating layer as a mask. This forms the metal layer 34 and wiring layer. A protective film 18 is formed on the substrate 10 to cover the source fingers 12, drain fingers 14, gate fingers 16, and metal layer 34. Openings 19a to 19c are formed in the protective film 18.

[0022] As shown in FIG. 8C, the underside of substrate 10 is ground or polished. This thins substrate 10. The thickness of substrate 10 is, for example, 10 μm to 100 μm. As shown in FIG. 8D, through-holes 20 and 21 penetrating substrate 10 are formed, for example, by etching. Thereafter, metal layer 22 is formed under substrate 10 and in through-holes 20 and 21, for example, by electroplating. The thickness of metal layer 22 is, for example, 5 μm to 50 μm. This completes the wafer shown in FIG. 7.

[0023] FIG. 9 is a plan view showing a method for measuring a semiconductor device in Example 1. FIG. 10 is a cross-sectional view taken along line AA in FIG. 9. A reference potential such as ground potential is supplied to stage 35. Stage 35 adsorbs frame 36 by vacuum suction or the like. Frame 36 is a metal plate such as stainless steel, and is electrically connected to and short-circuited with stage 35. An opening 36a is formed in the center of frame 36. A sheet 37 is attached within opening 36a. Sheet 37 is, for example, an insulating resin sheet. Wafer 30 is attached to sheet 37. A metal spring 38 is in contact with the upper surface of metal layer 34 of wafer 30. Metal spring 38 is fixed to frame 36 and is electrically connected and short-circuited. As a result, a reference potential is supplied to metal layer 34 via metal spring 38, frame 36, and stage 35.

[0024] In order to improve heat dissipation from the transistors 40 in the semiconductor device 100, the wafer 30 is very thin, for example, 10 μm to 100 μm. Therefore, the wafer 30 may warp. Furthermore, if the wafer 30 is placed in direct contact with the stage 35, the wafer 30 may crack. Therefore, the wafer 30 is attached to a sheet 37, and the sheet 37 is attached to a frame 36. This prevents the wafer 30 from warping and cracking. However, when the wafer 30 is attached to the sheet 37, the metal layer 22 on the underside of the wafer 30 is not electrically connected to the stage 35. Therefore, the stage 35 is electrically connected to the metal layer 34 via the frame 36 and the metal spring 38. This allows a reference potential to be supplied from the metal layer 34 to the source fingers 12 via the through-holes 21, the metal layer 22, and the through-holes 20.

[0025] FIG. 11 is an enlarged plan view of the wafer and its vicinity in FIG. 9. As shown in FIG. 11, needles 26a and 26b are brought into contact with drain pad 15 and gate pad 17, respectively, in chip region 32a on the top surface of wafer 30. A reference potential is supplied to source finger 12 via metal layer 34 and metal layer 22, and a potential is supplied from needles 26a and 26b to drain pad 15 and gate pad 17, thereby measuring the transistor characteristics of transistor 40 in chip region 32a. Thereafter, needles 26a and 26b are lifted from the wafer surface, and stage 35 is moved. Then, needles 26a and 26b are lowered to drain pad 15 and gate pad 17, respectively, in chip region 32b, and needles 26a and 26b are brought into contact with drain pad 15 and gate pad 17, respectively. This allows the transistor characteristics of transistor 40 in chip region 32b to be measured. Similarly, chip regions 32c to 32f The characteristics of the transistor 40 are measured.

[0026] After measuring the characteristics of the transistors 40 formed in the chip region 32, the wafer 30 is cut to manufacture the semiconductor device 100 according to the first embodiment. For example, the semiconductor devices 100 are selected based on the measurement results of the transistors 40, and good semiconductor devices 100 are advanced to the next process, while bad semiconductor devices 100 are not advanced to the next process as defective products.

[0027] [Comparative Example 1] Since the wafer 30 is thin, one possible method for suppressing warpage or cracking of the wafer 30 is to measure the transistor characteristics before thinning the wafer 30. Another possible method is to attach the wafer 30 to an insulating sheet after forming the metal layer 22 and then measure the transistors 40. In these cases, needles are brought into contact with the source fingers 12 to supply a reference potential to the source fingers 12.

[0028] 12 is a plan view of a semiconductor device according to Comparative Example 1. As shown in FIG. 12, in a semiconductor device 102 according to Comparative Example 1, an opening 19d is provided in a protective film 18 on a source finger 12. When measuring transistor characteristics, a needle is brought into contact with the source finger 12 through the opening 19d. Therefore, a needle mark 25c is formed on the source finger 12 within the opening 19d. In order to bring the needle into contact with the source finger 12, the width of the opening 19d needs to be about 80 μm to 100 μm. Therefore, the width of the source finger 12 in the X direction becomes wider. 。 This increases the chip size of the semiconductor device 102. Also, if conductive foreign matter adheres to the opening 19d, there is a possibility of short-circuiting with other fingers. Furthermore, if there is a defect in the through hole 20, the metal layer 22, etc., 、 This is not reflected in the characteristics of transistor 40.

[0029] Comparative Example 2 FIG. 13 is a plan view of a semiconductor device according to a second comparative example. Figure 13 As shown in Comparative Example 2 In the semiconductor device 104 according to the present invention, the openings 19d are provided in the source fingers 12 at both ends in the X direction. This allows the width of the source fingers 12 other than those at both ends to be narrowed in the X direction, making the chip size smaller than that of Comparative Example 1. However, the needles cannot contact the source fingers 12 other than those at both ends. For this reason, wiring 13 is provided to electrically connect the source fingers 12. The wiring 13 intersects with the gate fingers 16. This increases the parasitic capacitance between the gate and source, degrading the high-frequency characteristics of the transistor 40.

[0030] The transistor 40 also includes multiple unit transistors, each with a minimum layout that operates as a transistor. Each unit transistor has one gate finger 16 sandwiched between one source finger 12 and one drain finger 14. In a layout like Comparative Example 2, the unit transistors at both ends in the X direction are not uniformly spaced apart from the unit transistors at the other ends. For example, the width of the source fingers 12 in the X direction of the unit transistors at both ends is larger than the width of the source fingers 12 of the unit transistors at the other ends. This may result in degradation of the performance of the transistor 40. In particular, in transistors that operate with high-frequency signals, the high-frequency characteristics of individual unit transistors may differ. This can easily lead to degradation of the performance of the transistor 40. To avoid this degradation in Comparative Example 2, it is preferable to provide openings 19d in the protective film 18 above all source fingers 12, as in Comparative Example 1. Comparative Example 1 results in a larger chip size.

[0031] According to the first embodiment, as shown in FIG. 5, the wafer 30 includes a plurality of transistors 40 (semiconductor elements) provided on the substrate 10 in a plurality of chip regions 32, each corresponding to the other. As shown in FIGS. 1 to 4, in the transistor 40, a plurality of source fingers 12 (first electrodes) are connected to a metal layer 22 (first metal layer) via a through hole 20 (first through hole) and are electrically isolated from one another on the substrate 10. The gate fingers 16 (second electrodes) are provided alternately with the source fingers 12. The gate pad 17 (first pad) is connected to the plurality of gate fingers 16. As shown in FIGS. 5 to 7, the metal layer 34 (second metal layer) is provided on the substrate 10 in a region other than the plurality of chip regions 32 and is electrically connected to the metal layer 22 via a through hole 21 (second through hole). The wafer 30 is prepared as shown in FIGS. 8A to 8D and 7. Thereafter, as shown in FIGS. 9 to 11, the characteristics of the transistor 40 in the chip region 32 are measured by bringing the needle 26a into contact with the gate pad 17 in at least one chip region 32 and applying a potential to the metal layer 34.

[0032] This allows the characteristics of the transistor 40 to be measured without contacting the needles with the source fingers 12. Therefore, it is not necessary to widen the source fingers 12 to allow contact with the needles, as in Comparative Example 1. This allows the semiconductor device 100 to be miniaturized. Furthermore, it is not necessary to provide the wiring 13 connecting the source fingers 12, as in Comparative Example 2. This allows the gate-source parasitic capacitance to be suppressed, improving the high-frequency characteristics of the transistor 40. Furthermore, it is possible to suppress short circuits caused by foreign matter adhering to the opening 19d. If there are defects in the through-hole 20 and the metal layer 22, these defects will be reflected in the characteristics of the transistor 40.

[0033] Before the process of measuring the characteristics of the transistor 40, the underside of the wafer 30 and part of the underside of the metal frame 36 are attached to an insulating sheet 37, as shown in FIG. 10 . The underside of the insulating sheet 37 and the area of ​​the underside of the metal frame 36 where the insulating sheet 37 is not attached are brought into contact with the stage 35. The metal frame 36 and the upper surface of the metal layer 34 are electrically connected. This allows a potential to be supplied from the stage 35 to the metal layer 34 via the metal frame 36. Alternatively, a probe such as a metal spring 38 may be fixed to the stage 35, and a potential may be supplied to the metal layer 34 without going through the metal frame 36.

[0034] In the wafer 30 manufactured using this manufacturing method, the protective film 18 covers the source fingers 12 and the gate fingers 16, but does not cover at least a part of the gate pad 17 or at least a part of the metal layer 34. This allows the needle 26b to come into contact with the gate pad 17 and a probe such as a metal spring 38 to come into contact with the metal layer 34.

[0035] 9, the metal layer 34 is provided in the peripheral region of the wafer 30. This allows a probe such as a metal spring 38 to contact the upper surface of the metal layer 34 from outside the wafer 30. Figure 5 As shown in FIG. 1, by providing the metal layer 34 in the non-effective area 33, the metal layer 34 can be provided without reducing the number of chip areas 32.

[0036] 8B, the metal layer 34 is used as an electrode for forming wiring layers such as the drain pad 15 and the gate pad 17 by electrolytic plating, thereby eliminating the step of providing the metal layer 34.

[0037] In the semiconductor device 100 manufactured using this manufacturing method, as shown in FIGS. 1 to 4, the protective film 18 has an opening 19b (first opening) that exposes at least a portion of the gate pad 17 and an opening 19a (second opening) that exposes at least a portion of the drain pad 15. This allows the needles 26a and 26b to come into contact with the drain pad 15 and the gate pad 17, respectively. Furthermore, the semiconductor device 100 can be made smaller than in Comparative Examples 1 and 2. Therefore, a needle mark 25b is formed on the upper surface of the gate pad 17 within the opening 19b, and a needle mark 25a is formed on the upper surface of the drain pad 15 within the opening 19a. Furthermore, the protective film 18 does not have any openings that overlap the source fingers 12. No needle marks are formed on the upper surfaces of the source fingers 12.

[0038] 12 of Comparative Example 1, when the number of source fingers 12 in transistor 40 is three or more, the width of the source fingers 12 other than those on both sides becomes wider in the X direction to contact the needles with the source fingers 12 other than those on both sides, resulting in an increase in chip size. Furthermore, when wiring 13 is provided to connect the source fingers 12 as shown in FIG. 13 of Comparative Example 2, the high-frequency characteristics of transistor 40 deteriorate. Therefore, when the number of source fingers 12 is three or more, four or more, or five or more, it is preferable to electrically connect metal layer 34 and source fingers 12 via metal layer 22.

[0039] In the first embodiment, a FET is used as an example of the semiconductor element. The semiconductor element may be a transistor other than a FET, or may be a semiconductor element other than a transistor. When the semiconductor element is a multi-finger FET, the number of source fingers 12 increases. Furthermore, since the gate finger 16 is sandwiched between the source finger 12 and the drain finger 14, the gate finger 16 and the wiring 13 intersect, as in the second comparative example, and the gate-source parasitic capacitance increases. Therefore, it is preferable to electrically connect the metal layer 34 and the source finger 12 via the metal layer 22.

[0040] When the thickness of the substrate 10 is 100 μm or less, the wafer 30 warps. When the thickness of the substrate 10 is 50 μm or less, or even 30 μm or less, the wafer 30 warps even more. This makes it difficult to adsorb the wafer 30 to the stage 35. Therefore, it is preferable to electrically connect the metal layer 34 and the source fingers 12 via the metal layer 22.

[0041] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0042] 10, 10a board 10b Semiconductor layer 11 Active area 12 Source finger (first electrode) 13 Wiring 14 Drain Finger 15 Drain pad (second pad) 16 Gate finger (second electrode) 17 Gate pad (first pad) 18 Protective film 19a~19d opening 20, 21 Through holes 22 Metal layer (first metal layer) 25a~25c needle marks 26a, 26b needle 30 wafers 31 Effective Area 32, 32a to 32f Chip area 33 Inactive Area 34 Metal layer (second metal layer) 35 Stages 36a aperture 36 Frame (metal frame) 37 Sheet (insulating sheet) 38 Metal Spring 40 transistors 100, 102, 104 Semiconductor device

Claims

1. A substrate; a metal layer provided under the substrate; a semiconductor element including: a plurality of first electrodes provided on the substrate, each connected to the metal layer via a through-hole penetrating the substrate, and electrically isolated from one another on the substrate; a plurality of second electrodes provided on the substrate and arranged alternately with the plurality of first electrodes; and first pads provided on the substrate and to which the plurality of second electrodes are connected; a protective film provided on the substrate so as to cover the plurality of first electrodes and the plurality of second electrodes, the protective film having a first opening exposing at least a portion of the first pad, and no opening overlapping the plurality of first electrodes; Equipped with a needle mark is provided on an upper surface of the first pad in the first opening, and no needle mark is provided on an upper surface of the first electrode.

2. A substrate, a metal layer provided under the substrate; a semiconductor element including: a plurality of first electrodes provided on the substrate, each connected to the metal layer via a through-hole penetrating the substrate, and electrically isolated from one another on the substrate; a plurality of second electrodes provided on the substrate and arranged alternately with the plurality of first electrodes; and first pads provided on the substrate and to which the plurality of second electrodes are connected; a protective film that is provided on the substrate so as to cover the plurality of first electrodes and the plurality of second electrodes, the protective film having a first opening that exposes at least a portion of the first pad, and that does not have any openings that overlap the plurality of first electrodes; the semiconductor element includes a plurality of drain fingers provided on the substrate and a second pad to which the plurality of drain fingers are connected; the plurality of first electrodes are a plurality of source fingers, and the plurality of second electrodes are a plurality of gate fingers; the plurality of gate fingers are each sandwiched between one of the plurality of source fingers and one of the plurality of drain fingers; the protective film covers the plurality of drain fingers and has a second opening exposing at least a portion of the second pad; a needle mark is provided on an upper surface of the second pad in the second opening.

3. The semiconductor element comprises a plurality of drain fingers provided on the substrate and a second pad to which the plurality of drain fingers are connected; the plurality of first electrodes are a plurality of source fingers, and the plurality of second electrodes are a plurality of gate fingers; the plurality of gate fingers are each sandwiched between one of the plurality of source fingers and one of the plurality of drain fingers; the protective film covers the plurality of drain fingers and has a second opening exposing at least a portion of the second pad; 2. The semiconductor device according to claim 1, wherein a needle mark is provided on an upper surface of the second pad in the second opening.

4. The semiconductor device according to claim 1 , wherein the plurality of first electrodes are three or more first electrodes.

5. a substrate having a plurality of regions on which a plurality of chips are to be formed; a first metal layer disposed under the substrate; a plurality of semiconductor elements provided on the substrate in the plurality of regions corresponding to each other, each of which includes a plurality of first electrodes connected to the first metal layer via a first through hole penetrating the substrate and electrically isolated from one another on the substrate, a plurality of second electrodes provided alternately with the plurality of first electrodes, and pads to which the plurality of second electrodes are connected; a second metal layer provided on the substrate in a region other than the plurality of regions and electrically connected to the first metal layer via a second through hole penetrating the substrate; a protective film that covers the plurality of first electrodes and the plurality of second electrodes and does not cover at least a portion of the pad and at least a portion of the second metal layer; A wafer comprising:

6. 6. The wafer of claim 5, wherein the second metal layer is disposed on a peripheral region of the wafer.

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