Communication device, communication system, and communication method

Abstract

[Problem] To carry out high speed serial communication with a combination of differing communication methods. [Solution] This communication device is provided with a communication unit that either: attaches, to a single data block that includes a serial signal group transmitted from a master in synchronism with a clock and which conforms to a serial peripheral interface (SPI), identifying information identifying the data block, and transmits the data block to a communication counterpart device within a frame period of a predetermined communication protocol; or attaches, to a plurality of data blocks each including a part of the serial signal group, identifying information identifying each of the plurality of data blocks, and transmits the plurality of data blocks to the communication counterpart device in a plurality of frame periods.

Description

[Technical Field]

[0001] The present disclosure relates to a communication device, a communication system, and a communication method. [Background technology]

[0002] A technique has been proposed for performing high-speed serial communication between a Master SerDes and a Slave SerDes (see Patent Document 1).

[0003] When serial communication is performed between two SerDes, for example, FDD (Frequency Division Duplexing) or TDD (Time Division Duplex) methods are used. When there is a large difference between the amount of data transmitted from one SerDes to the other and the amount of data transmitted from the other SerDes to the first SerDes, it is possible to adopt TDD to create a difference in data transmission capacity between the upstream and downstream directions. TDD is a half-duplex communication method that cannot perform upstream and downstream communication simultaneously and is only capable of one-way communication. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-239011 Summary of the Invention [Problem to be solved by the invention]

[0005] One of the serial communication standards is called SPI (Serial Peripheral Interface). SPI is a full-duplex communication method that allows for simultaneous upstream and downstream communication. When each of the two SerDes mentioned above communicates with another communication device via SPI and transmits the SPI data via the SerDes to a communication device connected to the opposing SerDeS connected to the SerDes itself, if communication is performed using TDD between the two SerDes, the full-duplex SPI data cannot be transmitted as is using TDD, which is a half-duplex communication method.

[0006] Therefore, the present disclosure provides a communication device, a communication system, and a communication method that can perform high-speed serial communication by combining different communication methods. [Means for solving the problem]

[0007] In order to solve the above problems, according to the present disclosure, there is provided a communication device including a communication unit that adds identification information for identifying a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock, and transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmits the data blocks to the communication partner device over a plurality of frame periods.

[0008] a memory that stores a first group of serial signals conforming to the SPI and transmitted from the master in synchronization with the clock, and stores a second group of serial signals conforming to the SPI and transmitted from the slave in synchronization with the clock; a packet encoder that converts the first serial signal group stored in the memory into a first packet of the predetermined communication protocol and adds the identification information to the first packet; The communication device may further include a packet decoder that converts second packets of a predetermined communication protocol received from the communication partner device into the second group of serial signals.

[0009] The packet encoder may select the identification information from a plurality of identification information candidates in rotation.

[0010] The first packet may include frequency information and polarity information of the clock, and phase information of the clock relative to the data signals of the first group of serial signals conforming to the SPI.

[0011] The first packet may include information indicating that it contains a group of data blocks within the one frame period, or information indicating that it contains multiple data blocks divided according to the multiple frame periods.

[0012] When the first packet includes the plurality of data blocks, the first packet may include the total number of the plurality of data blocks and information on the division positions of the data blocks.

[0013] The second packet may include at least one of identification information of the second packet, information indicating an operating state of the slave, and interrupt information from the slave.

[0014] The memory may send an interrupt signal to the master when it is confirmed by interrupt information from the slave that data has been transmitted from the slave and when it is confirmed that the identification information of the first packet matches the identification information of the second packet.

[0015] The packet encoder may generate the first packet based on the first serial signal group transmitted from the master, regardless of whether interrupt information from the slave is received or not.

[0016] The first packet may include information of a slave select signal included in the first serial signal group conforming to the SPI for selecting the communication partner device or the slave.

[0017] The packet encoder may transmit the first packet to the communication partner device or the slave selected by the slave select signal.

[0018] The device may further include a shift register that stores each serial signal included in the first serial signal group in the memory in sequence in synchronization with the clock, and transmits each serial signal included in the second serial signal group to the master in sequence in synchronization with the clock.

[0019] The shift register may transmit a valid second serial signal group to the master if identification information included in the second packet before conversion into the second serial signal group matches identification information included in the first packet that was transmitted to the communication partner device before the second packet was received.

[0020] The communication unit may transmit the first packet at a first timing defined by the predetermined communication protocol, and may receive the second packet at a second timing defined by the predetermined communication protocol.

[0021] The communication unit may transmit and receive the first packet during a first period within each frame period, and the second packet during a second period within each frame period, between the communication device and the communication partner device using the communication protocol compliant with TDD (Time Division Duplex).

[0022] According to the present disclosure, there is provided a communication device including a communication unit that, in synchronization with a clock generated based on clock frequency information included in a packet from a communication partner device, adds identification information to identify a group of data blocks including a group of serial signals conforming to an SPI transmitted from a slave, and transmits the data block to the communication partner device within one frame period of a predetermined communication protocol, or adds identification information to identify each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the communication partner device over a plurality of frame periods.

[0023] a packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first serial signal group that complies with SPI; a clock generator that generates the clock based on the clock frequency information included in the first group of serial signals; a memory that stores the first group of serial signals in synchronization with the clock and that stores a second group of serial signals that conforms to the SPI and that are transmitted from a slave in synchronization with the clock; The communication device may further include a packet encoder that converts the second serial signal group stored in the memory into second packets of the predetermined communication protocol and adds the identification information to the second packets.

[0024] When the packet encoder transmits the second packet to the communication partner device in response to the first packet received from the communication partner device, the packet encoder may add identification information to the second packet that is the same as the identification information contained in the first packet.

[0025] The second packet may include information indicating that it contains a single data block transmitted within one frame period of the second serial signal group, or information indicating that it contains multiple data blocks transmitted over multiple frame periods.

[0026] The second packet may include interrupt information requesting the master to read the status of the slave.

[0027] The communication device may further include a shift register that stores each serial signal included in the second serial signal group in the memory and transmits each serial signal included in the first serial signal group to the slave.

[0028] The communication unit may transmit the second packet at a first timing defined by the predetermined communication protocol, and may receive the first packet at a second timing defined by the predetermined communication protocol.

[0029] The communication unit may transmit and receive the first packet during a first period within each frame period, and the second packet during a second period within each frame period, between the communication device and the communication partner device using the communication protocol compliant with TDD (Time Division Duplex).

[0030] According to the present disclosure, a first communication device and a second communication device are provided which transmit and receive packets using a predetermined communication protocol, the first communication device has a first communication unit that adds identification information for identifying a group of data blocks, including a group of serial signals conforming to SPI (Serial Peripheral Interface) and transmitted from a master in synchronization with a clock, to the second communication device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks, each of which includes a portion of the group of serial signals, to the second communication device within a plurality of frame periods; The second communication device A communication system is provided, which has a second communication unit that adds identification information to a group of data blocks including a group of serial signals conforming to an SPI transmitted from a slave in synchronization with a clock generated based on clock frequency information contained in a packet from the first communication device, and transmits the data block to the first communication device within one frame period of a predetermined communication protocol, or adds identification information to identify each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the first communication device over a plurality of frame periods.

[0031] According to the present disclosure, there is provided a communication method in which a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock is added with identification information for identifying the data block, and the data block is transmitted to a communication partner device within one frame period of a predetermined communication protocol, or a plurality of data blocks each including a portion of the group of serial signals are added with identification information for identifying each of the plurality of data blocks, and the data block is transmitted to the communication partner device over a plurality of frame periods. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a block diagram showing a schematic configuration of a communication system including a communication device according to a first embodiment. [Figure 2] Block diagram of the parts related to SPI communication between SPI / Master and SPI / Slave. [Figure 3] Basic signal waveform diagram of the SPI protocol. [Figure 4] FIG. 2 is a diagram illustrating the TDD method performed between M_SerDes and S_SerDes in FIG. 1. [Figure 5] FIG. 2 is a diagram for explaining information contained in a transmission packet generated by ECP. [Figure 6] Timing diagram of SPI / Master communicating with SPI / Slave. [Figure 7A]10 is a flowchart showing a processing procedure in which an SPI / Master communicates with an SPI / Slave. [Figure 7B] Flowchart following Figure 7A. [Figure 8] FIG. 1 is a diagram showing a schematic diagram of packets sent and received on the UP Link and the Down Link. [Figure 9] FIG. 10 is a timing diagram showing a case where the process of transmitting divided data within one frame period is repeated over multiple frames. [Figure 10A] 10 is a flowchart showing the processing procedure of the communication system that operates at the timing of FIG. 9; [Figure 10B] Flowchart following FIG. 10A. [Figure 10C] Flowchart following Figure 10B. [Figure 11] FIG. 11 is a diagram for explaining information included in a transmission packet generated by an ECP according to the third embodiment. [Figure 12] FIG. 11 is a timing diagram showing communication between an SPI / Master and an SPI / Slave in the third embodiment. [Figure 13A] 10 is a flowchart showing a processing procedure of a communication system according to a third embodiment. [Figure 13B] Flowchart following FIG. 13A. [Figure 14] FIG. 13 is a timing diagram showing communication between an SPI / Master and an SPI / Slave in the fourth embodiment. [Figure 15A] 10 is a flowchart showing a processing procedure of a communication system according to a fourth embodiment. [Figure 15B] Flowchart following FIG. 15A. [Figure 16] FIG. 10 is a block diagram of a main part of a communication system including a communication device according to a fifth embodiment. [Figure 17] FIG. 17 is a block diagram of a main part of a communication system including a communication device according to a modification of FIG. 16. DETAILED DESCRIPTION OF THE INVENTION

[0033] Hereinafter, embodiments of a communication device, a communication system, and a communication method will be described with reference to the drawings. The following description will focus on the main components of the communication device, the communication system, and the communication method, but the communication device, the communication system, and the communication method may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0034] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration of a communication system 2 including communication devices 1a and 1b according to the first embodiment. The communication system 2 in Fig. 1 includes an SPI / Master 11, a Master SerDes (M_SerDes) 31, an SPI / Slave 12, and a Slave SerDes (S_SerDes) 41. Of these, the M_SerDes 31 corresponds to the communication device 1a, and the S_SerDes 41 corresponds to the communication device 1b.

[0035] The SPI / Master 11 and M_SerDes 31 perform serial communication conforming to SPI (hereinafter, sometimes referred to as SPI communication). Similarly, the SPI / Slave 12 and S_SerDes 41 perform serial communication conforming to SPI (SPI communication). The M_SerDes 31 and S_SerDes 41 perform high-speed serial communication using the TDD method. In FIG. 1, the signal transmission path from M_SerDes 31 to S_SerDes 41 is called the UP Link, and the signal transmission path from S_SerDes 41 to M_SerDes 31 is called the Down Link. In SPI communication, serial communication is performed using a protocol conforming to the SPI standard (hereinafter, sometimes referred to as the SPI protocol). In this specification, serial data transmitted and received in SPI communication is sometimes referred to as SPI data.

[0036] As will be described later, the M_SerDes 31 includes a communication unit (DLL 31-4) that transmits a group of serial signals conforming to the SPI (Serial Peripheral Interface) transmitted from the master (SPI_Master 11) in synchronization with a clock to the communication partner device (S_SerDes 41) as a single data block within one frame period of a predetermined communication protocol, or transmits the group of serial signals to the communication partner device (S_SerDes 41) as multiple data blocks divided according to multiple frame periods. The S_SerDes 41 also has a communication unit (DLL 41-4) that synchronizes with a clock generated based on clock frequency information included in a packet from the communication partner device (M_SerDes 31) and transmits a group of serial signals conforming to the SPI transmitted from the slave (SPI_Slave 12) to the communication partner device (M_SerDes 31) as a single data block within one frame period of a predetermined communication protocol, or transmits the group of serial signals to the communication partner device (M_SerDes 31) as multiple data blocks divided according to multiple frame periods.

[0037] Figure 2 is a block diagram of the part related to SPI communication between the SPI / Master 11 and the SPI / Slave 12. For the sake of simplicity, Figure 2 shows an example in which the SPI / Master 11 and the SPI / Slave 12 directly perform serial communication conforming to the SPI.

[0038] 2, the SPI / Master 11 has a shift register 11-1 and a buffer / memory 11-2. Similarly, the SPI / Slave 12 has a shift register 12-1 and a buffer / memory 12-2.

[0039] The shift register 12-1 in the SPI / Slave 12 operates in synchronization with the clock SCK supplied from the SPI / Master 11. The shift register 11-1 in the SPI / Master 11 outputs serial data in synchronization with SCK, starting from the MSB (Most Significant Bit). The output serial data is input to the LSB (Least Significant Bit) side of the shift register 12-1 in the SPI / Slave 12 via the MOSI pin. The serial data output from the MSB side of the shift register 12-1 in the SPI / Slave 12 is input to the LSB side of the shift register 11-1 in the SPI / Master 11 via the MISO pin. The data held in the shift register 11-1 in the SPI / Master 11 can be stored in the buffer / memory 11-2. The shift register 11-1 can also hold the data stored in the buffer / memory 11-2. Similarly, data held in the shift register 12-1 in the SPI / Slave 12 can be stored in the buffer / memory 12-2. Also, the shift register 12-1 can hold the data stored in the buffer / memory 12-2.

[0040] Figure 3 is a basic signal waveform diagram of the SPI protocol. In the SPI protocol, there are four combinations of the polarity of SCK when the slave select signal (CS signal) output by the SPI / Master 11 is idle (high level in Figure 3) and the edge (rising edge or falling edge) of the clock (SCK) that latches data when the CS signal becomes active (low level in Figure 3). These four combinations are called SPI modes. The SPI / Master 11 can arbitrarily select one of the four SPI modes. The SPI / Master 11 must know in advance the SPI modes that the SPI / Slave supports and select the corresponding mode.

[0041] 3A to 3D are signal waveform diagrams of four SPI modes. In SPI mode=0 shown in FIG. 3A, SCK is low when the CS signal is idle, and data is held at the rising edge of SCK. In SPI mode=1 shown in FIG. 3B, SCK is low when the CS signal is idle, and data is held at the falling edge of SCK. In SPI mode=2 shown in FIG. 3C, SCK is high when the CS signal is idle, and data is held at the falling edge of SCK. In SPI mode=3 shown in FIG. 3D, SCK is high when the CS signal is idle, and data is held at the rising edge of SCK.

[0042] The SCK frequency is not specified in the SPI protocol and differs for each device that performs SPI communication, so the SPI / Master 11 selects the SCK frequency for each device that performs SPI communication. Therefore, the SPI / Master 11 must know in advance the SCK frequency that each device that performs SPI communication can support.

[0043] A communication method using the SPI protocol will be described below. In the example of FIG. 2, communication using the SPI protocol is performed between an SPI / Master 11 and an SPI / Slave 12. The SPI / Master 11 may be connected to one or more SPI / Slaves 12. When multiple SPI / Slaves 12 are connected to the SPI / Master 11, the SPI / Master 11 has multiple CS signals corresponding to the multiple SPI / Slaves 12, and can communicate by selecting the Slave with which it wants to communicate using the corresponding CS signal. The CS signal used by the SPI / Master 11 to select the SPI / Slave 12 with which it wants to communicate is included in the SPI control information, as will be described later. The SPI / Master 11 includes the SPI control information in the SPI data and transmits it to the M_SerDes 31.

[0044] When performing SPI communication, the SPI / Master 11 activates (low in FIGS. 3A to 3D) the CS signal connected to the SPI / Slave 12 with which it wishes to communicate. In this specification, putting various signals into an active state may be referred to as assertion, and putting them into an idle state may be referred to as deassertion.

[0045] The SPI / Master 11 and SPI / Slave 12 transfer the data they wish to transfer from their respective buffers / memory 11-2 and 12-2 to the shift registers 11-1 and 12-1. The SPI / Master 11 generates an SCK and supplies it to its own shift register 11-1, as well as to the shift register 12-1 in the SPI / Slave 12. Each shift register 11-1 and 12-1 shifts the held data one bit at a time by toggling the SCK. The data in the shift registers 11-1 and 12-1 is swapped by toggling the SCK by the number of stages of the shift registers 11-1 and 12-1. The SPI / Master 11 then transitions the CS signal to the idle state (high in Figures 3A to 3D). The SPI / Master 11 and the SPI / Slave 12 can acquire data from the buffer / memory 11-2 and 12-2 by transferring the data currently in the shift registers 11-1 and 12-1 to the buffer / memory 11-2 and 12-2, thereby completing the SPI communication.

[0046] While Fig. 2 shows an example in which SPI / Master 11 and SPI / Slave 12 perform direct SPI communication, Fig. 1 shows that M_SerDes 31 and S_SerDes 41 are arranged between SPI / Master 11 and M_SerDes 31. In Fig. 1, SPI / Master 11 and M_SerDes 31 perform SPI communication, M_SerDes 31 and S_SerDes 41 perform serial communication using the TDD method, and SPI / Slave 12 and S_SerDes 41 perform SPI communication.

[0047] Fig. 4 is a diagram explaining the TDD method performed between the M_SerDes 31 and S_SerDes 41 in Fig. 1. Fig. 4 shows a simplified internal configuration of the SPI / Master 11 and SPI / Slave 12 shown in Fig. 1. Fig. 4 also shows an example in which peripheral devices 32 and 42 are connected to the M_SerDes 31 and S_SerDes 41, respectively.

[0048] The M_SerDes 31 and the S_SerDes 41 are connected to each other by a cable 103, for example, several meters to tens of meters long. The M_SerDes 31 and the S_SerDes 41 perform high-speed serial communication via this cable 103. It is also possible to provide a plurality of pairs of two devices having the same configuration as the M_SerDes 31 and the S_SerDes 41 in Fig. 4, and perform high-speed serial communication for each pair. The M_SerDes 31 and the S_SerDes 41 in Fig. 4 can be widely used in applications that send and receive large amounts of data, such as an in-vehicle camera module.

[0049] The M_SerDes 31 and S_SerDes 41 perform high-speed serial communication using the TDD method. The lower right corner of Figure 4 shows the timing and frequency band of the TDD method. In the TDD method, as shown on the right side of Figure 4, one TDD cycle contains one upstream signal transmission period and one downstream signal transmission period, with no overlapping in time. The TDD timing diagram in Figure 4 shows an example in which the upstream signal transmission period from M_SerDes 31 to S_SerDes 41 (referred to as "UP Link") is much shorter than the downstream signal transmission period from S_SerDes 41 to M_SerDes 31 (referred to as "Down Link"). In other words, the UP Link signal ratio is much smaller than the Down Link signal ratio. For example, when a video signal captured by a sensor in S_SerDes 41 is transmitted to M_SerDes 31, the signal ratio is as shown in the TDD timing diagram in Figure 4.

[0050] The right side of Figure 4 illustrates the frequency bands used for uplink signal transmission and downlink signal transmission in the TDD system. As illustrated, in the TDD system, the frequency bands for uplink signal transmission and downlink signal transmission partially overlap. For example, when a video signal captured by a sensor in the S_SerDes 41 is transmitted to the M_SerDes 31, the downlink signal transmission, which has a large signal volume, requires a wider frequency band than the uplink signal transmission. Therefore, the downlink signal transmission is performed using a wider frequency band that includes the frequency band used for the uplink signal transmission. In the TDD system, the downlink signal transmission period does not overlap with the uplink signal transmission period, eliminating the need for an echo cancellation circuit to separate the two signals.

[0051] The M_SerDes 31 and S_SerDes 41 according to this embodiment are assumed to transmit signals using the TDD method, but may also transmit signals using the FDD method in some cases. The timing and frequency bands for the FDD method are shown in the lower left of Figure 4. In the FDD method, the frequency band used for signal transmission from the M_SerDes 31 to the S_SerDes 41 is different from the frequency band used for signal transmission from the S_SerDes 41 to the M_SerDes 31. This allows signal transmission from the M_SerDes 31 to the S_SerDes 41 and signal transmission from the S_SerDes 41 to the M_SerDes 31 to be performed at the same timing, and allows uplink signal transmission and downlink signal transmission to be performed using the entire period of one FDD cycle.

[0052] In addition, in the FDD system, upstream signal transmission, which has a large signal volume, is performed using a wide frequency band on the high frequency side. Downstream signal transmission, which has a small signal volume, is performed using a narrow frequency band on the low frequency side. In the example at the bottom left of Figure 4, to improve frequency utilization efficiency, the frequency band used for upstream signal transmission and the frequency band used for downstream signal transmission are partially overlapped. Also, as shown at the bottom left of Figure 4, the upstream signal transmission section and the downstream signal transmission section completely overlap in the time domain. These overlapping sections necessitate an echo cancellation circuit. An echo cancellation circuit is a circuit that accurately separates upstream and downstream signals.

[0053] In the following, an example will be described in which M_SerDes 31 and S_SerDes 41 perform high-speed serial communication using the TDD method, and M_SerDes 31 performs serial communication in accordance with SPI with SPI / Master 11, and S_SerDes 41 performs serial communication in accordance with SPI with SPI / Slave 12.

[0054] Serial communication between M_SerDes 31 and S_SerDes 41 is performed using TDD instead of SPI, so protocol conversion must be performed inside M_SerDes 31 and S_SerDes 41. Also, while serial communication using SPI is a full-duplex communication method, serial communication using TDD is a half-duplex communication method, so data from SPI / Master 11 or SPI_Slave cannot be sent and received using TDD at the same timing.

[0055] The following is a detailed description of the configuration of the communication system 2 in Fig. 1. As shown in Fig. 4, the SPI / Master 11 in Fig. 1 includes a shift register 11-1 and a buffer / memory 11-2, as well as a controller 11-3 and an SCK generator 11-4.

[0056] The controller 11-3 supplies a slave select signal (CS signal) for activating SPI communication to the M_SerDes 31 via the M_CSn pin. The number of CS signals provided is equal to the number of devices performing SPI communication with the SPI / Master 11. For example, in FIG. 1, different M_CSn pins are assigned to the M_SerDes 31, the S_SerDes 41, and the SPI / Slave 12. In this specification, the pin that outputs the CS signal output from the SPI / Master 11 may be referred to as M_CSn(x). For example, M_CSn(0) is assigned to the M_SerDes 31, and M_CSn(1) is assigned to the SPI / Slave 12.

[0057] The controller 11-3 controls the operation of the SCK generator 11-4, which outputs SCK when any of the CS signals is active. The shift register 11-1 performs a shift operation in synchronization with SCK.

[0058] The controller 11-3 detects that the SPI / Slave 12 has output the interrupt signal S_INT by the interrupt signal M_INT from the M_SerDes 31, and starts the SPI communication of the next frame using this interrupt signal M_INT as a trigger. Alternatively, when the controller 11-3 itself wants to transmit SPI data, it also starts the SPI communication in the same way (time t5 of M_CSn(1) in FIG. 6, which will be described later).

[0059] The M_SerDes 31 is connected to the SPI / Master 11. The M_SerDes 31 has an SPI block 31-1 for performing data communication with the SPI / Master 11 according to the SPI protocol. The SPI block 31-1 has a shift register 31-1-1 and a buffer / memory 31-1-2. When the controller 11-3 in the SPI / Master 11 activates the CS signal corresponding to the M_SerDes 31 and the SCK generator 11-4 outputs an SCK, the shift register 31-1-1 outputs SPI data in synchronization with this SCK and supplies it to the SPI / Master 11 via the MISO pin. The shift register 31-1-1 also captures the SPI data output from the SPI / Master 11 via the MOSI pin in synchronization with the SCK.

[0060] When the CS signal goes into the idle state, the controller 11-3 causes the SCK generator 11-4 to stop outputting SCK, thereby causing the shift register 31-1-1 to hold the state it was in immediately before SCK was stopped.

[0061] When the CS signal transitions to the idle state, the SPI block 31-1 in the M_SerDes 31 transfers all data in the shift register 31-1-1 to the buffer / memory 31-1-2, thereby completing the data transfer process from the SPI / Master 11 to the M_SerDes 31 according to the SPI protocol.

[0062] Note that data transfer from shift register 31-1-1 to buffer / memory 31-1-2 in M_SerDes 31 depends on the amount of data that SPI / Master 11 wants to transfer and the data capacity of shift register 31-1-1. Therefore, if there is a risk of data overflowing from shift register 31-1-1 while the CS signal is active, data loss can be prevented by transferring the data in shift register 31-1-1 to buffer / memory 31-1-2 before the overflow occurs.

[0063] In addition, the M_SerDes 31 has a packet encoder (ECP) 31-2, a packet decoder (DCP) 31-3, a DLL 31-4, and a PHY layer block (PHY) 31-5. The ECP 31-2 in the M_SerDes 31 converts the SPI data stored in the buffer / memory 31-1-2 into packets (SPI packets) that comply with the TDD method. The DLL 31-4 combines the SPI packets generated by the ECP 31-2 with other transmission packets other than the SPI packets to generate UP Link packets. The PHY 31-5 transmits the UP Link packets to the S_SerDes 41 via the UP Link.

[0064] The S_SerDes 41 in FIG. 1 is connected to the SPI / Slave 12. The S_SerDes 41 has an SPI block 41-1 for transmitting and receiving data to and from the SPI / Slave 12 according to the SPI protocol. The SPI block 41-1 has a controller (CNTR) 41-1-4, an SCK generator 41-1-3, a shift register 41-1-1, and a buffer / memory 41-1-2. The controller 41-1-4 controls the timing and frequency of the SCK output from the SCK generator 41-1-3 based on SPI control information from the SPI / Master 11. When the controller 41-1-4 activates the CS signal corresponding to the SPI / Slave 12 and the SCK generator 41-1-3 outputs an SCK, the shift register 41-1-1 outputs SPI data in synchronization with the SCK and supplies it to the SPI / Slave 12 via the S_MOSI pin. The shift register 41-1-1 also receives SPI data output from the SPI / Slave 12 via the S_MISO pin in synchronization with SCK. The S_SerDes 41 also includes a packet encoder (ECP) 41-2, a packet decoder (DCP) 41-3, a DLL 41-4, and a PHY layer block (PHY) 41-5. The ECP 41-2 in the S_SerDes 41 converts the SPI data stored in the buffer / memory 41-1-2 into a packet (SPI packet) conforming to the TDD method. The DLL 41-4 combines the SPI packet generated by the ECP 41-2 with other transmission packets other than the SPI packet to generate an UP Link packet. The PHY 41-5 transmits the UP Link packet to the S_SerDes 41 via the UP Link.

[0065] Figure 5 is a diagram explaining the information contained in the transmission packets generated by the ECPs 31-2 and 41-2. In Figure 5, for each piece of information in the transmission packet, an identification symbol, an information name, a function in the transmission packet for transmitting data from the SPI / Master 11 to the SPI / Slave 12, a function in the transmission packet for transmitting data from the SPI / Slave 12 to the SPI / Master 11, and a description are associated.

[0066] C-1 is the transmission mode, which is specified as a command by the SPI / Master 11. The transmission mode included in the packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. If C-1 is 0, a single data block is transmitted within one TDD frame period. If C-1 is 1, multiple data blocks divided according to multiple frame periods are transmitted.

[0067] C-2 is a slave select signal (CSn signal) that is issued as a command by the SPI / Master 11. The CSn signal included in a packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. The CSn signal is a signal that selects the SPI / Slave 12 with which the SPI / Master 11 wants to communicate. The CSn signal can not only select an individual SPI / Slave 12, but also select a SerDes (M_SerDes 31 or S_SerDes 41).

[0068] C-3 is the SCK frequency, and is specified as a command by the SPI / Master 11. The SCK frequency included in the packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. C-3 is used by the SPI / Master 11 to specify the SCK frequency on the SPI / Slave 12 side.

[0069] C-4 is the SPI mode, which is instructed as a command by the SPI / Master 11. The SPI mode included in the packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. For example, if C-4 is 0, mode=0 in FIG. 3A is selected, if it is 1, mode=1 in FIG. 3B is selected, if it is 2, mode=2 in FIG. 3C is selected, and if it is 3, mode=3 in FIG. 3D is selected.

[0070] C-5 is the total number of data block DBs, and is provided as information by the SPI / Master 11. The total number of DBs included in the packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. When C-1 is 0 (when a divided DB is being sent), C-5 is 1. The SPI / Slave 12 returns the number of DBs received since the start of SPI communication.

[0071] C-6 is the position of the current data block DB, and is provided as information by the SPI / Master 11. It is not included in packets from the SPI / Slave 12. If C-6 is 0, it indicates invalid information. If C-1 is 0, it becomes 0. If C-6 is 1, it indicates that it is the first divided data. If it is 2, it indicates that it is a divided data other than the first or last. If it is 3, it indicates that it is the last divided data.

[0072] C-7 indicates the current state of the data block DB, and is provided as information by both the SPI / Master 11 and the SPI / Slave 12. If C-7 is 0, it indicates dummy data, and if it is 1, it indicates valid data.

[0073] C-8 is the size of the data block DB and is provided as information by the SPI / Master 11. The data transmission size included in the packet from the SPI / Slave 12 is used by the SPI / Master 11 to monitor the status. C-8 indicates the data transmission size in bytes, with the maximum size being 511 bytes.

[0074] C-9 is interrupt information for the SPI / Slave 12, and is an interrupt flag that is not included in the packet sent by the SPI / Master 11 but is included in the packet sent by the SPI / Slave 12. If C-9 is 0, it indicates no interrupt, and if it is 1, it indicates an interrupt.

[0075] C-10 indicates the operating status of the SPI / Slave 12, and is not included in the packet sent by the SPI / Master 11, but is included in the packet from the SPI / Slave 12. If C-10 is 0, it indicates normal operation, if it is 1, it indicates busy (DCP31-3 is not empty), and if it is 2, it indicates that an error has occurred (SPI data has been corrupted).

[0076] C-11 is a reset of the SPI block 41-1, and is issued as a command by the SPI / Master 11. It is not included in the packet of the SPI / Slave 12. If C-11 is 0, no reset is performed, and if it is 1, the SPI block 41-1 of the S_SerDes 41 is reset.

[0077] D-1 is SPI data transmitted together with C-1 to C-11 described above, and the SPI data transmitted by the SPI / Master 11 is output from the M_MOSI pin, and the SPI data transmitted by the SPI / Slave 12 is output from the S_MISO pin.

[0078] E-1 is a CRC transmitted together with the above-mentioned C-1 to C-11 and D-1, and is included in both the SPI data transmitted from the SPI / Master 11 and the SPI data transmitted from the SPI / Slave 12. The CRC is used to detect errors in the control data C-1 to C-11 and the SPI data.

[0079] Fig. 6 is a timing diagram showing communication between the SPI / Master 11 and the SPI / Slave 12, and Figs. 7A and 7B are flowcharts showing the processing procedure for communication between the SPI / Master 11 and the SPI / Slave 12. Fig. 8 is a diagram showing packets sent and received on the Up Link and Down Link. Figs. 6 to 8 show the processing procedure for sending and receiving a group of data blocks in one TDD frame period.

[0080] First, the SPI / Master 11 generates SPI control information to be used by the ECP 31-2 and DCP 31-3 in the M_SerDes 31 and transmits it to the M_SerDes 31 (steps S1 to S4, times t1 to t4). The SPI control information includes, for example, the SPI transmission mode, SCK frequency information, the SPI mode, and the size and number of data blocks DB for SPI communication. The SPI / Master 11 stores the SPI control information in advance in the buffer / memory 11-2.

[0081] The controller 11-3 in the SPI / Master 11 asserts M_CSn(0) to an active state (low) in order to perform SPI communication with the M_SerDes 31 (step S1, time t1).

[0082] The controller 11-3 in the SPI / Master 11 controls the SCK generator 11-4 to output the clock M_SCK (step S2, time t2). In synchronization with the clock M_SCK, the SPI control information stored in the buffer / memory 11-2 is sequentially read out and transferred to the shift register 11-1. The transferred SPI control information includes the transmission mode, SCK frequency information, SPI mode, transmission data size, and number of data blocks. The shift register 11-1 sequentially outputs the SPI control information in synchronization with the clock M_SCK (steps S2 to S3, times t2 to t3). This SPI control information is input to the M_SerDes 31 via the M_MOSI pin. The shift register 31-1-1 in the M_SerDes 31 takes in the SPI control information from the SPI / Master 11 in synchronization with M_SCK.

[0083] While the shift register 31-1-1 takes in the SPI control information from the SPI / Master 11, it transmits the data held in the shift register 31-1-1 to the SPI / Master 11 via the M_MISO pin in synchronization with M_SCK. This data is invalid, so it is shown by a dashed line from time t2 to t3 in Figure 6. The SPI / Master 11 discards this data after receiving it.

[0084] When the data transfer of the SPI / Master 11 is completed, the controller 11-3 in the SPI / Master 11 causes the SCK generator 11-4 to stop generating M_SCK and deasserts M_CSn(0) to the idle state (step S4, time t4). When M_SCK stops, the shift register 31-1-1 in the M_SerDes 31 transfers the SPI control information held therein from the SPI / Master 11 to the buffer / memory 31-1-2.

[0085] The buffer / memory 31-1-2 in the M_SerDes 31 transfers the SPI control information from the SPI / Master 11 to the ECP 31-2. The ECP 31-2 converts the SPI control information into an SPI packet.

[0086] Next, the SPI / Master 11 transmits SPI data to the M_SerDes 31 for the purpose of transmitting data to the SPI / Slave 12. Specifically, the controller 11-3 in the SPI / Master 11 transitions (asserts) the M_CSn(1) corresponding to the SPI / Slave 12 from the idle state to the active state (step S5, time t5).

[0087] The controller 11-3 also causes the SCK generator 11-4 to output M_SCK (step S6, time t6). The buffer / memory 11-2 reads out the data to be transmitted to the SPI / Slave 12 in an amount equal to the transmission data size and inputs it to the shift register 11-1. The shift register 11-1 outputs the data for the SPI / Slave 12 sequentially via the M_MOSI pin in synchronization with M_SCK (step S7, time t7).

[0088] The shift register 31-1-1 in the M_SerDes 31 sequentially takes in the data output from the SPI / Master 11 in synchronization with SCK. When the controller 11-3 in the SPI / Master 11 has completed transferring data equal to the transmission data size, it causes the SCK generator 11-4 to stop outputting M_SCK (step S8, time t8). Thereafter, the controller 11-3 of the SPI / Master 11 sets M_CSn(1) to the idle state (deasserts) to end the SPI communication (step S9, time t9).

[0089] When M_SCK stops, M_SerDes 31 transfers the data held in shift register 31-1-1 to buffer / memory 31-1-2. Buffer / memory 31-1-2 transfers the data transferred from shift register 31-1-1 to ECP 31-2. ECP 31-2 generates data including the SPI control information received in the communication from time t1 to t3, a CS signal (M_CSn(1)) corresponding to SPI / Slave 12, and data intended for SPI / Slave 12. ECP 31-2 adds a flag indicating that the packet is valid to the generated data to generate a transmission packet.

[0090] 8, the ECP 31-2 transmits the generated transmission packet to the DLL 31-4 as an SPI packet 51. The DLL 31-4 combines the SPI packet 51 from the ECP 31-2 with other transmission packets to generate an UP Link packet 52, and outputs it to the PHY layer block 31-5. The PHY layer block 31-5 outputs the received UP Link packet 52 to the cable 103 in accordance with the UP Link output timing based on TDD (step S10, time t10).

[0091] The S_SerDes 41 communicates with the M_SerDes 31 in accordance with the TDD method, and also performs SPI communication with the SPI / Slave 12. A PHY layer block 41-5 in the S_SerDes 41 receives an UP Link Packet from the M_SerDes 31 via the cable 103, and outputs it to a link layer block (DLL) 41-4.

[0092] The link layer block 41-4 in the S_SerDes 41 extracts an SPI packet containing SPI data from the UP Link Packet and outputs it to a packet decoder (DCP) 41-3. The DCP 41-3 detects that the SPI / Slave 12 is the target of SPI communication based on the CSn information (C-2) in the received SPI packet. Then, in order to start SPI communication with the SPI / Slave 12, the controller 41-1-4 detects that all of the SPI data has been transmitted based on the transmission mode information (C-1) in the SPI packet, and obtains the number of SCK cycles required for one SPI communication based on the number of SPI data (C-5) and the size of the SPI data (C-8), and then activates (asserts) the slave select signal S_CS (step S11, time t11).

[0093] Next, the controller 41-1-4 in the S_SerDes 41 acquires the SCK frequency information (C-3) contained in the SPI packet and causes the SCK generator 41-1-3 to output S_SCK at the acquired frequency (step S12, time t12). At this time, the phase relationship between S_CS and SCK conforms to the SPI mode (C-4) in the SPI packet. This enables the S_SerDes 41 to transfer SPI data with the SPI / Slave 12. The data transferred to the SPI / Slave 12 is an SPI packet (D-1) and is stored in the buffer / memory 41-1-2.

[0094] The shift register 41-1-1 in the S_SerDes 41 sequentially outputs the SPI data transferred from the buffer / memory 41-1-2 from the S_MOSI pin in response to the SCK supplied from the SCK generator 41-1-3 (step S13, time t13). In parallel with this, the SPI data output from the SPI / Slave 12 to the S_MISO pin is stored in the shift register 41-1-1 and then transferred to the buffer / memory 41-1-2 at the appropriate time.

[0095] The SPI / Slave 12 sequentially takes in the SPI data from the S_MOSI pin of the S_SerDes 41 into the shift register 12-1 in synchronization with S_SCK, and sequentially outputs the data held in the shift register 12-1 from the S_MISO pin (step S14, time t14).

[0096] After driving S_SCK for the set SPI data size (C-8), the controller (41-1-4) stops SCK and returns S_CS to the idle state (deasserts) to end the SPI communication (step S15, time t15). In parallel with this, while receiving the SPI data from the S_MOSI pin of the S_SerDes 41, the SPI / Slave 12 transfers the SPI data from the S_MOSI pin from the shift register 12-1 to the buffer / memory 12-2 as appropriate, thereby finally completing the reception of data from the SPI / Master 11.

[0097] The buffer / memory 41-1-2 transfers the SPI data received from the SPI / Slave 12 to the packet encoder (ECP) 41-2 to send it to the SPI / Master 11. The ECP 41-2 adds the SPI control information it obtained in the SPI packet together with the received SPI data to the SPI packet 53. The ECP 41-2 also adds information indicating the operating status of the SPI / Slave 12 (C-10) in Figure 5 and the CRC (E-1) to the SPI packet.

[0098] Furthermore, if the SPI / Slave 12 outputs an interrupt signal (C-9), the ECP 41-2 also includes information about the interrupt signal in the SPI packet 53. In this case, the SPI packet 53 does not transmit SPI data from the SPI / Slave 12. The reason for providing an interrupt signal is that, in the SPI protocol, only the SPI / Master 11 controls the CS signal and SCK, and the SPI / Slave 12 cannot actively output data, so it outputs an interrupt signal and waits for instructions from the SPI / Master 11.

[0099] The Link layer block (DLL) 41-4 aggregates the SPI packet 53 received from the ECP 41-2 with other transmission packets to generate a Down Link packet 54, and outputs the Down Link packet 54 to the PHY layer block 41-5. The PHY layer block 41-5 outputs the received Down Link packet 54 to the cable 103 in accordance with the Down Link output timing (step S16, time t16).

[0100] The PHY layer block 31-5 of the M_SerDes 31 receives a Down Link packet including an SPI packet 53 from the SPI / Slave 12 output from the S_SerDes 41, and outputs it to the DLL 31-4. The DLL 31-4 extracts the SPI packet 53 from the received Down Link packet 54, and outputs it to a packet decoder (DCP) 31-3.

[0101] When DCP 31-3 in M_SerDes 31 receives SPI data O_DB#1 from Master 11, it also receives a packet including I_DB#1 sent to Master 11 and stores it in buffer / memory 31-1-2. To indicate that valid SPI data I_DB#1 has been returned from SPI / Slave 12, buffer / memory 31-1-2 asserts interrupt signal M_INT (step S17, time t17). Upon receiving interrupt signal M_INT, controller 11-3 of SPI / Master 11 starts SPI communication to read the SPI data from SPI / Slave 12 from M_SerDes 31, and activates (asserts) M_CSn(1) (step S18, time t18).

[0102] The controller 11-3 of the SPI / Master 11 controls the SCK generator 11-4 to output M_SCK (11-10-2) (step S19, time t19). The shift register 11-1 sequentially captures data from the M_MISO pin in synchronization with SCK, the amount of data being the transmission data size (c-8) set in Frame #1. At this time, the buffer / memory 31-1-2 in the M_SerDes 31 transfers data from the SPI / Slave 12 to the shift register 31-1-1 as needed, and the shift register 31-1-1 sequentially outputs the data in synchronization with the SCK generator 11-4 as described above. This data is captured from the M_MISO pin (step S20, time t20). In parallel with this, the SPI / Master 11 reads the SPI data to be transferred next to the SPI / Slave 12 from the buffer / memory 11-2, loads it into the shift register 11-1, and sequentially outputs it from the M_MOSI pin from the shift register 11-1 (step S21, time t21). After the necessary data has been read, the buffer / memory 31-1-2 returns the interrupt signal M_INT to the idle state (deasserts it) (step S22, time t22).

[0103] The operations up to this point complete the transfer of SPI data between the SPI / Master 11 and the SPI / Slave 12. The above series of operations is repeated the number of times necessary to transfer SPI data (step S23, time t23).

[0104] When the SPI / Master 11 reads the last SPI data from the SPI / Slave 12, the SPI / Master 11 asserts M_CSn(1) to output dummy data (step S24, time t24). This dummy data is invalid data and does not need to be transferred to the SPI slave, so it is discarded without being transferred from the shift register 31-1-1 of the M_SerDes 31 to the buffer / memory 31-1-2 (step S25, time t25). The last data from the SPI / Slave 12 is output from the shift register 31-1-1 in the M_SerDes 31 through the M_MISO pin and taken into the shift register 11-1 in the SPI / Master 11 (step S26, time t26).

[0105] In this way, in the first embodiment, a block of data transmitted by the SPI / Master 11 to the M_SerDes 31 by SPI communication can be transmitted to the S_SerDes 41 via the UP Link within one frame period of the TDD system, and a block of data transmitted by the SPI / Slave 12 to the S_SerDes 41 by SPI communication can be transmitted to the M_SerDes 31 via the DOWN Link. This allows serial communication to be performed between the SPI / Master 11 and the SPI / Slave 12 via the M_SerDes 31 and the S_SerDes 41 by combining the SPI communication of the full-duplex communication system and the TDD communication of the half-duplex communication system.

[0106] (Second embodiment) In the second embodiment, data transmitted and received by SPI communication is divided into a plurality of frame periods of the TDD method and transmitted and received.

[0107] The communication system 2 according to the second embodiment has the same configuration as that shown in FIG. 1, but the SPI control information that the SPI / Master 11 transmits to the M_SerDes 31 is different.

[0108] 9 is a timing diagram showing a case where the process of transmitting divided data within one frame period is repeated over a plurality of frames. FIGS. 10A, 10B, and 10C are flowcharts showing the processing procedure of the communication system 2 that operates at the timing of FIG.

[0109] Steps S31 to S38 (times t31 to t38) in Fig. 10A are the same as steps S1 to S8 (times t1 to t8) in Fig. 7, and the SPI / Master 11 generates SPI control information and sets it in ECP 31-2 and DCP 31-3 in M_SerDes 31. The processing operations from step S39 onwards are also basically the same as in Figs. 7A and 7B, but in Figs. 9, 10A, 10B and 10C, data to be transmitted in one SPI frame is divided into multiple pieces, and each of the multiple divided data is transmitted in one TDD frame period. The signal transmitted in one TDD frame period is called a TDD burst signal.

[0110] Until the transfer of all divided data in the SPI frame is completed, the Slave Select signal M_CSn(1) between the SPI / Master 11 and the M_SerDes 31 and the Slave Select signal S_CS between the S_SerDes 41 and the SPI / Slave 12 continue to be in the active state.

[0111] The SPI / Master 11 asserts a CS signal (M_CSn(1)) to start transmitting SPI data (step S35, time t35). The SPI / Master 11 causes the SCK generator 11-4 to output M_SCK in order to transmit one piece of divided data (data block DB) (step S36, time t36).

[0112] Next, the SPI / Master 11 outputs the SPI data sequentially from the shift register 11-1 in synchronization with SCK, and outputs it from the M_MOSI pin (step S37, time t37). The SPI / Master 11 also outputs a CS signal corresponding to the SPI / Slave 12 with which it is communicating to the M_SerDes 31 (step S38, time t38). Next, the ECP 31-2 in the M_SerDes 31 generates a packet including the SPI data and the CS signal (step S39, time t39). This packet is combined with other transmission packets in the PHY layer block 31-5 to generate an UP Link packet. This UP Link packet is transmitted to the S_SerDes 41 via the UP Link.

[0113] The SPI / Master 11 continues to assert the CS signal until all divided data have been transmitted (step S40, time t40). The SPI / Master 11 stops the output of M_SCK from the SCK generator 11-4 until the next divided data is transmitted (step S41, time t41).

[0114] The S_SerDes 41 acquires the CS signal and SPI data from the received packet and asserts S_CS (step S42, time t42). The controller 41-1-4 in the S_SerDes 41 causes the SCK generator 41-1-3 to output S_SCK (step S43, time t43). The S_SerDes 41 temporarily stores the SPI data in the received packet in the buffer / memory 41-1-2 and then transfers it to the shift register 41-1-1. The shift register 41-1-1 sequentially outputs the data in synchronization with S_SCK. The output data is input to the SPI / Slave 12 from the S_MOSI pin (step S44, time t44). Furthermore, data output from the shift register 12-1 in the SPI / Slave 12 in synchronization with S_SCK is input to the S_SerDes 41 from the S_MISO pin (step S45, time t45).

[0115] The DLL 41-4 in the S_SerDes 41 generates a transmission packet including data from the S_MISO pin. The PHY layer block 41-5 transmits the transmission packet to the Down Link at a timing specified by the TDD method (step S46, time t46).

[0116] The DLL 31-4 in the M_SerDes 31 transmits the SPI packet included in the transmission packet transmitted from the S_SerDes 41 to the DCP 31-3. When the DCP 31-3 receives the SPI data O_DB#1 from the Master 11, it also receives a packet including I_DB#1 transmitted to the Master 11 at the same time, and stores it in the buffer / memory 31-1-2. To indicate that valid SPI data I_DB#1 has been returned from the SPI / Slave 12, the buffer / memory 31-1-2 asserts the interrupt signal M_INT (step S47, time t47).

[0117] When the SPI / Master 11 detects that M_INT has been asserted, it causes the SCK generator 11-4 to output M_SCK (step S48, time t48). The buffer / memory 11-2 transfers the next data to be transmitted to the shift register 11-1, which then outputs the SPI data from the M_MOSI pin in synchronization with M_SCK (step S49, time t49). In parallel with this, the data output from the M_SerDes 31 via the M_MISO pin is taken into the shift register 11-1 (step S50, time t50).

[0118] When the SPI / Master 11 has read all the data from the M_SerDes 31, it returns (deasserts) M_INT to the idle state (step S51, time t51).

[0119] The S_SerDes 41 maintains the active state (asserted) of S_CS until all the divided data have been transmitted (step S52, time t52). Also, the SCK generator 41-1-3 in the S_SerDes 41 stops outputting S_SCK until the next SPI data is transmitted from the M_SerDes 31 (step S53, time t53).

[0120] Thereafter, the processing operations of steps S40 to S53 are repeated (step S54, time t54). When the M_SerDes 31 transmits the last fragmented packet on the UP Link (step S55, time t55), the S_SerDes 41 outputs S_SCK (step S56, time t56). Then, the S_SerDes 41 outputs SPI data via the S_MOSI pin (step S57, time t57) and receives the last SPI data from the SPI / Slave 12 via the S_MISO pin (step S58, time t58).

[0121] After receiving the last SPI data, the S_SerDes 41 puts S_CS into the idle state (deasserts it) (step S59, time t59). In addition, the S_SerDes 41 transmits a transmission packet including the last SPI data to the M_SerDes 31 via the Down Link (step S60, time t60).

[0122] As in step S47, the M_SerDes 31 activates M_INT (step S61, time t61). The M_SerDes 31 also causes the SCK generator 11-4 in the SPI / Master 11 to output M_SCK (step S62, time t62). In synchronization with M_SCK, data output from the shift register 31-1-1 via the M_MISO pin is captured into the shift register 11-1 in the SPI / Master 11 (steps S63 to S64, times t63 to t64). After capturing all the data, the SPI / Master 11 sets the CS signal to the idle state (step S65, time t65). The data output from the shift register 11-1 in step S63 is discarded because it is dummy (step S66, time t66).

[0123] In this way, in the second embodiment, the SPI / Master 11 divides a block of data transmitted to the M_SerDes 31 by SPI communication into multiple pieces of divided data, and transmits each divided data to the S_SerDes 41 via the Up Link in multiple frame periods of the TDD method, and the SPI / Slave 12 divides a block of data transmitted to the S_SerDes 41 by SPI communication into multiple pieces of divided data, and transmits each divided data to the M_SerDes 31 via the Down Link in multiple frame periods of the TDD method.

[0124] (Third embodiment) In the first and second embodiments, the SPI / Master 11 starts SPI communication with the SPI / Slave 12, and in response to a request from the SPI / Master 11, data output by the SPI / Slave 12 is transmitted from the S_SerDes 41 to the M_SerDes 31, which then transmits an interrupt signal M_INT to the SPI / Master 11. Triggered by this interrupt signal M_INT, the SPI / Master 11 starts SPI communication for the next frame. In this way, the SPI / Master 11 does not perform SPI communication for the next frame unless it receives the interrupt signal M_INT. Therefore, the SPI / Master 11 cannot perform SPI communication at high speed.

[0125] Therefore, the SPI / Master 11 according to the third embodiment is able to perform SPI communication of a plurality of consecutive frames without receiving the interrupt signal M_INT, thereby increasing the speed of SPI communication.

[0126] The communication system 2 according to the third embodiment has a block configuration similar to that of FIG. 1, but differs from the communication systems 2 according to the first and second embodiments described above in that the SPI packet generated by the M_SerDes 31 includes a packet ID for identifying the SPI packet, and the SPI / Master 11 performs SPI communication for the next frame without waiting for reception of the interrupt signal M_INT from the M_SerDes 31.

[0127] The M_SerDes 31 synchronizes the timing at which the SPI data received from the S_SerDes 41 is read from the buffer / memory 31-1-2 via the M_MISO pin with the timing at which the M_SerDes 31 transmits the SPI data to the S_SerDes 41 from the M_MOSI pin.

[0128] The SPI / Master 11 also knows in advance the turnaround time required for SPI communication, which is a parameter specific to this system. Here, the turnaround time is the time from when the SPI / Master 11 transmits SPI data to when it receives the corresponding SPI data from the SPI / Slave 12.

[0129] The SPI / Master 11 determines that the SPI data received from the SPI / Slave 12 before the turnaround time has elapsed is invalid and discards it.

[0130] In addition, in order to clearly indicate which packet transmitted by M_SerDes 31 the SPI data received from S_SerDes 41 corresponds to, when generating a transmission packet, ECP 31-2 in M_SerDes 31 adds a packet ID that identifies each individual transmission packet to the corresponding transmission packet.

[0131] 11 is a diagram illustrating information included in a transmission packet generated by the ECP 31-2 according to the third embodiment. In FIG. 11, C-12 is newly added to the information in FIG. 5. The ECP 31-2 in the M_SerDes 31 adds a packet ID to each transmission packet. When returning a transmission packet corresponding to a transmission packet from the M_SerDes 31, the S_SerDes 41 adds the same packet ID as the packet ID added to the transmission packet from the M_SerDes 31.

[0132] The packet ID may be a cyclic number. For example, the packet ID may cycle through the numbers 0 to 1023, and when it reaches 1023, it may cycle back to 0. ECP 31-2 adds the packet ID of a transmission packet to the header of the transmission packet as shown in FIG. 11.

[0133] Fig. 12 is a timing diagram showing communication between the SPI / Master 11 and the SPI / Slave 12 in the third embodiment. Figs. 13A and 13B are flowcharts showing the processing procedure of the communication system 2 according to the third embodiment. Figs. 13A and 13B show the processing procedure when a group of SPI data is transmitted from the SPI / Master 11 to the SPI / Slave 12 within one frame period. The processing operation of the communication system 2 according to the third embodiment will be described below with reference to Figs. 12, 13A, and 13B.

[0134] First, the SPI / Master 11 generates SPI control information to be used by the ECP 31-2 and DCP 31-3 in the M_SerDes 31 and transmits it to the M_SerDes 31 (steps S1 to S4, times t1 to t4). The SPI control information includes, for example, the SPI transmission mode, SCK frequency information, the SPI mode, and the size and number of data blocks DB for SPI communication. The SPI / Master 11 stores the SPI control information in advance in the buffer / memory 11-2.

[0135] The controller 11-3 in the SPI / Master 11 asserts M_CSn(0) to an active state (low) in order to perform SPI communication with the M_SerDes 31 (step S71, time t71).

[0136] The controller 11-3 in the SPI / Master 11 controls the SCK generator 11-4 to output the clock M_SCK (step S72, time t72). In synchronization with the clock M_SCK, the SPI control information stored in the buffer / memory 11-2 is sequentially read out and transferred to the shift register 11-1. The transferred SPI control information includes the transmission mode, SCK frequency information, SPI mode, transmission data size, and number of data blocks. The shift register 11-1 sequentially outputs the SPI control information in synchronization with the clock M_SCK (steps S72 to S73, times t72 to t73). This SPI control information is input to the M_SerDes 31 via the M_MOSI pin. The shift register 31-1-1 in the M_SerDes 31 takes in the SPI control information from the SPI / Master 11 in synchronization with M_SCK.

[0137] While the shift register 31-1-1 takes in the SPI control information from the SPI / Master 11, it transmits the data held in the shift register 31-1-1 to the SPI / Master 11 via the M_MISO pin in synchronization with M_SCK. This data is invalid, so it is indicated by a dashed line between times t72 and t73 in Figure 6. The SPI / Master 11 discards this data after receiving it.

[0138] When the data transfer of the SPI / Master 11 is completed, the controller 11-3 in the SPI / Master 11 causes the SCK generator 11-4 to stop generating M_SCK and deasserts M_CSn(0) to the idle state (step S74, time t74). When M_SCK stops, the shift register 31-1-1 in the M_SerDes 31 transfers the SPI control information held therein from the SPI / Master 11 to the buffer / memory 31-1-2.

[0139] The buffer / memory 31-1-2 in the M_SerDes 31 transfers the SPI control information from the SPI / Master 11 to the ECP 31-2. The ECP 31-2 converts the SPI control information into an SPI packet.

[0140] Next, the SPI / Master 11 transmits SPI data to the M_SerDes 31 for the purpose of transmitting data to the SPI / Slave 12. Specifically, the controller 11-3 in the SPI / Master 11 transitions (asserts) the M_CSn(1) corresponding to the SPI / Slave 12 from the idle state to the active state (step S75, time t75).

[0141] The controller 11-3 also causes the SCK generator 11-4 to output M_SCK (step S76, time t76). The buffer / memory 11-2 reads out the data to be transmitted to the SPI / Slave 12 in an amount equal to the transmission data size and inputs it to the shift register 11-1. The shift register 11-1, in synchronization with M_SCK, sequentially transmits the SPI data for the SPI / Slave 12 to the M_SerDes 31 via the M_MOSI pin (step S77, time t77). The M_SerDes 31 generates a transmission packet including the SPI data from the SPI / Master 11. As described above, a packet ID (e.g., ID=#1) is added to the header of the transmission packet.

[0142] In synchronization with the transmission of SPI data from the shift register via the M_MOSI pin, data from the M_SerDes 31 is input to the shift register 11-1 via the M_MISO pin in synchronization with M_SCK. At this point, the interrupt signal M_INT is not asserted, and as described above, the turnaround time has not yet elapsed, so the SPI / Master 11 determines the data to be invalid and discards it.

[0143] The shift register 31-1-1 in the M_SerDes 31 sequentially takes in the data output from the SPI / Master 11 in synchronization with SCK. When the controller 11-3 in the SPI / Master 11 has completed transferring data equal to the transmission data size, it causes the SCK generator 11-4 to stop outputting M_SCK (step S78, time t78). Thereafter, the controller 11-3 of the SPI / Master 11 sets M_CSn(1) to the idle state (deasserts) to end the SPI communication (step S79, time t79).

[0144] When M_SCK stops, M_SerDes 31 transfers the data held in shift register 31-1-1 to buffer / memory 31-1-2. Buffer / memory 31-1-2 transfers the data transferred from shift register 31-1-1 to ECP 31-2. ECP 31-2 generates a packet including the SPI control information received in the communication from time t71 to t73, a CS signal (M_CSn(1)) corresponding to SPI / Slave 12, and data intended for SPI / Slave 12. ECP 31-2 adds a flag indicating that the packet is valid and a packet ID to the generated packet to generate a transmission packet.

[0145] 8, the ECP 31-2 transmits the generated transmission packet to the DLL 31-4 as an SPI packet 51. The DLL 31-4 combines the SPI packet 51 from the ECP 31-2 with other transmission packets to generate an UP Link packet 52, and outputs it to the PHY layer block 31-5. The PHY layer block 31-5 outputs the received UP Link packet 52 to the cable 103 in accordance with the UP Link output timing based on TDD (step S80, time t80).

[0146] The S_SerDes 41 communicates with the M_SerDes 31 in accordance with the TDD method, and also performs SPI communication with the SPI / Slave 12. A PHY layer block 41-5 in the S_SerDes 41 receives an UP Link Packet from the M_SerDes 31 via the cable 103, and outputs it to a link layer block (DLL) 41-4.

[0147] The link layer block 41-4 in the S_SerDes 41 extracts an SPI packet containing SPI data from the UP Link Packet and outputs it to a packet decoder (DCP) 41-3. The DCP 41-3 detects that the SPI / Slave 12 is the target of SPI communication based on the CSn information (C-2) in the received SPI packet. Then, in order to start SPI communication with the SPI / Slave 12, the controller 41-1-4 detects that all of the SPI data has been transmitted based on the transmission mode information (C-1) in the SPI packet, and obtains the number of SCK cycles required for one SPI communication based on the number of SPI data (C-5) and the size of the SPI data (C-8), and then activates (asserts) the slave select signal S_CS (step S81, time t81).

[0148] Next, the controller 41-1-4 in the S_SerDes 41 acquires the SCK frequency information (C-3) contained in the SPI packet and causes the SCK generator 41-1-3 to output S_SCK at the acquired frequency (step S82, time t82). At this time, the phase relationship between S_CS and SCK complies with the SPI mode (C-4) in the SPI packet. This enables the S_SerDes 41 to transfer SPI data with the SPI / Slave 12. The data transferred to the SPI / Slave 12 is an SPI packet (D-1) and is stored in the buffer / memory 41-1-2.

[0149] The shift register 41-1-1 in the S_SerDes 41 sequentially outputs the SPI data transferred from the buffer / memory 41-1-2 from the S_MOSI pin in response to the SCK supplied from the SCK generator 41-1-3 (step S83, time t83). In parallel with this, the SPI data output from the SPI / Slave 12 to the S_MISO pin is stored in the shift register 41-1-1 and then transferred to the buffer / memory 41-1-2 as appropriate.

[0150] The SPI / Slave 12 sequentially takes in the SPI data from the S_MOSI pin of the S_SerDes 41 into the shift register 12-1 in synchronization with S_SCK, and sequentially outputs the data held in the shift register 12-1 from the S_MISO pin (step S84, time t84).

[0151] After driving S_SCK for the set SPI data size (C-8), the controller 41-1-4 stops SCK and returns S_CS to the idle state (deasserts) to end the SPI communication (step S85, time t85). In parallel with this, while receiving the SPI data from the S_MOSI pin of the S_SerDes 41, the SPI / Slave 12 transfers the SPI data from the S_MOSI pin from the shift register 12-1 to the buffer / memory 12-2 as appropriate, thereby finally completing the reception of data from the SPI / Master 11.

[0152] The buffer / memory 41-1-2 transfers the SPI data received from the SPI / Slave 12 to the packet encoder (ECP) 41-2 to send it to the SPI / Master 11. The ECP 41-2 adds the SPI control information it obtained in the SPI packet to the SPI packet 53 along with the received SPI data. The ECP 41-2 also adds information indicating the operating status of the SPI / Slave 12 (C-10) in FIG. 5, the packet ID (C-12), and the CRC (E-1) to the SPI packet. If the SPI data from the SPI / Slave 12 corresponds to the SPI data from the SPI / Master 11, the packet ID is set to the same ID as the packet ID (=#1) of the transmission packet containing the SPI data from the SPI / Master 11. By making the packet ID the same, the M_SerDes 31 can recognize that a transmission packet responding to the transmission packet sent to the S_SerDes 41 has been received.

[0153] Furthermore, if the SPI / Slave 12 outputs an interrupt signal (C-9), the ECP 41-2 also includes information about the interrupt signal in the SPI packet 53. In this case, the SPI packet 53 does not transmit SPI data from the SPI / Slave 12. The reason for providing an interrupt signal is that, in the SPI protocol, only the SPI / Master 11 controls the CS signal and SCK, and the SPI / Slave 12 cannot actively output data, so it outputs an interrupt signal and waits for instructions from the SPI / Master 11.

[0154] The link layer block (DLL) 41-4 aggregates the SPI packet 53 received from the ECP 41-2 with other transmission packets to generate a down link packet 54, and outputs the down link packet 54 to the PHY layer block 41-5. The PHY layer block 41-5 outputs the received down link packet 54 to the cable 103 in accordance with the down link output timing (step S86, time t86).

[0155] The PHY layer block 31-5 of the M_SerDes 31 receives a Down Link packet including an SPI packet 53 from the SPI / Slave 12 output from the S_SerDes 41, and outputs it to the DLL 31-4. The DLL 31-4 extracts the SPI packet 53 from the received Down Link packet 54, and outputs it to a packet decoder (DCP) 31-3.

[0156] When DCP 31-3 in M_SerDes 31 receives SPI data O_DB#1 from Master 11, it also receives a transmission packet containing I_DB#1, which was sent to Master 11 at the same time, from S_SerDes 41 and stores it in buffer / memory 31-1-2. M_SerDes 31 checks the packet ID attached to the transmission packet, and if it is the same as the packet ID attached to the transmission packet previously generated, it determines that valid SPI data has been returned from SPI / Slave 12, and buffer / memory 31-1-2 asserts interrupt signal M_INT (step S87, time t87). When controller 11-3 of SPI / Master 11 receives interrupt signal M_INT, if the turnaround time has elapsed, it determines that valid SPI data has arrived from SPI / Slave 12, and takes the SPI data input from the M_MISO pin into shift register 11-1.

[0157] The controller 11-3 of the SPI / Master 11 asserts M_CSn(1) (step S88, time t88), then controls the SCK generator 11-4 to output M_SCK(11-10-2) (step S89, time t19). The shift register 11-1 sequentially captures data from the M_MISO pin in synchronization with SCK, the amount of data being the transmission data size (C-8) set in Frame #1. At this time, the buffer / memory 31-1-2 in the M_SerDes 31 transfers data from the SPI / Slave 12 to the shift register 31-1-1 as needed, and the shift register 31-1-1 sequentially outputs the data in synchronization with the SCK generator 11-4, as described above. This data is captured by the M_MISO pin (step S90, time t90). In parallel with this, the SPI / Master 11 reads the SPI data to be transferred next to the SPI / Slave 12 from the buffer / memory 11-2, loads it into the shift register 11-1, and sequentially outputs it from the M_MOSI pin from the shift register 11-1 (step S91, time t91). After the necessary data has been read, the buffer / memory 31-1-2 returns the interrupt signal M_INT to the idle state (deasserts it) (step S92, time t92).

[0158] The operations up to this point complete the transfer of SPI data between the SPI / Master 11 and the SPI / Slave 12. The above series of operations is repeated the number of times necessary to transfer SPI data (step S93, time t93).

[0159] When the SPI / Master 11 reads the last SPI data from the SPI / Slave 12, the SPI / Master 11 asserts M_CSn(1) to output dummy data (step S94, time t94). This dummy data is invalid data and does not need to be transferred to the SPI slave, so it is discarded without being transferred from the shift register 31-1-1 of the M_SerDes 31 to the buffer / memory 31-1-2 (step S95, time t95). The last data from the SPI / Slave 12 is output from the shift register 31-1-1 in the M_SerDes 31 through the M_MISO pin and taken into the shift register 11-1 in the SPI / Master 11 (step S96, time t96).

[0160] As described above, in the third embodiment, when the M_SerDes 31 generates a transmission packet containing SPI data output by the SPI / Master 11, it adds a packet ID to the header of the transmission packet. Then, the S_SerDes 41, which receives this transmission packet, transmits the SPI data contained in the transmission packet to the SPI / Slave 12. When the S_SerDes 41 generates a transmission packet containing SPI data transmitted from the SPI / Slave 12 in response to this SPI data, it identifies which transmission packet from the M_SerDes 31 the transmission packet corresponds to, and adds a packet ID that is the same as the packet ID added to the identified transmission packet from the M_SerDes 31. When the M_SerDes 31 receives this transmission packet and confirms that the packet IDs are the same, it determines that the data is valid SPI data and asserts the interrupt signal M_INT. If the turnaround time has elapsed and the interrupt signal M_INT is asserted, the SPI / Master 11 determines that the data is valid SPI data. Furthermore, the SPI / Master 11 may read the SPI signal from the M_SerDes 31 if the turnaround time has elapsed, even if the interrupt signal M_INT is not asserted.

[0161] According to the third embodiment, since the packet ID can be used to associate a transmitted transmission packet with a received transmission packet, the SPI / Master 11 can continuously transmit multiple pieces of SPI data to the M_SerDes 31 even if the interrupt signal M_INT is not asserted, thereby improving transmission efficiency. Since the SPI / Master 11 knows in advance the turnaround time after transmitting SPI data, it can quickly determine that SPI data received before the turnaround time has elapsed is invalid data.

[0162] (Fourth embodiment) The fourth embodiment is a modification of the third embodiment, in which the process of transmitting divided data within one frame period is repeated over multiple frames. The SPI / Master 11 according to the fourth embodiment is characterized in that it can perform SPI communication of multiple divided data without receiving the interrupt signal M_INT.

[0163] The communication system 2 according to the fourth embodiment has a block configuration similar to that of FIG. 1, but differs from the communication systems 2 according to the first and second embodiments described above in that the SPI packet generated by the M_SerDes 31 includes a packet ID for identifying the SPI packet, and the SPI / Master 11 performs SPI communication for the next frame without waiting for reception of the interrupt signal M_INT from the M_SerDes 31.

[0164] Fig. 14 is a timing diagram showing communication between the SPI / Master 11 and the SPI / Slave 12 in the fourth embodiment. Fig. 15A and Fig. 15B are flowcharts showing the processing procedure of the communication system 2 according to the fourth embodiment. Fig. 15A and Fig. 15B show the processing procedure when transmitting divided data within one frame period.

[0165] Steps S101 to S104 (times t101 to t104) in Fig. 15A are the same as steps S71 to S74 (times t71 to t74) in Fig. 13A, and the SPI / Master 11 generates SPI control information and sets it in the ECP 31-2 and DCP 31-3 in the M_SerDes 31. The processing operations from step S105 onwards are also basically the same as those in Figs. 13A and 13B, but in this embodiment, data to be transmitted in one SPI frame is divided into multiple pieces, and each of the multiple divided data is transmitted in one TDD frame period. A signal transmitted in one TDD frame period is called a TDD burst signal.

[0166] The SPI / Master 11 asserts the CS signal (M_CSn(1)) to start the transmission of SPI data (step S105, time t105). M_CSn(1) continues to be asserted until the transmission of all the divided data is completed.

[0167] The SPI / Master 11 causes the SCK generator 11-4 to output M_SCK in order to transmit each divided data (data block DB) (step S106, time t106). M_SCK is output at a constant cycle until all divided data have been transmitted. The SPI / Master 11 outputs the first divided data O_DB#1 from the shift register 11-1 in synchronization with M_SCK. This divided data O_DB#1 is input to the M_SerDes 31 via the M_MOSI pin, and a transmission packet is generated in the M_SerDes 31. A packet ID (=#1) is added to this transmission packet.

[0168] In synchronization with the output of divided data O_DB#1 from shift register 11-1 to the M_MOSI pin, data is input from M_SerDes 31 to shift register 11-1 via the M_MISO pin. At this point, the turnaround time has not yet elapsed, so SPI / Master 11 determines this data to be invalid and discards it (step S107, time t107).

[0169] While the interrupt signal M_INT is not asserted, the SPI / Master 11 synchronizes with M_SCK and transmits the divided data O_DB#2 and O_DB#3 in sequence to the M_SerDes 31 at a fixed cycle. These divided data are stored in the buffer / memory 31-1-2 in the M_SerDes 31 in sequence.

[0170] The M_SerDes 31 transmits the transmission packet to the S_SerDes 41 at the output timing of the UP Link (step S108, time t108). The S_SerDes 41 acquires the SPI data and packet ID contained in the transmission packet and stores them in the buffer / memory 41-1-2. The S_SerDes 41 asserts a Slave Select signal S_CS for selecting the SPI / Slave 12 (step S109, time t109) and outputs an S_SCK for transmitting the SPI data (step S110, time t110).

[0171] The S_SerDes 41 transmits the SPI data O_DB#1 transferred from the buffer / memory 41-1-2 to the shift register 41-1-1 from the S_MOSI pin to the SPI / Slave 12 in synchronization with SCK (step S111, time t111).

[0172] Furthermore, the shift register 41-1-1 takes in the SPI data output from the SPI / Slave 12 from the S_MISO pin (step S112, time t112). The S_SerDes 41 generates a transmission packet I_DB#1 including the SPI data from the SPI / Slave 12, and adds to the header a packet ID that is the same as the packet ID of the transmission packet received immediately before from the M_SerDes 31. The S_SerDes 41 transmits the transmission packet to the M_SerDes 31 at the output timing of the Down Link (step S113, time t113).

[0173] When the M_SerDes 31 receives a transmission packet from the S_SerDes 41, it stores the SPI data included in the transmission packet in the buffer / memory 31-1-2. The M_SerDes 31 also checks that the packet ID in the header of the transmission packet matches the packet ID of the transmission packet sent immediately before to the S_SerDes 41. When it is confirmed that the packet IDs match, the M_SerDes 31 asserts an interrupt signal M_INT to the SPI / Master 11 (step S114, time t114).

[0174] The SPI / Master 11 determines that the SPI data is valid because the turnaround time has elapsed and the interrupt signal M_INT has been asserted. The shift register in the SPI / Master 11 takes in the SPI data I_DB#1 via the M_MISO pin and transmits the next divided data O_DB#4 from the M_MOSI pin to the M_SerDes 31 (step S115, time t115). Note that the SPI / Master 11 transmits the next divided data at regular intervals even if the M_SerDes 31 does not assert the interrupt signal M_INT.

[0175] Thereafter, the same operation is repeated. The SPI / Master 11 transmits the last divided data O_DB#5 to the M_SerDes 31, and receives SPI data I_DB#2 from the SPI / Slave 12 (step S116, time t116). At this point, SPI data from the SPI / Slave 12 for all of the divided data transmitted by the SPI / Master 11 has not yet arrived. Therefore, the SPI / Master 11 transmits dummy data until all of the SPI data from the SPI / Slave 12 arrives (steps S117 to S119, times t117 to t119). At time t119, the SPI / Master 11 receives the last SPI data from the SPI / Slave 12, and then deasserts M_CSn(1) at time t120 (step S120).

[0176] As described above, in the fourth embodiment, when the SPI / Master 11 transmits multiple pieces of divided data to the M_SerDes 31 by SPI communication to the S_SerDes 41 over multiple frame periods of the TDD system, the SPI / Master 11 can continuously transmit the multiple pieces of divided data even if the interrupt signal M_INT from the M_SerDes 31 is not asserted. This improves the transmission efficiency of SPI data. Furthermore, when the M_SerDes 31 transmits transmission packets including each piece of divided data to the S_SerDes 41, the M_SerDes 31 adds a packet ID to the header of the transmission packet. Upon receiving this transmission packet, the S_SerDes 41, upon generating a transmission packet including SPI data from the SPI / Slave 12, identifies which transmission packet from the M_SerDes 31 the transmission packet corresponds to, and adds the same packet ID as the packet ID added to the identified transmission packet from the M_SerDes 31. As a result, the M_SerDes 31 that receives this transmission packet can check the correspondence between the transmitted transmission packet and the received transmission packet using the packet ID. Therefore, the M_SerDes 31 can assert the interrupt signal M_INT after checking whether the SPI data included in the received transmission packet is valid. Furthermore, if the turnaround time has elapsed and the interrupt signal M_INT is asserted, the SPI / Master 11 can determine that the SPI data is valid. Furthermore, if the turnaround time has elapsed, the SPI / Master 11 may read the SPI signal from the M_SerDes 31 even if the interrupt signal M_INT has not been asserted.

[0177] (Fifth embodiment) In the fifth embodiment, an SPI / Master 11 performs serial communication with a plurality of SPI / Slaves 12.

[0178] Fig. 16 is a block diagram of the main parts of a communication system 2 including a communication device according to the fifth embodiment. Fig. 16 shows an S_SerDes 41 and a plurality of SPI / Slaves 12. The internal configurations of the SPI / Slaves 12 and M_SerDes 31 are the same as those in Fig. 1, and therefore are omitted from Fig. 16. In Fig. 16, the same reference numerals are used to designate components that are common to Fig. 1.

[0179] The SPI / Master 11 specifies the CSn signal of the SPI / Slave 12 with which it wishes to communicate in the SPI control information sent to the M_SerDes 31. The controller 41-1-4 in the S_SerDes 41 activates the CSn signal specified by the SPI / Master 11. Fig. 16 shows an example in which two SPI / Slave 12_1 and SPI / Slave 12_2 are connected to the S_SerDes 41.

[0180] When the SPI / Master 11 wishes to perform data communication with the SPI / Slave 12_1, it sets the CSn signal in the SPI control signal to CS1. This causes the controller 41-1-4 in the S_SerDes 41 to activate the S_CS1 pin that outputs the CS1 signal. The CS1 signal from the S_CS1 pin is input to the SPI / Slave 12_1, so that the SPI / Slave 12_1 receives SPI data in synchronization with S_SCK from the S_SerDes 41 and transmits SPI data to the S_SerDes 41 in synchronization with S_SCK.

[0181] Furthermore, when the SPI / Master 11 wishes to perform data communication with the SPI / Slave 12_2, it sets the CSn signal in the SPI control signal to CS2. This causes the controller 41-1-4 in the S_SerDes 41 to activate the S_CS2 pin that outputs the CS2 signal. The CS2 signal from the S_CS2 pin is input to the SPI / Slave 12_2, so that the SPI / Slave 12_2 receives SPI data in synchronization with S_SCK from the S_SerDes 41 and transmits SPI data to the S_SerDes 41 in synchronization with S_SCK.

[0182] In the communication system 2 of Figure 16, an example is shown in which the SPI / Master 11 specifies the SPI / Slave 12 with which it wants to communicate using the CSn signal in the SPI control signal, but multiple SPI / Slaves 12 may be daisy-chain connected as shown in Figure 17.

[0183] Fig. 17 is a block diagram of the main parts of a communication system 2 including a communication device according to a modified example of Fig. 16. Fig. 17 shows two SPI / Slaves 12 that can perform serial communication simultaneously with the SPI / Master 11, but three or more SPI / Slaves 12 may be configured to be able to perform serial communication simultaneously with the SPI / Master 11.

[0184] The shift registers 12-1 in the two SPI / Slaves 12_1 and 12_2 in FIG. 17 are daisy-chained together, and data output from the MSB of the shift register 12-1 in the SPI / Slave 12_2 in synchronization with SCK is input to the LSB of the shift register 12-1 in the SPI / Slave 12_1, and data output from the MSB is transmitted to the S_SerDes 41 via SPI communication.

[0185] In the communication device of FIG. 17, it is necessary to repeat the processing of steps S24 to S26 of FIG.

[0186] As described above, in the fifth embodiment, the SPI / Master 11 can specify each SPI / Slave 12 with a CSn signal in the SPI control information, thereby enabling bidirectional serial communication with multiple SPI / Slaves 12. Furthermore, by daisy-chaining multiple SPI / Slaves 12, the SPI / Master 11 can simultaneously perform serial communication with multiple SPI / Slaves 12.

[0187] The present technology can be configured as follows: (1) A communication device comprising a communication unit that adds identification information for identifying a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock, and transmits the data blocks to a communication partner device within one frame period of a specified communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmits the data blocks to the communication partner device over a plurality of frame periods. (2) a memory that stores a first group of serial signals conforming to the SPI and transmitted from the master in synchronization with the clock, and stores a second group of serial signals conforming to the SPI and transmitted from the slave in synchronization with the clock; a packet encoder that converts the first serial signal group stored in the memory into a first packet of the predetermined communication protocol and adds the identification information to the first packet; The communication device according to (1), further comprising: a packet decoder that converts second packets of a predetermined communication protocol received from the communication partner device into the second group of serial signals. (3) The communication device according to (2), wherein the packet encoder selects the identification information from a plurality of identification information candidates in rotation. (4) A communication device described in (2) or (3), wherein the first packet includes frequency information of the clock, polarity information, and phase information of the clock relative to the data signal of the first serial signal group conforming to the SPI. (5) A communication device described in any one of (2) to (4), wherein the first packet includes information indicating that the first packet includes a single data block within the one frame period, or information indicating that the first packet includes multiple data blocks divided according to the multiple frame periods. (6) The communication device according to (5), wherein, when the first packet includes the plurality of data blocks, the first packet includes the total number of the plurality of data blocks and division position information of the data blocks. (7) A communication device described in any one of (2) to (6), wherein the second packet includes at least one of identification information of the second packet, information indicating the operating status of the slave, and interrupt information from the slave. (8) The communication device described in (7), wherein the memory sends an interrupt signal to the master when it confirms that data has been sent from the slave through interrupt information from the slave and that the identification information of the first packet matches the identification information of the second packet. (9) A communication device described in (7) or (8), wherein the packet encoder generates the first packet based on the first group of serial signals transmitted from the master, regardless of whether interrupt information is received from the slave. (10) A communication device described in any one of (2) to (9), wherein the first packet includes information of a slave select signal included in the first serial signal group conforming to the SPI that selects the communication partner device or the slave. (11) The communication device according to (10), wherein the packet encoder transmits the first packet to the communication partner device or the slave selected by the slave select signal. (12) A communication device according to any one of (2) to (11), comprising a shift register that stores each serial signal included in the first serial signal group in the memory in sequence in synchronization with the clock, and transmits each serial signal included in the second serial signal group to the master in sequence in synchronization with the clock. (13) The communication device described in (12), wherein the shift register transmits a valid second serial signal group to the master when the identification information contained in the second packet before conversion to the second serial signal group matches the identification information contained in the first packet transmitted to the communication partner device before the second packet was received. (14) A communication device described in any one of (2) to (13), wherein the communication unit transmits the first packet at a first timing specified in the specified communication protocol and receives the second packet at a second timing specified in the specified communication protocol. (15) The communication device described in (14), wherein the communication unit transmits and receives the first packet during a first period within each frame period and transmits and receives the second packet during a second period within each frame period with the communication partner device using the communication protocol corresponding to TDD (Time Division Duplex). (16) A communication device comprising a communication unit that, in synchronization with a clock generated based on clock frequency information included in a packet from a communication partner device, adds identification information to identify a group of data blocks including a group of serial signals conforming to an SPI transmitted from a slave, and transmits the data block to the communication partner device within one frame period of a predetermined communication protocol, or adds identification information to identify each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the communication partner device over a plurality of frame periods. (17) a packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first serial signal group that complies with SPI; a clock generator that generates the clock based on the clock frequency information included in the first group of serial signals; a memory that stores the first group of serial signals in synchronization with the clock and that stores a second group of serial signals that conforms to the SPI and that are transmitted from a slave in synchronization with the clock; The communication device described in (16) further comprises a packet encoder that converts the second group of serial signals stored in the memory into a second packet of the predetermined communication protocol and adds the identification information to the second packet. (18) The communication device described in (17), wherein when the packet encoder transmits the second packet to the communication partner device in response to the first packet received from the communication partner device, the packet encoder adds identification information to the second packet that is the same as the identification information contained in the first packet. (19) A communication device described in (17) or (18), wherein the second packet includes information indicating that the second packet includes a single data block transmitted within one frame period of the second serial signal group, or information indicating that the second packet includes multiple data blocks transmitted divided over multiple frame periods. (20) The communication device according to any one of (17) to (19), wherein the second packet includes interrupt information requesting the master to read the status of the slave. (21) A communication device described in any one of (17) to (20), further comprising a shift register that stores each serial signal included in the second serial signal group in the memory and transmits each serial signal included in the first serial signal group to the slave. (22) A communication device described in any one of (17) to (20), wherein the communication unit transmits the second packet at a first timing specified in the specified communication protocol and receives the first packet at a second timing specified in the specified communication protocol. (23) The communication device described in (22), wherein the communication unit transmits and receives the first packet during a first period within each frame period and transmits and receives the second packet during a second period within each frame period with the communication partner device using the communication protocol corresponding to TDD (Time Division Duplex). (24) A first communication device and a second communication device are provided to transmit and receive packets using a predetermined communication protocol, the first communication device has a first communication unit that adds identification information for identifying a group of data blocks, including a group of serial signals conforming to SPI (Serial Peripheral Interface) and transmitted from a master in synchronization with a clock, to the second communication device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks, each of which includes a portion of the group of serial signals, to the second communication device within a plurality of frame periods; The second communication device a second communication unit that, in synchronization with a clock generated based on clock frequency information included in a packet from the first communication device, adds identification information to identify a group of data blocks including a group of serial signals conforming to SPI transmitted from a slave, and transmits the data block to the first communication device within one frame period of a predetermined communication protocol; or adds identification information to identify each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the first communication device over a plurality of frame periods. (25) A communication method in which a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock is added with identification information identifying the data block, and the data block is transmitted to a communication partner device within one frame period of a predetermined communication protocol, or a plurality of data blocks each including a portion of the group of serial signals are added with identification information identifying each of the plurality of data blocks, and the data blocks are transmitted to the communication partner device over a plurality of frame periods.

[0188] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0189] 1a Communication device 1b Communication device, 2 Communication system, 11 SPI / Master 11-1 Sequential shift register 11-1 Shift register, 11-2 Buffer / memory, 11-3 Controller, 11-4 SCK generator, 12 SPI / Slave, 12-1 Shift register, 12-2 Buffer / memory, 31 M_SerDes, 31-1 SPI block, 31-1-1 Shift register, 31-1-2 Buffer / memory, 31-3 Packet decoder (DCP), 31-5 PHY layer block, 32 Peripheral device, 41 S_SerDes, 41-1 SPI block, 41-1-1 Shift register, 41-1-2 Buffer / memory, 41-1-3 SCK generator, 41-1-4 Controller, 41-2 Packet encoder (ECP), 41-3 Packet decoder (DCP), 41-4 Link layer block (DLL), 41-5 PHY layer block, 42 ​​peripheral device, 103 cable

Claims

1. a communication unit that adds identification information for identifying a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock, and transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmits the data blocks to the communication partner device over a plurality of frame periods; a memory that stores a first group of serial signals conforming to the SPI and transmitted from the master in synchronization with the clock, and stores a second group of serial signals conforming to the SPI and transmitted from the slave in synchronization with the clock; a packet encoder that converts the first serial signal group stored in the memory into a first packet of the predetermined communication protocol and adds the identification information to the first packet; a packet decoder that converts second packets of a predetermined communication protocol received from the communication partner device into the second group of serial signals.

2. The communication device according to claim 1 , wherein the packet encoder selects the identification information from a plurality of identification information candidates in a rotating manner.

3. 3. The communication device according to claim 1, wherein the first packet includes frequency information of the clock, polarity information, and phase information of the clock relative to the data signals of the first group of serial signals conforming to the SPI.

4. 4. The communication device according to claim 1, wherein the first packet includes information indicating that the first packet includes a group of data blocks within the one frame period, or information indicating that the first packet includes a plurality of data blocks divided according to the plurality of frame periods.

5. The communication device according to claim 4 , wherein, when the first packet includes the plurality of data blocks, the first packet includes a total number of the plurality of data blocks and division position information of the data blocks.

6. The communication device according to claim 1 , wherein the second packet includes at least one of identification information of the second packet, information indicating an operating state of the slave, and interrupt information from the slave.

7. 7. The communication device according to claim 6, wherein the memory transmits an interrupt signal to the master when it is confirmed by interrupt information from the slave that data has been transmitted from the slave and when it is confirmed that the identification information of the first packet matches the identification information of the second packet.

8. 8. The communication device according to claim 6, wherein the packet encoder generates the first packet based on the first serial signal group transmitted from the master, regardless of whether interrupt information from the slave is received.

9. 9. The communication device according to claim 1, wherein the first packet includes information of a slave select signal included in the first serial signal group conforming to the SPI for selecting the communication partner device or the slave.

10. The communication device according to claim 9 , wherein the packet encoder transmits the first packet to the communication partner device or the slave selected by the slave select signal.

11. 11. The communication device according to claim 1, further comprising a shift register that sequentially stores each serial signal included in the first serial signal group in the memory in synchronization with the clock, and sequentially transmits each serial signal included in the second serial signal group to the master in synchronization with the clock.

12. 12. The communication device according to claim 11, wherein the shift register transmits a valid second serial signal group to the master when identification information included in the second packet before conversion into the second serial signal group matches identification information included in the first packet transmitted to the communication partner device before the second packet was received.

13. 13. The communication device according to claim 1, wherein the communication unit transmits the first packet at a first timing defined by the predetermined communication protocol, and receives the second packet at a second timing defined by the predetermined communication protocol.

14. 14. The communication device according to claim 13, wherein the communication unit transmits and receives the first packet during a first period within each frame period and transmits and receives the second packet during a second period within each frame period with the communication partner device using the communication protocol corresponding to TDD (Time Division Duplex).

15. a communication unit that adds identification information for identifying a group of data blocks including a group of serial signals conforming to SPI transmitted from a slave in synchronization with a clock generated based on clock frequency information contained in a packet from the communication partner device, and transmits the data block to the communication partner device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the communication partner device over a plurality of frame periods; a packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first serial signal group that complies with SPI; a clock generator that generates the clock based on the clock frequency information included in the first group of serial signals; a memory that stores the first group of serial signals in synchronization with the clock and stores a second group of serial signals that conforms to the SPI and that are transmitted from a slave in synchronization with the clock; a packet encoder that converts the second serial signal group stored in the memory into second packets of the predetermined communication protocol and adds the identification information to the second packets.

16. 16. The communication device according to claim 15, wherein when the packet encoder transmits the second packet to the communication partner device in response to the first packet received from the communication partner device, the packet encoder adds the same identification information to the second packet as the identification information included in the first packet.

17. 17. The communication device according to claim 15, wherein the second packet includes information indicating that the second packet includes a group of data blocks transmitted within one frame period of the second serial signal group, or information indicating that the second packet includes a plurality of data blocks transmitted divided over a plurality of frame periods.

18. 18. The communication device according to claim 15, wherein the second packet includes interrupt information requesting the master to read the status of the slave.

19. 19. The communication device according to claim 15, further comprising a shift register that stores each serial signal included in the second serial signal group in the memory and transmits each serial signal included in the first serial signal group to the slave.

20. 19. The communication device according to claim 15, wherein the communication unit transmits the second packet at a first timing defined by the predetermined communication protocol, and receives the first packet at a second timing defined by the predetermined communication protocol.

21. 21. The communication device according to claim 20, wherein the communication unit transmits and receives the first packet during a first period within each frame period and transmits and receives the second packet during a second period within each frame period with the communication partner device using the communication protocol according to TDD (Time Division Duplex).

22. a first communication device and a second communication device for transmitting and receiving packets in accordance with a predetermined communication protocol; The first communication device a first communication unit that adds identification information for identifying a group of data blocks including a group of serial signals conforming to an SPI (Serial Peripheral Interface) transmitted from a master in synchronization with a clock, and transmits the data block to the second communication device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmits the data block to the second communication device over a plurality of frame periods; a first memory that stores a first group of serial signals conforming to the SPI and transmitted from the master in synchronization with the clock, and stores a second group of serial signals conforming to the SPI and transmitted from the slave in synchronization with the clock; a first packet encoder that converts the first serial signal group stored in the first memory into a first packet of the predetermined communication protocol and adds the identification information to the first packet; a first packet decoder that converts second packets of a predetermined communication protocol received from the second communication device into the second serial signal group; the second communication device, a second communication unit that adds identification information for identifying a group of data blocks including a serial signal group conforming to an SPI transmitted from a slave in synchronization with a clock generated based on clock frequency information contained in a packet from the first communication device, and transmits the data block to the first communication device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of a plurality of data blocks including portions of the serial signal group, to the plurality of data blocks, and transmits the data block to the first communication device over a plurality of frame periods; a second packet decoder that converts a first packet of a predetermined communication protocol received from the first communication device into a first serial signal group that complies with SPI; a clock generator that generates the clock based on the clock frequency information included in the first group of serial signals; a second memory that stores the first group of serial signals in synchronization with the clock and stores a second group of serial signals conforming to the SPI that are transmitted from a slave in synchronization with the clock; a second packet encoder that converts the second group of serial signals stored in the second memory into second packets of the predetermined communication protocol and adds the identification information to the second packets.

23. adding identification information for identifying a group of data blocks including a group of serial signals conforming to SPI (Serial Peripheral Interface) transmitted from the master in synchronization with a clock, and transmitting the data blocks to a communication partner device within one frame period of a predetermined communication protocol; or adding identification information for identifying each of a plurality of data blocks including portions of the group of serial signals, and transmitting the data blocks to the communication partner device over a plurality of frame periods; storing a first group of serial signals conforming to the SPI and transmitted from the master in synchronization with the clock, and storing in a memory a second group of serial signals conforming to the SPI and transmitted from the slave in synchronization with the clock; converting the first serial signal group stored in the memory into a first packet of the predetermined communication protocol, and adding the identification information to the first packet; A communication method, comprising converting second packets of a predetermined communication protocol received from the communication partner device into the second group of serial signals.

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