Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of reducing a drain-source voltage surge.SOLUTION: A silicon carbide semiconductor device 30 includes a first semiconductor layer 2 containing silicon carbide, a plurality of first semiconductor pillar regions 3 of a first conductivity type containing silicon carbide, and a second semiconductor pillar region 4 of a second conductivity type containing silicon carbide. Each first semiconductor pillar region includes a first region 3a having a first impurity concentration and a second region 3b arranged side by side with the first region in a second direction perpendicular to a first direction from a first electrode (drain electrode 31) toward a second electrode (source electrode 37) and having a second impurity concentration higher than the first impurity concentration, and is provided between the first semiconductor layer and the second electrode. The second semiconductor pillar region includes a third region 4a having a third impurity concentration and a fourth region 4b arranged side by side with the third region in the second direction and having a fourth impurity concentration higher than the third impurity concentration, and is provided between the first semiconductor layer and the second electrode and located between the first semiconductor pillar regions in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a silicon carbide semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices made of silicon carbide and used for power control are expected to have higher breakdown voltage than semiconductor devices made of silicon. For example, when switching high voltages, drain-source voltage (Vds) surges can occur during turn-off operations, and it is desirable to reduce these Vds surges. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-064659 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An embodiment of the present invention provides a silicon carbide semiconductor device capable of reducing drain-source voltage (Vds) surges. [Means for solving the problem]

[0005] According to an embodiment, a silicon carbide semiconductor device includes a first electrode, a second electrode, a first semiconductor layer including silicon carbide provided between the second electrode, the first electrode, and the second electrode, a plurality of first semiconductor pillar regions of a first conductivity type including silicon carbide, and a second semiconductor pillar region of a second conductivity type including silicon carbide. The first semiconductor pillar regions include a first region having a first impurity concentration and a second region aligned with the first region in a second direction orthogonal to a first direction from the first electrode toward the second electrode and having a second impurity concentration higher than the first impurity concentration, and are provided between the first semiconductor layer and the second electrode. The second semiconductor pillar regions include a third region having a third impurity concentration and a fourth region aligned with the third region in the second direction and having a fourth impurity concentration higher than the third impurity concentration, and are provided between the first semiconductor layer and the second electrode and are located between the first semiconductor pillar regions in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a first embodiment. [Figure 2] 2A and 2B are views showing examples of plane patterns of a first semiconductor pillar region and a second semiconductor pillar region of the silicon carbide semiconductor device according to the first embodiment. [Figure 3] 2A and 2B are views showing examples of plane patterns of a first semiconductor pillar region and a second semiconductor pillar region of the silicon carbide semiconductor device according to the first embodiment. [Figure 4] FIG. 1 is a schematic cross-sectional view showing an example of a mask. [Figure 5] 1 is a flowchart showing an example of a method for forming a superjunction layer. [Figure 6] FIG. 1 is a schematic cross-sectional view showing an example of a mask. [Figure 7] FIG. 2 is a graph showing an example of a profile of n-type impurity concentration in the silicon carbide semiconductor device according to the first embodiment. [Figure 8] FIG. 2 is a graph showing an example of a profile of p-type impurity concentration in the silicon carbide semiconductor device according to the first embodiment. [Figure 9]3 is a conceptual diagram showing the expansion of a depletion layer at the time of turn-off in the silicon carbide semiconductor device of the first embodiment and a semiconductor device of a comparative example. FIG. [Figure 10] 10 is a graph illustrating the change in Vds shown in FIG. 9. [Figure 11] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a sixth embodiment. [Figure 16] FIG. 13 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to a seventh embodiment. [Figure 17] FIG. 13 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to an eighth embodiment. [Figure 18] FIG. 10 is a diagram for explaining simulation conditions. [Figure 19] FIG. 10 is a diagram showing an example of a simulation result. [Figure 20] FIG. 10 is a diagram showing an example of a simulation result. [Figure 21] FIG. 10 is a diagram showing an example of a simulation result. [Figure 22] FIG. 10 is a diagram showing an example of a simulation result. [Figure 23] FIG. 10 is a diagram showing an example of a simulation result. [Figure 24] FIG. 10 is a diagram for explaining other simulation conditions. [Figure 25] FIG. 10 is a diagram showing an example of another simulation result. [Figure 26] FIG. 10 is a diagram showing an example of another simulation result. [Figure 27] FIG. 10 is a diagram showing an example of another simulation result. [Figure 28]FIG. 10 is a diagram showing an example of another simulation result. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) 1 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device 30 made of silicon carbide (SiC). In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, for example. In FIG. 1, the direction from the drain electrode (first electrode) 31 to the source electrode (second electrode) 37 is defined as a first direction, and the direction perpendicular to the first direction is defined as a second direction. The direction perpendicular to the first and second directions is defined as a third direction.

[0009] FIG. 1 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device 30 according to this embodiment.

[0010] The substrate 1 is, for example, a single crystal bulk substrate made of silicon carbide. In this embodiment, the substrate 1 is, for example, an n-type substrate. The concentration of n-type impurities contained in the substrate 1 is, for example, 1×10 20 / cm 3 The thickness of the substrate 1 is, for example, 350 μm to 500 μm. The n-type impurity is, for example, nitrogen (N) or phosphorus (P).

[0011] The semiconductor layer 2 is formed on the main surface of the substrate 1 by epitaxial growth using silicon carbide as a material. The semiconductor layer 2 is, for example, n-type. The concentration of n-type impurities in the semiconductor layer 2 is, for example, 1×10 18 / cm 3 The thickness of the semiconductor layer 2 is, for example, 3 μm.

[0012] A superjunction layer SJ made of silicon carbide is stacked in a direction (first direction) substantially perpendicular to the major surface of the semiconductor layer 2. The superjunction layer SJ is formed to have a periodic structure in which first semiconductor pillar regions 3 and second semiconductor pillar regions 4 are alternately arranged in a direction (second direction) substantially parallel to the major surface of the semiconductor layer 2.

[0013] The first semiconductor pillar region 3 is an n-type pillar region containing n-type impurities. The first semiconductor pillar region 3 includes a first region 3a having a first concentration (first impurity concentration) and a second region 3b having a second concentration (second impurity concentration) higher than the first concentration. In addition, in a direction (second direction) substantially parallel to the major surface of the semiconductor layer 2, the second region 3b is formed between the two first regions 3a. In this embodiment, the conductivity type of the first semiconductor pillar region 3 is, for example, n-type. The n-type impurity is, for example, nitrogen (N) or phosphorus (P). The first concentration of the first region 3a is 1×10 16 / cm 3 ~1×10 17 / cm 3 However, in this embodiment, for example, 5×10 16 / cm 3 The second concentration of the second region 3b is 5×10 16 / cm 3 ~5×10 17 / cm 3 However, in this embodiment, for example, 1×10 17 / cm 3 The width (½) W of the first region 3a is, for example, 0.5 μm, and the width W of the second region 3b is, for example, 1.0 μm. In this embodiment, the term “width” refers to the length in a direction substantially parallel to the major surface of the semiconductor layer 2.

[0014] The second semiconductor pillar region 4 is a p-type pillar region containing p-type impurities. The second semiconductor pillar region 4 has a third concentration (third impurity concentration). 3 The second semiconductor pillar region 4 includes a region 4a and a fourth region 4b having a fourth concentration (fourth impurity concentration) higher than the third concentration. In addition, in a direction (second direction) substantially parallel to the major surface of the semiconductor layer 2, the fourth region 4b is formed between two third regions 4a. In this embodiment, the conductivity type of the second semiconductor pillar region 4 is, for example, p-type. The second impurity is, for example, boron (B) or aluminum (Al). The third concentration of the third region 4a is 1×10 16 / cm 3 ~1×10 17 / cm 3 However, in this embodiment, for example, 5×10 16 / cm 3 The fourth concentration of the fourth region 4b is 5×10 16 / cm 3 ~5×10 17 / cm 3 However, in this embodiment, for example, 1×10 17 / cm 3 The width (1 / 2) W of the third region 4a is, for example, 0.5 μm, and the width W of the fourth region 4b is, for example, 1.0 μm.

[0015] The first semiconductor pillar region 3 and the second semiconductor pillar region 4 are formed to a predetermined pillar depth by repeating epitaxial growth and ion implantation of n-type impurities and p-type impurities. The thickness of the superjunction layer SJ formed in this manner is, for example, 10.0 μm. The thickness of one epitaxially grown layer is preferably, for example, 0.5 μm to 4.0 μm, but in this embodiment, it is, for example, 2.0 μm. The withstand voltage of the semiconductor element composed of the substrate 1, semiconductor layer 2, and superjunction layer SJ is, for example, 1200 V.

[0016] The planar pattern of the first semiconductor pillar region 3 and the second semiconductor pillar region 4 on the main surface of the semiconductor layer 2 may be a stripe pattern extending in the third direction as shown in Fig. 2, or may be an island pattern as shown in Fig. 3. In Fig. 3, the second semiconductor pillar region 4 is a rectangular region. , th The first semiconductor pillar region 3 is a rectangular region that surrounds the second semiconductor pillar region 4. In Figures 2 and 3, AR indicates an active region, and Figure 1 shows a cross-sectional structure within the active region AR.

[0017] A drain electrode 31 is formed on the surface of the substrate 1 opposite to the surface on which the semiconductor layer 2 is formed. A p-base 32 is formed on the upper surface of the superjunction layer SJ. The p-base 32 is formed on the upper side of the second semiconductor pillar region 4 so that both ends are connected to parts of the second region 3b of the adjacent first semiconductor pillar region 3. A source layer 33 is formed on part of the upper surface of the p-base 32. The central portion of the source layer 33 is formed of the same p-type as the region 4b, and the end portions are formed of n-type. Pillars 34 are formed between each p-base 32. The pillars 34 are, for example, n-type.

[0018] An insulating film 35 is formed so as to overlap the ends of two adjacent source layers 33. The insulating film 35 includes a gate electrode 36. The source layer 33 side of the insulating film 35 is made of silicon dioxide (SiO2). The opposite side of the insulating film 35 to the source layer 33 is made of silicon dioxide. The gate electrode 36 is, for example, a p-type gate electrode made of polysilicon doped with boron. It may also be an n-type gate electrode doped with phosphorus. A source electrode 37 is formed on the source layer 33 and the insulating film 35. That is, the silicon carbide semiconductor device 30 of this embodiment is a planar gate SJ-MOSFET (metal-oxide-semiconductor field-effect transistor) type silicon carbide semiconductor device.

[0019] Next, a method of forming superjunction layer SJ of silicon carbide semiconductor device 30 will be described. FIG. 4 is a schematic cross-sectional view illustrating a mask used in forming the superjunction layer SJ, and FIG. 5 is a flowchart showing an example of a method for forming the superjunction layer SJ.

[0020] 4, for example, four masks M11 to M14 are used to form the superjunction layer SJ. To clearly show the differences between the masks M11 to M14, the masks M11 to M14 are shown arranged above the first semiconductor pillar region 3 and the second semiconductor pillar region 4. Mask M11 is a mask used to form the first region 3a, mask M12 is a mask used to form the second region 3b, mask M13 is a mask used to form the third region 4a, and mask M14 is a mask used to form the fourth region 4b. For this reason, the openings of masks M11 to M14 are the same size as the first region 3a, the second region 3b, the third region 4a, and the fourth region 4b, respectively. Each of the masks M11 to M14 is an ion implantation mask formed by photolithography and dry etching on an SiO2 film (UDO: Undoped Oxide) having a thickness sufficient to block ion implantation and deposited on the main surface of the superjunction layer SJ by a CVD (Chemical Vapor Deposition) method. The thickness of the SiO2 mask is preferably 0.5 μm to 2.0 μm, for example, 1 μm. The mask material and thickness may be appropriately selected to have sufficient ion implantation blocking ability.

[0021] 5, for example, an epitaxial growth layer made of silicon carbide is formed on a substrate 1 or above the previously formed first semiconductor pillar region 3 and second semiconductor pillar region 4 (ST101). Next, a mask M11 is placed above the epitaxial growth layer (ST102), and n-type impurities are ion-implanted into the portion corresponding to the first region a so that the portion corresponding to the first region 3a has a first concentration (ST103).

[0022] Next, a mask M12 is placed on the upper side of the epitaxial growth layer (ST104), and n-type impurities are ion-implanted into the portion corresponding to the second region 3b, thereby forming the first region 3 a The portion corresponding to the third region 4a is implanted with a second concentration (ST105). Next, a mask M13 is placed above the epitaxial growth layer (ST106), and p-type impurities are ion-implanted into the portion corresponding to the third region 4a, so that the portion corresponding to the third region 4a has a third concentration (ST107). Next, a mask M14 is placed above the epitaxial growth layer (ST108), and p-type impurities are ion-implanted into the portion corresponding to the fourth region 4b, so that the portion corresponding to the fourth region 4b has a fourth concentration (ST109).

[0023] Then, it is determined whether stacking is complete (ST110). If the specified stacking is not complete (ST110: NO), the process returns to step ST101, and the processes of steps ST101 to ST109 are executed. If stacking is complete (ST110: YES), the formation of p-base 32 and the like, annealing treatment, etc. are performed to complete the semiconductor device (ST111). As a result, the first region 3a of the first concentration and the second region 3b of the second concentration are formed. b , a third region 4a of a third concentration and a fourth region 4b of a fourth concentration are formed.

[0024] In this specific example, the first region 3a, the second region 3b, the third region 4a, and the fourth region 4b are formed using the masks M11 to M14 described in FIG. 4, but this is not limited to this, and masks M21 to M24 shown in FIG. 6 may also be used. The openings of masks M21 and M23 correspond to the first semiconductor pillar region 3 (first region 3a, second region 3b) and the second semiconductor pillar region 4 (third region 4a, fourth region 4b), respectively, and the openings of masks M22 and M24 correspond to the second region 3b and the fourth region 4b, respectively. When these masks M21 to M24 are used, first, impurities are ion-implanted into the first semiconductor pillar region 3 using mask M21 to form a region with a first concentration, and then mask M22 is used to form the second region 3b with a second concentration. Similarly, impurities are ion-implanted into the second semiconductor pillar region 4 using mask M23 to form a region with a third concentration, and then impurities are ion-implanted into the second semiconductor pillar region 4 using mask M24 to form the fourth region 4b with a fourth concentration. In this manner, the superjunction layer SJ may be formed.

[0025] Next, the impurity concentration profile of silicon carbide semiconductor device 30 will be described. Fig. 7 shows a profile of n-type impurity concentration, and Fig. 8 shows a profile of p-type impurity concentration. The profiles shown in Fig. 7 and Fig. 8 are profiles of impurity concentration at a predetermined depth and in the cross section of the superjunction layer SJ shown in Fig. 1, for example. In this specification, "impurity concentration" refers to the effective impurity concentration that contributes to the conduction of a semiconductor, and when a certain region contains both impurities that act as donors and impurities that act as acceptors, it refers to the concentration excluding the offset amounts.

[0026] As shown in Fig. 7, the n-type impurity profile has a first concentration in the two first regions 3a and a second concentration in the second region 3b between the two first regions 3a. Also, as shown in Fig. 8, the p-type impurity profile has a third concentration in the two second regions 3b and a fourth concentration in the fourth region 4b between the two third regions 4a. In this way, the n-type impurity and p-type impurity profiles are stepped, forming so-called box profiles.

[0027] Next, the operation of silicon carbide semiconductor device 30 will be described. In the silicon carbide semiconductor device 30, when a predetermined voltage is applied to the gate electrode 36, a channel is formed near the surface of the p-base 32 directly below the gate electrode 36, thereby establishing electrical continuity between the source layer 33 and the first semiconductor pillar regions 3a and 3b. As a result, a main current path is formed between the source electrode 37 and the drain electrode 31 via the source layer 33, the first semiconductor pillar regions 3a and 3b, and the semiconductor layer 2, thereby establishing an ON state between these main electrodes. In this manner, the silicon carbide semiconductor device 30 is configured to be electrically conductive. Furthermore, when the voltage applied to the gate electrode 36 is stopped, the channel formed near the surface of the p-base 32 directly below the gate electrode 36 disappears, thereby disabling electrical continuity between the source layer 33 and the first semiconductor pillar regions 3a and 3b. As a result, no main current path is formed between the source electrode 37 and the drain electrode 31, thereby establishing an OFF state between these main electrodes. In this manner, the silicon carbide semiconductor device 30 can be switched between an ON state and an OFF state. Switching from an ON state to an OFF state is called a turn-off, and switching from an OFF state to an ON state is called a turn-on.

[0028] FIG. 9 is a conceptual diagram showing the expansion of the depletion layer at turn-off in the silicon carbide semiconductor device 30 of this embodiment and a semiconductor device of a comparative example. FIG. 9(a) shows the expansion of the depletion layer DL in the first semiconductor pillar region 3 and the second semiconductor pillar region 4 of the silicon carbide semiconductor device 30, and FIG. 9(b) shows the expansion of the depletion layer DL in the n-type pillar region 13 and the p-type pillar region 14 of the comparative example. FIGS. 9(a) and 9(b) show the expansion of the depletion layer DL from the pn interface, showing changes over time in four stages from top to bottom. Also, in FIGS. 9(a) and 9(b), Vds also increases over time. The pillar regions 13 and 14 of the comparative example have approximately uniform impurity concentrations, i.e., the silicon carbide semiconductor device 30 of this embodiment does not have the first region 3a and the third region 4a.

[0029] In both cases, the depletion layer DL spreads to the left and right pillar regions as the drain-source voltage (Vds) increases during turn-off. In the comparative example, the depletion layer DL spreads rapidly as Vds increases, and the pillar regions 13 and 14 are completely depleted. In contrast, in the semiconductor device 30 of this embodiment, after the depletion layer DL spreads to the first region 3a and the third region 4a as Vds increases, the spread of the depletion layer DL is suppressed in the second region 3b and the fourth region 4b because of the high impurity concentrations there. In other words, the speed at which the depletion layer DL spreads before it is completely depleted slows down, and the depletion layer spreads more slowly.

[0030] FIG. 10 is a graph illustrating the change in Vds shown in FIG. 9. In FIG. 10, the horizontal axis represents the elapsed time since turn-off, and the vertical axis represents voltage (V). During turn-off, the depletion layer DL expands rapidly, and the pillar regions 13 and 14 suddenly become completely depleted. This causes a sudden change in the feedback capacitance Crss, which causes Vds to jump up and generate a so-called surge. The feedback capacitance Crss is equal to the gate-drain capacitance Cgd. V(BR)DSS is the drain-source breakdown voltage. V(BR)DSS is the drain-source breakdown voltage. In the comparative example, the generated surge exceeds V(BR)DSS.

[0031] In contrast, in the silicon carbide semiconductor device 30 of this embodiment, the impurity concentrations (second concentration, fourth concentration) are high in the pillar central portions (second region 3b, fourth region 4b) and low in the regions adjacent to the pillar central portions (first region 3a, third region 4a) in the first semiconductor pillar region 3 and the second semiconductor pillar region 4. In other words, in the silicon carbide semiconductor device 30 of this embodiment, both the first semiconductor pillar region 3 and the second semiconductor pillar region 4 have regions with clearly different impurity concentrations. According to this embodiment, as illustrated in FIG. 9(a), by providing the high-concentration second region 3b and fourth region 4b, the expansion speed of the depletion layer DL can be slowed down during the turn-off operation. As a result, the change in capacitance Crss during full depletion can be made gentle. As shown by the dashed line in FIG. 10, in this embodiment, the change in Vds per unit time, i.e., dVds / dt, becomes gentle at the end of the turn-off operation, and the generated surge does not exceed V(BR)DSS. In other words, the silicon carbide semiconductor device 30 of this embodiment can suppress surges caused by a jump in Vds.

[0032] More specifically, the depletion layer expands from the interface between the first region 3a and the third region 4a, which have a low concentration, toward the second region 3b and the fourth region 4b, which have a high concentration. Therefore, for example, at the end of turn-off, when the depletion layer reaches the second region 3b and the fourth region 4b, the concentration changes from the first concentration to the second concentration and from the third concentration to the fourth concentration. In other words, the higher impurity concentration makes it difficult for the depletion layer to extend laterally. Therefore, compared to the semiconductor device of the comparative example, the change in capacitance is gentler and the change in source-drain voltage is suppressed. As a result, compared to the semiconductor device of the comparative example, the silicon carbide semiconductor device 30 of this embodiment can suppress breakdown of the silicon carbide semiconductor device 30 due to a surge voltage exceeding the drain-source breakdown voltage V(BR)DSS.

[0033] For example, if silicon is used as the semiconductor device material, impurities will diffuse between the pillars during heat treatment after ion implantation. Therefore, when compared under the same conditions as the profiles shown in Figures 7 and 8, the profile for silicon material will have a peak concentration at the center of the pillar, with the concentration gradually decreasing. In contrast, the silicon carbide semiconductor device 30 of this embodiment uses silicon carbide as its material. Because the diffusion coefficient of impurities in silicon carbide is lower than that in silicon, n-type impurities and p-type impurities remain in the first semiconductor pillar region 3 and the second semiconductor pillar region 4, respectively, during activation heat treatment, and diffusion is slow. Therefore, in each of the first semiconductor pillar region 3 and the second semiconductor pillar region 4, a roughly step-like concentration profile with different impurity concentrations can be easily formed, as shown in FIGS. 7 and 8 . That is, according to this embodiment, for example, the impurity concentrations and region widths W of the high-concentration second region 3b and fourth region 4b can be precisely controlled. This facilitates precise control of the expansion of the depletion layer in the silicon carbide semiconductor device 30, making it possible to control the change in capacitance at turn-off and the associated occurrence of a Vds surge.

[0034] Furthermore, in this embodiment, as described above, the first concentration and the third concentration are approximately (substantially) the same concentration, and the second concentration and the fourth concentration are approximately (substantially) the same concentration, which enables the silicon carbide semiconductor device 30 to maintain charge balance between the first semiconductor pillar region 3 and the second semiconductor pillar region 4.

[0035] Furthermore, in silicon carbide semiconductor device 30, an n-type buffer layer may be provided on semiconductor layer 2. By providing the n-type buffer layer, it is possible to prevent the generation of a region in semiconductor layer 2 where ions are directly implanted.

[0036] Furthermore, in the above embodiment, the first semiconductor pillar region 3 and the second semiconductor pillar region 4 are both described as forming regions with different impurity concentrations, but this is not limiting. For example, the first semiconductor pillar region 3 may be formed to have different impurity concentrations like the first region 3a and second region 3b described above, and the second semiconductor pillar region 4 may be formed so that the impurity concentration is uniform with the impurity concentration of the third region 4a.

[0037] The superjunction structure consisting of the substrate 1, the semiconductor layer 2, the first semiconductor pillar region 3, and the second semiconductor pillar region 4 can be applied not only to a planar gate SJ-MOSFET type semiconductor device but also to other types of semiconductor devices. The following describes the case where the superjunction structure of this embodiment is applied to other types of semiconductor devices.

[0038] (Second embodiment) The second embodiment is a trench-gate SJ-MOSFET (metal-oxide-semiconductor field-effect transistor) type silicon carbide semiconductor device. The following describes configurations that differ from the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions of these components will be omitted.

[0039] Fig. 11 is a schematic cross-sectional view showing an example of the structure of silicon carbide semiconductor device 40 according to this embodiment. Fig. 12 is another schematic cross-sectional view showing an example of the structure of silicon carbide semiconductor device 40. 11, a drain electrode 41 is formed on the underside of the substrate 1. A p-type semiconductor region 42 is formed on the upper side of the second semiconductor pillar region 4 and below the trench T. Furthermore, an n-type semiconductor region 43 is formed on the upper side of the first semiconductor pillar region 3.

[0040] A p-type base 44 is formed on the upper side of the n-type semiconductor region 43. A source layer 45 is formed on the upper side surface of the p-type base 44. The source layer 45, the p-type base 44, and n A trench T is formed so as to penetrate the p-type semiconductor region 43 and to be embedded in the p-type semiconductor region 42. A gate electrode 47 is formed in the trench T via an insulating film 46. The portion of the insulating film 46 that penetrates the source layer 45, the p-base 44, and the n-type semiconductor region 43 is made of silicon dioxide (SiO2) that has been subjected to NO oxynitridation treatment that includes nitrogen at the interface. The insulating film 46 above the source layer 45 is made of silicon dioxide. A source electrode 48 is formed above the source layer 45 and the trench T.

[0041] In the schematic cross-sectional view shown in Figure 11, the p-type semiconductor region 42 and the p-base 44 are not connected, but in the schematic cross-sectional view shown in Figure 12, the p-type semiconductor region 42 is formed so that the p-type semiconductor region 42 and the p-base 44 are connected. In this way, the trench gate SJ-MOSFET type silicon carbide semiconductor device 40 can also achieve the same effects as those of the first embodiment.

[0042] Modified examples of trench-gate SJ-MOSFET type silicon carbide semiconductor devices will be described below with reference to Figures 13 to 19. Therefore, differences from silicon carbide semiconductor device 40 of the second embodiment will be described in detail. Note that the same components as those in the first and second embodiments will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0043] (Third embodiment) FIG. 13 is a schematic cross-sectional view showing an example of the structure of a silicon carbide semiconductor device 60 in accordance with this embodiment. 13 , compared to the silicon carbide semiconductor device 40, the silicon carbide semiconductor device 60 differs in that a p-type semiconductor region 61 is formed above the second semiconductor pillar region 4 of the superjunction layer SJ and below the p-base 44. The trench T is formed so as to be embedded in the n-type semiconductor region 62 formed above the first semiconductor pillar region 3. Such a trench-gate SJ-MOSFET type silicon carbide semiconductor device 60 can also achieve the same effects as the second embodiment.

[0044] (Fourth embodiment) Fig. 14 is a schematic cross-sectional view showing an example of the structure of silicon carbide semiconductor device 70 according to this embodiment. Fig. 15 is another schematic cross-sectional view showing an example of the structure of silicon carbide semiconductor device 70. 14 , the silicon carbide semiconductor device 70 differs from the silicon carbide semiconductor device 40 in that a p-type semiconductor region 71 is formed above the second semiconductor pillar region 4 of the superjunction layer SJ and below the p-base 44. The silicon carbide semiconductor device 70 further differs in that a p-type semiconductor region 72 is formed above a portion including part of the first region 3 a and the second region 3 b and below the insulating film 46. A trench T is formed so that a portion of the lower side of the insulating film 46 is embedded in the p-type semiconductor region 72.

[0045] In the schematic cross-sectional view shown in Figure 14, the p-type semiconductor region 72 and the p-base 44 are not connected, but in the cross-section shown in Figure 15, the p-type semiconductor region 72 is formed so that the p-type semiconductor region 72 and the p-base 44 are connected. Such a trench gate SJ-MOSFET type silicon carbide semiconductor device 70 can also achieve the same effects as those of the second embodiment.

[0046] In a trench-gate SJ-MOSFET type silicon carbide semiconductor device, the configuration and number of n-type and p-type semiconductor regions that electrically connect the superjunction layer SJ and the p-base 44 can be adjusted as appropriate.

[0047] (Fifth embodiment) Next, a PN (pn) diode type silicon carbide semiconductor device 10 will be described. Below, configurations different from those of the first embodiment will be described. Note that the same components as those of the first embodiment will be assigned the same reference numerals, and detailed descriptions thereof will be omitted.

[0048] 16 , silicon carbide semiconductor device 10 includes a substrate 1, a semiconductor layer 2, a superjunction layer SJ, a p-type semiconductor layer 11, a cathode electrode 5, and an anode electrode 6. The p-type semiconductor layer 11 is provided between the superjunction layer SJ and the anode electrode 6. Since the superjunction layer SJ has the same structure as that of the silicon carbide semiconductor device 30, the behavior of the depletion layer in the superjunction layer SJ when reverse biased is similar to that of the silicon carbide semiconductor device 30.

[0049] A cathode electrode 5 is provided on the surface of the substrate 1 opposite to the surface on which the semiconductor layer 2 is provided. 2 An anode electrode 6 is provided on the upper surface of the semiconductor pillar region 4 (the surface opposite to the semiconductor layer 2 side) via a p-type semiconductor layer 11. The cathode electrode 5 and the anode electrode 6 are made of metal. In this embodiment, the p-type semiconductor layer 11 is made of silicon carbide and includes a first layer 11a and a second layer 11b. The first layer 11a is formed on the upper side surface of the super junction layer SJ, and the second layer 11b is formed between the first layer 11a and the anode electrode 6.

[0050] The first layer 11a and the second layer 11b contain p-type impurities, such as aluminum. The first layer 11a is p-type and has an impurity concentration of, for example, 1×10 18 / cm 3 The thickness of the first layer 11a is, for example, 0.2 μm. The second layer 11b is p-type and has an impurity concentration of, for example, 1×10 19 / cm 3 The second layer 11b has a thickness of, for example, 0.2 μm. The PN diode type silicon carbide semiconductor device 20 configured in this manner can also achieve the same effects as those of the first embodiment.

[0051] (Sixth embodiment) Next, a Schottky barrier diode (SBD) type silicon carbide semiconductor device 20 will be described. The following describes configurations that differ from the first embodiment. Note that the same components as those in the first and fifth embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0052] FIG. 17 is a schematic cross-sectional view showing an example of the structure of silicon carbide semiconductor device 20 according to this embodiment. As shown in FIG. 17 , in silicon carbide semiconductor device 20, super junction layer SJ and anode electrode 6 are connected, and compared to silicon carbide semiconductor device 10, p The difference is that the Schottky barrier diode type silicon carbide semiconductor device 20 does not have a shaped semiconductor layer 11 formed therein. The anode electrode 6 forms a Schottky junction with the first semiconductor pillar region 3 and an ohmic contact with the second semiconductor pillar region 4. Since the superjunction layer SJ has the same structure as that of the silicon carbide semiconductor device 30, the behavior of the depletion layer in the superjunction layer SJ when reverse biased is similar to that of the silicon carbide semiconductor device 30. In this way, the Schottky barrier diode type silicon carbide semiconductor device 20 can also achieve the same effects as those of the first embodiment.

[0053] (Simulation results) Next, we will explain the results of a simulation of changes that occur when the applied voltage increases in the superjunction layer SJ used in each of the silicon carbide semiconductor devices described above. This simulation uses the structure of the SBD-type silicon carbide semiconductor device 20 described in the sixth embodiment. The anode-cathode capacitance C of the silicon carbide semiconductor device 20 corresponds to the output capacitance Coss of the MOSFET-type silicon carbide semiconductor devices 30, 40, 60, and 70 described above, so the output capacitance Coss and the feedback capacitance Crss are correlated. Therefore, by simulating the capacitance characteristics of the structure of the SBD-type silicon carbide semiconductor device 20, we can also investigate the behavior of Crss of the MOSFET-type silicon carbide semiconductor device. The output capacitance Coss is the sum of the drain-source capacitance Cds and the gate-drain capacitance Cgd.

[0054] FIG. 18(a) shows the simulation conditions for the superjunction structure of a silicon carbide semiconductor device serving as a comparative example, and FIG. 18(b) shows the simulation conditions for the superjunction structure of this embodiment.

[0055] 18(a), the superjunction structure serving as a comparative example has a first semiconductor pillar region N and a second semiconductor pillar region P. The first semiconductor pillar region N and the second semiconductor pillar region P have the same width W and the same impurity concentration D. In other words, the first semiconductor pillar region N and the second semiconductor pillar region P have the same impurity concentration.

[0056] 18(b), the superjunction structure of this embodiment has a first semiconductor pillar region 3 extending from its center to its edge, and a second semiconductor pillar region 4 extending from its center to its edge, which is adjacent to the edge of the first semiconductor pillar region 3. The width of the first semiconductor pillar region 3 and the second semiconductor pillar region 4 is width W, and the widths of the first region 3a, the second region 3b, the third region 4a, and the fourth region 4b are half of width W. The impurity concentrations of the second region 3b and the fourth region 4b are 1.5 times the concentration D of the comparative example. Two simulation patterns were performed for the impurity concentrations of the first region 3a and the third region 4a: one where the concentration is half of concentration D, and the other where the concentration is D.

[0057] FIG. 19 is a diagram showing an example of a simulation result in which the reverse voltage Vr applied to the first electrode (cathode electrode) E1 and the second electrode (anode electrode) E2 during reverse bias is 0V. 19(a) and 19(b), a simulation was performed using a so-called Schottky structure in which a first electrode E1 was placed below the first semiconductor pillar region N, the second semiconductor pillar region P, the first semiconductor pillar region 3, and the second semiconductor pillar region 4, respectively, and a second electrode E2 was placed above the second semiconductor pillar region P and the second semiconductor pillar region 4. The temperature used in the simulation was 25 degrees.

[0058] When the voltage Vds is 0 V, the depletion layer DL1 shown in FIG. 19(a) and the depletion layer DL2 shown in FIG. 19(b) are almost the same.

[0059] FIG. 20 is a diagram showing an example of a simulation result of a change in capacitance when the voltage Vds is increased from 0 V. In FIG. 20, graph g1 shows the simulation results for the superjunction structure of the comparative example shown in Fig. 18(a), and graphs g2 and g3 show the simulation results for the superjunction structure of this embodiment shown in Fig. 18(b). Graph g2 shows the case where the concentrations in the first region 3a and the third region 4a are half of concentration D, and graph g3 shows the case where the concentrations in the first region 3a and the third region 4a are concentration D.

[0060] The change in capacitance is more gradual in graphs g2 and g3 than in graph g1. This means that the steep change in surge voltage is also gradual. Furthermore, the change in capacitance is more gradual in graph g3 than in graph g2. This shows that the change in capacitance is more gradual when the concentration difference between the second region 3b and the fourth region 4b and the first region 3a and the third region 4a is reduced.

[0061] 21 to 23 are diagrams showing an example of the simulation results of the change in the depletion layer when the reverse voltage Vr is increased.

[0062] 21A to 21D are diagrams showing an example of simulation results of changes in the depletion layer of the superjunction structure shown in Fig. 18A, which is a comparative example. Figs. 21A to 21D show the cases where the reverse voltage Vr is 25V, 50V, 75V, and 100V, respectively. Depletion layers DL11 to DL14 correspond to the voltages 25V, 50V, 75V, and 100V, respectively.

[0063] 22 shows an example of the simulation results of the change in the depletion layer of the superjunction structure when the concentrations in the first region 3a and the third region 4a are half of the concentration D. Figures 22(a) to 22(d) show the cases where the reverse voltage Vr is 25V, 50V, 75V, and 100V, respectively. Depletion layers DL21 to DL24 correspond to the voltages 25V, 50V, 75V, and 100V, respectively.

[0064] 23 is a diagram showing an example of a simulation result of the change in the depletion layer of the superjunction structure when the concentration of the first region 3a and the third region 4a is concentration D. Figures 23(a) to 23(d) show the cases where the voltage Vds is 25V, 50V, 75V, and 100V, respectively. Depletion layers DL31 to DL34 correspond to the voltages 25V, 50V, 75V, and 100V, respectively.

[0065] 21 to 23, the depletion layer in the superjunction structure of this embodiment spreads more slowly toward the end of depletion than in the superjunction structure of the comparative example. Also, the changes in the depletion layers DL31 to DL34 shown in FIG. 23 are more gradual than the changes in the depletion layers DL21 to DL24 shown in FIG.

[0066] Therefore, it can be seen that the superjunction structure of this embodiment can moderate the change in the depletion layer at turn-off, thereby reducing the surge voltage exceeding the drain-source breakdown voltage V(BR)DSS. Thus, by forming regions with high impurity concentrations in the central portions (second region 3b, fourth region 4b) of the first semiconductor pillar region 3 and the second semiconductor pillar region 4, respectively, the silicon carbide semiconductor device of the above embodiment can suppress breakdown of the silicon carbide semiconductor device due to a surge voltage exceeding the drain-source breakdown voltage V(BR)DSS. Furthermore, it can be seen that the change in capacitance becomes more gradual when the concentration difference between the second region 3b and the fourth region 4b and the first region 3a and the third region 4a is reduced.

[0067] (Other embodiments) Next, another embodiment will be described. This other embodiment differs in the superjunction structure. More specifically, as shown in FIG. 24, the second region 3 b 26, regions 3c and 3d corresponding to the upper portions of the second region 3b are formed, and regions 4d and 4c are formed instead of the fourth region 4b. Region 3c is formed on the upper side of the figure, region 3d on the lower side of the figure, region 4d on the upper side of the figure, and region 4c on the lower side of the figure. In this embodiment, regions 3c and 3d and regions 4c and 4d have the same pillar depth. The impurity concentrations of regions 3c and 4c are the same as those of the first region 3a and the third region 4a, respectively, and are concentration D. On the other hand, the impurity concentrations of regions 3d and 4d are 1.5 times the concentration D of the first region 3a and the third region 4a, respectively. In other words, regions with high impurity concentrations are formed in region 3d on the lower left side and region 3d on the upper right side of FIG. 26.

[0068] (Simulation results of other embodiments) Next, the simulation results will be described. 24, this simulation was performed under the same conditions as the simulation conditions described above, except that the regions with high impurity concentrations were different. Simply put, the differences in the simulation conditions are that in the second region 3b, only the lower half region 3d has a second concentration (1.5 times the concentration D) and the upper half region 3c has a first concentration (concentration D), and in the fourth region 4b, only the upper half region 4d has a fourth concentration (1.5 times the concentration D) and the lower half region 4c has a third concentration (concentration D).

[0069] FIG. 25 is a diagram showing an example of a simulation result in which the reverse voltage Vr applied to the first electrode E1 and the second electrode E2 at the time of turn-off is 0V. When the reverse voltage Vr is 0V, the depletion layer DL41 shown in FIG. 25(a) and the depletion layer DL42 shown in FIG. 25(b) are almost the same.

[0070] 26 is a diagram showing an example of a simulation result of a change in capacitance when the reverse voltage Vr is increased, where the capacitance is shown on a logarithmic scale in this simulation. In FIG. 26, graph g11 shows the simulation results of the superjunction structure serving as the comparative example shown in FIG. 26(a), and graph g12 shows the simulation results of the superjunction structure of this other embodiment shown in FIG.

[0071] The change in capacitance is more gradual in graph g12 than in graph g11, which indicates that the magnitude of the surge voltage is smaller.

[0072] 27A to 27D are diagrams showing an example of simulation results of changes in the depletion layer of the superjunction structure shown in Fig. 18A, which is a comparative example. Figs. 27A to 27D show the cases where the voltage Vds is 50 V, 80 V, 100 V, and 200 V, respectively. Depletion layers DL51 to DL54 correspond to the voltages 50 V, 80 V, 100 V, and 200 V, respectively.

[0073] 28A to 28D are diagrams showing an example of simulation results of changes in the depletion layer of the superjunction structure of this other embodiment. Figures 28A to 28D show the cases where the reverse voltage Vr is 50 V, 80 V, 100 V, and 200 V, respectively. Depletion layers DL61 to DL64 correspond to the voltages 50 V, 80 V, 100 V, and 200 V, respectively.

[0074] 27 and 28, it can be seen that the depletion layer in the superjunction structure of this embodiment spreads more slowly at the end of the turn-off period than in the superjunction structure of the comparative example. Therefore, the silicon carbide semiconductor device having the superjunction structure of this embodiment can also achieve the same effects as the silicon carbide semiconductor device of each of the above embodiments.

[0075] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0076] REFERENCE SIGNS LIST 1...substrate, 2...semiconductor layer, 3...first semiconductor pillar region, 3a...first region, 3b...second region, 4...second semiconductor pillar region, 4a...third region, 4b...fourth region, 5...cathode electrode, 6...anode electrode, 7...buffer layer, 8...drift layer, 10, 20, 30, 40, 60, 70...silicon carbide semiconductor device, 11...I-type semiconductor layer, 31...drain layer, 32, 44, 51...p-base, 33, 45...source layer, 35, 46...insulating film, 36, 47...gate electrode, 37, 48...source electrode, W...width, T...trench, SJ...superjunction layer

Claims

1. A first electrode; A second electrode; a first semiconductor layer including silicon carbide provided between the first electrode and the second electrode; a first region having a first impurity concentration; a second region aligned with the first region in a second direction perpendicular to a first direction from the first electrode toward the second electrode, and having a second impurity concentration higher than the first impurity concentration; a plurality of first semiconductor pillar regions of a first conductivity type including silicon carbide, the first semiconductor pillar regions being provided between the first semiconductor layer and the second electrode; a third region having a third impurity concentration; a fourth region aligned with the third region in the second direction and having a fourth impurity concentration higher than the third impurity concentration; a second semiconductor pillar region of a second conductivity type that is provided between the first semiconductor layer and the second electrode, is located between the first semiconductor pillar regions in the second direction, and contains silicon carbide; Equipped with a concentration difference between the first impurity concentration of the first region and the second impurity concentration of the second region is stepwise; a difference in concentration between the third impurity concentration in the third region and the fourth impurity concentration in the fourth region is stepped;

2. Further, a second semiconductor layer is provided between the first semiconductor layer, the first semiconductor pillar region, and the second semiconductor pillar region. The silicon carbide semiconductor device according to claim 1 .

3. the first semiconductor pillar region is a stripe-shaped region extending on the first semiconductor layer in a direction perpendicular to the first direction and the second direction, the second semiconductor pillar region is a stripe-shaped region on the first semiconductor layer adjacent to the first semiconductor pillar region; The silicon carbide semiconductor device according to claim 1 .

4. the second semiconductor pillar region is a rectangular region on the first semiconductor layer, the first semiconductor pillar region is a rectangular region on the first semiconductor layer that surrounds the second semiconductor pillar region; The silicon carbide semiconductor device according to claim 1 .

5. In the second direction, the second region is provided between two of the first regions, In the second direction, the fourth region is provided between two of the third regions. The silicon carbide semiconductor device according to any one of claims 1 to 4.

6. the first impurity concentration and the third impurity concentration are the same; the second impurity concentration and the fourth impurity concentration are the same; The silicon carbide semiconductor device according to any one of claims 1 to 5.

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