Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving a withstand voltage.SOLUTION: A semiconductor device 1A includes: a p-type first region 6 which is formed on a second main surface 4 side in a chip 2; an n-type second region 7 which is formed on a first main surface 3 side in the chip 2 and forms a first pn-junction portion 9 with the first region 6; a first trench structure 13 including a first trench 15 which penetrates the first pn-junction portion 9, a first insulating film 16 which exposes the first region 6 from a wall surface of the first trench 15, and a first polysilicon 17 which is buried in the first trench 15 with the first insulating film 16 interposed between the first trench and the first polysilicon, and partitioning a device region 10; and a second trench structure 14 including a second trench 22 which penetrates the first pn-junction portion 9, a second insulating film 23 which exposes the first region 6 from a wall surface of the second trench 22, and a second polysilicon 24 which is buried in the second trench 22 with the second insulating film 23 interposed between the second trench and the second polysilicon, and partitioning the device region 10 on a device region 10 side rather than the first trench structure 13.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a p-type region, a first p-epitaxial region, an n-type buried region, a second p-epitaxial region, and a deep trench isolation (DTI) structure. The first p-type epitaxial region is formed on the p-type region. The n-type buried region is formed on the first p-epitaxial region. The second p-epitaxial region is formed on the n-type buried region. The DTI structure surrounds a region where a high-voltage lateral MOS transistor is formed in a plan view. The DTI structure penetrates the second p-epitaxial region, the n-type buried region, and the first p-epitaxial region to reach the p-type region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-122543 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor device capable of improving breakdown voltage. [Means for solving the problem]

[0005] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; a first region of a first conductivity type formed on the second main surface side within the chip; a second region of a second conductivity type formed on the first main surface side within the chip and forming a p-n junction with the first region; a device region provided on the first main surface; a first trench structure that defines the device region, the first trench including: a first trench penetrating from the first main surface to the p-n junction, a first insulating film exposing the first region from a wall surface of the first trench, and first polysilicon embedded in the first trench with the first insulating film sandwiched between them; and a second trench structure that defines the device region on the device region side of the first trench structure, the second trench including: a second trench penetrating from the first main surface to the p-n junction, a second insulating film exposing the first region from a wall surface of the second trench, and second polysilicon embedded in the second trench with the second insulating film sandwiched between them.

[0006] One embodiment provides a semiconductor device including: a chip having a main surface; a first pn junction formed in the chip so as to extend along the main surface; a device region provided on the main surface; a trench penetrating from the main surface to the first pn junction; an insulating film exposing a bottom wall of the trench within the trench; and polysilicon embedded in the trench across the insulating film, the trench structure separating the device region from other regions; and a second pn junction formed in the polysilicon.

[0007] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of region II shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a main part of the structure shown in FIG. [Figure 5] FIG. 5 is an enlarged view of a main part showing the electric field distribution of a semiconductor device according to a reference embodiment. [Figure 6] FIG. 6 is an enlarged view of a main part showing the electric field distribution of the semiconductor device shown in FIG. [Figure 7A] FIG. 7A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 7B] FIG. 7B is a cross-sectional view showing a step subsequent to the step shown in FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view showing a step subsequent to the step shown in FIG. 7B. [Figure 7D] FIG. 7D is a cross-sectional view showing a step subsequent to the step shown in FIG. 7C. [Figure 7E] FIG. 7E is a cross-sectional view showing a step subsequent to the step shown in FIG. 7D. [Figure 7F] FIG. 7F is a cross-sectional view showing a step subsequent to the step shown in FIG. 7E. [Figure 7G] FIG. 7G is a cross-sectional view showing a step subsequent to the step shown in FIG. 7F. [Figure 7H] FIG. 7H is a cross-sectional view showing a step subsequent to the step shown in FIG. 7G. [Figure 7I] FIG. 7I is a cross-sectional view showing a step subsequent to the step shown in FIG. 7H. [Figure 7J] FIG. 7J is a cross-sectional view showing a step subsequent to the step shown in FIG. 7I. [Figure 7K] FIG. 7K is a cross-sectional view showing a step subsequent to the step shown in FIG. 7J. [Figure 7L] FIG. 7L is a cross-sectional view showing a step subsequent to the step shown in FIG. 7K. [Figure 7M] FIG. 7M is a cross-sectional view showing a step subsequent to the step shown in FIG. 7L. [Figure 7N] FIG. 7N is a cross-sectional view showing a step subsequent to the step shown in FIG. 7M. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing the second region according to the first modified example. [Figure 11] FIG. 11 is a cross-sectional view showing the second region according to the second modified example. [Figure 12] FIG. 12 is a cross-sectional view showing the second region according to the third modified example. [Figure 13] FIG. 13 is a cross-sectional view showing a first region according to a modified example. [Figure 14] FIG. 14 is a cross-sectional view showing a first removal section and a second removal section according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 2. FIG. 4 is an enlarged cross-sectional view of a main part of the structure shown in FIG. 3. Referring to FIGS. 1 to 4, the semiconductor device 1A includes a rectangular parallelepiped chip 2 (semiconductor chip). In this embodiment, the chip 2 is a Si (silicon) chip. The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0011] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0012] The semiconductor device 1A includes a p-type (first conductivity type) first region 6 formed in a region on the second main surface 4 side within the chip 2. The first region 6 may also be referred to as a "base region." The first region 6 may also be considered a component of the chip 2. The first region 6 extends in a layered manner along the second main surface 4 and is exposed from parts of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first region 6 has a concentration gradient in which the p-type impurity concentration on the first main surface 3 side is lower than the p-type impurity concentration on the second main surface 4 side. Specifically, the first region 6 has a stacked structure including a p-type first high concentration region 6a and a p-type first low concentration region 6b stacked in this order from the second main surface 4 side.

[0013] The first high concentration region 6a has a relatively high p-type impurity concentration. The p-type impurity concentration of the first high concentration region 6a is 1×10 17 cm -3 More than 1×10 20 cm -3 The first high concentration region 6a may contain boron (B) as a p-type impurity. The first high concentration region 6a may have a thickness of 50 μm or more and 500 μm or less. In this embodiment, the first high concentration region 6a is made of a p-type semiconductor substrate (Si substrate).

[0014] The first low concentration region 6b has a p-type impurity concentration lower than that of the first high concentration region 6a and is stacked on the first high concentration region 6a. The p-type impurity concentration of the first low concentration region 6b is 1×10 14 cm -3 More than 1×10 17 cm -3The first low concentration region 6b may contain boron (B) as a p-type impurity. The first low concentration region 6b has a thickness less than that of the first high concentration region 6a. The thickness of the first low concentration region 6b may be 1 μm or more and 20 μm or less. In this embodiment, the first low concentration region 6b is made of a p-type epitaxial layer (Si epitaxial layer).

[0015] The semiconductor device 1A includes a second region 7 of n-type (second conductivity type) formed in a region on the first main surface 3 side of the chip 2. The second region 7 may be referred to as a "buried region." The second region 7 may be considered a component of the chip 2. The second region 7 is stacked on the first region 6 and electrically connected to the first region 6. The second region 7 extends in a layered manner along the first region 6 and is exposed from portions of the first to fourth side surfaces 5A to 5D. The second region 7 has a concentration gradient in which the n-type impurity concentration on the first main surface 3 side is higher than the n-type impurity concentration on the second main surface 4 side. Specifically, the second region 7 has a stacked structure including a second low-concentration region 7a and a second high-concentration region 7b stacked in this order from the first region 6 side.

[0016] The second low-concentration region 7a has a relatively low n-type impurity concentration and is stacked on the first low-concentration region 6b of the first region 6. The n-type impurity concentration of the second low-concentration region 7a is 1×10 14 cm -3 More than 1×10 18 cm -3 The second low-concentration region 7a may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the second low-concentration region 7a is preferably 0.5 μm or more and 2.5 μm or less. In this embodiment, the second low-concentration region 7a is made of an n-type epitaxial layer (Si epitaxial layer).

[0017] The second high-concentration region 7b has a higher n-type impurity concentration than the second low-concentration region 7a and is stacked on the second low-concentration region 7a. The n-type impurity concentration of the second high-concentration region 7b is 1×10 16 cm -3 More than 1×10 21 cm -3The second high-concentration region 7b may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the second high-concentration region 7b is preferably 0.5 μm or more and 2.5 μm or less. In this embodiment, the second high-concentration region 7b is made of an n-type epitaxial layer (Si epitaxial layer).

[0018] The semiconductor device 1A includes a p-type or n-type third region 8 formed in a region on the first main surface 3 side within the chip 2. The third region 8 may be referred to as a "drift region." The third region 8 may be considered a component of the chip 2. The third region 8 is formed in a region on the first main surface 3 side relative to the second region 7. The conductivity type (p-type or n-type) of the third region 8 is arbitrary and is selected according to the specifications of the semiconductor device 1A. In this embodiment, an example in which the third region 8 is n-type is described, but the conductivity type of the third region 8 is not intended to be limited to n-type.

[0019] The third region 8 is stacked on the second region 7 and is electrically connected to the second region 7. The third region 8 extends in a layered manner along the second region 7 and is exposed from the first main surface 3 and parts of the first to fourth side surfaces 5A to 5D. The third region 8 may have a uniform n-type impurity concentration in the thickness direction, or may have a concentration gradient in which the n-type impurity concentration increases toward the first main surface 3.

[0020] The n-type impurity concentration of the third region 8 is preferably lower than that of the second region 7 (second high concentration region 7b). The n-type impurity concentration of the third region 8 is preferably 1×10 14 cm -3 More than 1×10 17 cm -3 The third region 8 may have a thickness of 5 μm or more and 30 μm or less. In this embodiment, the third region 8 is made of an n-type epitaxial layer (Si epitaxial layer).

[0021] The semiconductor device 1A includes a first pn-junction portion 9 formed midway in the thickness direction between the first main surface 3 and the second main surface 4 within the chip 2. The first pn-junction portion 9 may be considered a component of the chip 2. The first pn-junction portion 9 may also be referred to as a "first pn-connection portion" or a "first pn-boundary portion." The first pn-junction portion 9 extends horizontally along the first main surface 3 (perpendicular to the thickness direction).

[0022] The first pn junction 9 is formed at the boundary between the first region 6 (first low-concentration region 6b) and the second region 7 (second low-concentration region 7a). In other words, the second region 7 is stacked on the first region 6 so as to form the first pn junction 9 with the first region 6. As a result, the semiconductor device 1A includes a first diode D1 between the first region 6 and the second region 7, having the first region 6 as an anode and the second region 7 as a cathode.

[0023] The semiconductor device 1A includes a plurality of device regions 10 provided on the first main surface 3. The plurality of device regions 10 are regions in which various functional devices are formed, utilizing regions inside and outside the chip 2. The plurality of device regions 10 are each defined in the inner part of the first main surface 3 at intervals from the first to fourth side surfaces 5A to 5D in a plan view. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0024] The plurality of functional devices may each include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0025] The semiconductor rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse. In this embodiment, the multiple device regions 10 include at least one transistor region 11. The structure of the transistor region 11 will be specifically described below.

[0026] 2 to 4, semiconductor device 1A includes trench isolation structure 12 (groove structure) as an example of a region separation structure that partitions transistor region 11 on first main surface 3. Trench isolation structure 12 has a multi-trench structure including at least one first trench structure 13 (first trench structure) and at least one second trench structure 14 (second trench structure). In this embodiment, trench isolation structure 12 has a double trench structure including a single first trench structure 13 and a single second trench structure 14.

[0027] Referring to FIG. 2, the first trench structure 13 is formed on the first main surface 3 so as to define the transistor region 11. In this embodiment, the first trench structure 13 is formed in a ring shape (a square ring shape in this embodiment) in a plan view, and defines the transistor region 11 having a predetermined shape (a square shape in this embodiment). In this embodiment, the first trench structure 13 has corners (four corners) that are curved in an arc shape in a plan view. The planar shape of the first trench structure 13 (the planar shape of the transistor region 11) is arbitrary. The first trench structure 13 may be formed in a polygonal ring shape, a circular ring shape, or an elliptical ring shape in a plan view, and define the transistor region 11 having a polygonal, circular, or elliptical shape in a plan view.

[0028] The first trench structure 13 has a first width W1. The first width W1 is the width (maximum value) in a direction perpendicular to the direction in which the first trench structure 13 extends in a plan view. The first width W1 may be 0.5 μm or more and 10 μm or less. The first width W1 is preferably 2 μm or more and 4 μm or less.

[0029] 3 and 4 , first trench structure 13 is formed in first main surface 3 so as to penetrate first pn junction 9. Specifically, first trench structure 13 penetrates third region 8 and second region 7 to reach first region 6, and defines transistor region 11 in third region 8. More specifically, first trench structure 13 extends from first main surface 3 toward second main surface 4 to reach first high concentration region 6a of first region 6, and penetrates third region 8, second region 7, and first low concentration region 6b of first region 6.

[0030] The first trench structure 13 includes an inner peripheral wall on the transistor region 11 side, an outer peripheral wall on the opposite side of the inner peripheral wall (the peripheral edge side of the chip 2), and a bottom wall connecting the inner peripheral wall and the outer peripheral wall. The first trench structure 13 may be formed in a vertical shape in a cross-sectional view. The first trench structure 13 may be formed in a tapered shape that tapers toward the second main surface 4 in a cross-sectional view. The bottom wall of the first trench structure 13 may be formed in a curved shape that curves toward the second main surface 4. The bottom wall of the first trench structure 13 may have a flat surface parallel to the first main surface 3.

[0031] The first trench structure 13 protrudes from the first pn junction 9 toward the second main surface 4 side by a first protrusion amount P1. The first protrusion amount P1 may be 1 μm or more and 30 μm or less. The first protrusion amount P1 is preferably 5 μm or more and 25 μm or less. The first protrusion amount P1 is particularly preferably 10 μm or more and 20 μm or less. It is preferable that the first protrusion amount P1 exceeds the distance D between the first main surface 3 and the first pn junction 9 (D < P1).

[0032] The first trench structure 13 includes a first trench 15, a first insulating film 16, and a first polysilicon 17. The first trench 15 is formed on the first main surface 3 so as to penetrate the first pn junction 9 and partitions the wall surface of the first trench structure 13. Specifically, the first trench 15 penetrates the second region 7 so as to reach the first region 6. More specifically, the first trench 15 extends from the first main surface 3 toward the second main surface 4 side so as to reach the first high-concentration region 6a of the first region 6 and penetrates the second region 7 and the first low-concentration region 6b of the first region 6.

[0033] The first insulating film 16 covers the wall surface of the first trench 15 and has a first removed portion 16a that exposes the first region 6 from the first trench 15. Specifically, the first insulating film 16 covers the first region 6, the second region 7, and the third region 8 on the inner and outer peripheral walls of the first trench 15. The first removed portion 16a exposes the first high-concentration region 6a of the first region 6 from at least the bottom wall of the first trench 15. In this embodiment, the first removed portion 16a is formed in an annular shape extending along the first trench 15 in a plan view. The first removed portion 16a may also be formed in an end-band shape extending along the first trench 15 in a plan view.

[0034] In this embodiment, the first insulating film 16 has a layered structure in which multiple insulating films are stacked. Specifically, the first insulating film 16 has a layered structure including a first lower insulating film 18 and a first upper insulating film 19, which are stacked in this order from the wall surface side of the first trench 15 (see FIG. 4). The first lower insulating film 18 covers the inner and outer peripheral walls of the first trench 15 and exposes the first high-concentration region 6a of the first region 6 from the bottom wall of the first trench 15. The first lower insulating film 18 is preferably made of an insulating film with a relatively high density. The first lower insulating film 18 may include a silicon oxide film. The first lower insulating film 18 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0035] The first upper insulating film 19 covers the inner and outer peripheral walls of the first trench 15 with the first lower insulating film 18 sandwiched therebetween, and exposes the first high-concentration region 6a of the first region 6 from the bottom wall of the first trench 15. The first upper insulating film 19 is thicker than the first lower insulating film 18. The first upper insulating film 19 is preferably made of an insulating film having a lower density than the first lower insulating film 18. The first upper insulating film 19 may include a silicon oxide film. The first upper insulating film 19 is preferably made of a TEOS (Tetraethyl orthosilicate) film.

[0036] The first polysilicon 17 is buried in the first trench 15 with the first insulating film 16 sandwiched therebetween. The first polysilicon 17 has an exposed portion exposed from the bottom wall of the first trench 15 (the first removed portion 16a of the first insulating film 16), and is mechanically connected to the first region 6 (the first high-concentration region 6a) at the exposed portion. The first polysilicon 17 is electrically insulated from the second region 7 and the third region 8 by the first insulating film 16.

[0037] The first polysilicon 17 includes a first portion 20 and a second portion 21. In Figures 3 and 4, the boundary between the first portion 20 and the second portion 21 is indicated by a dashed line. The first portion 20 is formed in the form of a film along the wall surfaces (inner peripheral wall, outer peripheral wall, and bottom wall) of the first trench 15 so as to define a recess space within the first trench 15. The first portion 20 is mechanically connected to the first region 6 (first high-concentration region 6a) at the bottom wall of the first trench 15.

[0038] The second portion 21 is embedded in the first trench 15 with the first portion 20 sandwiched therebetween. The second portion 21 faces the bottom wall (first region 6) of the first trench 15 with the first portion 20 sandwiched therebetween. The second portion 21 forms a boundary with the first portion 20 that extends along the wall surface of the first trench 15. The second portion 21 may form minute voids with the first portion 20 at the boundary. Of course, the second portion 21 may be formed completely integrally with the first portion 20 to the extent that the second portion 21 is indistinguishable from the first portion 20.

[0039] The second trench structure 14 is formed on the first main surface 3 so as to partition the transistor region 11 in a region closer to the transistor region 11 side than the first trench structure 13 in a plan view. The second trench structure 14 is formed at an interval from the first trench structure 13 toward the transistor region 11 side in a plan view, and extends in a strip shape along the first trench structure 13. In this form, the second trench structure 14 is formed in an annular shape (a square annular shape in this form) that extends substantially parallel to the first trench structure 13 in a plan view, and partitions the transistor region 11 having a predetermined shape (a square shape in this form). In this form, the second trench structure 14 has corner portions (four corners) that are curved in an arc shape along the corner portions (four corners) of the first trench structure 13 in a plan view.

[0040] The planar shape of the second trench structure 14 (the planar shape of the transistor region 11) is arbitrary, and the second trench structure 14 does not necessarily have a planar shape that matches the planar shape of the first trench structure 13. The second trench structure 14 may be formed in a polygonal annular shape, a circular annular shape, or an elliptical annular shape in a plan view, and may partition the transistor region 11 having a polygonal shape, a circular shape, or an elliptical shape in a plan view.

[0041] The second trench structure 14 has a second width W2. The second width W2 is the width (maximum value) in a direction orthogonal to the direction in which the second trench structure 14 extends in a plan view. It is preferable that the second width W2 is less than the first width W1 (W2 < W1). The second width W2 may be 0.5 μm or more and 10 μm or less. It is preferable that the second width W2 is 1.5 μm or more and 3.5 μm or less.

[0042] Referring to FIGS. 3 and 4, the second trench structure 14 is formed on the first main surface 3 so as to penetrate the first pn junction 9. Specifically, the second trench structure 14 penetrates the third region 8 and the second region 7 so as to reach the first region 6. More specifically, the second trench structure 14 extends from the first main surface 3 toward the second main surface 4 side so as to reach the first high-concentration region 6a of the first region 6, and penetrates the third region 8, the second region 7, and the first low-concentration region 6b of the first region 6.

[0043] The second trench structure 14 includes an inner peripheral wall on the transistor region 11 side, an outer peripheral wall on the first trench structure 13 side, and a bottom wall connecting the inner peripheral wall and the outer peripheral wall. The second trench structure 14 may be formed in a vertical shape in a cross-sectional view. The second trench structure 14 may be formed in a tapered shape toward the first region 6 side in a cross-sectional view. The bottom wall of the second trench structure 14 may be formed in a curved shape toward the second main surface 4. The bottom wall of the second trench structure 14 may have a flat surface parallel to the first main surface 3.

[0044] Referring to FIG. 4, the second trench structure 14 protrudes from the first pn junction 9 toward the second main surface 4 side by a second protrusion amount P2. The second protrusion amount P2 may be 1 μm or more and 30 μm or less. The second protrusion amount P2 is preferably 5 μm or more and 25 μm or less. The second protrusion amount P2 is particularly preferably 10 μm or more and 20 μm or less. The second protrusion amount P2 may be less than the first protrusion amount P1 (P2 < P1).

[0045] In this case, the difference (P1 - P2) between the first protrusion amount P1 and the second protrusion amount P2 is preferably 5 μm or less. The difference (P1 - P2) is particularly preferably 1 μm or less. Of course, the second protrusion amount P2 may be substantially equal to the first protrusion amount P1 of the first trench structure 13 (P1 ≒ P2). The second protrusion amount P2 preferably exceeds the distance D between the first main surface 3 and the first pn junction 9 (D < P2).

[0046] The second trench structure 14 includes a second trench 22, a second insulating film 23, and a second polysilicon 24. The second trench 22 is formed on the first main surface 3 so as to penetrate the first pn junction 9 and partitions the wall surface of the second trench structure 14. Specifically, the second trench 22 penetrates the third region 8 and the second region 7 so as to reach the first region 6. More specifically, the second trench 22 extends from the first main surface 3 toward the second main surface 4 side so as to reach the first high-concentration region 6a of the first region 6 and penetrates the third region 8, the second region 7, and the first low-concentration region 6b of the first region 6.

[0047] The second insulating film 23 covers the wall surface of the second trench 22 and has a second removed portion 23a that exposes the first region 6 from the second trench 22. Specifically, the second insulating film 23 covers the first region 6, the second region 7, and the third region 8 on the inner and outer peripheral walls of the second trench 22. The second removed portion 23a exposes the first high-concentration region 6a of the first region 6 from at least the bottom wall of the second trench 22. In this embodiment, the second removed portion 23a is formed in an annular shape extending along the second trench 22 in a plan view. The second removed portion 23a may also be formed in an end-band shape extending along the second trench 22 in a plan view.

[0048] In this embodiment, the second insulating film 23 has a layered structure in which a plurality of insulating films are stacked. Specifically, the second insulating film 23 has a layered structure including a second lower insulating film 25 and a second upper insulating film 26 stacked in this order from the wall surface side of the second trench 22 (see FIG. 4). The second lower insulating film 25 covers the inner and outer peripheral walls of the second trench 22, and exposes the first high-concentration region 6a of the first region 6 from the bottom wall of the second trench 22.

[0049] The second lower insulating film 25 preferably has a thickness substantially equal to that of the first lower insulating film 18. The second lower insulating film 25 is preferably made of an insulating film having a relatively high density. The second lower insulating film 25 may include a silicon oxide film. The second lower insulating film 25 preferably includes a silicon oxide film made of an oxide of the chip 2. The second lower insulating film 25 preferably includes the same insulating material as the first lower insulating film 18.

[0050] The second upper insulating film 26 covers the inner and outer peripheral walls of the second trench 22 with the second lower insulating film 25 in between, and exposes the first high-concentration region 6a of the first region 6 from the bottom wall of the second trench 22. The second upper insulating film 26 is thicker than the second lower insulating film 25. The second lower insulating film 25 preferably has a thickness approximately equal to that of the first upper insulating film 19.

[0051] The second upper insulating film 26 is preferably made of an insulating film having a lower density than the second lower insulating film 25. The second upper insulating film 26 may contain a silicon oxide film or a silicon nitride film. The second upper insulating film 26 is preferably made of a TEOS film. The second lower insulating film 25 preferably contains the same insulating material as the first upper insulating film 19.

[0052] The second polysilicon 24 is embedded in the second trench 22 with the second insulating film 23 interposed therebetween. The second polysilicon 24 has an exposed portion exposed from the bottom wall of the second trench 22 (the second removal portion 23a of the second insulating film 23), and is mechanically connected to the first region 6 (the first high-concentration region 6a) at the exposed portion. The second polysilicon 24 is electrically insulated from the second region 7 and the third region 8 by the second insulating film 23.

[0053] The semiconductor device 1A includes a mesa portion 27 partitioned in the region between the first trench structure 13 and the second trench structure 14 within the chip 2. The mesa portion 27 is partitioned by the inner peripheral wall of the first trench structure 13 and the outer peripheral wall of the second trench structure 14, and includes a part of the first region 6, a part of the second region 7, and a part of the third region 8.

[0054] The mesa portion 27 has a third width W3. The third width W3 is the width (maximum value) in a direction orthogonal to the direction in which the mesa portion 27 extends in a plan view. The third width W3 is also the distance between the first trench structure 13 and the second trench structure 14. The third width W3 may be 0.5 μm or more and 10 μm or less. The third width W3 is preferably 1 μm or more and 3 μm or less. The third width W3 is preferably less than the first width W1 (W1>W3). The third width W3 is particularly preferably less than the second width W2 (W3<W2). Of course, the third width W3 may be equal to or greater than the second width W2 (W2≦W3), or may be equal to or greater than the first width W1 (W1≦W3).

[0055] The semiconductor device 1A includes a p-type first impurity region 31 (semiconductor region) formed in the first polysilicon 17. The first impurity region 31 may be considered a component of the first trench structure 13. The first impurity region 31 is formed in the first polysilicon 17 so as to be electrically connected to the first region 6. Specifically, the first impurity region 31 has an exposed portion exposed from the bottom wall of the first trench 15 (the first removed portion 16a of the first insulating film 16), and is electrically connected to the first high-concentration region 6a of the first region 6 at the exposed portion. The first impurity region 31 preferably forms ohmic contact with the first region 6.

[0056] The first impurity region 31 is preferably located in a thickness range between the bottom wall of the first trench 15 and the first pn junction 9 in a cross-sectional view. It is particularly preferable that the first impurity region 31 is formed in the first polysilicon 17 so as to cross the depth position of the first pn junction 9 in a cross-sectional view. In this embodiment, the first impurity region 31 is formed throughout the entire first polysilicon 17 in a cross-sectional view.

[0057] The first impurity region 31 is formed in a band shape extending along the first polysilicon 17 in a plan view. Specifically, the first impurity region 31 is formed in a ring shape (a quadrangular ring in this embodiment) extending along the first polysilicon 17 in a plan view. That is, the first impurity region 31 is formed over the entire area of ​​the first polysilicon 17 in a plan view and a cross-sectional view.

[0058] In this embodiment, the first impurity region 31 has a concentration gradient in which the p-type impurity concentration gradually decreases from the inner side of the first polysilicon 17 toward the wall surface side of the first trench 15 in a cross-sectional view. In other words, the first impurity region 31 has a concentration gradient in which the p-type impurity concentration on the peripheral side of the first polysilicon 17 is lower than the p-type impurity concentration on the inner side of the first polysilicon 17.

[0059] The first impurity region 31 specifically includes a first concentration portion 32 and a second concentration portion 33. The first concentration portion 32 is a low concentration portion having a relatively low p-type impurity concentration, and is formed in the peripheral portion of the first polysilicon 17. The first concentration portion 32 is specifically formed in the shape of a film extending along the wall surface of the first trench 15, and is electrically connected to the first high concentration region 6a of the first region 6 at the bottom wall of the first trench 15. More specifically, the first concentration portion 32 is formed in the first portion 20 of the first polysilicon 17. The first concentration portion 32 is preferably formed throughout the entire first portion 20.

[0060] The first concentration section 32 includes an n-type impurity (pentavalent element) introduced at a first concentration and a p-type impurity (trivalent element) introduced at a second concentration greater than the first concentration. That is, the first concentration section 32 is composed of a p-type offset region in which an n-type section is replaced with a p-type section. The offset region may also be referred to as a "canceling region" or a "compensation region."

[0061] The p-type impurity concentration (first concentration) of the first concentration portion 32 is 1×10 16 cm -3 More than 1×10 19 cm -3 The n-type impurity concentration (second concentration) of the first concentration portion 32 may be 1×10 12 cm -3 More than 1×10 16 cm -3 The first concentration region 32 may contain boron (B) as a p-type impurity and may contain phosphorus (P) or arsenic (As) as an n-type impurity. The first concentration region 32 preferably contains phosphorus (P) as an n-type impurity.

[0062] The second concentration portion 33 is a high concentration portion having a higher p-type impurity concentration than the first concentration portion 32, and is formed in an inner portion of the first polysilicon 17. Specifically, the second concentration portion 33 is formed in a region surrounded by the first concentration portion 32 within the first polysilicon 17. More specifically, the second concentration portion 33 is formed in the second portion 21 of the first polysilicon 17. It is preferable that the second concentration portion 33 is formed throughout the entire second portion 21.

[0063] The second concentration portion 33 contains p-type impurities (trivalent elements). The p-type impurity concentration of the second concentration portion 33 is 1×10 16 cm -3 More than 1×10 22 cm -3 or less. The p-type impurity concentration of the second concentration portion 33 may be approximately equal to the p-type impurity concentration (first concentration) of the first concentration portion 32. The second concentration portion 33 may contain boron (B) as a p-type impurity. Of course, the second concentration portion 33 may also contain a trace amount of n-type impurity diffused from the first concentration portion 32.

[0064] The semiconductor device 1A includes a p-type second impurity region 34 (semiconductor region) formed in the second polysilicon 24. The second impurity region 34 may be considered a component of the second trench structure 14. The second impurity region 34 is formed in the second polysilicon 24 so as to be electrically connected to the first region 6. Specifically, the second impurity region 34 has an exposed portion exposed from the bottom wall of the second trench 22 (the second removed portion 23a of the second insulating film 23), and is electrically connected to the first high-concentration region 6a of the first region 6 at the exposed portion. The second impurity region 34 preferably forms ohmic contact with the first region 6.

[0065] The second impurity region 34 is preferably located in a thickness range between the bottom wall of the second trench 22 and the first pn junction 9 in a cross-sectional view. The second impurity region 34 is preferably not formed in the entire area of ​​the second polysilicon 24 in a cross-sectional view. The second impurity region 34 is preferably formed at an interval from the upper end to the lower end of the second polysilicon 24 so as not to be exposed from the upper end of the second polysilicon 24 in a cross-sectional view.

[0066] The second impurity region 34 is preferably formed at a distance from the depth position of the first pn junction 9 toward the lower end of the second polysilicon 24 so as not to cross the depth position of the first pn junction 9 in a cross-sectional view. In this embodiment, the second impurity region 34 is formed at a distance from the intermediate portion of the first pn junction 9 and the bottom wall of the second trench 22 toward the lower end of the second polysilicon 24.

[0067] The second impurity region 34 is formed at a distance from the depth position of the boundary between the first high concentration region 6a and the first low concentration region 6b of the first region 6 to the lower end side of the second polysilicon 24 so as not to cross the boundary. In other words, the second impurity region 34 faces the first high concentration region 6a across the second insulating film 23, but does not face the first low concentration region 6b across the second insulating film 23.

[0068] The second impurity region 34 is formed in a band shape extending along the second polysilicon 24 in a plan view. Specifically, the second impurity region 34 is formed in a ring shape (a quadrangular ring in this embodiment) extending along the second polysilicon 24 in a plan view. In other words, the first impurity region 31 is formed over the entire lower end portion of the first polysilicon 17 in a plan view.

[0069] The second impurity region 34 contains n-type impurities introduced at a third concentration and p-type impurities introduced at a fourth concentration that exceeds the third concentration. In other words, the second impurity region 34 is a p-type offset region in which an n-type portion is replaced with a p-type portion. The p-type impurity concentration (third concentration) of the second impurity region 34 is 1×10 17 cm -3More than 1×10 20 cm -3 The n-type impurity concentration (fourth concentration) of the second impurity region 34 may be 1×10 12 cm -3 More than 1×10 16 cm -3 It may be the following:

[0070] The n-type impurity concentration (third concentration) of the second impurity region 34 is preferably approximately equal to the n-type impurity concentration (first concentration) of the first concentration portion 32 of the first impurity region 31. The p-type impurity concentration (fourth concentration) of the second impurity region 34 is preferably different from the p-type impurity concentration (second concentration) of the second concentration portion 33 of the first impurity region 31. The second impurity region 34 contains boron (B) as a p-type impurity and may contain phosphorus (P) or arsenic (As) as an n-type impurity. The second impurity region 34 and the first concentration portion 32 preferably contain phosphorus (P) as an n-type impurity.

[0071] The semiconductor device 1A includes an n-type third impurity region 35 (semiconductor region) formed in a region different from the second impurity region 34 in the second polysilicon 24. The third impurity region 35 may be considered as a component of the second trench structure 14. The third impurity region 35 has a concentration of 1×10 12 cm -3 More than 1×10 16 cm -3 The n-type impurity concentration may be as follows:

[0072] The n-type impurity concentration of the third impurity region 35 is preferably approximately equal to the n-type impurity concentration (first concentration) of the first concentration portion 32 of the first impurity region 31. In other words, the n-type impurity concentration of the third impurity region 35 is preferably approximately equal to the n-type impurity concentration (fourth concentration) of the second impurity region 34. The third impurity region 35 may contain phosphorus (P) or arsenic (As) as the n-type impurity. The third impurity region 35 preferably contains phosphorus (P) as the n-type impurity.

[0073] The third impurity region 35 is formed closer to the upper end of the second polysilicon 24 than the second impurity region 34 in a cross-sectional view. The third impurity region 35 is located in a thickness range between the second impurity region 34 and the first pn junction 9 in a cross-sectional view, and is electrically connected to the second impurity region 34. The third impurity region 35 is preferably electrically connected to the second impurity region 34 in a region on the bottom wall side of the second trench 22 with respect to the depth position of the first pn junction 9 (i.e., a region on the lower end side of the second polysilicon 24).

[0074] The third impurity region 35 is preferably formed to cross the depth position of the first pn junction 9 in a cross-sectional view. In this embodiment, the third impurity region 35 is formed in a thickness range between the upper end of the second polysilicon 24 and the second impurity region 34 so as to be exposed from the upper end of the second polysilicon 24 in a cross-sectional view. The third impurity region 35 faces the first region 6, the second region 7, and the third region 8 with the second insulating film 23 sandwiched therebetween.

[0075] That is, the third impurity region 35 is electrically insulated from the first region 6, the second region 7, and the third region 8 by the second insulating film 23. The third impurity region 35 is formed in a band shape extending along the second polysilicon 24 in a plan view. Specifically, the third impurity region 35 is formed in a ring shape (a quadrangular ring in this embodiment) extending along the second polysilicon 24 in a plan view. That is, the third impurity region 35 is formed in the entire region on the upper end side of the second polysilicon 24 in a plan view.

[0076] The semiconductor device 1A includes a second pn-junction portion 36 formed in the middle part in the thickness direction of the second polysilicon 24. The second pn-junction portion 36 may be regarded as a component of the second trench structure 14. The second pn-junction portion 36 may be referred to as "a second pn-connection portion" or "a second pn-boundary portion". The second pn-junction portion 36 is formed at the boundary between the second impurity region 34 and the third impurity region 35.

[0077] That is, the third impurity region 35 is formed in the second polysilicon 24 so as to form the second impurity region 34 and the second pn-junction portion 36. The second pn-junction portion 36 is located in the region on the bottom wall side of the second trench 22 with respect to the depth position of the first pn-junction portion 9. Also, the second pn-junction portion 36 is formed in the thickness range facing the first high-concentration region 6a of the first region 6 with the second insulating film 23 interposed therebetween.

[0078] The distance DJ between the second pn-junction portion 36 and the bottom wall of the second trench 22 (that is, the thickness of the second impurity region 34) is preferably less than the distance D between the first main surface 3 and the first pn-junction portion 9 (DJ < D). The distance DJ is preferably less than the distance between the first pn-junction portion 9 and the second pn-junction portion 36. The distance DJ is preferably 1 / 2 or less of the second protrusion amount P2 of the second trench structure 14 (DJ < 1 / 2 × P2). The distance DJ is preferably 1 / 2 or less of the first protrusion amount P1 of the first trench structure 13 (DJ < 1 / 2 × P1). The distance DJ may be less than the third width W3 of the mesa portion 27 (DJ < W3).

[0079] As described above, the semiconductor device 1A includes a second diode D2 having the second impurity region 34 as an anode and the third impurity region 35 as a cathode in the second trench 22. That is, the second diode D2 is formed in a region between the first region 6 and the third impurity region 35 via the bottom wall of the second trench 22. The anode of the second diode D2 is electrically connected to the anode of the first diode D1 via the first region 6. That is, the second diode D2 (second pn junction 36) is reverse-bias connected to the first diode D1 (first pn junction 9) via the bottom wall of the second trench 22.

[0080] The semiconductor device 1A includes at least one (in this embodiment, multiple) n-type sinker region 37 covering the sidewall of the second trench structure 14 in the chip 2. The multiple sinker regions 37 are formed in the third region 8 so as to cover the inner and outer peripheral walls of the second trench structure 14, respectively. The multiple sinker regions 37 have a higher n-type impurity concentration than the third region 8. The n-type impurity concentration of the multiple sinker regions 37 is 1×10 15 cm -3 More than 1×10 19 cm -3 It may be the following:

[0081] The plurality of sinker regions 37 extend in the thickness direction of the chip 2 along the inner and outer peripheral walls of the second trench structure 14 in a cross-sectional view. The lower ends of the plurality of sinker regions 37 may be connected to the second region 7 (second high-concentration region 7b). The plurality of sinker regions 37 are each formed in an annular shape extending along the inner and outer peripheral walls of the second trench 22 in a plan view.

[0082] In this embodiment, the sinker region 37 on the outer peripheral wall side is formed at a distance from the first trench structure 13 and does not cover the first trench structure 13. Of course, the sinker region 37 may be formed to cover the inner peripheral wall of the first trench structure 13. Alternatively, the sinker region 37 may be formed to cover the outer peripheral wall of the first trench structure 13.

[0083] The semiconductor device 1A includes a p-type bottom wall region 38 formed in a region along the bottom wall of the first trench structure 13 in the chip 2. The bottom wall region 38 is formed in the first region 6 so as to cover the bottom wall of the first trench structure 13. The bottom wall region 38 has a higher p-type impurity concentration than the first region 6. Specifically, the bottom wall region 38 is formed in the first high concentration region 6a in the first region 6, and has a higher p-type impurity concentration than the first high concentration region 6a. The bottom wall region 38 may cover the lower end of the sidewall of the first trench structure 13.

[0084] 3 and 4, the semiconductor device 1A includes a plurality of first trench isolation structures 41 formed on the first main surface 3. The first trench isolation structures 41 are not shown in FIG. 2. The plurality of first trench isolation structures 41 may also be referred to as shallow trench isolation structures (STI structures). The plurality of first trench isolation structures 41 are formed at intervals from one another to cover the inner and outer circumferential walls of the first trench 15 and expose the first polysilicon 17.

[0085] The multiple first trench insulation structures 41 are formed at intervals from the first pn junction 9 toward the first main surface 3. In this embodiment, the multiple first trench insulation structures 41 are formed at intervals from the second region 7 toward the first main surface 3. That is, the multiple first trench insulation structures 41 are formed within the thickness range of the third region 8. The multiple first trench insulation structures 41 are formed in strip shapes extending along the first trench structure 13 in plan view. In this embodiment, the multiple first trench insulation structures 41 are formed in ring shapes (square rings in this embodiment) extending along the first trench structure 13 in plan view.

[0086] Each first trench isolation structure 41 includes a first shallow trench 42 and a first buried insulator 43. The first shallow trench 42 is formed at a position overlapping the sidewall (inner or outer peripheral wall) of the first trench 15, and exposes the third region 8, the first insulating film 16, and the first polysilicon 17. In other words, the first shallow trench 42 exposes the first impurity region 31.

[0087] The first buried insulator 43 is buried in the first shallow trench 42. The first buried insulator 43 contacts the third region 8, the first insulating film 16, and the first polysilicon 17 in the first shallow trench 42. That is, the first buried insulator 43 contacts the first impurity region 31 (the first concentration portion 32 and the second concentration portion 33) in the first shallow trench 42. The first buried insulator 43 may include at least one of silicon oxide and silicon nitride.

[0088] 3 and 4, the semiconductor device 1A includes a plurality of second trench isolation structures 44 formed on the first main surface 3. The second trench isolation structures 44 are not shown in FIG. 2. The plurality of second trench isolation structures 44 may also be referred to as STI structures. The plurality of second trench isolation structures 44 are formed at intervals from one another to cover the inner and outer circumferential walls of the second trench 22 and expose the second polysilicon 24.

[0089] The plurality of second trench insulation structures 44 are formed at intervals from the first pn junction 9 toward the first main surface 3. In this embodiment, the plurality of second trench insulation structures 44 are formed at intervals from the second region 7 toward the first main surface 3. That is, the plurality of second trench insulation structures 44 are formed within the thickness range of the third region 8. The plurality of second trench insulation structures 44 are formed in strip shapes extending along the second trench structure 14 in plan view. In this embodiment, the plurality of second trench insulation structures 44 are formed in ring shapes (square rings in this embodiment) extending along the second trench structure 14 in plan view.

[0090] Each second trench isolation structure 44 includes a second shallow trench 45 and a second buried insulator 46. The second shallow trench 45 is formed at a position overlapping the sidewall (inner or outer peripheral wall) of the second trench 22, exposing the third region 8, the second insulating film 23, and the second polysilicon 24. The second shallow trench 45 exposes the third impurity region 35 but not the second impurity region 34. In this embodiment, the second shallow trench 45 exposes a plurality of sinker regions 37.

[0091] The second buried insulator 46 is buried in the second shallow trench 45. The second buried insulator 46 contacts the third region 8, the second insulating film 23, and the second polysilicon 24 in the second shallow trench 45. That is, the second buried insulator 46 contacts the third impurity region 35 in the second shallow trench 45. The second buried insulator 46 may include at least one of silicon oxide and silicon nitride.

[0092] 3, the semiconductor device 1A includes a planar-gate MISFET cell 50 as an example of a functional device formed in the transistor region 11. The MISFET cell 50 is not shown in FIG. 2. The MISFET cell 50 can take any one of the following forms depending on the magnitude of the drain-source voltage: a high-voltage (HV) MISFET cell (e.g., 100 V to 1000 V), a middle-voltage (MV) MISFET cell (e.g., 30 V to 100 V), and a low-voltage (LV) MISFET cell (e.g., 1 V to 30 V). While this embodiment describes an example in which the MISFET cell 50 is an HV-MISFET cell, it is not intended to limit the form of the MISFET cell 50 to an HV-MISFET cell.

[0093] In this embodiment, the MISFET cell 50 includes, in cross section, at least one (one in this embodiment) n-type first well region 51, at least one (multiple in this embodiment) p-type second well region 52, at least one (multiple in this embodiment) n-type drain region 53, at least one (multiple in this embodiment) n-type source region 54, at least one (multiple in this embodiment) p-type channel region 55, at least one (multiple in this embodiment) p-type contact region 56, and at least one (multiple in this embodiment) planar gate structure 57.

[0094] The first well region 51 is formed in a surface layer portion of the third region 8 in the transistor region 11. The first well region 51 has a higher n-type impurity concentration than the third region 8. The plurality of second well regions 52 are formed in a surface layer portion of the third region 8 at intervals from the first well region 51 in the transistor region 11. One of the second well regions 52 is formed at an interval on one side of the first well region 51 in the first direction X, and the other second well region 52 is formed at an interval on the other side of the first direction X from the first well region 51.

[0095] The drain region 53 is formed in a surface layer portion of the first well region 51 at a distance inward from the periphery of the first well region 51. The plurality of source regions 54 are each formed in a surface layer portion of the corresponding second well region 52 at a distance inward from the periphery of the corresponding second well region 52. The plurality of channel regions 55 are each formed between the third region 8 and the source region 54 in the surface layer portion of the corresponding second well region 52. The plurality of contact regions 56 are each formed in a surface layer portion of the corresponding second well region 52 at a distance inward from the periphery of the corresponding second well region 52. The plurality of contact regions 56 are adjacent to the corresponding source region 54.

[0096] The plurality of planar gate structures 57 are formed on the first main surface 3 so as to cover the corresponding channel regions 55, and control the on / off of the corresponding channel regions 55. In this embodiment, the plurality of planar gate structures 57 are each formed so as to straddle the first well region 51 and the corresponding source region 54.

[0097] The plurality of planar gate structures 57 include a gate insulating film 58 and a gate electrode 59 stacked in this order from the first main surface 3 side. The gate insulating film 58 may include a silicon oxide film. The gate insulating film 58 preferably includes a silicon oxide film made of an oxide of the chip 2. The gate electrode 59 preferably includes polysilicon. The gate electrode 59 may include either or both of an n-type region and a p-type region formed in the polysilicon.

[0098] 3, the semiconductor device 1A includes a plurality of third trench isolation structures 60 formed on the first main surface 3. The third trench isolation structures 60 are not shown in FIG. 2. The plurality of third trench isolation structures 60 may also be referred to as STI structures. In this embodiment, the plurality of third trench isolation structures 60 are formed spaced apart from one another so as to separate the drain region 53 from other regions and to separate the outer edges of the plurality of second well regions 52 from other regions.

[0099] The plurality of third trench insulation structures 60 are formed at intervals from the first pn junction 9 toward the first main surface 3. In this embodiment, the plurality of third trench insulation structures 60 are formed at intervals from the second region 7 toward the first main surface 3. In other words, the plurality of third trench insulation structures 60 are formed within the thickness range of the third region 8.

[0100] Each third trench isolation structure 60 includes a third shallow trench 61 and a third buried insulator 62. The third shallow trench 61 is dug down from the first main surface 3 toward the second main surface 4. The third buried insulator 62 is buried in the third shallow trench 61. The third buried insulator 62 may include at least one of silicon oxide and silicon nitride.

[0101] In the transistor region 11, a drain potential VD is applied to the drain region 53 via a drain contact electrode 63. In FIG. 3, the drain contact electrode 63 is simply indicated by an arrow. The drain potential VD is the maximum device potential in the transistor region 11. A source potential VS less than the drain potential VD is applied to the source region 54 via a source contact electrode 64. In FIG. 3, the source contact electrode 64 is simply indicated by an arrow. A gate potential VG is applied to the gate electrode 59 via a gate contact electrode 65. In FIG. 3, the gate contact electrode 65 is simply indicated by an arrow.

[0102] A first potential V1 is applied to the first trench structure 13 via a first contact electrode 71. In FIGS. 3 and 4, the first contact electrode 71 is simply indicated by an arrow. The first potential V1 is also a potential applied to the first impurity region 31. The first potential V1 applied to the first trench structure 13 is applied to the first region 6 via the first trench structure 13.

[0103] This fixes the first region 6 to the same potential as the first trench structure 13. The first potential V1 is preferably a potential equal to or lower than the drain potential VD (preferably lower than the drain potential VD). In other words, the first potential V1 is preferably lower than the maximum device potential. The first potential V1 may be a reference potential that serves as a reference for circuit operation, or may be ground potential. The first potential V1 is preferably ground potential.

[0104] A second potential V2 is applied to the second trench structure 14 via a second contact electrode 72. In Figures 3 and 4, the second contact electrode 72 is simply indicated by an arrow. The second potential V2 is preferably a potential equal to or lower than the drain potential VD (preferably lower than the drain potential VD). In other words, the second potential V2 is preferably lower than the maximum device potential.

[0105] The second potential V2 is preferably equal to or higher than the first potential V1 (V1≦V2). Particularly preferably, the second potential V2 exceeds the first potential V1 (V1<V2). The potential difference V2-V1 between the second potential V2 and the first potential V1 is preferably set to be a reverse bias voltage with respect to the second pn junction 36 (the second diode D2). Under this condition, the conduction (forward current) of the second diode D2 in the second trench structure 14 is reliably suppressed.

[0106] The second potential V2 may be a reference potential, a ground potential, or a floating potential. The floating potential means that the second trench structure 14 is formed in an electrically floating state. In this case, since no specific potential is applied to the second trench structure 14 from a specific member or region, the second potential V2 that varies due to the potential around the second trench structure 14 is applied to the second trench structure 14.

[0107] A third potential V3 is applied to the mesa portion 27 via the third contact electrode 73. In FIGS. 3 and 4, the third contact electrode 73 is shown simplified by an arrow. The third potential V3 is preferably a potential equal to or lower than the drain potential VD (preferably less than the drain potential VD). That is, the third potential V3 is preferably less than the maximum device potential.

[0108] The third potential V3 is preferably equal to or higher than the first potential V1 (V1≦V3). Particularly preferably, the third potential V3 exceeds the first potential V1 (V1<V3). The third potential V3 is preferably equal to or lower than the second potential V2 (V3≦V2). Particularly preferably, the third potential V3 is less than the second potential V2 (V3<V2). In this case, the first to third potentials V1 to V3 are preferably set to gradually decrease in the direction away from the transistor region 11 (in the order of VD>V2>V3>V1).

[0109] The potential difference V3-V1 between the third potential V3 and the first potential V1 is preferably set to be a reverse bias voltage with respect to the first pn junction 9 (first diode D1). This condition reliably suppresses conduction (forward current) of the first diode D1 in the mesa portion 27.

[0110] The third potential V3 may be a reference potential, a ground potential, or a floating potential. A floating potential means that the mesa portion 27 is formed in an electrically floating state. In this case, no specific potential is applied to the mesa portion 27 from a specific member or region, and therefore the third potential V3, which fluctuates depending on the potential around the mesa portion 27, is applied to the mesa portion 27.

[0111] As described above, the semiconductor device 1A includes a chip 2, a first region 6 of p-type (first conductivity type), a second region 7 of n-type (second conductivity type), a transistor region 11 (device region 10), a first trench structure 13 (first groove structure), and a second trench structure 14 (second groove structure). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The first region 6 is formed on the second main surface 4 side within the chip 2. The second region 7 is formed on the first main surface 3 side within the chip 2, and forms a first pn junction 9 with the first region 6. The transistor region 11 is provided on the first main surface 3.

[0112] The first trench structure 13 defines the transistor region 11 on the first main surface 3. The first trench structure 13 includes a first trench 15 (first groove), a first insulating film 16, and a first polysilicon 17. The first trench 15 penetrates from the first main surface 3 to the first pn junction 9. The first insulating film 16 exposes the first region 6 from the wall surface of the first trench 15. The first polysilicon 17 is buried in the first trench 15 with the first insulating film 16 sandwiched therebetween.

[0113] The second trench structure 14 defines the transistor region 11 on the first main surface 3, closer to the transistor region 11 than the first trench structure 13. The second trench structure 14 includes a second trench 22 (second groove), a second insulating film 23, and second polysilicon 24. The second trench 22 penetrates from the first main surface 3 to the first pn junction 9. The second insulating film 23 exposes the first region 6 from the wall surface of the second trench 22. The second polysilicon 24 is embedded in the second trench 22 with the second insulating film 23 sandwiched therebetween.

[0114] According to this structure, a semiconductor device 1A can be provided that can improve the breakdown voltage (withstand voltage) by using a multi-trench isolation structure including a first trench structure 13 that exposes the first region 6 and a second trench structure 14 that exposes the first region 6.

[0115] The first polysilicon 17 is preferably connected to the first region 6 and buried in the first trench 15 with a first insulating film 16 interposed therebetween so as to be electrically insulated from the second region 7. The second polysilicon 24 is preferably connected to the first region 6 and buried in the second trench 22 with a second insulating film 23 interposed therebetween so as to be electrically insulated from the second region 7.

[0116] The semiconductor device 1A preferably includes a p-type first impurity region 31 formed in the first polysilicon 17 and a p-type second impurity region 34 formed in the second polysilicon 24. The first impurity region 31 is preferably located in a thickness range between the bottom wall of the first trench 15 and the first pn junction 9 so as to be electrically connected to the first region 6. The second impurity region 34 is preferably located in a thickness range between the bottom wall of the second trench 22 and the first pn junction 9 so as to be electrically connected to the first region 6.

[0117] The second impurity region 34 is preferably formed in a region on the lower end side of the second polysilicon 24, spaced from the upper end toward the lower end side of the second polysilicon 24. The second impurity region 34 is preferably formed in a partial region of the second polysilicon 24, and not formed throughout the entire second polysilicon 24. The second impurity region 34 is preferably formed in a region on the lower end side of the second polysilicon 24 so as not to cross the depth position of the first pn junction 9. The first impurity region 31 is preferably formed in the first polysilicon 17 so as to cross the depth position of the first pn junction 9. The first impurity region 31 is preferably formed throughout the entire first polysilicon 17.

[0118] The semiconductor device 1A preferably includes an n-type third impurity region 35 formed in a region different from the second impurity region 34 inside the second polysilicon 24. The third impurity region 35 preferably forms a second pn junction 36 together with the second impurity region 34 inside the second trench 22. The third impurity region 35 is preferably formed in a region on the upper end side of the second polysilicon 24 so as to form the second pn junction 36 together with the second impurity region 34 in a region on the lower end side of the second polysilicon 24 with respect to the depth position of the first pn junction 9.

[0119] The structure having the second pn junction 36 (the second impurity region 34 and the third impurity region 35) provides the effects described below with reference to Figures 5 and 6. Figure 5 is an enlarged view of a main part showing the electric field distribution (see the thick line in Figure 5) of a semiconductor device 74 according to a reference embodiment. In the semiconductor device 74 according to the reference example, a second insulating film 23 is formed to cover the entire wall surface of the second trench 22, and the second polysilicon 24 is electrically insulated from the first region 6.

[0120] The semiconductor device 74 according to the reference example includes a p-type impurity region 75 formed throughout the entire interior of the second polysilicon 24. In other words, the second pn junction 36 (i.e., the second diode D2) is not formed within the second polysilicon 24. In the semiconductor device 74 according to the reference example, a region where the electric field distribution becomes dense is formed at the intersection of the second trench structure 14 and the first pn junction 9 (see the region enclosed by the two-dot chain line in FIG. 5). In the semiconductor device 74 according to the reference example, this type of electric field concentration causes a decrease in the breakdown voltage (i.e., the breakdown voltage).

[0121] 6 is an enlarged view of a main portion showing the electric field distribution (see the thick line in FIG. 6) of the semiconductor device 1A shown in FIG. 1. Referring to FIG. 6, unlike the semiconductor device 74 according to the reference example, the semiconductor device 1A includes a chip 2, a first pn junction 9, a transistor region 11 (device region 10), a second trench structure 14 (groove structure), and a second pn junction 36. The chip 2 has a first main surface 3. The first pn junction 9 is formed in the chip 2 so as to extend along the first main surface 3. The transistor region 11 is provided on the first main surface 3.

[0122] The second trench structure 14 defines the transistor region 11 on the first main surface 3. The second trench structure 14 includes a second trench 22 (groove), a second insulating film 23, and a second polysilicon 24. The second trench 22 penetrates from the first main surface 3 to a second pn junction 36. The second insulating film 23 exposes the first region 6 from the wall surface of the second trench 22. The second polysilicon 24 is buried in the second trench 22 with the second insulating film 23 sandwiched therebetween. The second pn junction 36 is formed in the second polysilicon 24.

[0123] This structure makes it possible to make the electric field distribution sparse at the intersection of the second trench structure 14 and the first pn junction 9. This makes it possible to suppress electric field concentration in the second trench structure 14, thereby providing a semiconductor device 1A that can improve the breakdown voltage (i.e., withstand voltage).

[0124] In such a structure, the second pn junction 36 is preferably reverse-bias connected to the first pn junction 9 via the bottom wall of the second trench 22. The second pn junction 36 is preferably located in a region closer to the bottom wall of the second trench 22 with respect to the depth position of the first pn junction 9. That is, the second impurity region 34 is preferably formed in a region closer to the lower end of the second polysilicon 24 with respect to the depth position of the first pn junction 9, and the third impurity region 35 is preferably formed in the second polysilicon 24 so as to cross the depth position of the first pn junction 9. The distance from the first pn junction 9 to the bottom wall of the second trench 22 is preferably greater than the distance from the first pn junction 9 to the first main surface 3.

[0125] 7A to 7N are cross-sectional views showing an example of a manufacturing method for the semiconductor device 1A shown in FIG. 1. FIGS. 7A to 7N are cross-sectional views of a portion corresponding to FIG. 4. The manufacturing process for the trench isolation structure 12 and its surrounding structure will be described below. Referring to FIG. 7A, a disk-shaped epitaxial wafer 80 is prepared. The epitaxial wafer 80 has a wafer main surface 81. The epitaxial wafer 80 includes a first region 6, a second region 7, and a third region 8. The first region 6 includes a first high-concentration region 6a and a first low-concentration region 6b. The first high-concentration region 6a is made of a p-type wafer. The first low-concentration region 6b is made of a p-type epitaxial layer stacked on the wafer by epitaxial growth.

[0126] The second region 7 includes a second low-concentration region 7a and a second high-concentration region 7b. The second low-concentration region 7a is made of an n-type epitaxial layer deposited on the first low-concentration region 6b by epitaxial growth. The second high-concentration region 7b is made of an n-type epitaxial layer deposited on the second low-concentration region 7a by epitaxial growth. The third region 8 is made of an n-type epitaxial layer deposited on the second high-concentration region 7b by epitaxial growth.

[0127] Next, referring to FIG. 7B , a first mask 82 having a predetermined pattern is formed on the wafer main surface 81. The first mask 82 exposes regions of the wafer main surface 81 where the first trenches 15 and second trenches 22 are to be formed, and covers other regions. Next, the epitaxial wafer 80 is selectively removed by etching through the first mask 82. The etching method may be dry etching and / or wet etching. In this process, the first trenches 15 and second trenches 22 are formed, exposing at least the third region 8 and not exposing the first region 6. The width of the second trenches 22 is less than the width of the first trenches 15. The first mask 82 is then removed.

[0128] Next, referring to FIG. 7C, a second mask 83 having a predetermined pattern is formed on the wafer main surface 81. The second mask 83 exposes the second trench 22 and covers the other regions. Next, n-type impurities are introduced into the wall surface of the second trench 22 by ion implantation via the second mask 83. This forms n-type sinker regions 37 along the wall surface of the second trench 22 in the third region 8. Thereafter, the second mask 83 is removed.

[0129] Next, referring to FIG. 7D , a third mask 84 having a predetermined pattern is formed on the wafer main surface 81. The third mask 84 exposes regions on the wafer main surface 81 where the first trench 15 and the second trench 22 are to be formed, and covers other regions. Next, the epitaxial wafer 80 is selectively removed by etching through the third mask 84, and the first trench 15 and the second trench 22 are further deepened. The first trench 15 and the second trench 22 are deepened to penetrate the third region 8 and the second region 7 and reach the first region 6. The etching method is preferably RIE (reactive ion etching), an example of a dry etching method. Thereafter, the third mask 84 is removed.

[0130] 7E, a base insulating film 85 that serves as a base for the first insulating film 16 and the second insulating film 23 is formed on the wafer main surface 81. This process includes forming a lower base insulating film 86 and an upper base insulating film 87 in this order from the wafer main surface 81 side. The lower base insulating film 86 serves as a base for the first lower insulating film 18 of the first insulating film 16 and the second lower insulating film 25 of the second insulating film 23. The lower base insulating film 86 may be formed by an oxidation process (for example, a thermal oxidation process). The upper base insulating film 87 may be formed by a CVD (chemical vapor deposition) process. A base insulating film 85 is formed that includes the lower base insulating film 86 and the upper base insulating film 87 that has a density different from that of the lower base insulating film 86.

[0131] 7F , a fourth mask 88 having a predetermined pattern is formed on the base insulating film 85. The fourth mask 88 exposes the portions of the base insulating film 85 that cover the first trench 15 and the second trench 22, and covers the remaining regions. Next, by etching using the fourth mask 88, the portions of the base insulating film 85 that cover the bottom walls of the first trench 15 and the second trench 22 are removed.

[0132] The etching method is preferably an anisotropic etching method. The etching method may be, for example, an RIE method, which is an example of a dry etching method. As a result, a first removed portion 16a exposing the bottom wall of the first trench 15 and a second removed portion 23a exposing the bottom wall of the second trench 22 are formed. In this step, the first removed portion 16a exposing the lower end of the side wall of the first trench 15 may be formed. Also, the second removed portion 23a exposing the lower end of the side wall of the second trench 22 may be formed. Thereafter, the fourth mask 88 is removed.

[0133] 7G, a first polysilicon film 89, which serves as the base of the first portion 20 of the first polysilicon 17 and the second polysilicon 24, is formed on the base insulating film 85. In this embodiment, the first polysilicon film 89 is made of undoped polysilicon with no added impurities. The first polysilicon film 89 may be formed by a CVD method. The first polysilicon film 89 is formed in a film shape on the base insulating film 85 so as to follow the wafer main surface 81, the wall surfaces of the first trench 15, and the wall surfaces of the second trench 22.

[0134] The first polysilicon film 89 backfills the entire second trench 22 and defines a recess space within the first trench 15. The first polysilicon film 89 does not necessarily need to backfill the second trench 22 completely, and may be formed in the form of a film on the wall surface of the second trench 22 so as to define the recess space.

[0135] 7H, n-type impurities (pentavalent elements) are introduced into the first polysilicon film 89 by ion implantation. This gives the first polysilicon film 89 an n-type conductivity. If the first polysilicon film 89 defines a recess space in the second trench 22, the first polysilicon film 89 may be formed again to fill the recess space in the second trench 22 before or after the step of introducing the n-type impurities. Of course, the first polysilicon film 89 may be made of doped polysilicon to which n-type impurities have been added. In this case, the step of FIG. 7H may be omitted.

[0136] Next, referring to FIG. 7I, a second polysilicon film 90, which will be the base of the second portion 21 of the first polysilicon 17, is formed on the first polysilicon film 89. In this embodiment, the first polysilicon film 89 is made of doped polysilicon into which p-type impurities (trivalent elements) have been introduced. The first polysilicon film 89 may be formed by a CVD method. The second polysilicon film 90 is formed in a film shape on the first polysilicon film 89 so as to conform to the wafer main surface 81 and the wall surfaces of the first trench 15. The second polysilicon film 90 backfills the recess space defined by the first polysilicon film 89 in the first trench 15.

[0137] 7J, the first polysilicon film 89 and the second polysilicon film 90 are selectively removed. This process includes removing the second polysilicon film 90, the first polysilicon film 89, and the base insulating film 85 by a grinding method until the epitaxial wafer 80 (third region 8) is exposed. The grinding method may be a chemical mechanical polishing (CMP) method. As a result, the first insulating film 16 and the first polysilicon 17 are formed in the first trench 15, and the second insulating film 23 and the second polysilicon 24 are formed in the second trench 22. Of course, in this process, an etching method (wet etching method and / or dry etching method) may be used instead of the grinding method.

[0138] 7K, the epitaxial wafer 80 is subjected to a heat treatment (drive-in treatment) to diffuse the p-type impurities in the first polysilicon 17 into the first polysilicon 17. This process changes the conductivity type of the first portion 20 in the first polysilicon 17 from n-type to p-type. As a result, a p-type first impurity region 31 is formed throughout the inside of the first polysilicon 17.

[0139] In this step, the n-type impurities in the second polysilicon 24 are diffused into the second polysilicon 24. In this step, the p-type impurities (trivalent elements) in the first region 6 (first high-concentration region 6a) are diffused to the lower end of the second polysilicon 24 through the bottom wall of the second trench 22. As a result, a p-type second impurity region 34 is formed in a region on the lower end side of the second polysilicon 24, and an n-type third impurity region 35 is formed in a region on the upper end side of the second polysilicon 24. In this step, the p-type impurities in the first polysilicon 17 are diffused into the first region 6 through the bottom wall of the first trench 15. As a result, a p-type bottom wall region 38 having a higher concentration than the first region 6 is formed in a region along the bottom wall of the first trench 15 in the first region 6.

[0140] Next, referring to FIG. 7L, a fifth mask 91 having a predetermined pattern is formed on the wafer main surface 81. The fifth mask 91 exposes regions of the wafer main surface 81 where the first shallow trenches 42, the second shallow trenches 45, and the third shallow trenches 61 are to be formed, and covers the remaining regions. Next, the epitaxial wafer 80, the first insulating film 16, the first polysilicon 17, the second insulating film 23, and the second polysilicon 24 are selectively removed by etching (wet etching and / or dry etching) through the fifth mask 91. This forms the first shallow trenches 42, the second shallow trenches 45, and the third shallow trenches 61. The fifth mask 91 is then removed.

[0141] 7M, a base buried insulating film 92 that serves as a base for the plurality of first buried insulators 43, the plurality of second buried insulators 46, and the plurality of third buried insulators 62 is formed on the wafer main surface 81. The base insulating film 85 may be formed by a CVD method.

[0142] Next, referring to FIG. 7N, unnecessary portions of the base-buried insulating film 92 are removed. In this step, the unnecessary portions of the base-buried insulating film 92 are removed by a grinding method until the epitaxial wafer 80 (third region 8) is exposed. The grinding method may be a CMP method. As a result, a plurality of first buried insulators 43, a plurality of second buried insulators 46, and a plurality of third buried insulators 62 are formed. Of course, the unnecessary portions of the base-buried insulating film 92 may be removed by an etching method (wet etching method and / or dry etching method) instead of the grinding method. The semiconductor device 1A is formed by the steps including those described above.

[0143] 8 is a cross-sectional view showing a semiconductor device 1B according to a third embodiment. Referring to FIG. 8, the semiconductor device 1B includes a first concentration portion 101 in place of the first concentration portion 32 in the first impurity region 31. Like the first concentration portion 32, the first concentration portion 101 has a relatively low p-type impurity concentration and is formed in the peripheral portion of the first polysilicon 17. In this embodiment, the first concentration portion 101 includes only p-type impurities (trivalent elements) and does not include n-type impurities (pentavalent elements). Of course, the first concentration portion 101 may also include n-type impurities.

[0144] The semiconductor device 1B includes a resistor region 102 in place of the third impurity region 35 in the second polysilicon 24. The resistor region 102 may be considered a component of the second trench structure 14. The resistor region 102 has a lower impurity concentration than the second impurity region 34 and a higher resistance value than the second impurity region 34. The resistor region 102 also has a lower impurity concentration than the first impurity region 31 and a higher resistance value than the first impurity region 31. In this embodiment, the resistor region 102 is made of an undoped region of the second polysilicon 24.

[0145] The resistance region 102 is formed closer to the upper end of the second polysilicon 24 than the second impurity region 34 in a cross-sectional view. The resistance region 102 is located in a thickness range between the second impurity region 34 and the first pn junction 9 in a cross-sectional view, and is electrically connected to the second impurity region 34. The resistance region 102 is preferably electrically connected to the second impurity region 34 in a region on the bottom wall side of the second trench 22 with respect to the depth position of the first pn junction 9 (i.e., a region on the lower end side of the second polysilicon 24).

[0146] The resistance region 102 is preferably formed so as to cross the depth position of the first pn junction 9 in a cross-sectional view. In this embodiment, the resistance region 102 is formed in a thickness range between the upper end of the second polysilicon 24 and the second impurity region 34 so as to be exposed from the upper end of the second polysilicon 24 in a cross-sectional view. The resistance region 102 faces the first region 6, the second region 7, and the third region 8 with the second insulating film 23 sandwiched therebetween.

[0147] That is, the resistance region 102 is electrically insulated from the first region 6, the second region 7, and the third region 8 by the second insulating film 23. The resistance region 102 is formed in a band shape extending along the second polysilicon 24 in a plan view. Specifically, the resistance region 102 is formed in a ring shape (a quadrangular ring in this embodiment) extending along the second polysilicon 24 in a plan view. That is, the resistance region 102 is formed over the entire region on the upper end side of the second polysilicon 24 in a plan view and a cross-sectional view.

[0148] The semiconductor device 1B includes a node portion 103 formed in the middle portion in the thickness direction of the second polysilicon 24. The node portion 103 may be regarded as a component of the second trench structure 14. The node portion 103 is a connection portion between the second impurity region 34 and the resistance region 102. That is, the resistance region 102 is formed in the second polysilicon 24 so as to form the second impurity region 34 and the node portion 103. The node portion 103 is located in a region on the bottom wall side of the second trench 22 with respect to the depth position of the first pn junction 9. Further, the node portion 103 is formed in a thickness range facing the first high-concentration region 6a of the first region 6 with the second insulating film 23 interposed therebetween.

[0149] The distance DN between the node portion 103 and the bottom wall of the second trench 22 (that is, the thickness of the second impurity region 34) is preferably less than the distance D between the first main surface 3 and the first pn junction 9 (DN < D) (see also FIG. 4). The distance DN is preferably less than the distance between the first pn junction 9 and the node portion 103. The distance DN is preferably 1 / 2 or less of the second protrusion amount P2 of the second trench structure 14 (DN < 1 / 2×P2). The distance DN is preferably 1 / 2 or less of the first protrusion amount P1 of the first trench structure 13 (DN < 1 / 2×P1). The distance DN may be less than the third width W3 of the mesa portion 27 (DN < W3).

[0150] The application conditions of the first to third potentials V1 to V3 are the same as those in the case of the first embodiment. The first impurity region 31, the second impurity region 34, and the resistance region 102 of the semiconductor device 1B are formed of a polysilicon having a relatively low impurity concentration (p-type impurity concentration or n-type impurity concentration) or a non-doped polysilicon without impurity addition in the step of FIG. 7G described above, and then the step of FIG. 7H is omitted. As described above, the semiconductor device 1B also exhibits the same effects as those described for the semiconductor device 1A.

[0151] 9 is a cross-sectional view showing a semiconductor device 1C according to a third embodiment. FIG. 9 is a cross-sectional view of a portion corresponding to FIG. 4. Referring to FIG. 9, the semiconductor device 1C includes a p-type first contact region 104 formed in a surface layer portion on the upper end side of the first polysilicon 17. The first contact region 104 has a higher p-type impurity concentration than the first impurity region 31 (second concentration portion 33). The first contact region 104 is preferably formed at an interval from the depth position of the second region 7 (the bottom of the third region 8) toward the first main surface 3.

[0152] The semiconductor device 1C includes an n-type second contact region 105 formed in a surface layer portion on the upper end side of the second polysilicon 24. The second contact region 105 has a higher n-type impurity concentration than the third impurity region 35. The second contact region 105 is preferably formed at a distance from the depth position of the second region 7 (the bottom of the third region 8) toward the first main surface 3.

[0153] The semiconductor device 1C includes an n-type third contact region 106 formed in a surface layer portion of the mesa portion 27. The third contact region 106 has a higher n-type impurity concentration than the third region 8. The third contact region 106 is preferably formed at a distance from the depth position of the second region 7 (the bottom of the third region 8) toward the first main surface 3.

[0154] As described above, the semiconductor device 1C also achieves the same effects as those described for the semiconductor device 1A. According to the semiconductor device 1C, the ohmic contact of the first contact electrode 71 with respect to the first impurity region 31 can be improved by the first contact region 104. According to the semiconductor device 1C, the ohmic contact of the second contact electrode 72 with respect to the third impurity region 35 can be improved by the second contact region 105. According to the semiconductor device 1C, the ohmic contact of the third contact electrode 73 with respect to the mesa portion 27 can be improved by the third contact region 106.

[0155] The semiconductor device 1C only needs to include at least one of the first to third contact regions 104 to 106, and does not need to simultaneously include all of the first to third contact regions 104 to 106. Furthermore, at least one of the first to third contact regions 104 to 106 may be applied to the second embodiment.

[0156] Modifications that can be applied to the first to third embodiments described above will be described below with reference to Figures 10 to 14. The following modifications or combinations of the following modifications are appropriately applied to the first to third embodiments described above.

[0157] FIG. 10 is a cross-sectional view showing the second region 7 according to the first modification. Here, an example in which the second region 7 according to the first modification is applied to the first embodiment is shown, but the second region 7 according to the first modification can also be applied to the second and third embodiments. Referring to FIG. 10, the second region 7 according to the first modification may have a single-layer structure including only either the second low-concentration region 7a or the second high-concentration region 7b. Even with such a structure, the same effects as those described for the semiconductor device 1A can be achieved.

[0158] 11 is a cross-sectional view showing the second region 7 according to the second modification. Here, an example is shown in which the second region 7 according to the second modification is applied to the first embodiment, but the second region 7 according to the second modification can also be applied to the second and third embodiments. Referring to FIG. 11, the second region 7 according to the second modification is formed in a region surrounded by the second trench structure 14 and spaced apart from the second trench structure 14. In other words, the second region 7 exposes the first region 6 in the region between the second trench structure 14 and the second trench structure 14.

[0159] The second region 7 may have a multilayer structure including the second low-concentration region 7 a and the second high-concentration region 7 b, or may have a single-layer structure including only one of the second low-concentration region 7 a and the second high-concentration region 7 b. In this embodiment, the first pn junction 9 is formed at the boundary between the first region 6 and the second region 7 and at the boundary between the first region 6 and the third region 8. This structure also achieves the same effects as those described for the semiconductor device 1A.

[0160] FIG. 12 is a cross-sectional view showing the second region 7 according to the third modification. Here, an example is shown in which the second region 7 according to the third modification is applied to the first embodiment, but the second region 7 according to the third modification can also be applied to the second and third embodiments. Referring to FIG. 12, the second region 7 according to the third modification is formed as part of the third region 8. That is, the second region 7 according to the third modification is formed with the n-type impurity concentration of the third region 8. In other words, the third region 8 is formed with an n-type impurity concentration approximately equal to that of the second region 7. This structure also achieves the same effects as those described for the semiconductor device 1A.

[0161] 13 is a cross-sectional view showing a first region 6 according to a modified example. Here, an example in which the first region 6 according to the modified example is applied to the first embodiment is shown, but the first region 6 according to the modified example can also be applied to the second and third embodiments. Referring to FIG. 13, the first region 6 according to the modified example has a single-layer structure made of a p-type semiconductor substrate 107 in this embodiment. Even with such a structure, the same effects as those described for the semiconductor device 1A can be achieved.

[0162] 14 is a cross-sectional view showing a first removal section 16a and a second removal section 23a according to a modified example. Here, an example is shown in which the first removal section 16a and the second removal section 23a according to the modified example are applied to the first embodiment, but the first removal section 16a and the second removal section 23a according to the modified example can also be applied to the second and third embodiments.

[0163] 14, first removed portion 16a may expose first region 6 (first high-concentration region 6a) from either or both of the lower end of the inner circumferential wall and the lower end of the outer circumferential wall of first trench 15, in addition to the bottom wall of first trench 15. Furthermore, second removed portion 23a may expose first region 6 (first high-concentration region 6a) from either or both of the lower end of the inner circumferential wall and the lower end of the outer circumferential wall of second trench 22, in addition to the bottom wall of second trench 22.

[0164] Although the embodiments and modifications have been described above, the above-described embodiments can be implemented in other forms. For example, in each of the above-described embodiments, an example has been described in which the trench isolation structure 12 defines the transistor region 11. However, the device region 10 defined by the trench isolation structure 12 is not limited to the transistor region 11. In other words, the trench isolation structure 12 may define the device region 10 in which at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device is formed.

[0165] In each of the above-described embodiments, the trench isolation structure 12 may include a plurality of first trench structures 13. In this case, the plurality of first trench structures 13 may be formed at intervals (for example, a third width W3) from one another so as to surround the device region 10. In other words, the plurality of first trench structures 13 may define a plurality of mesa portions 27.

[0166] The same first potential V1 may be applied to the plurality of first trench structures 13, or a plurality of first potentials V1 may be applied thereto that are set to gradually decrease in the direction away from the device region 10. The same third potential V3 may be applied to the plurality of mesa portions 27, or a plurality of third potentials V3 may be applied thereto that are set to gradually decrease in the direction away from the device region 10.

[0167] In each of the above-described embodiments, the trench isolation structure 12 may include a plurality of second trench structures 14. In this case, the plurality of second trench structures 14 may be formed at intervals (for example, a third width W3) between the device region 10 and the first trench structure 13 so as to surround the device region 10. In other words, the plurality of second trench structures 14 may define a plurality of mesa portions 27.

[0168] The same second potential V2 may be applied to the plurality of second trench structures 14, or a plurality of second potentials V2 may be applied thereto that are set to gradually decrease in the direction away from the device region 10. The same third potential V3 may be applied to the plurality of mesa portions 27, or a plurality of third potentials V3 may be applied thereto that are set to gradually decrease in the direction away from the device region 10.

[0169] Of course, in each of the above-described embodiments, a plurality of first trench structures 13 and a single second trench structure 14 may be formed. Also, in each of the above-described embodiments, a single first trench structure 13 and a plurality of second trench structures 14 may be formed. Also, in each of the above-described embodiments, a plurality of first trench structures 13 and a plurality of second trench structures 14 may be formed. In these cases, the first to third potentials V1 to V3 may be set to gradually decrease in a direction away from the device region 10.

[0170] In the above-described embodiments, examples have been described in which the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type may be n-type and the second conductivity type may be p-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings. The terms "first conductivity type" and "second conductivity type" are merely expressions used to clarify the order of the description, and the p-type may be expressed as the "second conductivity type" and the n-type as the "first conductivity type."

[0171] In each of the above-described embodiments, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically, perpendicular) relationship.

[0172] Below, examples of features extracted from this specification and drawings are presented. Below, a semiconductor device capable of improving breakdown voltage is provided. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments.

[0173] [A1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, a first region (6) of a first conductivity type (p-type) formed on the second main surface (4) side in the chip (2), second regions (7, 8) of a second conductivity type (n-type) formed on the first main surface (3) side in the chip (2) and forming a pn junction (9) with the first region (6), device regions (10, 11) provided on the first main surface (3), a first trench (15) penetrating the pn junction (9) from the first main surface (3), a first insulating film (16) exposing the first region (6) from a wall surface of the first trench (15), and a first insulating film (17) formed on the first insulating film (18). a first trench structure (13) including first polysilicon (17) embedded in the first trench (15) across a pn junction (9) and partitioning the device regions (10, 11); a second trench (22) penetrating from the first main surface (3) through the pn junction (9), a second insulating film (23) exposing the first region (6) from a wall surface of the second trench (22), and a second trench structure (14) including second polysilicon (24) embedded in the second trench (22) across the second insulating film (23), and partitioning the device regions (10, 11) on the side of the device region (10, 11) relative to the first trench structure (13).

[0174] [A2] The semiconductor device (1A, 1B, 1C) according to A1, wherein the first polysilicon (17) is connected to the first region (6) and buried in the first trench (15) with the first insulating film (16) sandwiched therebetween so as to be electrically insulated from the second region (7, 8), and the second polysilicon (24) is connected to the first region (6) and buried in the second trench (22) with the second insulating film (23) sandwiched therebetween so as to be electrically insulated from the second region (7, 8).

[0175] [A3] The semiconductor device (1A, 1B, 1C) according to A1 or A2, further including a first impurity region (31) of a first conductivity type (p-type) formed in the first polysilicon (17), and a second impurity region (34) of the first conductivity type (p-type) formed in the second polysilicon (24).

[0176] [A4] A semiconductor device (1A, 1B, 1C) according to A3, wherein the first impurity region (31) is located in a thickness range between a bottom wall of the first trench (15) and the pn junction (9) so as to be electrically connected to the first region (6), and the second impurity region (34) is located in a thickness range between a bottom wall of the second trench (22) and the pn junction (9) so as to be electrically connected to the first region (6).

[0177] [A5] The semiconductor device (1A, 1B, 1C) according to A3 or A4, wherein the second impurity region (34) is formed in a region on the lower end side of the second polysilicon (24) with a gap between the upper end and the lower end side of the second polysilicon (24).

[0178] [A6] A semiconductor device (1A, 1B, 1C) according to any one of A3 to A5, wherein the second impurity region (34) is formed in a region on the lower end side of the second polysilicon (24) so ​​as not to cross the depth position of the pn junction (9).

[0179] [A7] A semiconductor device (1A, 1B, 1C) according to any one of A3 to A6, wherein the first impurity region (31) is formed in the first polysilicon (17) so as to cross the depth position of the pn junction (9).

[0180] [A8] The semiconductor device (1A, 1B, 1C) according to any one of A3 to A7, wherein the first impurity region (31) is formed over the entire area of ​​the first polysilicon (17).

[0181] [A9] The semiconductor device (1A, 1B, 1C) according to any one of A3 to A8, further including a third impurity region (35) of a second conductivity type (n-type) formed in a region different from the second impurity region (34) within the second polysilicon (24).

[0182] [A10] A semiconductor device (1A, 1B, 1C) according to A9, wherein the third impurity region (35) is formed inside the second polysilicon (24) so ​​as to form a second pn junction (36) with the second impurity region (34).

[0183] [A11] A semiconductor device (1A, 1B, 1C) according to A10, wherein the third impurity region (35) forms the second pn junction (36) with the second impurity region (34) in a region on the lower end side of the second polysilicon (24) relative to the depth position of the pn junction (9).

[0184] [A12] A semiconductor device (1A, 1B, 1C) according to any one of A3 to A8, further including a resistor region (102) formed in the second polysilicon (24) at a lower concentration than the second impurity region (34) and in a region different from the second impurity region (34).

[0185] [A13] The semiconductor device (1A, 1B, 1C) according to A12, wherein the resistor region (102) is formed inside the second polysilicon (24) at a concentration lower than that of the first impurity region (31).

[0186] [A14] The semiconductor device (1A, 1B, 1C) according to A13, wherein the resistor region (102) is formed in a region on the upper end side of the second polysilicon (24).

[0187] [A15] The semiconductor device (1A, 1B, 1C) according to any one of A12 to A14, wherein the resistor region (102) is made of an undoped region of the second polysilicon (24).

[0188] [A16] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A15, wherein the first groove structure (13) has a first width (W1), and the second groove structure (14) has a second width (W2) that is less than the first width (W1).

[0189] [B1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, a first region (6) of a first conductivity type (p-type) formed on the second main surface (4) side in the chip (2), second regions (7, 8) of a second conductivity type (n-type) formed on the first main surface (3) side in the chip (2) and forming a pn junction (9) with the first region (6), device regions (10, 11) provided on the first main surface (3), a first trench (15) penetrating the pn junction (9) from the first main surface (3), a first insulating film (16) exposing the first region (6) from a wall surface of the first trench (15), and first polysilicon (17) embedded in the first trench (15) across the first insulating film (16), a second trench structure (14) including a first trench structure (13) that partitions the device regions (10, 11) on the device region (10, 11) side of the first trench structure (13); a second trench (22) that penetrates from the first main surface (3) through the pn junction (9); a second insulating film (23) that exposes the first region (6) from a wall surface of the second trench (22); and second polysilicon (24) that is buried in the second trench (22) across the second insulating film (23), the second trench structure (14) partitioning the device regions (10, 11) on the device region (10, 11) side of the first trench structure (13); a first semiconductor region (31) of a first conductivity type (p-type) formed in the first polysilicon (17); and a second semiconductor region (35) of a second conductivity type (n-type) formed in the second polysilicon (24).

[0190] [B2] The semiconductor device (1A, 1B, 1C) according to B1, wherein the first semiconductor region (31) is formed in the first polysilicon (17) so as to cross the depth position of the pn junction (9), and the second semiconductor region (35) is formed in the second polysilicon (24) so ​​as to cross the depth position of the pn junction (9).

[0191] [B3] The semiconductor device (1A, 1B, 1C) according to B1 or B2, further comprising a second pn junction (36) formed between the first region (6) and the second semiconductor region (35) in the second polysilicon (24).

[0192] [B4] The semiconductor device (1A, 1B, 1C) according to B3, wherein the second pn junction (36) is connected in reverse bias to the pn junction (9).

[0193] [B5] The semiconductor device (1A, 1B, 1C) according to B3 or B4, wherein the second pn junction (36) is located in a region on the bottom wall side of the groove (22) relative to the depth position of the first pn junction (9).

[0194] [B6] A semiconductor device (1A, 1B, 1C) according to any one of B1 to B5, wherein the first groove structure (13) has a first width (W1), and the second groove structure (14) has a second width (W2) that is less than the first width (W1).

[0195] [C1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, a first region (6) of a first conductivity type (p-type) formed on the second main surface (4) side in the chip (2), second regions (7, 8) of a second conductivity type (n-type) formed on the first main surface (3) side in the chip (2) and forming a pn junction (9) with the first region (6), device regions (10, 11) provided on the first main surface (3), a first trench (15) penetrating the pn junction (9) from the first main surface (3), a first insulating film (16) exposing the first region (6) from a wall surface of the first trench (15), and first polysilicon (17) embedded in the first trench (15) across the first insulating film (16), a second trench structure (14) including a first trench structure (13) that partitions the device regions (10, 11), a second trench (22) that penetrates from the first main surface (3) through the pn junction (9), a second insulating film (23) that exposes the first region (6) from a wall surface of the second trench (22), and second polysilicon (24) that is embedded in the second trench (22) across the second insulating film (23), and that partitions the device regions (10, 11) on the device region (10, 11) side of the first trench structure (13); a first semiconductor region (31) of a first conductivity type (p-type) formed in the first polysilicon (17); and a resistor region (102) formed in the second polysilicon (24) at a concentration lower than that of the first semiconductor region (31).

[0196] [C2] The semiconductor device (1A, 1B, 1C) according to C1, wherein the first semiconductor region (31) is formed in the first polysilicon (17) so as to cross the depth position of the pn junction (9), and the resistance region (102) is formed in the second polysilicon (24) so ​​as to cross the depth position of the pn junction (9).

[0197] [C3] The semiconductor device (1A, 1B, 1C) according to C1 or C2, wherein the resistor region (102) is made of an undoped region of the second polysilicon (24).

[0198] [C4] A semiconductor device (1A, 1B, 1C) according to any one of C1 to C3, wherein the first groove structure (13) has a first width (W1), and the second groove structure (14) has a second width (W2) that is less than the first width (W1).

[0199] [D1] A semiconductor device (1A, 1B, 1C) comprising: a chip (2) having a main surface (3); a first pn junction (9) formed in the chip (2) so as to extend along the main surface (3); a device region (10, 11) provided on the main surface (3); a trench (22) penetrating the first pn junction (9) from the main surface (3); an insulating film (23) exposing a bottom wall of the trench (22) within the trench (22); and polysilicon (24) embedded in the trench (22) across the insulating film (23), the trench structure (14) separating the device region (10, 11) from other regions; and a second pn junction (36) formed in the polysilicon (24).

[0200] [D2] A semiconductor device (1A, 1B, 1C) according to D1, wherein the second pn junction (36) is reverse-bias connected to the first pn junction (9) via the bottom wall of the groove (22).

[0201] [D3] A semiconductor device (1A, 1B, 1C) according to D1 or D2, wherein the second pn junction (36) is located in a region on the bottom wall side of the groove (22) relative to the depth position of the first pn junction (9).

[0202] [D4] A semiconductor device (1A, 1B, 1C) according to any one of D1 to D3, wherein the distance from the first pn junction (9) to the bottom wall of the groove structure (14) is greater than the distance from the first pn junction (9) to the main surface (3).

[0203] [E1] A semiconductor device (1A, 1B, 1C) comprising: a chip (2) having a main surface (3); a pn junction (9) formed in the chip (2) so as to extend along the main surface (3); a device region (10, 11) provided in the main surface (3); a trench (22) penetrating the pn junction (9) from the main surface (3); an insulating film (23) exposing a bottom wall of the trench (22) within the trench (22); and polysilicon (24) embedded in the trench (22) across the insulating film (23), the trench structure (14) separating the device region (10, 11) from other regions; and an impurity-free resistor region (102) formed in the polysilicon (24).

[0204] [E2] The semiconductor device (1A, 1B, 1C) according to E1, wherein the resistance region (102) is formed in the polysilicon (24) so ​​as to cross the depth position of the pn junction (9).

[0205] [E3] A semiconductor device (1A, 1B, 1C) according to E1 or E2, wherein the distance from the pn junction (9) to the bottom wall of the trench structure (14) is greater than the distance from the pn junction (9) to the main surface (3).

[0206] Although the embodiments have been described in detail, these are merely examples used to clarify the technical content, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0207] 1A Semiconductor Device 1B Semiconductor Devices 1C Semiconductor Device 2 chips 3 First main surface 4 Second main surface 6 First area 7 Second area 8 Third area 9 1st pn junction 10 Device Area 11 Transistor area (device area) 13 First trench structure (first groove structure) 14 Second trench structure (second groove structure) 15 First trench (first trench) 16 First insulating film 17 First Polysilicon 22 Second trench (second groove) 23 Second insulating film 24 Second Polysilicon 31 1st impurity region 34 Second impurity region 35 Third impurity region 36 2nd pn junction 102 Resistance area W1 1st width W2 Second width

Claims

1. a chip having a first major surface on one side and a second major surface on the other side; a first region of a first conductivity type formed on the second main surface side within the chip; a second region of a second conductivity type formed on the first main surface side of the chip and forming a pn junction with the first region; a device region provided on the first main surface; a first trench structure that defines the device region, the first trench including: a first trench that penetrates the pn junction from the first main surface; a first insulating film that exposes the first region from a wall surface of the first trench; and first polysilicon that is embedded in the first trench with the first insulating film sandwiched therebetween; a second trench structure including a second trench penetrating the pn junction from the first main surface, a second insulating film exposing the first region from a wall surface of the second trench, and second polysilicon embedded in the second trench with the second insulating film sandwiched therebetween, the second trench structure partitioning the device region on the device region side of the first trench structure; a first impurity region of a first conductivity type formed in the first polysilicon; a second impurity region of the first conductivity type formed in a region on the lower end side of the second polysilicon so as not to cross a depth position of the pn junction; a third impurity region of a second conductivity type formed in a region different from the second impurity region in the second polysilicon, the third impurity region is formed inside the second polysilicon so as to form a second pn junction with the second impurity region.

2. the first polysilicon is connected to the first region and is buried in the first trench with the first insulating film interposed therebetween so as to be electrically insulated from the second region; 2. The semiconductor device according to claim 1, wherein said second polysilicon is connected to said first region and buried in said second trench with said second insulating film therebetween so as to be electrically insulated from said second region.

3. the first impurity region is located in a thickness range between a bottom wall of the first trench and the pn junction so as to be electrically connected to the first region; 3. The semiconductor device according to claim 1, wherein said second impurity region is located in a thickness range between a bottom wall of said second trench and said pn junction so as to be electrically connected to said first region.

4. 4. The semiconductor device according to claim 1, wherein the second impurity region is formed in a region on the lower end side of the second polysilicon with a gap between the upper end and the lower end side of the second polysilicon.

5. 5. The semiconductor device according to claim 1, wherein said first impurity region is formed in said first polysilicon so as to cross a depth position of said pn junction portion.

6. 6. The semiconductor device according to claim 1, wherein said first impurity region is formed over the entire area of ​​said first polysilicon.

7. The semiconductor device according to any one of claims 1 to 6, wherein the third impurity region forms the second pn junction with the second impurity region in a region on the lower end side of the second polysilicon relative to the depth position of the pn junction.

8. the first groove structure has a first width; 8. The semiconductor device according to claim 1, wherein the second trench structure has a second width that is less than the first width.

Images