Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device having a deep groove penetrating a semiconductor substrate and a manufacturing method thereof.SOLUTION: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a groove that penetrates to the second main surface in plan view of the first main surface. The groove has a longitudinal direction in a first direction, a short direction in a second direction perpendicular to the first direction, and a third direction is perpendicular to the first direction and the second direction and perpendicular to the semiconductor substrate, and the side surfaces of the groove, which are planes between the first direction and the third direction and planes between the second direction and the third direction include (111) planes.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A semiconductor capacitor is known in which a capacitor is formed inside a trench in a semiconductor substrate. The semiconductor capacitor is formed by forming a trench on the surface of a semiconductor substrate, depositing an insulating film inside the trench, and then filling the trench with a conductive material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2002-503395 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional semiconductor capacitors, in order to increase the capacitance of the capacitor, it is necessary to increase the depth of the groove.

[0005] SUMMARY OF THE INVENTION Embodiments of the present invention provide a semiconductor device having a deep trench extending through a semiconductor substrate, and a method for fabricating the same. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present invention includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a trench extending through the first main surface to the second main surface in a plan view. an insulating film disposed inside the trench and in contact with the semiconductor substrate; a dielectric film disposed inside the trench and in contact with the insulating film; and an electrode electrically connected to the semiconductor substrate and the dielectric film. The groove has a longitudinal direction in a first direction, a lateral direction in a second direction perpendicular to the first direction, a third direction perpendicular to the first and second directions and perpendicular to the semiconductor substrate, and side surfaces of the groove that are planes between the first direction and the third direction and planes between the second direction and the third direction comprise a (111) plane. [Effects of the Invention]

[0007] According to an embodiment of the present invention, it is possible to provide a semiconductor device having a deep trench penetrating a semiconductor substrate, and a method for manufacturing the same. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing the arrangement of grooves relative to the surface of a semiconductor substrate in a semiconductor device according to a first embodiment. [Figure 2A] FIG. 2A is an enlarged view of a main part of the semiconductor device according to the first embodiment. [Figure 2B] FIG. 2B is a cross-sectional view taken along line A1-A1 in FIG. 2A. [Figure 3A] FIG. 3A is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3C] FIG. 3C is a cross-sectional view (part 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3D] FIG. 3D is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view for explaining the relationship between the length of the inclined (111) plane involved in the formation of the groove and the etching depth. [Figure 5A] FIG. 5A is an enlarged view of a main part of a semiconductor device according to a modified example of the first embodiment. [Figure 5B] FIG. 5B is a cross-sectional view taken along line A2-A2 in FIG. 5A. [Figure 5C] FIG. 5C is a comparative mask pattern diagram for explaining mask patterns on the front and back surfaces of a semiconductor device according to a modification of the first embodiment. [Figure 6A] FIG. 6A is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 6B]FIG. 6B is a cross-sectional view (part 2) illustrating a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 6C] FIG. 6C is a cross-sectional view (part 3) illustrating a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 7A] FIG. 7A is an enlarged view of a main part of the semiconductor device according to the second embodiment. [Figure 7B] FIG. 7B is a cross-sectional view taken along line A3-A3 in FIG. 7A. [Figure 7C] FIG. 7C is a comparative mask pattern diagram for explaining mask patterns on the first and second main surfaces of the semiconductor device according to the second embodiment. [Figure 8A] FIG. 8A is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8B] FIG. 8B is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 8C] FIG. 8C is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9A] FIG. 9A is an enlarged view of a main part of the semiconductor device according to the third embodiment. [Figure 9B] FIG. 9B is a cross-sectional view taken along line A4-A4 in FIG. 9A. [Figure 9C] FIG. 9C is a comparative mask pattern diagram for explaining mask patterns on the first and second main surfaces of the semiconductor device according to the third embodiment. [Figure 10A] FIG. 10A is an enlarged view of a main part of the semiconductor device according to the fourth embodiment. [Figure 10B] FIG. 10B is a cross-sectional view taken along line A5-A5 in FIG. 10A. [Figure 10C] FIG. 10C is a comparative mask pattern diagram for explaining mask patterns on the first and second main surfaces of the semiconductor device according to the fourth embodiment. [Figure 11A]FIG. 11A is a cross-sectional view (part 1) illustrating a manufacturing method for forming a groove by wet etching. [Figure 11B] FIG. 11B is a cross-sectional view (part 2) illustrating a manufacturing method for forming a groove by wet etching. [Figure 11C] FIG. 11C is a cross-sectional view (part 3) illustrating a manufacturing method involving the formation of grooves by wet etching. [Figure 11D] FIG. 11D is a cross-sectional view (part 4) illustrating a manufacturing method for forming a groove by wet etching. [Figure 11E] FIG. 11E is a cross-sectional view (part 5) illustrating a manufacturing method for forming a groove by wet etching. [Figure 12A] FIG. 12A is a cross-sectional view (part 1) illustrating a manufacturing method relating to the formation of a groove by another wet etching method. [Figure 12B] FIG. 12B is a cross-sectional view (part 2) illustrating a manufacturing method for forming a groove by another wet etching method. [Figure 12C] FIG. 12C is a cross-sectional view (part 3) illustrating a manufacturing method for forming a groove by another wet etching method. [Figure 13] FIG. 13 is an enlarged view of a main part of a semiconductor device in which a plurality of grooves are used. [Figure 14A] FIG. 14A is a cross-sectional view (part 1) of a semiconductor capacitor included in a semiconductor device according to an embodiment. [Figure 14B] FIG. 14B is a cross-sectional view (part 2) of a semiconductor capacitor included in the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, identical parts are designated by the same reference numerals, and their description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like may differ from the actual ones. Furthermore, the dimensional relationships and ratios may differ between the drawings.

[0010] (First embodiment) FIG. 1 is a top view showing the arrangement of grooves 2 relative to the semiconductor substrate surface of a semiconductor substrate 1 in a semiconductor device 10 according to a first embodiment. FIG. 2A is an enlarged view of a main portion P of the semiconductor device 10. FIG. 2B is a cross-sectional view taken along line A1-A1 in FIG. 2A. The configuration of the semiconductor device 10 according to the first embodiment will be described below with reference to FIGS. 1, 2A, and 2B. In the following description, an XYZ coordinate system, which is an example of a Cartesian coordinate system, is used. That is, a plane parallel to the surface of the semiconductor substrate 1 is defined as the XY plane, and a direction perpendicular to the XY plane is defined as the Z axis. The X and Y axes are defined as two perpendicular directions within the XY plane. For ease of explanation, the following description will be made in a vertical relationship in which the positive side of the Z axis (the first main surface 1a side) is defined as the top of the drawing, and the negative side of the Z axis (the second main surface 1c side) is defined as the bottom of the drawing. However, this does not represent a universal vertical relationship.

[0011] 1 and 2A, the semiconductor device 10 includes a semiconductor substrate 1 and a groove 2. In the following description, the groove 2 will also be referred to as a trench 2.

[0012] As shown in FIG. 1, the semiconductor substrate 1 has a first main surface 1a and a second main surface 1c opposite to the first main surface 1a. The semiconductor substrate 1 also has an orientation flat 1b that exhibits an orientation flat (hereinafter referred to as an orientation flat). Specifically, the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 may be, for example, (110) surfaces. The orientation flat 1b may be, for example, perpendicular to the (110) surfaces of the first main surface 1a and the second main surface 1c. <100> It may be a surface.

[0013] The semiconductor substrate 1 has, for example, a diamond crystal structure. Specifically, the semiconductor substrate 1 includes, for example, a silicon substrate 1. The thickness t of the semiconductor substrate 1 is, for example, about 625 to 665 μm.

[0014] As shown in FIGS. 2A and 2B , the trench 2 is formed so as to penetrate all the way to the second main surface 1c in a plan view of the first main surface 1a. The trench 2 has, on the first main surface 1a, one longitudinal end La and another lateral end Wa perpendicular to the longitudinal direction. Although not shown, the trench 2 has, on the second main surface 1c, one longitudinal end Lb and another lateral end Wb perpendicular to the longitudinal direction. In the following description, the longitudinal ends La and Lb of the trench 2 are also referred to as the length La and Lb of the trench 2, and the lateral ends Wa and Wb of the trench 2 are also referred to as the width Wa and Wb of the trench 2. The opening of the trench 2 on the first main surface 1a side is also referred to as the upper portion 2a of the trench 2, and the opening of the trench 2 on the second main surface 1c side is also referred to as the lower portion 2c of the trench 2. The longitudinal direction of the trench 2 is also referred to as the first direction, the lateral direction of the trench 2 as the second direction, and the direction perpendicular to the longitudinal and lateral directions of the trench 2 (depth direction) as the third direction.

[0015] As shown in FIG. 2A, the trench 2 is arranged such that the length La of the trench 2 is parallel to the (111) plane of the semiconductor substrate 1 in plan view. Also, as shown in FIG. 2A, the trench 2 is arranged such that the width Wa of the trench 2 is perpendicular to the (111) plane of the semiconductor substrate 1 in plan view. Specifically, in the (110) planes of the first main surface 1a and the second main surface 1c, <100> The plane having an angle θ1 of 35.3° with respect to the (100) plane is the (111) plane. In other words, the plane having an angle θ1 with respect to the (100) plane shown in FIG. 2A is the (111) plane.

[0016] As shown in FIG. 2B , the trench 2 penetrates perpendicularly to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1. A side surface 2b1 of the trench 2 on the length La side, which is a plane between the first direction and the third direction, comprises, for example, a (111) plane. A side surface 2b2 of the trench 2 on the width Wa side, which is a plane between the second direction and the third direction, comprises, for example, a (111) plane. The correlation between the lengths La and Lb of the trench 2 and the thickness t of the semiconductor substrate 1 will be described in detail, for example, in the description of FIG. 4.

[0017] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described below with reference to the drawings. Note that the method for manufacturing the semiconductor device 10 described below is an example of forming trenches 2 in a semiconductor substrate 1 by wet etching, and various other manufacturing methods can also be used. Note that the masking step used when forming trenches 2 will be described in detail, for example, in the description of FIGS. 11A to 12C.

[0018] First, as shown in FIG. 3A, a semiconductor substrate 1 is prepared.

[0019] Next, as shown in FIGS. 2A and 3B, the length direction of the trench 2 is aligned with the (111) plane of the semiconductor substrate 1, and the trench 2 regions of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 are anisotropically etched from both sides. Specifically, the etching solution used for wet etching the semiconductor substrate 1 is an alkaline aqueous solution. Examples of alkaline aqueous solutions include potassium hydroxide (hereinafter also referred to as KOH) and tetramethylammonium hydroxide (hereinafter also referred to as TMAH). When etching is performed with an alkaline aqueous solution, the wet etching is anisotropic. That is, although not shown, the semiconductor substrate 1 is etched vertically in the thickness direction of the first main surface 1a and the second main surface 1c at one end side of the lengths La and Lb of the trench 2. Furthermore, at the other end side of the widths Wa and Wb of the trench 2, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, forming inclined surfaces 2d1 and 2d2, as shown in FIG. 3B. Furthermore, central portions 2e1 and 2e2 of trench 2 are formed by etching first main surface 1a and second main surface 1c of semiconductor substrate 1. In the following description, the bottom surfaces of trench 2 formed by etching first main surface 1a and second main surface 1c of semiconductor substrate 1 are referred to as central portions 2e1 and 2e2 of trench 2.

[0020] Next, as shown in FIG. 3C, an anisotropic etching process is performed on the central portions 2e1 and 2e2 of the trench 2. Specifically, further wet etching is performed in the thickness direction of the first main surface 1a and the second main surface 1c to completely etch and penetrate the central portions 2e1 and 2e2 of the trench 2. Here, to form the trench 2 perpendicular to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, the trenches 2 wet-etched from both sides must penetrate each other at the central portions 2e1 and 2e2 of the trench 2. In the following description, the central portions 2e1 and 2e2 of the trench 2 that penetrate are also referred to as starting penetration portions. Note that this starting penetration portion will be described in detail, for example, in the description of FIG. 4.

[0021] Next, as shown in FIG. 3D, an anisotropic etching process is performed on the slopes 2d1 and 2d2 of the trench 2. Specifically, the slopes 2d1 and 2d2 of the semiconductor substrate 1 are wet-etched in the planar direction of the semiconductor substrate 1 from the tip ends of the slopes 2d1 and 2d2 of the semiconductor substrate 1 to the other ends of the trench 2 with widths Wa and Wb. After the initial penetration portion penetrates, etching progresses in the planar direction of the semiconductor substrate 1 on the slopes 2d1 and 2d2. Finally, the trench 2 is formed such that the side surfaces at the other ends of the trench 2 with widths Wa and Wb are perpendicular to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, which are (111) planes.

[0022] As described above, the trench 2 can be formed in the region of the trench 2 on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by aligning the length direction of the trench 2 parallel or perpendicular to the (111) plane of the semiconductor substrate 1 and forming the trench 2 by anisotropic etching using wet etching.

[0023] Next, the conditions for forming the initial through-holes by anisotropic etching using wet etching from both sides will be described with reference to FIG.

[0024] FIG. 4 shows an example in which the lengths of trenches 2 etched by wet etching on the first and second main surfaces 1a and 1c of the semiconductor substrate 1 are La and Lb, respectively, and the depths of the trenches 2 are Da and Db, respectively. Here, the lengths of the slopes formed at the other ends of the width of the trenches 2 on the first and second main surfaces 1a and 1c are Lae and Lbe, respectively, and the length of the "initial penetration portion" is Lt. Furthermore, the sum of the depths of the trenches 2, Da and Db, respectively, is the thickness t of the semiconductor substrate 1. These relationships are expressed by the following equations (1), (2), and (3).

[0025] La = 2Lae + Lt (1) Lb=2Lbe+Lt (2) Da+Db=t (3) In the semiconductor substrate 1, due to the crystal structure, the relationship between the length of the inclined surface ((111) plane) formed by wet etching and the etching depth is expressed by the following formulas (4) and (5).

[0026] Lae=√2Da (4) Lbe=√2Db (5) From the above relationship, the sum of the lengths La and Lb of the trenches 2 in the first main surface 1a and the second main surface 1c is given by equation (6) from the above equations (1) to (5).

[0027] La+Lb=2√2t+2Lt (6) Therefore, the length Lt of the trigger penetration part is given by the following equation (7).

[0028] Lt=(La+Lb) / 2-√2t (7) From equation (7), in order for the trigger penetration part to be formed, the length of the trigger penetration part Lt must be greater than 0. Therefore, when taking into account the length of the trigger penetration part Lt > 0, equation (7) becomes the following equation (8).

[0029] Lt=(La+Lb) / 2-√2t>0 (8) Furthermore, from equation (8), the sum of the lengths La and Lb of the trench 2 is expressed by the following equation (9).

[0030] La+Lb>2√2t (9) In other words, when the sum of the length La of the trench 2 in the first direction of the first main surface 1a and the length Lb of the trench 2 in the first direction of the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, a trigger penetration portion is formed.

[0031] As shown in FIG. 2B, when the lengths La and Lb of the trenches 2 on the first and second main surfaces 1a and 1c are equal (La=Lb=L), equation (9) becomes equation (10) below, and when the lengths La and Lb of the trenches 2 are equal, the length L of the trenches 2 becomes equation (11) below.

[0032] La+Lb=2L>2√2t (10) L>√2t (11) According to formulas (10) and (11), when the length L of the trench 2 is equal to or greater than √2 times the thickness t of the semiconductor substrate 1, an initial through portion is formed, and the trench 2 is formed perpendicular to the first main surface 1a and the second main surface 1c. In other words, the lengths of the trenches 2 or the mask patterns of the trenches 2 on the first and second main surfaces are equal, and the lengths of the respective trenches 2 or the mask patterns of the trenches 2 are equal to or greater than √2 times the thickness t of the semiconductor substrate 1.

[0033] (Modification of the first embodiment) The configuration of a semiconductor device 10 according to a modification of the first embodiment will be described with reference to FIGS. 5A to 6C. In the semiconductor device 10 according to the modification of the first embodiment, as shown in FIG. 5A, the length La2 and width Wa2 of trench 2A, which are an example of a trench, differ from the length La and width Wa of trench 2 in the first embodiment. Similarly, although not shown, the length Lb2 and width Wb2 of trench 2A differ from the length Lb and width Wa of trench 2 in the first embodiment. For components that overlap with the first embodiment, reference numerals will be used and their description will be omitted. The following description will focus on the differences.

[0034] As shown in FIGS. 5B and 5C, the length LaM2 of the mask pattern of the trench 2A in the first direction on the first main surface 1a is shorter than the length LbM2 of the mask pattern of the trench 2A in the first direction on the second main surface 1c. Similarly, as shown in FIG. 5C, the width WaM2 of the mask pattern of the trench 2 in the second direction on the first main surface 1a is shorter than the width WbM2 of the mask pattern of the trench 2 in the second direction on the second main surface 1c. That is, when the sum of the length LaM2 of the mask pattern of the trench 2A in the first direction on the first main surface 1a and the length LbM2 of the mask pattern of the trench 2A in the first direction on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, a starting penetration portion is formed, and a trench 2A perpendicular to the first main surface 1a and the second main surface 1c is formed. Furthermore, the length of the trench 2A is the longer of the mask pattern lengths LaM2 and LbM2.

[0035] A method for manufacturing the semiconductor device 10 according to the modified example of the first embodiment will be described below with reference to the drawings.

[0036] First, as shown in FIG. 5C, the length direction of the trench 2A is aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1, and an anisotropic etching process is performed on both sides of the trench 2A region of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1. In the thickness direction of the first main surface 1a and the second main surface 1c, the semiconductor substrate 1 is etched vertically at one end side of the length La2, Lb2 of the trench 2A, although not shown. Furthermore, at the other end side of the width Wa, Wb of the trench 2A, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, forming slopes 2d1, 2d2, as shown in FIG. 6A. Furthermore, the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 are anisotropically etched to form central portions 2e1, 2e2 of the trench 2A.

[0037] 6B, central portions 2e1 and 2e2 of trench 2A are subjected to anisotropic etching. Specifically, wet etching is further performed in the thickness direction of first main surface 1a and second main surface 1c to completely etch through central portions 2e1 and 2e2 of trench 2A.

[0038] Next, as shown in FIG. 6C, an anisotropic etching process is performed on the slopes 2d1 and 2d2 of the trench 2A. Specifically, the slopes 2d1 and 2d2 of the semiconductor substrate 1 are wet-etched in the planar direction of the semiconductor substrate 1 from the tip ends of the slopes 2d1 and 2d2 of the semiconductor substrate 1 to the other end of the width Wa2 of the trench 2A. That is, after the initial penetration portion penetrates, etching progresses in the planar direction of the semiconductor substrate 1 on the slopes 2d1 and 2d2. Ultimately, a trench 2A is formed that is perpendicular to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, whose side surfaces at the other end of the width Wa2 of the trench 2A are (111) planes. That is, as shown in FIGS. 5A to 6C, even if the mask pattern of the trench 2A on the first main surface 1a has a length LaM2, the length La2 of the formed trench 2A is approximately equal to the length LbM2 of the mask pattern of the trench 2A. Similarly, although not shown, even if the width WaM2 of the mask pattern of the trench 2A on the first main surface 1a is the same, the width Wa2 of the trench 2A to be formed will be substantially equal to the width WbM2 of the mask pattern of the trench 2A.

[0039] As described above, in the modified example of the first embodiment, the trench 2A can be formed in the region of the trench 2A on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by aligning the longitudinal direction of the trench 2A with the (111) plane of the semiconductor substrate 1 and forming the trench 2A by anisotropic etching using wet etching.

[0040] Furthermore, even if the length and width of the mask pattern of the trench 2A on the first main surface 1a are misaligned with the length and width of the mask pattern of the trench 2A on the second main surface 1c, a starting penetration portion is formed, and the trench 2A can be formed by penetrating through by anisotropic etching.

[0041] (Second embodiment) The configuration of a semiconductor device 10 according to the second embodiment will be described with reference to FIGS. 7A to 8C. In the semiconductor device 10 according to the second embodiment, as shown in FIG. 7A, the length La3 and width Wa3 of a trench 2B, which is an example of a trench, are substantially equal to the length La and width Wa of the trench 2 in the first embodiment. Similarly, although not shown, the length Lb3 and width Wb3 of the trench 2B are substantially equal to the length Lb and width Wa of the trench 2 in the first embodiment. The difference from the first embodiment is the mask pattern used when forming the trench 2B. Components that overlap with the first embodiment will be referenced by reference numerals and will not be described again. The following description will focus on the differences.

[0042] 7B and 7C, the length LaM3 of the mask pattern of the trench 2B in the first direction on the first main surface 1a is longer than the length LbM3 of the mask pattern of the trench 2B in the first direction on the second main surface 1c. Also, as shown in FIG. 7C, the width WaM3 of the mask pattern of the trench 2B in the second direction on the first main surface 1a is approximately equal to the width WbM3 of the mask pattern of the trench 2B in the second direction on the second main surface 1c. That is, when the sum of the length LaM3 of the mask pattern of the trench 2B in the first direction on the first main surface 1a and the length LbM3 of the mask pattern of the trench 2B in the first direction on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, a starting penetration portion is formed, and a trench 2B perpendicular to the first main surface 1a and the second main surface 1c is formed. The length of trench 2B is the longer of the mask pattern length LaM3 and the mask pattern length LbM3.

[0043] A method for manufacturing the semiconductor device 10 according to the second embodiment will be described below with reference to the drawings.

[0044] First, as shown in FIG. 7C, the length direction of the trench 2B is aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1, and the trench 2B region of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 is anisotropically etched from both sides. In the thickness direction of the first main surface 1a and the second main surface 1c, the semiconductor substrate 1 is etched vertically at one end side of the length La2, Lb2 of the trench 2B, although this is not shown. Furthermore, at the other end side of the width Wa, Wb of the trench 2B, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, forming slopes 2d1, 2d2, as shown in FIG. 8A. Furthermore, the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 are anisotropically etched to form central portions 2e1, 2e2 of the trench 2B.

[0045] 8B, central portions 2e1 and 2e2 of trench 2B are subjected to anisotropic etching. Specifically, wet etching is further performed in the thickness direction of first main surface 1a and second main surface 1c to completely etch through central portions 2e1 and 2e2 of trench 2B.

[0046] Next, as shown in FIG. 8C, an anisotropic etching process is performed on the slopes 2d1 and 2d2 of the trench 2B. Specifically, the slopes 2d1 and 2d2 of the semiconductor substrate 1 are wet-etched in the planar direction of the semiconductor substrate 1 from the tip ends of the slopes 2d1 and 2d2 of the semiconductor substrate 1 to the other end of the width Wa2 of the trench 2B. That is, after the initial penetration portion penetrates, etching progresses in the planar direction of the semiconductor substrate 1 on the slopes 2d1 and 2d2. Ultimately, a trench 2B is formed that is perpendicular to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, whose side surfaces at the other end of the width Wa2 of the trench 2B are (111) planes. That is, as shown in FIGS. 7A to 8C, even if the mask pattern length of the trench 2B on the second main surface 1c is LbM3, the lengths La3 and Lb3 of the formed trench 2B are approximately equal to the length LaM3 of the mask pattern of the trench 2A.

[0047] As described above, in the second embodiment, the trench 2B can be formed in the region of the trench 2B on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by aligning the longitudinal direction of the trench 2B with the (111) plane of the semiconductor substrate 1 and forming the trench 2B by anisotropic etching using wet etching.

[0048] Furthermore, even if the length and width of the mask pattern of the trench 2B on the first main surface 1a are misaligned with the length and width of the mask pattern of the trench 2B on the second main surface 1c, a starting penetration portion is formed, and the trench 2B can be formed by penetrating through by anisotropic etching.

[0049] Furthermore, when forming a trench of the desired length, the length and width of the mask pattern of the trench 2B on the first main surface 1a are used as a reference, and the length and width of the mask pattern of the trench 2B on the second main surface 1c are made shorter than the length and width of the mask pattern of the trench 2B on the first main surface 1a, thereby making it possible to form the desired trench length.

[0050] (Third embodiment) The configuration of a semiconductor device 10 according to the second embodiment will be described with reference to FIGS. 9A to 9C. In the semiconductor device 10 according to the third embodiment, as shown in FIG. 9A, the length La4 and width Wa4 of a trench 2C, which is an example of a trench, are substantially equal to the length La and width Wa of the trench 2 in the first embodiment. Similarly, although not shown, the length Lb4 and width Wb4 of the trench 2C are substantially equal to the length Lb and width Wa of the trench 2 in the first embodiment. The difference from the first embodiment is the mask pattern used when forming the trench 2C. Components that overlap with the first embodiment will be referred to by reference numerals and will not be described again. The following description will focus on the differences.

[0051] 9B and 9C, the length LaM4 of the mask pattern of the trench 2C in the first direction on the first main surface 1a is approximately equal to the length LbM4 of the mask pattern of the trench 2C in the first direction on the second main surface 1c. Furthermore, the width WaM4 of the mask pattern of the trench 2C in the second direction on the first main surface 1a is greater than the width WbM4 of the mask pattern of the trench 2C in the second direction on the second main surface 1c. That is, if the lengths LaM4 and LbM4 of the mask pattern of the trench 2C in the first direction on the first main surface 1a and the second main surface 1c are equal and each of the lengths LaM4 and LbM4 of the mask pattern of the trench 2C in the first direction is equal to or greater than √2 times the thickness t of the semiconductor substrate 1, a starting through-portion is formed, and a trench 2C perpendicular to the first main surface 1a and the second main surface 1c is formed. The width of trench 2C is the larger of the mask pattern width WaM4 and the mask pattern width WbM4. Note that the manufacturing method will be omitted because the explanation of the cross-sectional views is the same as in the first embodiment.

[0052] As described above, in the third embodiment, the trench 2C can be formed in the region of the trench 2C on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by aligning the longitudinal direction of the trench 2C with the (111) plane of the semiconductor substrate 1 and forming the trench 2C by anisotropic etching using wet etching.

[0053] Furthermore, even if the length and width of the mask pattern of the trench 2C on the first main surface 1a are misaligned with the length and width of the mask pattern of the trench 2C on the second main surface 1c, a starting penetration portion is formed, and the trench 2C can be formed by penetrating through by anisotropic etching.

[0054] (Fourth embodiment) The configuration of a semiconductor device 10 according to the fourth embodiment will be described with reference to FIGS. 10A to 10C. In the semiconductor device 10 according to the fourth embodiment, as shown in FIG. 10A, the length La5 of a trench 2D, which is an example of a trench, and the width Wa5 of the trench 2D are substantially equal to the length La and width Wa of the trench 2 in the first embodiment. Similarly, although not shown, the length Lb5 of the trench 2D and the width Wb5 of the trench 2D are substantially equal to the length Lb and width Wa of the trench 2 in the first embodiment. The difference from the first embodiment is the mask pattern used when forming the trench 2D. Components that overlap with the first embodiment will be designated by reference numerals and will not be described again. The following description will focus on the differences.

[0055] 10B and 10C, the length LaM5 of the mask pattern of the trench 2D in the first direction on the first main surface 1a is longer than the length LbM5 of the mask pattern of the trench 2D in the first direction on the second main surface 1c. Similarly, as shown in FIG. 10C, the width WaM5 of the mask pattern of the trench 2D in the second direction on the first main surface 1a is longer than the width WbM5 of the mask pattern of the trench 2D in the second direction on the second main surface 1c. That is, the length LaM5 of the mask pattern of the trench 2D in the first direction on the first main surface 1a and the width WaM5 of the mask pattern of the trench 2D in the second direction on the first main surface 1a are longer than the length LbM5 of the mask pattern of the trench 2D in the first direction on the second main surface 1c and the width WbM5 of the mask pattern of the trench 2D in the second direction on the second main surface 1c, respectively. Furthermore, when the sum of the length LaM5 of the mask pattern of the trench 2D in the first direction on the first main surface 1a and the length LbM5 of the mask pattern of the trench 2D in the first direction on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, a starting penetration portion is formed, and a trench 2D perpendicular to the first main surface 1a and the second main surface 1c is formed. The length of the trench 2D is the longer of the mask pattern lengths LaM5 and LbM5. Furthermore, the width of the trench 2D is the longer of the mask pattern widths WaM5 and WbM5. The manufacturing method will be omitted because the cross-sectional views are the same as those in the second embodiment.

[0056] As described above, in the fourth embodiment, the trench 2D can be formed in the region of the trench 2D on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by aligning the longitudinal direction of the trench 2D with the (111) plane of the semiconductor substrate 1 and forming the trench 2D by anisotropic etching using wet etching.

[0057] Furthermore, even if the length and width of the mask pattern of the trench 2D on the first main surface 1a are misaligned with the length and width of the mask pattern of the trench 2D on the second main surface 1c, a starting penetration portion is formed, and the trench 2D can be formed by penetrating through by anisotropic etching.

[0058] Furthermore, when forming a trench of the desired length, the length and width of the mask pattern of the trench 2D on the first main surface 1a are used as a reference, and the length and width of the mask pattern of the trench 2D on the second main surface 1c are made shorter than the length and width of the mask pattern of the trench 2D on the first main surface 1a, thereby making it possible to form the desired trench length.

[0059] (First mask method) Hereinafter, a first masking method for the semiconductor device 10 according to the first to fourth embodiments will be described with reference to the drawings. Here, an example of a process flow for forming a trench 2 using wet etching will be described. In the first masking method, a nitride film 3, which is an example of a mask material, is provided.

[0060] First, as shown in FIG. 11A, a nitride film 3, which is an example of a mask material, is formed on the first main surface 1a and the second main surface 1c. Specifically, the semiconductor substrate 1 is, for example, a silicon substrate. The first main surface 1a of the semiconductor substrate 1 is, for example, a (110) plane. The film is formed on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 by, for example, a chemical vapor deposition method (hereinafter referred to as a CVD method). Note that the method for forming the nitride film 3 is not limited to the CVD method as long as the nitride film 3 can be formed.

[0061] 11B, a resist 4 is formed on the nitride film 3 on the first main surface 1a and the second main surface 1c. Specifically, a resist is applied to the entire surface of the nitride film 3 on the first main surface 1a and the second main surface 1c. After application, the resist 4 is patterned by exposure and development.

[0062] 11C, the nitride film 3 is etched on the first main surface 1a and the second main surface 1c using the resist 4 as a mask. Specifically, the nitride film 3 may be etched on the first main surface 1a and the second main surface 1c by using, for example, a dry etching method.

[0063] 11D, the resist 4 is removed from the first main surface 1a and the second main surface 1c. Specifically, the resist 4 may be removed from the first main surface 1a and the second main surface 1c by oxygen ashing using, for example, a plasma ashing method.

[0064] Next, as shown in FIG. 11E, the semiconductor substrate 1 is wet-etched on the first main surface 1a and the second main surface 1c using the nitride film 3 as a mask. Specifically, for example, the semiconductor substrate 1 is anisotropically etched using the nitride film 3 as a mask by wet etching. Here, the etching liquid used in the wet etching is an alkaline aqueous solution. Specifically, for example, KOH or TMAH can be used as the alkaline aqueous solution. The following steps are omitted as they are a commonly known process flow.

[0065] As described above, by using the nitride film 3 as the mask material, the process can be simplified, and the construction period and costs can be reduced.

[0066] (Second mask method) Hereinafter, a second mask method for the semiconductor device 10 according to the first to fourth embodiments will be described with reference to the drawings. Here, an example of a process flow for forming the trench 2 using wet etching will be described.

[0067] The difference between the first and second masking methods is the mask material. The second masking method uses a resist 4, which is an example of a mask material. Here, a resist that is resistant to etching liquid can be used as the resist 4.

[0068] First, as shown in FIG. 12A, a resist 4, which is an example of a mask material, is formed on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1. Specifically, the semiconductor substrate 1 is, for example, a silicon substrate. The first main surface 1a of the semiconductor substrate 1 is, for example, a (110) surface. A resist is applied to the entire surface of the semiconductor substrate 1, on the first main surface 1a and the second main surface 1c.

[0069] 12B, the resist 4 is patterned on the first main surface 1a and the second main surface 1c. Specifically, the resist 4 is patterned by exposure and development.

[0070] Next, as shown in FIG. 12C, the semiconductor substrate 1 is wet-etched on the first main surface 1a and the second main surface 1c using the resist 4 as a mask. Specifically, for example, the semiconductor substrate 1 is anisotropically etched using the resist 4 as a mask by wet etching. Here, the etching liquid used in the wet etching is an alkaline aqueous solution. Specifically, for example, KOH or TMAH can be used as the alkaline aqueous solution. The following steps are omitted as they are a commonly known process flow.

[0071] The second mask method can reduce the number of steps and the number of formation processes compared to the first mask method by using the resist 4 as the mask material. Also, the second mask method can achieve lower costs compared to the first mask method.

[0072] Although the embodiments of the present invention have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0073] For example, although the case where one trench 2 is used has been described, a stripe pattern may be used by using a plurality of trenches 2 as shown in Fig. 13. Note that the trench 2 may be selectively formed on the semiconductor substrate 1, for example.

[0074] 14A and 14B, the semiconductor capacitor may be provided with a trench 2 including the semiconductor device 10 according to the first to fourth embodiments. A specific example of the semiconductor capacitor will be described with reference to FIGS. 14A and 14B.

[0075] 14A, the semiconductor capacitor further includes an insulating film 6 in contact with the inside of the trench 2 and the first and second main surfaces 1a and 1c of the semiconductor substrate 1. The semiconductor capacitor also includes a dielectric film 5 in contact with the insulating film 6. The insulating film 6 and the dielectric film 5 are formed by stacking one layer on top of the other. The semiconductor capacitor also includes an electrode 11 electrically connected to the semiconductor substrate 1 and the dielectric film 5.

[0076] 14B, the semiconductor capacitor has a structure formed by laminating three layers of insulating films 6 and dielectric films 5. Furthermore, an electrode 11 is provided that electrically connects the semiconductor substrate 1 and the second dielectric film 5.

[0077] The insulating film 6 may be, for example, an oxide film. The dielectric film 5 may be, for example, polysilicon. The insulating film 6 and the dielectric film 5 are disposed inside the trench 2. The electrode 11 may be, for example, aluminum.

[0078] The semiconductor capacitor having the trench 2 including the semiconductor device 10 according to the first to fourth embodiments can form a vertically deep trench compared to a trench having a slope of the (111) plane on the side, so the side area is larger and the capacitance of the capacitor is increased. Also, by forming a three-layer stacked structure as shown in FIG. 14B, the capacitance of the capacitor can be made larger than that of the single layer shown in FIG. 14A. [Explanation of symbols]

[0079] 1. Semiconductor substrate 2 grooves 3. Nitride film 4 Resist 5 Dielectric film 6. Insulating film 11 electrodes 1a First principal surface 1c Second principal surface 2d1, 2d2 slope 2e1, 2e2 central part La, La2, La3, La4, La5 groove length Lb, Lb2, Lb3, Lb4, Lb5 Groove length Wa, Wa2, Wa3, Wa4, Wa5 Groove width Wb, Wb2, Wb3, Wb4, Wb5 Groove width LaM2, LaM3, LaM4, LaM5 Mask pattern length LbM2, LbM3, LbM4, LbM5 Mask pattern length WaM2, WaM3, WaM4, WaM5 Mask pattern width WbM2, WbM3, WbM4, WbM5 Mask pattern width

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a groove that penetrates the first main surface to the second main surface in a plan view; an insulating film disposed inside the trench and in contact with the semiconductor substrate; a dielectric film disposed inside the groove and in contact with the insulating film; an electrode electrically connected to the semiconductor substrate and the dielectric film; Equipped with The groove is a first direction is the longitudinal direction of the groove; The width direction of the groove is in a second direction perpendicular to the first direction, a third direction is a direction perpendicular to the semiconductor substrate and perpendicular to the first direction and the second direction; a side surface of the groove that is a plane between the first direction and the third direction and a plane between the second direction and the third direction has a (111) plane; Semiconductor device.

2. a sum of a length of the groove in the first main surface in the first direction and a length of the groove in the second main surface in the first direction is 2√2 times or more the thickness of the semiconductor substrate; The semiconductor device according to claim 1 .

3. the lengths of the grooves in the first main surface and the second main surface in the first direction are equal, and the lengths of each of the grooves in the first direction are equal to or greater than √2 times the thickness of the semiconductor substrate; The semiconductor device according to claim 1 .

4. the semiconductor substrate comprises a silicon substrate; The semiconductor device according to claim 1 .

5. The first major surface has a (110) plane. The semiconductor device according to claim 3 .

6. A method for manufacturing a semiconductor device, comprising: forming a trench by wet etching in a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; forming a mask material on both the first main surface and the second main surface of the semiconductor substrate; The mask material is a first direction is a longitudinal direction of the groove; The width direction of the groove is in a second direction perpendicular to the first direction, a third direction is a direction perpendicular to the semiconductor substrate and perpendicular to the first direction and the second direction; forming a mask pattern of the groove so that the side surfaces of the groove, which are planes between the first direction and the third direction and planes between the second direction and the third direction, are (111) planes; A method for manufacturing a semiconductor device.

7. forming an insulating film on the semiconductor substrate inside the trench; forming a dielectric film on the insulating film inside the trench; forming an electrode electrically connected to the semiconductor substrate and the dielectric film; The method for manufacturing a semiconductor device according to claim 6 .

8. a sum of a length in the first direction of the mask pattern on the first main surface and a length in the first direction of the mask pattern on the second main surface is 2√2 times or more the thickness of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 6 .

9. the lengths of the mask patterns on the first main surface and the second main surface in the first direction are equal, and the lengths of the mask patterns in the first direction are equal to or greater than √2 times the thickness of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 6 .

10. The length of the groove in the first main surface in the first direction of the mask pattern is a length longer than the length of the groove in the second main surface in the first direction of the mask pattern; The method for manufacturing a semiconductor device according to claim 6 .

11. The width of the mask pattern on the first main surface in the second direction is a width greater than the width of the mask pattern on the second main surface in the second direction; The method for manufacturing a semiconductor device according to claim 6 .

12. The length in the first direction and the width in the second direction of the mask pattern on the first main surface are the length in the first direction and the width in the second direction of the mask pattern on the second main surface are larger than each other, The method for manufacturing a semiconductor device according to claim 6 .

13. the semiconductor substrate comprises a silicon substrate; The method for manufacturing a semiconductor device according to claim 6 .

14. The first major surface has a (110) plane. The method for manufacturing a semiconductor device according to claim 13.

15. The etching solution used for wet etching includes an alkaline aqueous solution. The method for manufacturing a semiconductor device according to claim 14.

16. The alkaline aqueous solution contains potassium hydroxide or tetramethylammonium hydroxide. The method for manufacturing a semiconductor device according to claim 15.

17. The mask material comprises a nitride film. The method for manufacturing a semiconductor device according to claim 6 .

18. The mask material comprises a resist having etching solution resistance. The method for manufacturing a semiconductor device according to claim 6 .

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