Electrothermal Method to Fabricate Single-Crystal Vertically Oriented Silicon Channel for Three-Dimensional (3D) NAND Memory

Abstract

A method for forming a number of vertical NAND memory cells includes, in part, forming a number of insulating materials (20, 30) on a silicon substrate (50), forming trenches in the insulating material to expose a surface of the silicon substrate, depositing a layer of polysilicon (70) along sidewalls of the trenches, filling the trenches with an oxide (80), forming a metal layer (90) over the trenches, and forming a single-crystalline channel for the NAND memory cell by applying a voltage (98) between the silicon substrate and the metal layer to melt the polysilicon sidewalls and allowing the melted polysilicon sidewalls to recrystallize into a single-crystalline channel.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit under 35 U.S.C. §119(e) of U.S. patent application Ser. No. 62 / 956,920, filed Jan. 3, 2020, entitled "Electro-Thermal Method to Manufacture Monocrystalline Vertically Oriented Silicon Channels for Advanced 3D NAND Memories," the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates generally to integrated circuit memories and corresponding integrated circuit memory fabrication systems. In particular, the present disclosure relates to systems and methods for electrothermal fabrication of monocrystalline vertically oriented silicon channels for 3D NAND memories. [Background technology]

[0003] Advanced NAND memory manufacturing is transitioning to vertically stacked strings of NAND memory cells, commonly referred to as three-dimensional NAND or 3D NAND cells. Vertical stacking relaxes cell feature size requirements, thereby reducing short-channel related effects and crosstalk interference between cells, while increasing memory density per chip. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method of forming multiple vertical NAND memory cells includes, in part, forming multiple insulating materials on a silicon substrate, forming trenches in the insulating material to expose a surface of the silicon substrate, depositing a layer of polysilicon along sidewalls of the trenches, filling the trenches with oxide, forming a metal layer over the trenches, and applying a voltage between the silicon substrate and the metal layer to melt the polysilicon sidewalls, thereby forming a single-crystalline channel for the NAND memory cell. The melted polysilicon sidewalls are allowed to recrystallize into the single-crystalline channel.

[0005] In one embodiment, the method further includes, in part, forming a metal layer over the plurality of insulating materials. In one embodiment, the method further includes, in part, forming an epitaxial layer near a bottom of the trench. In one embodiment, the method further includes, in part, forming an epitaxial layer near a top of the trench. In one embodiment, the method further includes, in part, removing portions of the trench and portions of the insulating material.

[0006] In one embodiment, the method further includes, in part, applying multiple pulses between the metal layer and the substrate after the voltage is applied between the silicon substrate and the metal layer. In one embodiment, the insulating material includes, in part, alternating layers of oxide and nitride. In one embodiment, the method further includes, in part, removing the nitride layer and forming multiple openings along the trench. Each such opening is associated with and adapted to form a different one of the multiple NAND memory cells. The method further includes, in part, depositing at least first and second layers of oxide along sidewalls and a bottom of each opening. The first layer of oxide forms a tunnel oxide of the associated NAND memory cell, and the second layer of oxide forms a storage oxide of the associated NAND memory cell.

[0007] In one embodiment, the method further includes depositing at least a third layer of oxide along the sidewalls and bottom of each opening. In one embodiment, the method further includes depositing a metal layer in each opening following the deposition of the third layer of oxide. In one embodiment, the voltage applied between the silicon substrate and the metal layer is determined by the resistivity of the polysilicon sidewalls.

[0008] According to one embodiment of the present disclosure, a method of forming a number of vertical NAND memory cells includes, in part, forming a number of alternating layers of metal and oxide on a silicon substrate; forming trenches in the alternating layers of metal and oxide to expose a surface of the silicon substrate; depositing a first layer of oxide, a second layer of oxide, and a third layer of oxide along sidewalls of the trenches; depositing a layer of polysilicon along sidewalls of the trenches and adjacent to the first layer of oxide in the trenches; filling the trenches with the oxide; forming a metal layer over the trenches; and forming a single-crystalline channel for the plurality of NAND memory cells by applying a voltage between the silicon substrate and the metal layer to melt the polysilicon sidewalls and allowing the melted polysilicon sidewalls to recrystallize into the single-crystalline channel.

[0009] In one embodiment, the method further includes, in part, forming a metal layer over the multiple alternating layers of metal and oxide. In one embodiment, the method further includes, in part, forming an epitaxial layer near a bottom of the trench. In one embodiment, the method further includes, in part, forming an epitaxial layer near a top of the trench. In one embodiment, the method further includes, in part, removing portions of the trench and portions of the multiple alternating layers of metal and oxide.

[0010] In one embodiment, the method further includes, in part, applying multiple pulses between the metal layer and the substrate after applying the voltage. In one embodiment, the pulse height applied between the first and second time points is higher than the pulse height applied between the second and third time points. The first time point occurs before the second time point, and the second time point occurs before the third time point. In one embodiment, the applied voltage is determined by the resistivity of the polysilicon sidewall.

[0011] A vertical NAND memory structure includes, in part, a silicon substrate and first and second NAND memory cells. The first NAND memory cell is disposed above the silicon substrate and includes a channel defined by single-crystal silicon substantially perpendicular to the substrate. The first NAND memory cell further includes, in part, a tunnel oxide adjacent to the channel, a storage oxide adjacent to the tunnel oxide, and a blocking oxide adjacent to the storage oxide. The second NAND memory cell is disposed above the silicon substrate and includes a channel defined by single-crystal silicon. The second NAND memory cell further includes, in part, a tunnel oxide adjacent to the channel, a storage oxide adjacent to the tunnel oxide, and a blocking oxide adjacent to the storage oxide.

[0012] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of embodiments of the present disclosure and do not limit the scope of the present disclosure to these particular embodiments. Furthermore, the drawings are not necessarily drawn to scale. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 illustrates a semiconductor structure including a stack of alternating layers of silicon dioxide and silicon nitride formed above a silicon substrate and used to form strings of vertical 3D NAND memory cells, according to one exemplary embodiment of the present disclosure. [Figure 2] 2 illustrates the semiconductor structure of FIG. 1 after formation of trenches in the stack, according to an exemplary embodiment of the present disclosure. [Figure 3] 3 illustrates the semiconductor structure of FIG. 2 after forming polysilicon along the sidewalls of the trenches, according to an exemplary embodiment of the present disclosure. [Figure 4] 4 illustrates the semiconductor structure of FIG. 3 after filling the trench with silicon dioxide, according to an exemplary embodiment of the present disclosure. [Figure 5] 5 illustrates the semiconductor structure of FIG. 4 after formation of a metal layer above the stack, according to an exemplary embodiment of the present disclosure. [Figure 6] 6 illustrates the semiconductor structure of FIG. 5 after formation of an ohmic contact in the substrate and application of a voltage between the metal layer and the ohmic contact, according to an exemplary embodiment of the present disclosure. [Figure 7] FIG. 7 illustrates the semiconductor structure of FIG. 6 after melting and recrystallizing the polysilicon sidewalls to form a channel of a 3D NAND memory cell, according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 5 illustrates the semiconductor structure of FIG. 4 after forming metal segments above the trench and polysilicon sidewalls, forming ohmic contacts in the substrate, and applying a voltage between the metal segments and the ohmic contacts, according to an exemplary embodiment of the present disclosure. [Figure 9A] 4 illustrates the semiconductor structure of FIG. 3 after deposition of an epitaxial layer in the bottom of the trench, according to an exemplary embodiment of the present disclosure. [Figure 9B] 5 illustrates the semiconductor structure of FIG. 4 after deposition of an epitaxial layer at the top and bottom of the trench, according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 9 is a timing diagram of tapering voltage pulses that may be applied to the semiconductor of FIGS. 6 and 8 after melting of the polysilicon sidewalls, according to an exemplary embodiment of the present disclosure. [Figure 11] 8 illustrates the semiconductor structure of FIG. 7 after removal of the metal and one or more layers of the stack, according to an exemplary embodiment of the present disclosure. [Figure 12] 8 illustrates the semiconductor structure of FIG. 7 after removing the metal and silicon nitride layers and forming openings in the stack, according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 13 illustrates the semiconductor structure of FIG. 12 after formation of a tunnel oxide, a storage oxide, and a blocking oxide along the bottom and sidewalls of the opening formed in the stack, according to one exemplary embodiment of the present disclosure. [Figure 14] FIG. 14 illustrates the semiconductor structure of FIG. 13 after filling the openings in the stack with metal to form gates of the 3D NAND memory cells, according to an exemplary embodiment of the present disclosure. [Figure 15] FIG. 1 illustrates a semiconductor structure including a stack of alternating layers of silicon dioxide and metal formed above a silicon substrate and used to form strings of vertical 3D NAND memory cells, according to an exemplary embodiment of the present disclosure. [Figure 16] 16 illustrates the semiconductor structure of FIG. 15 after formation of trenches in the stack, according to an exemplary embodiment of the present disclosure. [Figure 17] 17 illustrates the semiconductor structure of FIG. 16 after formation of a tunnel oxide, a storage oxide, and a blocking oxide along the sidewalls of the trench, according to an exemplary embodiment of the present disclosure. [Figure 18] 18 illustrates the semiconductor structure of FIG. 17 after formation of polysilicon adjacent to the tunnel oxide and along the sidewalls of the trench, according to an exemplary embodiment of the present disclosure. [Figure 19] FIG. 19 illustrates the semiconductor structure of FIG. 18 after filling the trenches with silicon dioxide, according to an exemplary embodiment of the present disclosure. [Figure 20] FIG. 20 illustrates the semiconductor structure of FIG. 19 after forming metal segments above the trench and polysilicon sidewalls, forming ohmic contacts in the substrate, and applying a voltage between the metal segments and the ohmic contacts, according to an exemplary embodiment of the present disclosure. [Figure 21]FIG. 21 illustrates the semiconductor structure of FIG. 20 after melting and recrystallizing the polysilicon sidewalls to form a channel of a 3D NAND memory cell, according to an exemplary embodiment of the present disclosure. [Figure 22A] FIG. 1 illustrates, in part, a semiconductor structure including a polysilicon sidewall, a metal gate, a tunnel oxide, a storage oxide, and a blocking oxide according to one exemplary embodiment of the present disclosure. [Figure 22B] FIG. 22B illustrates the semiconductor structure of FIG. 22A after the polysilicon sidewalls have been melted and recrystallized to form a single-crystalline silicon channel, according to an exemplary embodiment of the present disclosure. [Figure 23A] FIG. 1 illustrates, in part, a semiconductor structure including a polysilicon sidewall, a metal gate, a tunnel oxide, a storage oxide, and a blocking oxide according to one exemplary embodiment of the present disclosure. [Figure 23B] FIG. 23B illustrates the semiconductor structure of FIG. 23A after the polysilicon sidewalls have been melted and recrystallized to form a monocrystalline silicon channel, according to an exemplary embodiment of the present disclosure. [Figure 24] FIG. 1 is a schematic diagram of an exemplary computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION OF THE INVENTION

[0014] The semiconductor processes used in the fabrication of vertically integrated 3D NAND memory strings can form deep cylindrical trenches through a multilayer stack of materials, as well as the subsequent deposition of (i) an amorphous silicon layer to form the vertical channel and (ii) an internal oxide core to improve gate control. The deposited amorphous silicon layer crystallizes into polycrystalline silicon grains during the remainder of the fabrication process. Polycrystalline silicon channels have higher resistance than single-crystal silicon, thus degrading the performance of 3D NAND memory cells. Furthermore, inter-grain boundaries act as charge trapping sites, resulting in further random telegraph noise fluctuations and carrier mobility degradation. Such stochastic instabilities can result in significant read / write errors.

[0015] One known technique for partially mitigating the effects of read / write errors is to use an error correction code (ECC) algorithm, but the circuitry required to implement the ECC algorithm occupies a relatively large silicon area, thereby negating the benefits obtained from vertical 3D NAND cells.

[0016] According to an embodiment of the present disclosure, a string of 3D NAND memory cells includes a vertical integration channel with single-crystal silicon. The amorphous silicon and inner core oxide deposition steps are followed by electro-thermal annealing and cooling of the semiconductor material. According to one aspect of the present disclosure, a current is forced into the polysilicon sidewalls, thereby inducing localized Joule heating and melting of the polysilicon. Melting is facilitated by the thin geometries of the polysilicon sandwiched between the oxides.

[0017] The presence of the single crystal seed, according to one aspect of the present disclosure, serves as a starting point for channel crystallization during a cooling period during which the molten polysilicon cools and recrystallizes from the location of the seed, gradually advancing the cooling / crystallization to the remainder of the polysilicon, according to one aspect of the present disclosure.

[0018] FIG. 1 illustrates a stack 10 of alternating layers of silicon dioxide (alternatively referred to herein as oxide) 20 and silicon nitride (alternatively referred to herein as nitride) 30 formed on a crystalline silicon substrate 50 (hereinafter alternatively referred to as substrate) and used to form a plurality of 3D NAND memory cells according to one embodiment of the present disclosure. It is understood that the diagrams illustrated herein are two-dimensional (2D) cross-sections of cylindrical structures. The stack 10 can be fabricated using typical semiconductor processes. The stack 10 of alternating layers of oxide 20 and nitride 30 is an insulating material. Next, using masking and patterning steps, trenches 60 are formed in the stack using, for example, high-aspect ratio reactive ion etch, as shown in FIG. 2. The trenches 60 expose the surface of the substrate 50.

[0019] Next, as shown in FIG. 3, a layer of polysilicon 70 is deposited along the sidewalls of trench 60. Thereafter, as shown in FIG. 4, trench 60 is filled with oxide 80 to form semiconductor memory structure (alternatively referred to herein as semiconductor structure or memory structure) 100. Oxide 80 improves electrostatic control and drivability of the channel, as described further below. Next, as shown in FIG. 5, a layer of metal 90 is deposited on top of memory structure 100, and an ohmic contact 95 is formed to the bottom region of substrate 50, forming memory structure 120, shown in FIG. 6. Metal layer 90 is shown covering top oxide 20, trench oxide 80, and polysilicon sidewalls 70 of layer 100.

[0020] 6, a voltage 98 is then applied between the metal layer 90 and the ohmic contact 95. The voltage level so applied is selected to cause current (shown using dashed line 92) flowing through the polysilicon sidewall 70 between the two metal nodes to cause localized melting of the polysilicon sidewall. The voltage level is determined in part by the resistivity of the polysilicon sidewall, which forms the channel of the 3D NAND memory cell. The relatively small dimensions of the channel (alternatively referred to herein as a nanowire) may increase electrothermal efficiency and therefore reduce the current required to bring the polysilicon sidewall to its melting point.

[0021] The voltage required to melt the polysilicon depends in part on the resistivity of the polysilicon. Such resistivity can be modified, for example, by doping the polysilicon or by applying a voltage to the control gate (word line) of the NAND cell, as explained further below. A typical temperature required to induce localized melting of the polysilicon is about 1400°C. The induced temperature must be less than 1710°C to prevent melting of the surrounding oxide. The amplitude, shape, and duration of the voltage will depend in part on (i) the length of the NAND string (which may, for example, contain 100 memory cells), (ii) the composition of the materials forming the stack, and (iii) the thickness of each such material. The power delivered to the channel using an applied voltage is P = V 2The power is defined by P / R, where V represents the voltage amplitude in volts and R represents the channel string resistance in ohms. The Joule heat Q associated with this power is defined by Q = P·t, where t is the duration of the voltage pulse. A significant portion of the heat thus generated is dissipated through the substrate, the top interconnect, and the lateral sidewalls. A relatively smaller portion of the heat causes an increase in channel temperature. In one example, to achieve the temperature increase required to melt the polysilicon without melting the surrounding oxide, the voltage amplitude and duration are selected to induce energy 100 to 1000 times higher than the energy delivered to the NAND string during a memory read operation, for example.

[0022] As described further below, the channel of the memory cell is then formed in the stack 10. After a melting condition is established along the polysilicon sidewall 70, the voltage is removed to allow the melted polysilicon sidewall to cool. Because the silicon substrate 50 represents a relatively large heat sink, the melted polysilicon sidewall will begin to cool and crystallize at the interface between the polysilicon sidewall and the silicon substrate 50. Crystallization will then propagate from the bottom of the melted polysilicon sidewall (i.e., the interface between the polysilicon sidewall and the substrate 50) to the top of the polysilicon sidewall. Thus, according to an embodiment of the present disclosure, melting of the polysilicon sidewall is achieved by the Joule effect, and recrystallization of the melted polysilicon is achieved by different, asymmetric heat dissipation. FIG. 7 shows the memory structure of FIG. 6 after the polysilicon sidewall 70 has melted and recrystallized to form the channel 85 of the NAND memory cell channel in the stack 10.

[0023] In some embodiments, such as that shown in FIG. 8 , the top metal layer 90 is patterned to form relatively small metal segments 12 that cover only the trench fill oxide 80 and the polysilicon sidewalls 70 prior to application of a voltage. The relatively small size of the metal segments 12 reduces heat dissipation therethrough, thereby increasing the electrothermal effect. Reducing the area of ​​the top metal layer 90 further mitigates premature cooling of the top of the molten polysilicon, thus allowing the recrystallizing wave to fully propagate from the bottom near the interface of the substrate 50 and the polysilicon sidewalls 70.

[0024] In some embodiments, after deposition of the polysilicon sidewalls as shown in FIG. 3, an epitaxial layer of silicon is deposited at the bottom of the trench and then etched to form a relatively thin epitaxial layer 135 near the bottom of the trench, as shown in FIG. 9A. The trench is then filled with oxide 80. The epitaxial layer 135 forms a crystalline super-seed, increasing both the seeding surface of the molten polysilicon sidewalls and the crystallinity propagation efficiency. (Not shown) In some embodiments, the epitaxial layer is formed above substrate 50 before formation of stack 10 and trench 60. In some embodiments, an epitaxial layer is formed both at the bottom of the trench and above the trench. 9B, a first epitaxial layer of silicon 135 is shown formed within the trench, and a second epitaxial layer of silicon 137 is shown formed above the trench. In yet other embodiments, an epitaxial layer is formed above the trench, but not at the bottom of the trench.

[0025] In some embodiments, the polysilicon sidewalls are melted and recrystallized after deposition of the metal gate, tunnel oxide, storage oxide, and blocking oxide. FIG. 22A shows a semiconductor memory structure 400 that is similar to the memory structure shown in FIG. 14 , except that the memory structure 400 includes polysilicon sidewalls that have not been melted and recrystallized. After application of a voltage (not shown) between the metal layer 12 and the ohmic contact 95 of the memory structure 400, the polysilicon sidewalls 70 are melted and recrystallized to form a single-crystalline silicon channel. FIG. 22B shows the memory structure of FIG. 22A after application of such a voltage, followed by melting and recrystallization of the polysilicon sidewalls 70 to form the single-crystalline silicon channel 70. Referring to FIG. 22A , by varying the voltage applied to the metal gate 180, and thus changing the resistivity of the polysilicon sidewalls 70, the voltage level required to melt the polysilicon sidewalls 70 can be changed.

[0026] According to one embodiment of the present disclosure, a method for forming a number of vertically oriented NAND memory cells includes, in part, forming multiple alternating layers of first and second insulators on a silicon substrate to form a stack; forming trenches in the multiple first and second insulators that expose a surface of the silicon substrate; depositing a layer of polysilicon along sidewalls of the trenches; filling the trenches with an oxide; forming a metal layer above the trenches; and removing the first insulator layer from the stack and forming multiple openings along the trenches. Each such opening is associated with and adapted to one of the NAND memory cells. The method further includes, in part, depositing at least first, second, and third layers of oxide along the sidewalls and bottom of each opening; depositing a gate metal layer in each opening following the deposition of the first, second, and third layers of oxide; and forming single-crystal channels for the multiple NAND memory cells. The single-crystal channel is formed by applying at least a first voltage between each metal gate and the substrate to change the resistivity of the polysilicon sidewalls, applying a second voltage between the silicon substrate and the metal layer to melt the polysilicon sidewalls, and allowing the melted polysilicon sidewalls to recrystallize into the single-crystal channel.

[0027] In some embodiments, a series of decreasing voltage pulses may be applied to the memory structure, e.g., using metal layer 90 (or metal segments 12) and ohmic contacts 95, to assist in the propagation of a crystallization wave from the bottom of the molten polysilicon sidewall (i.e., at the interface of substrate 50 and polysilicon sidewall 70) and / or to control the positive feedback loop (thermal runaway) induced by the decrease in polysilicon resistivity with increasing temperature. Figure 10 is an exemplary timing diagram of decreasing voltage pulses that may be applied to the memory structures shown in Figures 6 and 8.

[0028] In some embodiments, after melting and recrystallizing the polysilicon sidewalls to form channel 85, as described above, top metal layer 90 and an upper portion of the memory device structure are removed. For example, referring to memory structure 150 of FIG. 11 , after removal of metal layer 90 (or metal segment 12 shown in FIG. 8 ), portion 140 of the memory structure is removed using, for example, an etching process or chemical mechanical polishing (CMP). In FIG. 11 , exemplary portion 140 is shown as including two layers of oxide 20 and one layer of nitride 30, along with an adjacent trench. However, it is understood that more layers of oxide and nitride in stack 10 may be removed. Removing portion 140 also removes polysilicon sidewall 70 in portion 140 that may not have undergone recrystallization due to premature heat loss from the top contact. The remaining portion of memory structure 150 has channel 85 with uniformity of crystallization. To accommodate such removal, the stack of alternating oxide and nitride layers, and the trench, may be adapted to be longer than desired so that the trench reaches the desired length after the removal step.

[0029] After melting and crystallization of the polysilicon sidewalls, removal of the metal layer / segments from the top of the memory structure, and optional removal of portions of the top of the memory structure as described with reference to Figure 11, the nitride layer 30 is removed using an etching process, thereby forming the memory structure 160 shown in Figure 12. The removal of the nitride layer results in the formation of an opening 36 in the stack 10, as shown in Figure 12.

[0030] Next, as shown in FIG. 13, a layer of tunnel oxide 172, a layer of storage oxide 174, and a layer of blocking oxide 176 are formed along the sidewalls and bottom of each opening 36. Thereafter, as shown in FIG. 14, a layer of metal 180 is deposited in each opening 36. Each metal 180 forms a gate of a NAND memory cell. Each gate 180, along with its associated tunnel oxide 172, storage oxide 174, and blocking oxide 176 formed in the same opening 36, forms a vertical NAND memory cell. The channel for each such memory cell is the portion of the polysilicon channel 85 facing the tunnel oxide 172, as is well known. A memory structure such as that shown in FIG. 14 may have, for example, 100 NAND memory cells in a vertical stack 10.

[0031] 15-21 illustrate various processing steps used in forming a string of vertical 3D NAND memory cells according to another embodiment of the present disclosure. Figure 15 shows a stack 300 of alternating layers of oxide 20 and metal (such as tungsten) 30 formed on a crystalline silicon substrate 350 using deposition, patterning, and etching steps. Next, as shown in Figure 16, a trench 360 extending to the surface of the substrate 350 is formed in the stack 300 using masking and patterning steps.

[0032] Next, a layer of blocking oxide 376, a layer of storage oxide 374, and a layer of tunnel oxide 372 are respectively deposited along the sidewalls of the trench, as shown in Figure 17. Thereafter, a layer of polysilicon 380 is formed along the sidewalls of the trench and adjacent to the tunnel oxide layer 372, as shown in Figure 18. The trench is then filled with oxide 390, as shown in Figure 19.

[0033] 20, a layer of metal 392 is formed over the polysilicon sidewalls 380 and oxide 390. In some embodiments (not shown), the metal layer 392 covers the top surface of the stack 300. After an ohmic contact 394 is formed in the substrate 350, a voltage 396 is applied between the metal layer 392 and the ohmic contact 394. The applied voltage causes a current to flow between the two metal nodes and through the polysilicon sidewalls 380 (shown using dashed line 396), causing localized melting of the polysilicon sidewalls. The voltage level is determined in part by the resistivity of the polysilicon sidewalls.

[0034] After the melting condition is reached within the polysilicon sidewalls, the voltage is removed to allow the molten polysilicon to cool. Because the silicon substrate 350 represents a relatively large heat sink, the molten polysilicon cools and begins to recrystallize at the interface between the polysilicon and the silicon substrate 350. The recrystallization will then propagate from the bottom (i.e., the interface between the polysilicon and the substrate 350) to the top of the polysilicon near the surface of the stack 300. Thus, according to embodiments of the present disclosure, melting of the polysilicon sidewalls is achieved by the Joule effect, and recrystallization of the molten polysilicon is achieved by different, asymmetric heat dissipation.

[0035] 21 shows the memory device structure of FIG. 20 after the polysilicon sidewalls have been melted and crystallized to form memory cell channel 385. Each metal layer 330, along with its associated tunnel oxide 372, storage oxide 374, blocking oxide 376, and the portion of polysilicon channel 385 facing tunnel oxide 172, forms a NAND memory cell in stack 300. One such NAND cell is identified in FIG. 21 as NAND memory cell 400.

[0036] FIG. 23A illustrates a semiconductor memory structure 500 that is similar to the memory structure illustrated in FIG. 21 , except that the memory structure 500 includes polysilicon sidewalls 380 that have not been melted and recrystallized. After application of a voltage (not shown) between the metal layer 392 and the ohmic contact 394 of the memory structure 500, the polysilicon sidewalls 380 are melted and recrystallized to form a single-crystalline silicon channel. FIG. 23B illustrates the memory structure of FIG. 23A after such a voltage has been applied, followed by melting and recrystallization of the polysilicon sidewalls 380 to form a single-crystalline silicon channel 385. Referring to FIG. 23A , by varying the voltage applied to the metal gate 370, and thus altering the resistivity of the polysilicon sidewalls 380, the voltage level required to melt the polysilicon sidewalls 380 can be changed.

[0037] According to one embodiment of the present disclosure, a method for forming a number of vertically oriented NAND memory cells includes, in part, forming multiple alternating layers of metal gates and oxides on a silicon substrate, forming trenches in the alternating layers of metal gates and oxides to expose a surface of the silicon substrate, depositing a first layer of oxide, a second layer of oxide, and a third layer of oxide along sidewalls of the trenches, depositing a layer of polysilicon along the sidewalls of the trenches and adjacent to the first layer of oxide within the trenches, filling the trenches with the oxide, forming a metal layer over the trenches, and forming single-crystalline channels for the plurality of NAND memory cells. The single-crystalline channels are formed by applying at least a first voltage between each metal gate and the substrate to change the resistivity of the polysilicon sidewalls, applying a second voltage between the silicon substrate and the metal layer to melt the polysilicon sidewalls, and allowing the melted polysilicon sidewalls to recrystallize into single-crystalline channels.

[0038] 24 illustrates an exemplary machine of computer system 900 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies described herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0039] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, web appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Moreover, while a single machine is shown, the term "machine" should also be taken to include any collection of machines that individually or jointly execute a set of instructions (or multiple sets) to perform any one or more of the methodologies described herein.

[0040] The exemplary computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0041] Processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 902 may be configured to execute instructions 926 to perform the operations and steps described herein.

[0042] Computer system 900 may further include a network interface device 908 for communicating over a network 920. Computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0043] The data storage device 918 may include a machine-readable storage medium 924 (also known as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 926 or software that embody any one or more of the methodologies or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during their execution by the computer system 900, with the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0044] In some implementations, instructions 926 include instructions for performing functionality corresponding to the present disclosure. While machine-readable storage medium 924 is shown in the exemplary implementation to be a single medium, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium capable of storing or encoding a set of instructions for execution by a machine and that cause the machine and processing device 902 to perform any one or more of the methodologies of the present disclosure. Accordingly, the term "machine-readable storage medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0045] Some portions of the foregoing detailed descriptions are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. Operations require physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0046] It should be noted, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically indicated, as will be apparent from this disclosure, certain terms will be understood throughout this description to refer to the actions and processes of a computer system, or similar electronic computing device, that manipulate and convert data represented as physical (electronic) quantities in the computer system's registers and memory into other data that are similarly represented as physical quantities in the computer system's memory or registers or other such information storage devices.

[0047] This disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored within the computer. Such a computer program may be stored in a computer-readable storage medium such as any type of disk, including, but not limited to, floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions and each coupled to a computer system bus.

[0048] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. Additionally, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0049] The present disclosure may be provided as a computer program product, or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) media includes machine- (e.g., computer-) readable storage media such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0050] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific exemplary implementations thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the implementations of the present disclosure as set forth in the appended claims. Where the present disclosure refers to several elements in the singular, more than one element may be shown in the figures, and similar elements will be labeled with similar reference numerals. Therefore, the present disclosure and the drawings should be taken in an illustrative, and not a limiting, sense.

Claims

1. 1. A method of forming a plurality of vertical NAND memory cells, the method comprising: forming a plurality of insulating materials on a silicon substrate; forming trenches in the plurality of insulating materials, the trenches exposing a surface of the silicon substrate; depositing a layer of polysilicon along the sidewalls of the trench to form polysilicon sidewalls; filling the trench with oxide; forming a metal layer over the trench; forming a single crystal channel for the plurality of vertical NAND memory cells; applying a voltage between the silicon substrate and the metal layer to cause a current to flow between the silicon substrate and the metal layer, thereby melting the polysilicon sidewalls; and allowing the molten polysilicon sidewall to recrystallize into the single crystal channel; forming the single crystal channel by forming an epitaxial layer near one or more of a top of the trench and a bottom of the trench; A method comprising:

2. The method of claim 1 , further comprising forming the metal layer over the plurality of insulating materials.

3. The method of claim 1 , further comprising removing portions of the trench and the plurality of insulating materials.

4. The method of claim 1 , further comprising applying a plurality of pulses between the metal layer and the silicon substrate after the application of the voltage.

5. The method of claim 1 , wherein the plurality of insulating materials comprises alternating layers of oxide and nitride.

6. removing the nitride layers in the alternating layers and forming a plurality of openings along the trench, each opening associated with and adapted to form a different one of the plurality of vertical NAND memory cells; depositing at least first and second layers of oxide along the sidewalls and bottom of each opening, the first layer of oxide forming a tunnel oxide of the associated vertical NAND memory cell and the second layer of oxide forming a storage oxide of the associated vertical NAND memory cell; The method of claim 5 further comprising:

7. 7. The method of claim 6, further comprising depositing at least a third layer of oxide along the sidewalls and the bottom of each opening.

8. 8. The method of claim 7, further comprising depositing a metal layer in each opening following said depositing said third layer of oxide.

9. 2. The method of claim 1, wherein the voltage is defined by the resistivity of the polysilicon sidewalls.

10. 1. A method of forming a plurality of vertical NAND memory cells, the method comprising: forming a plurality of alternating layers of metal and oxide on a silicon substrate; forming trenches in the alternating layers of metal and oxide, the trenches exposing a surface of the silicon substrate; depositing a first layer of oxide, a second layer of oxide, and a third layer of oxide along sidewalls of the trench; depositing a layer of polysilicon along sidewalls of the trench and adjacent to the first layer of oxide in the trench to form polysilicon sidewalls; filling the trench with oxide; forming an epitaxial layer near one or more of a top of the trench and a bottom of the trench; forming a metal layer over the trench; forming a single crystal channel for the plurality of vertical NAND memory cells; applying a voltage between the silicon substrate and the metal layer to cause a current to flow between the silicon substrate and the metal layer, thereby melting the polysilicon sidewalls; and allowing the molten polysilicon sidewall to recrystallize into the single crystal channel; forming the single crystal channel by A method comprising:

11. The method of claim 10 further comprising forming the metal layer over the multiple alternating layers of metal and oxide.

12. The method of claim 10 further comprising removing portions of the trench and the multiple alternating layers of metal and oxide.

13. The method of claim 10 , further comprising applying a plurality of pulses between the metal layer and the silicon substrate after the application of the voltage.

14. 14. The method of claim 13, wherein a pulse height applied between a first time point and a second time point is higher than a pulse height applied between the second time point and a third time point, the first time point occurring before the second time point, and the second time point occurring before the third time point.

15. The method of claim 10 , wherein the voltage is defined by the resistivity of the polysilicon sidewalls.

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