MEMORY SYSTEM AND MEMORY SYSTEM PROCESSING METHOD - Patent application

Abstract

To provide a memory system capable of making a NAND flash memory that is once determined to be unusable, reusable and a method of processing the memory system.SOLUTION: A memory system 1 includes a substrate Sub1, a memory controller P2 provided on the substrate Sub1, a connector 80 provided on the substrate Sub1, and a memory device P1 attachable to / detachable from the connector 80. By removing the memory device P1 where execution of operation is disabled and performing an annealing process thereon, the characteristics thereof are restored, thereby, the memory device P1 is made reusable.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to memory systems and methods of operating memory systems. [Background technology]

[0002] Memory systems including NAND flash memory are produced and provided. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0240388 [Patent Document 2] U.S. Patent No. 10,289,343 [Patent Document 3] US Patent Application Publication No. 2013 / 0185487 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce the cost of the memory system. [Means for solving the problem]

[0005] The memory system of the embodiment includes: a substrate including a first portion including a first connector and a second portion including a second connector configured to be detachable from the first connector; a memory controller provided on the first portion; a memory device provided on the second portion and communicating with the memory controller via the first and second connectors; and an electronic component provided on the second portion, wherein the heat resistance of the electronic component is higher than the heat resistance of the memory controller; . [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] FIG. 1 is a circuit diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 3] 1 is a cross-sectional view showing an example of the configuration of a memory system according to an embodiment; [Figure 4] 1 is a cross-sectional view showing an example of the configuration of a memory system according to an embodiment; [Figure 5]FIG. 1 is a diagram showing the relationship between the threshold voltage and data of a memory cell. [Figure 6] FIG. 1 is a diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 7] FIG. 1 is a diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 8] FIG. 1 is a diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 9] FIG. 1 is a diagram showing an apparatus for processing a memory system according to an embodiment. [Figure 10] 10 is a flowchart showing a processing method of the memory system according to the embodiment. [Figure 11] 5A and 5B are diagrams for explaining a processing method of the memory system according to the embodiment; [Figure 12] FIG. 1 is a diagram showing an application example of a memory system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, elements having the same functions and configurations are designated by the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference symbols with distinguishing numbers / letters at the end do not need to be distinguished from each other, descriptions (reference symbols) with the numbers / letters at the end omitted are used.

[0008] [Embodiment] A memory system according to an embodiment will be described with reference to FIGS.

[0009] (1) Configuration example FIG. 1 is a block diagram illustrating an example of the configuration of a memory system 1 according to this embodiment.

[0010] 1, the memory system 1 of the embodiment is connected to a host device 5 via a host bus. The memory system 1 of the embodiment can be requested by the host device 5 to write data, read data, and erase data.

[0011] The host device 5 is, for example, a personal computer or a server. TM The interface is a bus based on an interface standard such as SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), PCIe (Peripheral component interconnect express), or NVMe (Non-volatile memory express). The memory system 1 may be connected to the host device 5 via wireless communication.

[0012] The memory system 1 of this embodiment includes a NAND flash memory 100 and a memory controller 200. For example, the memory system 1 is an SSD (Solid State Drive), a memory card, a USB memory, or the like.

[0013] The memory controller 200 is electrically coupled to the NAND flash memory 100. The memory controller 200 sends a command CMD, address information ADD, and a plurality of control signals to the NAND flash memory 100. The NAND flash memory 100 is an example of a memory device according to an embodiment. The NAND flash memory 100 is a nonvolatile semiconductor memory device. For example, the NAND flash memory 100 is a collection of multiple semiconductor chips.

[0014] The NAND flash memory 100 receives a command CMD, address information ADD, and a number of control signals. Data DT is transferred between the NAND flash memory 100 and the memory controller 200. Hereinafter, the data DT transferred from the memory controller 200 to the NAND flash memory 100 during a write sequence is referred to as write data. The write data DT is written into the NAND flash memory 100. During a read sequence, the data DT transferred from the NAND flash memory 100 to the memory controller 200 is referred to as read data. The read data DT is read from the NAND flash memory 100.

[0015] The NAND flash memory 100 includes, for example, a memory cell array 110, a command register 120, an address register 130, a row control circuit 140, a sense amplifier circuit 150, a driver circuit 160, a voltage generation circuit 170, an input / output circuit 180, and a sequencer 190.

[0016] The memory cell array 110 stores data. A plurality of bit lines and a plurality of word lines are provided within the memory cell array 110. The memory cell array 110 includes a plurality of blocks BLK (BLK0, BLK1, . . . , BLKk-1), where k is a natural number equal to or greater than 2. A block BLK is a collection of a plurality of memory cells. Each memory cell is associated with one bit line and one word line. The memory cell array 110 includes a plurality of select gate lines for selecting a control unit within the memory cell array 110.

[0017] For example, a certain number of specific blocks BLK among the multiple blocks BLK store information INF such as setting information and management information for the operation of the NAND flash memory 100, and information AN about the state / status of the NAND flash memory 100. Hereinafter, this information INF will also be referred to as ROM information INF. The blocks BLK that store ROM information INF will also be referred to as ROM blocks.

[0018] The internal configuration of the memory cell array 110 will be described later.

[0019] The command register 120 holds a command CMD from the memory controller 200. The command CMD is, for example, a signal including an instruction to cause the sequencer 190 to execute a read sequence, a write sequence, an erase sequence, or the like.

[0020] The address register 130 holds address information (selected address) ADD from the memory controller 200. The address information ADD includes, for example, a block address, a page address (word line address), and a column address. The block address, page address, and column address are used to select a block BLK, a word line, a select gate line, and a bit line, respectively. Hereinafter, a block selected based on a block address is referred to as a selected block. A word line selected based on a page address is referred to as a selected word line.

[0021] The row control circuit 140 controls operations related to the rows of the memory cell array 110. The row control circuit 140 selects one block BLK in the memory cell array 110 based on the block address in the address register 130. The row control circuit 140, for example, transfers a voltage applied to a wiring corresponding to the selected word line to the selected word line in the selected block. The row control circuit 140 controls the selection and non-selection of select gate lines based on address information ADD. The row control circuit 140 includes a block decoder, a word line decoder, a select gate line decoder, a switch circuit, etc.

[0022] The sense amplifier circuit 150 controls operations related to columns of the memory cell array 110. In a write sequence, the sense amplifier circuit 150 applies a voltage to each bit line provided in the memory cell array 110 in accordance with write data DT from the memory controller 200. In a read sequence, the sense amplifier circuit 150 determines the data stored in the memory cell based on the presence or absence of current generation or fluctuations in the potential of the bit line. The sense amplifier circuit 150 transfers data based on this determination result to the memory controller 200 as read data DT. The sense amplifier circuit 150 includes a bit line selection circuit, an amplifier circuit, etc.

[0023] The driver circuit 160 outputs a plurality of voltages used in a read sequence, a write sequence, an erase sequence, etc. to the memory cell array 110. Based on address information ADD in the address register 130, the driver circuit 160 applies predetermined voltages to wiring corresponding to word lines, bit lines, etc.

[0024] The voltage generation circuit 170 generates a plurality of voltages for various operations of the NAND flash memory 100. The voltage generation circuit 170 outputs the generated voltages to the driver circuit 160.

[0025] The input / output circuit 180 functions as an interface circuit on the NAND flash memory 100 side between the NAND flash memory 100 and the memory controller 200. For example, the input / output circuit 180 communicates with the memory controller 200 based on a NAND interface standard such as ONFi (Open NAND flash interface). A command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal DQ, and the like are used for communication between the NAND flash memory 100 and the memory controller 200.

[0026] The command latch enable signal CLE is a signal indicating that the input / output signal DQ received by the NAND flash memory 100 is a command CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received by the NAND flash memory 100 is address information ADD. The write enable signal WEn is a signal that instructs the NAND flash memory 100 to input the input / output signal DQ. The read enable signal REn is a signal that instructs the NAND flash memory 100 to output the input / output signal DQ.

[0027] The ready / busy signal RBn is a signal that notifies the memory controller 200 from the NAND flash memory 100 whether the NAND flash memory 100 is in a ready state where it can accept commands from the memory controller 200, or in a busy state where it cannot accept commands.

[0028] The input / output signals DQ are, for example, an 8-bit wide signal set, and may include a command CMD, address information ADD, write / read data DT, and the like.

[0029] The sequencer 190 controls the overall operation of the NAND flash memory 100. For example, the sequencer 190 controls each circuit based on the command CMD in the command register 120.

[0030] <Memory cell array> FIG. 2 is a circuit diagram showing the circuit configuration of one block BLK in the memory cell array 110. As shown in FIG.

[0031] 2, one block BLK includes multiple (e.g., five) string units SU (SU0 to SU4). Each string unit SU includes multiple NAND strings NS. The number of blocks BLK in the memory cell array 110, the number of string units SU in each block BLK, and the number of NAND strings NS in each string unit SU are arbitrary.

[0032] Each of the NAND strings NS includes a plurality of memory cells MT (MT0 to MTn-1) and select transistors STD and STS, where n is a natural number equal to or greater than 2. The memory cells MT are connected in series between the source of the select transistor STD and the drain of the select transistor STS.

[0033] The memory cell MT stores data in a substantially non-volatile manner. The memory cell (also called a memory cell transistor) MT is a field effect transistor having a control gate and a charge storage layer.

[0034] The gate of the select transistor STD in each of the string units SU0 to SU4 is connected to a corresponding one of a plurality of drain-side select gate lines SGD0 to SGD4. The gates of the select transistors STS in each of the string units SU0 to SU4 are commonly connected to a source-side select gate line SGS, for example. The gates of the select transistors STS may be connected to different select gate lines SGS for each of the string units SU0 to SU4.

[0035] The control gates of the memory cells MT0 to MTn-1 that belong to the same block BLK are each connected to a corresponding one of a plurality of word lines WL (WL0 to WLn-1).

[0036] The drains of the select transistors STD of the NAND strings NS belonging to the same column in the memory cell array 110 are connected to corresponding ones of the multiple bit lines BL (BL0 to BL(m-1)), where m is a natural number of 2 or more. The sources of the select transistors STS are commonly connected to a source line SL.

[0037] A string unit SU is a collection of NAND strings NS connected to different bit lines BL and the same select gate line SGD. Hereinafter, in each string unit SU, a collection of memory cells MT commonly connected to the same word line WL (memory cell group) is also referred to as a cell unit CU (or memory group). A block BLK is a collection of multiple string units SU that share multiple word lines WL. A memory cell array 110 is a collection of multiple blocks BLK that share multiple bit lines BL.

[0038] FIG. 3 is a cross-sectional view of a partial area of ​​the block BLK.

[0039] In FIG. 3, the X direction corresponds to the extension direction of the word lines WL, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the direction perpendicular to the surface of the substrate (e.g., semiconductor substrate) 20 used to form the NAND flash memory 100.

[0040] As shown in FIG. 3, the memory cell array 110 has a structure (stacked wiring) in which a plurality of conductive layers 22 (22a, 22b, 22c) and a plurality of insulating layers 32 (32a, 32b, 32c) are stacked in the Z direction.

[0041] A p-type well region 21 is provided in the semiconductor layer of the semiconductor substrate 20 .

[0042] An insulating layer 32a is provided on the upper surface of the p-type well region 21. A conductive layer 22a is provided on the upper surface of the insulating layer 32a. The conductive layer 22a is, for example, a plate-shaped layer extending along an XY plane formed by the X and Y directions. The conductive layer 22a is used as a select gate line SGS. The conductive layer 22a includes, for example, tungsten.

[0043] On the upper surface of the conductive layer 22a, a plurality of insulating layers 32b and a plurality of conductive layers 22b are alternately stacked in the Z direction. The conductive layer 22b is, for example, a plate-like layer extending along the XY plane. The stacked conductive layers 22b are used as word lines WL0 to WLn-1, respectively, in order from the semiconductor substrate 20 side. The conductive layer 22b contains, for example, tungsten.

[0044] A conductive layer 22c is provided above the uppermost conductive layer 22b with an insulating layer 32c interposed therebetween. The conductive layer 22c is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22c is used as a select gate line SGD. The conductive layer 22c includes, for example, tungsten.

[0045] An insulating layer 34 is provided on the upper surface of the conductive layer 22c. The insulating layer 34 may be composed of multiple insulating layers. A conductive layer 25 is provided on the upper surface of the insulating layer 34. The conductive layer 25 is, for example, a linear layer extending in the Y direction. The conductive layer 25 is used as a bit line BL. In a region not shown, multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 includes, for example, copper.

[0046] Each of the memory pillars MP extends along the Z direction and is provided in the stacked wiring. The memory pillars MP penetrate the insulating layer 32 and the conductive layer 22. The bottom of the memory pillar MP contacts the p-type well region 21. The side of the memory pillar MP faces the conductive layer 22. The portion where the memory pillar MP intersects with the conductive layer 22a functions as a select transistor STS. The portion where the memory pillar MP intersects with one conductive layer 22b functions as one memory cell MT. The portion where the memory pillar MP intersects with the conductive layer 22c functions as a select transistor STD.

[0047] Each of the memory pillars MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is provided to extend along the Z direction. For example, the upper end of the core member 40 is located above the conductive layer 22c. The semiconductor layer 41 is provided between the lower end of the core member 40 and the p-type well region 21. The semiconductor layer 41 covers the periphery of the core member 40. At the bottom of the memory pillar MP, a portion of the semiconductor layer 41 is in contact with the p-type well region 21. The stacked film 42 covers the side surface of the semiconductor layer 41. The core member 40 includes an insulator such as silicon oxide, etc. The semiconductor layer 41 includes silicon, for example.

[0048] Contacts CV are provided on the top surface of the semiconductor layer 41 in the memory pillar MP. In the illustrated region, two contacts CV are shown corresponding to two of the six memory pillars MP. Of the multiple memory pillars MP shown in FIG. 3, memory pillars MP that do not overlap with the slit SHE and are not connected to a contact CV are connected to the contact CV in a region not shown (for example, a region toward the front or back of the page).

[0049] One conductive layer 25 (that is, one bit line BL) is in contact with the upper surface of the contact CV.

[0050] The slits SLT have a portion provided along, for example, the XZ plane, and separate the plurality of conductive layers 22. The contacts LI are provided along the slits SLT. A portion of the upper end of the contact LI is in contact with the insulating layer 34. The lower end of the contact LI is in contact with the p-type well region 21. The contacts LI are used, for example, as part of the source lines SL. A spacer SP is provided at least between the contact LI and the conductive layer 22. The contacts LI are separated and insulated from the conductive layer 22 by the spacer SP.

[0051] The slit SHE has a portion provided along, for example, the XZ plane and divides at least the conductive layer 22c. The upper end of the slit SHE is in contact with the insulating layer 34. The lower end of the slit SHE is in contact with the insulating layer 32c between the uppermost conductive layer 22b and the conductive layer 22c. The slit SHE includes an insulator such as silicon oxide.

[0052] A plurality of the above configurations are arranged in the depth direction (or forward direction) of the paper surface of Fig. 3. A set of a plurality of NAND strings NS arranged in the depth direction constitutes a string unit SU.

[0053] The structure of the memory cell array 110 is not limited to the above example, and may have other structures. For example, the memory cell array 110 may be provided above the semiconductor substrate 20 via an insulating layer. In this case, elements (e.g., field-effect transistors) constituting the row control circuit 140 and the like may be provided on the semiconductor substrate 20 below the memory cell array 110.

[0054] FIG. 4 is a cross-sectional view showing the structure of the memory cell MT in more detail.

[0055] As shown in FIG. 4, the stacked film 42 includes a gate insulating film 421, a charge storage layer 422, and a block insulating film 423.

[0056] The semiconductor layer 41 functions as a current path for the NAND string NS. The semiconductor layer 41 is a region where the channels of the memory cell MT and the select transistors STD and STS are formed (hereinafter referred to as a channel region). The channel region of the memory cell MT faces the conductive layer 22 in a direction parallel to the surface of the semiconductor substrate 20.

[0057] The gate insulating film 421 surrounds the side surfaces of the semiconductor layer 41. The charge storage layer 422 surrounds the side surfaces of the gate insulating film 421. The block insulating film 423 surrounds the side surfaces of the charge storage layer 422. The charge storage layer 422 is provided between the gate insulating film 421 and the block insulating film 423.

[0058] The gate insulating film 421 functions as a tunnel barrier between the semiconductor layer 41 and the charge storage layer 422. The gate insulating film 421 includes, for example, silicon oxide.

[0059] The charge storage layer 422 can store charges injected into the charge storage layer 422 from the semiconductor layer 41 via the gate insulating film 421. The charge storage layer 422 contains, for example, silicon nitride. The charge storage layer 422 may also contain silicon.

[0060] The block insulating film 423 prevents charge transfer between the charge storage layer 422 and the conductive layer 22. The block insulating film 423 includes, for example, silicon oxide or aluminum oxide.

[0061] In the NAND flash memory 100, when the memory cells MT0 to MTn-1 and the select transistors STD and STS are turned on, a current flows between the bit line BL and the contact LI (source line SL) via the memory pillar MP.

[0062] A single memory cell MT can store one or more bits of data depending on the association between the threshold voltage of the memory cell MT and the data to be stored. A memory cell MT that stores one bit of data is called an SLC. A memory cell MT that stores two bits of data is called an MLC. A memory cell MT that stores three bits of data is called a TLC. A memory cell MT that stores four bits of data is called a QLC.

[0063] 5 is a diagram showing an example of the relationship between the threshold voltage of a memory cell MT and data. The horizontal axis of the graph in FIG. 5 represents the threshold voltage (voltage value) of the memory cell MT. The vertical axis of the graph in FIG. 5 represents the number of memory cells.

[0064] FIG. 5 shows an example in which the memory cells are QLC. 5, when each memory cell MT stores 4-bit data, the threshold voltage distribution of the memory cell MT has 16 different states. In this embodiment, these 16 states are referred to as "Q0," "Q1," "Q2," "Q3," "Q4," "Q5," "Q6," "Q7," "Q8," "Q9," "Q10," "Q11," "Q12," "Q13," "Q14," and "Q15" states, in order from lowest to highest threshold voltage. Each of the "Q0" to "Q15" states is assigned a different 4-bit data.

[0065] An example of data allocation for each of the "Q0" to "Q15" states is shown below. Here, for each state, 4-bit data is shown in the order of "Top bit / Upper bit / Middle bit / Lower bit."

[0066] “Q0” state: “1111” data “Q1” state: “0111” data “Q2” state: “0011” data “Q3” state: “1011” data “Q4” state: “1001” data “Q5” state: “0001” data “Q6” state: “0101” data “Q7” state: “1101” data “Q8” state: “1100” data “Q9” state: “0100” data “Q10” state: “0000” data “Q11” state: “1000” data “Q12” state: “1010” data “Q13” state: “0010” data “Q14” state: “0110” data “Q15” state: “1110” data In this way, data having a specific data pattern (bit arrangement) is associated with each of the states of the multiple threshold voltage distributions.

[0067] A read voltage is set between each adjacent state. Specifically, a read voltage R1 is set between the states "Q0" and "Q1." A read voltage R2 is set between the states "Q1" and "Q2." A read voltage R3 is set between the states "Q2" and "Q3." A read voltage R4 is set between the states "Q3" and "Q4." A read voltage R5 is set between the states "Q4" and "Q5." A read voltage R6 is set between the states "Q5" and "Q6." A read voltage R7 is set between the states "Q6" and "Q7." A read voltage R8 is set between the states "Q7" and "Q8." A read voltage R9 is set between the states "Q8" and "Q9." A read voltage R10 is set between the states "Q9" and "Q10." A read voltage R11 is set between the states "Q10" and "Q11." Between the states "Q11" and "Q12", a read voltage R12 is set. Between the states "Q12" and "Q13", a read voltage R13 is set. Between the states "Q13" and "Q14", a read voltage R14 is set. Between the states "Q14" and "Q15", a read voltage R15 is set.

[0068] If the threshold voltage of the memory cell MT is higher than the applied read voltage, the memory cell MT is turned off. If the threshold voltage of the memory cell MT is equal to or lower than the applied read voltage, the memory cell MT is turned on. In this way, the magnitude relationship of the threshold voltage of the memory cell relative to the applied read voltage can be determined by turning the memory cell MT on or off in response to the application of the read voltage.

[0069] One page of data (lower page data) composed of lower bits is determined by one threshold voltage determination (memory cell on / off determination) using read voltage R8. That is, the lower page data is determined by one read voltage among read voltages R1 to R15. The read voltage is applied once when reading the lower page data.

[0070] One page of data (middle page data) composed of the middle bits is determined by two threshold voltage determinations using two read voltages R4 and R12. That is, the middle page data is determined by two read voltages among the read voltages R1 to R15. The number of read voltages applied when reading the middle page data is two.

[0071] One page of data (upper page data) consisting of the upper bits is determined by four threshold voltage determinations using four read voltages R2, R6, R10, and R14. That is, the upper page data is determined by four read voltages among the read voltages R1 to R15. The number of read voltages applied when reading the upper page data is four.

[0072] One page of data (top page data) consisting of the most significant bit is determined by eight threshold voltage determinations using eight read voltages R1, R3, R5, R7, R9, R11, R13, and R15. That is, the top page data is determined by eight read voltages among the read voltages R1 to R15. The number of read voltages applied when reading the top page data is eight.

[0073] Hereinafter, a read operation of lower page data is referred to as a "lower read." A read operation of middle page data is referred to as a "middle read." A read operation of upper page data is referred to as an "upper read." A read operation of top page data is referred to as a "top read."

[0074] The data allocation described above is called, for example, "1-2-4-8" coding, since the read voltage is applied once, twice, four times, and eight times in the lower, middle, upper, and highest read operations, respectively.

[0075] When the memory cell MT stores 4-bit data, the data may be allocated in a different manner. Also, each memory cell MT may store 5-bit or more data.

[0076] The structure of the memory cell MT is not limited to the structure shown in Fig. 4. For example, the memory cell MT may be a memory cell with a stack gate structure having a floating gate electrode.

[0077] In the operation sequence of the NAND flash memory 100, a cycle in which an erase sequence for a block BLK including a selected address to which data is to be written is followed by a write sequence for the selected address is treated as one cycle (hereinafter referred to as a P / E cycle). In the erase sequence, an erase voltage having a relatively large voltage value is applied to the memory cell MT to erase the charge in the memory cell MT. In the write sequence, a program voltage having a relatively large voltage value is applied to the memory cell MT to inject charge into the memory cell MT.

[0078] 4, in a memory cell MT of the NAND flash memory 100, when data is repeatedly written to and erased from the memory cell MT, a defect 999 occurs in the memory cell MT due to stress caused by a large voltage applied to the memory cell MT. For example, the defect 999 is formed inside the gate insulating film 421, inside the charge storage layer 422, inside the block insulating film 423, etc. The defect 999 causes deterioration of the characteristics of the memory cell MT. As the number of P / E cycles increases, the deterioration of the characteristics of the memory cell MT becomes more noticeable.

[0079] The defect 999 in the memory cell MT can be removed by annealing (heat treatment) under certain conditions, and as a result, the characteristics of the memory cell MT can be restored.

[0080] In this embodiment, the deterioration of the memory cell MT is restored by the following configuration and processing.

[0081] As a result, according to this embodiment, the NAND flash memory 100 that was once determined to be unusable is reused.

[0082] (2) Configuration and processing for recovery processing (2-1) Modular structure The module structure of the memory system 1 of this embodiment will be described with reference to FIGS. 6 to 8. FIG. 6 is a schematic diagram showing an example of a module structure of the memory system 1 of this embodiment.

[0083] 6, the memory system 1 of this embodiment includes a plurality of package devices P1, P2, and P3. The plurality of package devices P1, P2, and P3 are provided on a module substrate Sub1.

[0084] The package device P1 is a semiconductor package of the NAND flash memory 100. Hereinafter, the package device P1 is also referred to as a memory package P1. For example, the memory package P1 includes multiple semiconductor chips (not shown) that constitute the NAND flash memory 100 on a package substrate (not shown) of a certain structure.

[0085] The package device P2 is a semiconductor package of the memory controller 200. Hereinafter, the package device P2 will also be referred to as a controller package P2.

[0086] The package device P3 is, for example, a semiconductor package for a power supply IC. Hereinafter, the package device P3 will also be referred to as a power supply IC package P3. The power supply IC package P3 supplies various voltages to the memory package P1 and the controller package P2. For example, the power supply IC package includes a regulator circuit, a DC-AC conversion circuit, a protection circuit, etc.

[0087] The memory package P1 is electrically connected to the controller package P2, the power supply IC package P3, and electronic components (not shown) via wiring (not shown) provided on the surface of the module substrate Sub1 or inside the module substrate Sub1.

[0088] In this embodiment, the memory package P1 of the NAND flash memory 100 is configured to be detachable from the module substrate Sub1. The memory package P1 is connected to the module substrate Sub1 via a connector 80 on the module substrate Sub1.

[0089] FIG. 7 is a schematic bird's-eye view showing an example of the configuration of the memory package P1 and the connector 80 in the memory system 1 of this embodiment.

[0090] For example, the memory package P1 has a BGA (Ball Grid Array) structure. The memory package P1 has a plurality of terminals (for example, solder balls) SB on the bottom of a package substrate (not shown).

[0091] However, the memory package P1 may have a package structure other than the BGA structure, such as a PGA (Pin Grid Array) structure, as long as it is detachable from the module substrate Sub1.

[0092] In the module substrate Sub1, a socket 800 is provided as the connector 80. The socket 800 has a plurality of connection portions 801 and a plurality of terminals 802.

[0093] Each connection portion 801 is provided on the upper surface side of the socket 800. The terminals 802 are provided on the lower surface side of the socket 800. Each terminal 802 is electrically connected to a corresponding one of the multiple connection portions 801 via wiring within the socket 800. Each connection portion 801 is connected to a wiring or terminal of the module substrate Sub1 via the corresponding terminal 802. For example, the terminals 802 are pins or lead portions.

[0094] Each of the plurality of terminals SB of the memory package P1 is connected to a corresponding one of the plurality of connection portions 801.

[0095] When the memory package P1 is connected to the socket 800, it is fixed to the socket 800 by a fixing part (not shown), such as a top cover or a plate.

[0096] As a result, the memory package P1 is mounted (implemented) on the module substrate Sub1 so as to be detachable from the module substrate Sub1 by the socket 800.

[0097] When the memory system 1 is shipped or used, the memory package P1 is connected to the socket 800 of the module substrate Sub1. During recovery processing on the NAND flash memory 100, the memory package P1 is removed from the socket 800 of the module substrate Sub1. Annealing processing for the recovery processing is performed on the removed memory package P1. After the annealing process, the memory package P1 is reconnected to the socket 800.

[0098] This selectively anneals the memory package P1 among the multiple package devices P1, P2, and P3 in the memory system 1. The package devices P1 and P2 other than the memory package P1 in the memory system 1 are prevented from being exposed to the high temperature conditions of the annealing process.

[0099] FIG. 8 shows an example of a module structure different from that shown in FIG.

[0100] The module substrate Sub2 may have a plurality of separable portions 81a and 81b, which are referred to herein as substrate portions 81a and 81b. Each of the substrate units 81a and 81b has a connector 82a or 82b. The substrate units 81a and 81b are electrically connected via the connectors 82a and 82b. Signals and voltages are transferred between the substrate units 81a and 81b via the connectors 82a and 82b. This allows the NAND flash memory 100 to communicate with the memory controller 200 via the connectors 82a and 82b. The power supply IC package P3 also supplies various voltages (e.g., power supply voltage and ground voltage) to the NAND flash memory 100 via the connectors 82a and 82b.

[0101] For example, the controller package P2 and the power supply IC package P3 are provided on the substrate portion 81a of the module substrate Sub2. The memory package P1 is provided on the substrate portion 81b of the module substrate Sub2.

[0102] The memory system 1 includes a memory package P1, a controller package P2, and a plurality of electronic components 85, 85X such as capacitors.

[0103] For example, among the multiple electronic components, the electronic component 85, which is preferably provided near the memory package P1, is provided on the substrate portion 81b of the module substrate Sub2. The electronic component 85 provided on the substrate portion 81b desirably has heat resistance sufficient to withstand annealing treatment. The heat resistance of the electronic component 85 is higher than that of the controller package P2 (memory controller 200) and / or the power supply system IC package (power supply system IC) P3.

[0104] For example, electronic component 85X is provided on substrate portion 81a. The function (type) of electronic component 85X is the same as the function (type) of electronic component 85. The heat resistance of electronic component 85 is higher than that of electronic component 85X.

[0105] When the memory system 1 is in use, the board unit 81b is connected to the board unit 81a via the connectors 82a and 82b. When the recovery process for the NAND flash memory 100 is performed on the memory package P1, the substrate part 81b is separated from the substrate part 81a. The annealing treatment for the recovery process is performed on the entire substrate portion 81b on which the package device P1 is mounted.

[0106] In this way, by configuring the portion 81b on which the memory package P1 is provided to be detachable from the module substrate Sub2, it is possible to relatively easily avoid exposing devices other than the memory package P1, such as the controller package P2, to high temperature conditions during the annealing process.

[0107] (2-2) Recovery processing device With reference to FIG. 9, a device for performing recovery processing on the memory system 1 of this embodiment will be described.

[0108] FIG. 9 is a diagram showing an example of the configuration of a recovery processing device 9 for executing recovery processing for the NAND flash memory 100.

[0109] The recovery processing device 9 in FIG. 9 executes various operations, processes, and controls for the recovery process on the NAND flash memory 100. For example, the recovery processing device 9 includes an attachment / detachment processing unit 90, an operation execution unit 91, an annealing processing unit 92, a test unit 93, a determination unit 94, a storage unit 98, a control unit 99, and the like.

[0110] The attachment / detachment processing unit 90 removes the NAND flash memory 100 (memory package P1) from the module substrate Sub (Sub1, Sub2). The attachment / detachment processing unit 90 attaches the memory package P1 to the module substrate Sub. The attachment / detachment processing unit 90 includes a stage (not shown) for holding the NAND flash memory 100 within the recovery processing device 9. The attachment / detachment processing unit 90 has, for example, a mechanical unit (for example, a manipulator and an end effector) for attaching and detaching the memory package P1.

[0111] The operation execution unit 91 executes various operations of the NAND flash memory 100 held in the recovery processing device 9, such as a write sequence, an erase sequence, and a read sequence. The operation execution unit 91 reads various information and data from the NAND flash memory 100 through a read sequence and stores the read information in the storage unit 98. The operation execution unit 91 erases data in the NAND flash memory 100 through an erase sequence. The operation execution unit 91 writes information and data in the storage unit 98 to the NAND flash memory 100 through a write sequence.

[0112] For example, the operation execution unit 91 reads the ROM information INF from the ROM block BLK. In this embodiment, the ROM information INF includes, in addition to the setting information and management information, information AN relating to the annealing process of the NAND flash memory 100. Hereinafter, the information AN relating to the annealing process will be referred to as annealing process information AN.

[0113] The annealing process information AN includes history information regarding the annealing process of the NAND flash memory 100 to be processed. The annealing process information AN includes the number of annealing processes that have been performed on the NAND flash memory 100 to be processed. The annealing process information AN may also include information regarding the temperature and time of the annealing process. Hereinafter, the number of annealing processes that have been performed is also referred to as the cumulative number of annealing processes.

[0114] The setting information includes parameters used to operate the chips of the NAND flash memory 100. For example, the setting information includes a plurality of parameters related to voltage values ​​and various controls used in each operation sequence, such as program voltage parameters, read voltage parameters, and erase voltage parameters. The management information includes, for example, addresses of defective word lines, addresses of defective blocks, redundancy information, etc. The setting information and management information are written to one or more ROM blocks BLK of each chip of the NAND flash memory 100 during wafer die sorting.

[0115] The annealing unit 92 performs annealing under desired conditions on the NAND flash memory 100. For example, the annealing temperature is set to any temperature within a range from 120°C to 280°C. For example, the annealing time is set to any time within a range from 1 hour to 3 days (72 hours). The annealing temperature and time are not limited to the above values ​​and can be changed as appropriate depending on the type and characteristics of the NAND flash memory 100 and the materials constituting the NAND flash memory 100.

[0116] The test unit 93 can execute various test processes on the NAND flash memory 100. For example, the test unit 93 can obtain, as a test result, the magnitude of the distribution of the threshold voltages of a plurality of memory cells MT based on the results of writing and reading certain data to and from the plurality of memory cells MT.

[0117] The determining unit 94 performs various determination processes related to the recovery process of the NAND flash memory 100. For example, the determining unit 94 determines whether or not an annealing process has been performed.

[0118] The storage unit 98 stores ROM information and data read from the NAND flash memory 100. The storage unit 98 can store various types of information related to recovery processing and various types of information used by the units 90, 91, 92, 93, 94, and 99 in the recovery processing device 9. For example, the storage unit 98 can hold a program for recovery processing of the NAND flash memory 100.

[0119] The control unit 99 controls the operation and processing of each unit 90, 91, 92, 93, and 94 of the recovery processing device 9. For example, the control unit 99 uses information, data, and programs in the storage unit 98 to perform various controls.

[0120] The above-mentioned components 90, 91, 92, 93, 94, 98, and 99 of the recovery processing device 9 are realized by software (programs), hardware (circuits and mechanisms), and a combination of software and hardware, respectively.

[0121] (3) Processing example An example of processing performed by the memory system 1 of this embodiment will be described with reference to FIGS.

[0122] FIG. 10 is a flowchart for explaining an example of recovery processing in the memory system 1 of this embodiment.

[0123] <s0> In the memory system 1 of this embodiment, whether or not the NAND flash memory 100 has reached its usage limit is determined by the memory controller 200 (or the host device 5).

[0124] For example, the memory controller 200 determines whether the usage limit of the NAND flash memory 100 has been reached based on information about the usage status of the memory system 1, such as the total amount of written data in the NAND flash memory 100.

[0125] If the NAND flash memory 100 has not reached its usage limit (No in S0), the process flow ends.

[0126] <s1> If the NAND flash memory 100 has reached its usage limit (Yes in S0), recovery processing of the NAND flash memory 100 is started.

[0127] <s2> The NAND flash memory 100 is mounted on the recovery processing device 9. For example, in the recovery processing device 9, the control unit 99 causes the attachment / detachment processing unit 90 to remove the NAND flash memory 100 from the module substrate Sub of the memory system 1. The control unit 99 causes the attachment / detachment processing unit 90 to place the NAND flash memory 100 on the stage of the recovery processing device 9.

[0128] <s3> The cumulative number of annealing operations of the NAND flash memory 100 is confirmed. For example, in the recovery processing device 9, the control unit 99 instructs the operation execution unit 91 to read the annealing process information AN.

[0129] The operation execution unit 91 accesses the ROM block BLK of the NAND flash memory 100 and reads the annealing process information AN from the ROM block BLK. The read annealing process information AN is stored in the storage unit 98, for example.

[0130] The control unit 99 checks the cumulative number of annealing operations in the annealing process information AN stored in the storage unit 98.

[0131] <s4> The control unit 99 determines whether the read cumulative number of anneals is less than the upper limit of the cumulative number of anneals of the NAND flash memory 100 by the determination unit 94.

[0132] <s5> If the determining unit 94 determines that the cumulative number of annealing operations of the NAND flash memory 100 has reached the upper limit (No in S4), the control unit 99 recognizes that recovery of the NAND flash memory 100 is impossible. Based on this result, the control unit 99 discards the NAND flash memory 100 that is determined to be unrecoverable without performing the annealing process described below. In this case, the recovery process for the NAND flash memory 100 ends.

[0133] <s6> When the determining unit 94 determines that the cumulative number of annealing operations of the NAND flash memory 100 is less than the upper limit (Yes in S4), the control unit 99 recognizes that the NAND flash memory 100 can be recovered. This allows the control unit 99 to check the deterioration state of the NAND flash memory 100.

[0134] For example, the control unit 99 reads various types of information from the NAND flash memory 100 and executes various operations on the NAND flash memory 100. For example, the control unit 99 obtains the total amount of written data in the NAND flash memory 100 from the information read from the NAND flash memory 100. Alternatively, the control unit 99 calculates the bit error rate of data in the NAND flash memory 100 based on the writing and reading of data by the operation execution unit 91.

[0135] As an example for checking the deterioration state of the NAND flash memory 100, the control unit 99 can check the deterioration state of the NAND flash memory 100 based on the distribution width of the threshold voltage distribution of the memory cells obtained from the write sequence and read sequence for the NAND flash memory 100.

[0136] In this case, the control unit 99 uses a write sequence to write data of a certain pattern to the NAND flash memory 100. After a certain period T1 has elapsed since the data was written, the control unit 99 uses a read sequence to read the data of the certain pattern written to the NAND flash memory 100 from the NAND flash memory 100.

[0137] The control unit 99 calculates the distribution width of the threshold voltage distribution in a certain pattern of data based on the data read from the NAND flash memory 100. If the distribution width is greater than the criterion, the control unit 99 determines that the characteristics of the flash memory 100 have deteriorated (NAND For example, the calculated distribution width of the threshold voltage distribution for a certain pattern of data is stored in the storage unit 98.

[0138] In this way, the control unit 99 can estimate the degree of deterioration of the NAND flash memory 100 based on the calculated width of the threshold voltage distribution.

[0139] Furthermore, the calculation of the distribution width of the threshold voltage distribution for estimating the degree of deterioration may be performed for all threshold voltage distributions corresponding to the pattern of data that the memory cell MT can store, or may be performed for only one specific threshold voltage distribution, or may be performed for multiple specific threshold voltage distributions.

[0140] For example, the distribution width of the threshold voltage distribution can be calculated and estimated by screening the threshold voltages of memory cells MT within a certain voltage range set from two adjacent read voltages using well-known read operations, hard bit determination and soft bit determination, etc.

[0141] These processes can determine the relative degrees of deterioration of the films 421, 422, and 423 of the memory cell MT. Based on these results, the control unit 99 calculates the amount of deterioration of the memory cell MT.

[0142] <s7> The control unit 99 determines whether the deterioration of the memory cells MT is equal to or greater than a reference value based on the information on the deterioration state of the NAND flash memory 100 acquired by the determination unit 94.

[0143] <s8> If the determining unit 94 determines that the deterioration of the memory cell MT is less than the reference value (No in S7), the control unit 99 recognizes that the NAND flash memory 100 can be reused without the annealing process described below. In this case, the control unit 99 causes the attachment / detachment processing unit 90 to reattach the NAND flash memory 100 to the module substrate Sub of the memory system 1 without performing the annealing process.

[0144] <s9> If the determination unit 94 determines that the deterioration of the memory cell MT is equal to or greater than the reference value (Yes in S7), the control unit 99 saves various information and data in the NAND flash memory 100 to outside the NAND flash memory 100.

[0145] For example, in response to an instruction from the control unit 99, the operation execution unit 91 accesses a ROM block BLK of the NAND flash memory 100 and reads out ROM information INF including setting information, management information, and annealing process information AN. The operation execution unit 91 stores the various pieces of information AN and INF that have been read out in the storage unit 98. At this time, the operation execution unit 91 (or the control unit 99) may store information relating to the degradation state of the NAND flash memory 100 obtained in S6 in the storage unit 98 together with the various pieces of information AN and INF.

[0146] The operation execution unit 91 may read user data from a plurality of blocks BLK of the NAND flash memory 100 together with the various pieces of information AN and INF, and store the data in the storage unit 98.

[0147] <s10> After saving the information AN, INF and data, the control unit 99 erases the data in all memory cells MT in the NAND flash memory 100. In response to an instruction from the control unit 99, the operation execution unit 91 executes an erase sequence for all blocks BLK, including the ROM block, of the NAND flash memory 100. As a result, the data in all memory cells MT in the NAND flash memory 100 is erased.

[0148] <s11> The control unit 99 causes the annealing unit 92 to perform annealing processing to recover the deterioration (characteristics) of the memory cells MT.

[0149] The annealing processing unit 92 performs annealing under predetermined heating conditions on the NAND flash memory 100 that is the target of the recovery processing in response to an instruction from the control unit 99. At this time, other package devices P2 and P3 such as the memory controller 200 are separated from the NAND flash memory 100 and placed outside the recovery processing device 9. Therefore, the memory controller 200 and power supply ICs of the memory system 1 are not annealed.

[0150] For example, the annealing temperature is set to any temperature within the range of 120°C to 280°C. For example, the annealing time is set to any time within the range of 1 hour to 3 days (72 hours). The annealing time is set depending on the temperature used for the annealing. For example, if the annealing temperature is 250°C, the annealing time is set to a time within the range of 2 hours to 3 hours. If the annealing temperature is 125°C, the annealing time is set to a time within the range of 1 day to 2 days.

[0151] The recovery of the deteriorated memory cells MT can be improved and made more efficient by performing an annealing process on the memory cells MT in the data erased state. However, the annealing process may be performed on the NAND flash memory 100 including the memory cells MT in the data programmed state without erasing the data from the memory cells MT (S10).

[0152] <s12> The control unit 99 causes the test unit 93 to execute a test process on the NAND flash memory 100 that has been annealed.

[0153] In response to an instruction from the control unit 99, the operation execution unit 91 writes test data to a specific address in the NAND flash memory 100. The operation execution unit 91 reads the written test data from the NAND flash memory 100 after a certain period T1 has elapsed.

[0154] The test section 93 checks the threshold distribution of the memory cells MT based on the test data read results.

[0155] FIG. 11 is a diagram for explaining the relationship between the threshold voltage distribution of the memory cells MT and the state of the memory cells MT.

[0156] The horizontal axis of Figure 11 represents the voltage value of the threshold voltage of the memory cell. The vertical axis of Figure 11 represents the number of memory cells. Figure 11 shows a threshold voltage distribution D1 of certain data in memory cells MT at the start of use of memory system 1 (at the time of new shipment) after a certain period (T1) has elapsed since certain data was written, a threshold voltage distribution D2 of certain data in memory cells MT in a deteriorated state, and a threshold voltage distribution D3 of certain data in memory cells MT after a recovery process (annealing process).

[0157] 11, a threshold voltage distribution D1 for certain data obtained from a plurality of memory cells MT at the start of use has a distribution width W1 after a period T1 has elapsed. For example, the recovery processing device 9 stores the distribution width W1 of the threshold voltage distribution D1 for each data retention state as reference value data.

[0158] As the number of P / E cycles increases with use of memory system 1, the characteristics of memory cells MT deteriorate due to the occurrence of defects 999 in films 421, 422, and 423, as shown in FIG. 4 above. When a period T1 has elapsed since certain data was written to a memory cell MT in a deteriorated state, threshold voltage distribution D2 has a distribution width W2. Distribution width W2 is larger than distribution width W1 by 2×ΔV1. For example, value ΔV1 is the difference between the voltage value at one end of threshold voltage distribution D1 and the voltage value at one end of threshold voltage distribution D2 with respect to the central axis of threshold voltage distribution D1.

[0159] For example, the difference between the distribution width W1 of the threshold voltage distribution D1 of the memory cell MT at the start of use and the distribution width of a certain threshold distribution is treated as the deterioration amount of the memory cell MT. In this case, the deterioration amount of the memory cell MT forming the threshold voltage distribution D2 is 2×ΔV1. For example, the control unit 99 can calculate the degradation amount (2×ΔV1) of the memory cell MT in a degraded state based on the distribution width (for example, distribution width W1) of the threshold voltage distribution serving as the reference value through the process of S6.

[0160] When certain data is written to multiple memory cells MT after the annealing process in S11, the threshold voltage distribution D3 of the memory cells MT after the annealing process has a distribution width W3. The distribution width W3 is smaller than the distribution width W2. For example, the distribution width W3 is larger than the distribution width W1 by 2×ΔV2. The degradation amount of the memory cells after the annealing process obtained from the threshold voltage distribution D3 is 2×ΔV2. For example, the value ΔV2 is the difference between the voltage value at one end of the threshold voltage distribution D1 and the voltage value at one end of the threshold voltage distribution D3 with respect to the central axis of the threshold voltage distribution D1.

[0161] In this way, the deterioration amount (2×ΔV2) of the memory cell MT after the annealing process is smaller than the deterioration amount (2×ΔV1) of the memory cell MT in a deteriorated state.

[0162] Therefore, it is shown that the characteristics of the memory cell MT are restored by the annealing treatment under predetermined conditions.

[0163] <s13> The control unit 99 determines whether the result of the test process (amount of deterioration) satisfies an allowable value using the determination unit 94. In this way, the control unit 99 confirms whether the characteristics of the memory cell MT have been recovered by the annealing process.

[0164] If the determination unit 94 determines that the result of the test process does not satisfy the allowable value (No in S13), the control unit 99 executes the processes from S10 to S12. If it is determined that the characteristics of the memory cell MT have not been restored by the test process, the annealing process is executed again on the NAND flash memory 100 under the same or different heating conditions.

[0165] In addition, in order to confirm recovery of the characteristics of the NAND flash memory 100 in the test process, the test unit 93 and the judgment unit 94 may determine whether the distribution width of the threshold voltage distribution obtained from the test data read results is smaller than the distribution width of the threshold voltage distribution obtained in S6.

[0166] In this case, in S12, the test unit 93 compares the deterioration amount (2×ΔV2) of the memory cell MT after the annealing process with the deterioration amount (2×ΔV1) of the memory cell MT in a deteriorated state. The test unit 93 may compare the distribution width W3 with the distribution width W2, or may compare the deterioration amount (ΔV2) with the deterioration amount (ΔV1). In S13, if the deterioration amount (2×ΔV2) is smaller than the deterioration amount (2×ΔV1) (or if the distribution width W3 is smaller than the distribution width W2), the judgment unit 94 judges that the characteristics of the NAND flash memory 100 have been recovered by the annealing process.

[0167] The test unit 93 and the determination unit 94 may compare the amount of degradation (2×ΔV2) with a certain value to determine whether or not the characteristics of the NAND flash memory 100 have recovered. If the amount of degradation (2×ΔV2) is less than the certain value, it is determined that the characteristics of the NAND flash memory 100 have recovered. It is desirable that the certain value be calculated and set based on the amount of deterioration (2×ΔV1) or the distribution widths W1 and W2.

[0168] <s14> If the determination unit 94 determines that the result of the test process satisfies the allowable value (Yes in S13), the control unit 99 writes various information and data stored in the storage unit 98 to the NAND flash memory 100. In response to an instruction from the control unit 99, the operation execution unit 91 writes the ROM information INF in the storage unit 98 to a predetermined ROM block BLK.

[0169] At this time, the control unit 99 updates the cumulative number of annealing operations in the annealing process information AN. The operation execution unit 91 writes the ROM information INF including the updated annealing process information AN into one or more ROM blocks BLK.

[0170] The control unit 99 may also update parameters of the setting information to change the function of the NAND flash memory 100. For example, the control unit 99 changes parameters to change the number of bits that can be stored in one memory cell MT. If the memory cell MT before the annealing process is QLC, the control unit 99 rewrites the parameters of the ROM information INF so that the memory cell after the annealing process becomes TLC. This makes the number of bits that can be stored in the memory cell MT after the annealing process smaller than the number of bits that can be stored in the memory cell MT before the annealing process.

[0171] In this way, the ROM information INF such as the setting information and the annealing process information AN can be appropriately changed and written back to the NAND flash memory 100 after the annealing process.

[0172] <s15> The control unit 99 removes the NAND flash memory 100 from the recovery processing device 9 using the attachment / detachment processing unit 90. The control unit 99 mounts the NAND flash memory 100 in the memory system 1 using the attachment / detachment processing unit 90. For example, the attachment / detachment processing unit 90 attaches the NAND flash memory 100 to a module substrate Sub of the memory system 1.

[0173] The NAND flash memory 100 that is determined to be reused without annealing in the above-mentioned S8 is mounted in the memory system 1 by the mounting / removal processing unit 90.

[0174] <s16> After the NAND flash memory 100 is installed in the memory system 1, the control unit 99 ends the recovery process for the NAND flash memory 100.

[0175] The recovery process of the memory system 1 of this embodiment is completed through the above processing flow.

[0176] (4) Summary NAND flash memory writes and erases data to and from memory cells by utilizing the tunneling phenomenon of charges caused by the application of a relatively large voltage. Therefore, due to stress caused by the application of voltage and tunneling of charges, defects occur in the materials that make up the memory cell, which can cause electrons to be trapped or detrapped.

[0177] As the number of data write and erase cycles (P / E cycle number) increases, defects in memory cells increase. As a result, deterioration of memory cell characteristics becomes more pronounced. If the deterioration of memory cell characteristics exceeds the allowable range for use of the NAND flash memory, the NAND flash memory will be unable to perform normal operations, and the memory system including the NAND flash memory will become unusable.

[0178] In a typical memory system, not only the NAND flash memory that is no longer able to perform operations, but also the entire memory system, including the memory controller and electronic components that remain usable, is replaced with a new memory system.

[0179] The memory system 1 of this embodiment is configured so that the NAND flash memory 100 can be attached to and detached from the memory system 1. In this embodiment, when the characteristics of the NAND flash memory 100 deteriorate, an annealing process is performed on the removable NAND flash memory 100. As a result, according to this embodiment, the characteristics of the NAND flash memory 100 are restored.

[0180] Therefore, the memory system 1 of this embodiment can provide a memory system including a reused NAND flash memory 100.

[0181] In recent years, society has been called upon to make various contributions toward realizing a sustainable society, such as reducing carbon dioxide emissions from manufacturing. In this context, the manufacturing of semiconductor devices, such as NAND flash memory, consumes a large amount of electricity and resources. Furthermore, the manufacturing of semiconductor devices emits carbon dioxide, placing a burden on the natural environment.

[0182] The memory system 1 of this embodiment recovers the characteristics of the memory cells MT through annealing, thereby enabling the reuse of the NAND flash memory 100. This allows the memory system 1 of this embodiment to reduce resource consumption and carbon dioxide emissions for manufacturing new semiconductor chips such as the NAND flash memory 100. In this way, according to this embodiment, it is possible to provide a memory system with a small environmental impact.

[0183] As described above, the memory system 1 of this embodiment can reduce costs.

[0184] (5) Application examples An application example of the memory system 1 of this embodiment will be described with reference to FIG.

[0185] FIG. 12 is a schematic diagram for explaining an application example of the memory system 1 of this embodiment. The memory system 1 of this embodiment is provided to the market and users on a subscription basis.

[0186] The information processing system 900 includes the memory system 1 of this embodiment and a host device 5. The information processing system 900 is a data center, a server, industrial equipment, a personal computer, a home appliance, a game device, or the like.

[0187] A user of an information processing system 900 pays a usage fee 901 periodically (or temporarily) to a storage provision system 990 that provides the memory system 1 in order to use the memory system 1 that includes a NAND flash memory 100 such as an SSD.

[0188] The storage provision system 990 receives a usage fee 901 from a user. The storage provision system 990 provides the memory system 1 of this embodiment to the user in accordance with the usage fee 901 received.

[0189] In response to a request from a user, the storage provision system 990 may write predetermined data 902 to the memory system 1 before providing the memory system 1. In this way, the memory system 1 is provided to the user with the predetermined data 902 stored in the memory system 1.

[0190] For example, the data 902 written in advance in the memory system 1 by the storage provision system 990 is one or more data selected from video data, image data, text data, audio data, software (application), and the like. The storage provision system 990 collects the memory system 1 based on a request from the user, the number of days that have passed since the memory system 1 was provided, and the like.

[0191] The storage provision system 990 executes the processing flow of Fig. 10 described above for the memory system 1. The storage provision system 990 appropriately executes an annealing process for recovering the memory cells MT for the NAND flash memory 100 of the recovered memory system 1 using the recovery processing device 9.

[0192] The storage provider system 990 reuses the annealed NAND flash memory 100 in the memory system 1.

[0193] The storage provision system 990 provides a memory system 1 including a reused NAND flash memory 100 to a user.

[0194] The user connects the provided memory system 1 to the host device 5. In this way, the user uses the information processing system 900 including the memory system 1 of this embodiment.

[0195] Furthermore, when providing a memory system 1 including a reused NAND flash memory 100 to the user from whom the memory system 1 was collected, a memory system 1 different from the memory system 1 at the time of collection may be provided to the user who has signed a subscription contract.

[0196] In this way, the memory system 1 of this embodiment can be applied to the market with a consumption cycle that places a small burden on the environment.

[0197] (6) Other In the memory system 1 of this embodiment, a NAND flash memory is exemplified as a memory device used in the memory system 1. However, the memory device used in the memory system 1 of this embodiment may be a memory device other than a NAND flash memory as long as the characteristics of the memory device can be restored by annealing and the memory device can be reused. For example, the memory device may be a NOR flash memory.

[0198] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0199] 1: memory system, 9: recovery processing device, 100: NAND flash memory, MT: memory cell, Sub: module substrate, 80: connector.

Claims

1. a substrate including a first portion including a first connector and a second portion including a second connector configured to be detachable from the first connector; a memory controller disposed on the first portion; a memory device disposed on the second portion and communicating with the memory controller via the first and second connectors; an electronic component provided on the second portion; Equipped with The heat resistance of the electronic component is higher than the heat resistance of the memory controller. Memory system.

2. The memory device is a NAND flash memory.

10. The memory system of claim 1.

3. A power supply system IC provided on the first portion. Further comprising: the power supply system IC supplies a voltage to the memory device via the first and second connectors; 3. The memory system according to claim 1.

4. The heat resistance of the electronic component is higher than the heat resistance of the power supply system IC.

4. The memory system of claim 3.

5. Removing the memory device from a connector on a board of the memory system; reading first information from the memory device; subjecting the memory device to an annealing treatment; writing the first information to the memory device; attaching the memory device to the connector; A processing method for a memory system comprising:

6. The memory device is a NAND flash memory.

6. The method of claim 5, wherein the memory system includes:

7. Reading the first information from the memory device is performed before performing the annealing treatment on the memory device; writing the first information to the memory device after performing the annealing process on the memory device; 7. A processing method for a memory system according to claim 5 or 6.

8. the first information includes setting information of the memory device and information about the annealing treatment; A method for processing a memory system according to any one of claims 5 to 7.

9. the information regarding the annealing process includes the number of times the annealing process has been performed; 9. The method of claim 8, wherein the memory system includes:

10. The annealing temperature is 125° C. or more and 250° C. or less, and the annealing time is 1 hour or more and 3 days or less. A method for processing a memory system according to any one of claims 5 to 9.

11. After the annealing process, changing the number of bits that can be stored in a memory cell of the memory device from k (where k is a natural number equal to or greater than 2) to k-1 or less; 11. The method of claim 5, further comprising:

12. writing user data to the memory device after the annealing process; providing the memory system to an information and communication system after attaching the memory device to the connector; 12. The method of claim 5, further comprising:

13. The method of claim 12, wherein the user data is data read from the memory device before the annealing process.

13. The method of claim 12, wherein the memory system includes:

14. a first distribution width of a threshold voltage distribution for a first data of the memory device after the annealing process is smaller than a second distribution width of a threshold voltage distribution for the first data of the memory device before the annealing process; A method for processing a memory system according to any one of claims 5 to 13.

Images