Memory system and method

Abstract

To provide a memory system capable of reducing a processing cost of an address translation table.SOLUTION: According to an embodiment, a memory system comprises a controller controlling a non-volatile memory. The controller manages an address translation table having a hierarchical structure including a first node holding a correspondence between logical addresses and physical addresses and a second node holding information showing whether logical addresses consecutive by a controlled first node are associated with consecutive physical addresses. When update information in which logical addresses and physical addresses are consecutive is input to a queue with update information of the address translation table accumulated in the queue, the controller accumulates both update information in the queue. When a target of the accumulated update information reaches a boundary of the second node, the controller outputs the update information from the queue and updates the address translation table including update of the first node or the second node.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to memory systems and methods. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread. One such memory system is a solid-state drive (SSD) equipped with a NAND flash memory. SSDs are widely used as storage devices for information processing devices such as servers and personal computers.

[0003] An SSD performs a process of converting a logical address, which indicates a logical location in nonvolatile memory and is used by a host such as an information processing device to specify a location in nonvolatile memory, into a physical address, which indicates a physical location in nonvolatile memory. The process of converting a logical address to a physical address, or converting a physical address to a logical address, is also called address resolution.

[0004] For address resolution, SSDs use an address translation table, also known as an L2P (Logical Block Address [LBA] to Physical Block Address [PBA]) table, to manage the correspondence between logical addresses and physical addresses. It is desirable for SSDs to reduce the overhead of processing the L2P table. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0026548 [Patent Document 2] Japanese Patent Publication No. 2020-113187 [Patent Document 3] U.S. Patent No. 9,946,462 Summary of the Invention [Problem to be solved by the invention]

[0006] One embodiment of the present invention provides a memory system and method that can reduce the processing cost of an address translation table. [Means for solving the problem]

[0007] According to an embodiment, a memory system is capable of communicating with a host and includes a nonvolatile memory and a controller. The controller controls the nonvolatile memory. The controller manages an address translation table that maintains a correspondence between logical addresses, which indicate logical locations by the host, and physical addresses, which indicate physical locations in the nonvolatile memory. The address translation table has a hierarchical structure including at least a first node that maintains a one-to-one correspondence between logical addresses and physical addresses, and a second node higher than the first node that corresponds to a first number of first nodes and maintains information indicating whether consecutive logical addresses and consecutive physical addresses are associated with each other for the first number of first nodes. The controller has a queue that accumulates update information for the address translation table, including a logical address and a physical address that indicate a start position for writing data to the nonvolatile memory, and the length of data to be written to the nonvolatile memory. When second update information including a first logical address indicating a data write end position obtained from the first update information accumulated in the queue and a second logical address and a second physical address corresponding to the second logical address, at least one of which is not consecutive with the first logical address and the physical address corresponding to the first logical address, is input to the queue, the controller outputs the first update information accumulated in the queue from the queue and updates the first node based on the output first update information. When third update information including a third logical address and a third physical address consecutive with the first logical address and the first physical address, the controller accumulates the input third update information in the queue along with the first update information accumulated in the queue. When the sum of the length of the data included in the first update information and the length of the data included in the third update information reaches a length that extends from the data write start position included in the first update information accumulated in the queue to the boundary of the second node, the controller outputs fourth update information generated from the first update information and the third update information accumulated in the queue from the queue and updates the first node or the second node based on the output fourth update information. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] 3A and 3B are diagrams for explaining the structure of an L2P table used in the memory system of the embodiment and management of the L2P table. [Figure 3] 5A and 5B are diagrams for explaining a first example of the operation of the continuity determination module of the memory system according to the embodiment. [Figure 4] 10A and 10B are diagrams for explaining a second example of the operation of the continuity determination module of the memory system according to the embodiment. [Figure 5] 10 is a flowchart showing an operation procedure of a continuity determination module of the memory system according to the embodiment. [Figure 6] 5 is a diagram for explaining a modified example of the operation (second example) of the continuity determination module shown in FIG. 4; FIG. [Figure 7] 5 is a diagram for explaining another modified example of the operation (second example) of the continuity determination module shown in FIG. 4; FIG. [Figure 8] 10A and 10B are diagrams for explaining division of write address information that can be performed by a continuity determination module of the memory system according to the embodiment. [Figure 9] 10A and 10B are diagrams for explaining an example in which a continuity determination module of the memory system according to the embodiment handles data overwriting. [Figure 10] FIG. 1 is a diagram showing an example of a configuration in which a memory system according to an embodiment has a plurality of continuity determination modules. [Figure 11] FIG. 2 is a diagram showing an example of the configuration of a nonvolatile memory included in the memory system of the embodiment. [Figure 12] FIG. 2 is a diagram showing an example of the configuration of a NAND chip included in a nonvolatile memory of the memory system of the embodiment. [Figure 13] FIG. 2 is a diagram showing an example of the configuration of a logical block generated in the memory system according to the embodiment. [Figure 14] 10A and 10B are diagrams showing an example of transition of the state of a logical block generated in the memory system of the embodiment; [Figure 15] 11 is a diagram for explaining an example of operation in a state in which logical blocks of the plurality of continuity determination modules shown in FIG. 10 are assigned. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Fig. 1 is a diagram showing an example of the configuration of a memory system 1 according to an embodiment. Fig. 1 also shows an example of the configuration of an information processing system including the memory system 1 and a host 2 connected to the memory system 1. The host 2 is an information processing device such as a server or a personal computer.

[0010] The memory system 1 includes a controller 10 and a nonvolatile memory 20. The nonvolatile memory 20 is a NAND flash memory (NAND). Here, the memory system 1 is an SSD as an example.

[0011] The controller 10 controls the nonvolatile memory 20. The controller 10 is, for example, NVM Express. TM (NVMe TM The controller 10 is capable of communicating with the host 2 using a protocol conforming to the IEEE 802.11a specification. The controller 10 controls the writing of data to the nonvolatile memory 20 and the reading of data from the nonvolatile memory 20 in response to commands from the host 2. Even when not receiving commands from the host 2, the controller 10 may also independently control the writing of data to the nonvolatile memory 20 and the reading of data from the nonvolatile memory 20, for example, to maintain the appropriate state of the nonvolatile memory 20 or the state of the data stored in the nonvolatile memory 20. The controller 10 is configured, for example, as an SoC (System-On-Chip).

[0012] The controller 10 includes a NAND management module 11, a continuity determination module 12, and an L2P management module 13.

[0013] The NAND management module 11 manages the storage area of ​​the nonvolatile memory 20, including mapping the physical address space to the logical address space. When the host 2 issues, for example, a write command to the memory system 1, it specifies a data write location using a logical address indicating a logical location in the nonvolatile memory 20. The logical address is, for example, an LBA. The write command also specifies the length of the data to be written. The NAND management module 11 controls the correspondence between the location in the nonvolatile memory 20 where the data is to be written, that is, the physical address indicating the physical location in the nonvolatile memory 20, and the logical address specified by the host 2. Specifically, the NAND management module 11 outputs write address information for updating an address translation table (an L2P table 131, described later) that maintains the correspondence between logical addresses and physical addresses to the latest state. The physical address is, for example, a PBA.

[0014] The write address information includes a logical address (LBA) specified by the host 2 as the data write destination, a physical address (PBA) indicating the physical location in the nonvolatile memory 20 where the data is actually written, and the length of the data. The length of the data is expressed by the number of LBAs or PBAs.

[0015] The address conversion table is managed by the L2P management module 13 as an L2P table 131. Therefore, the write address information output by the NAND management module 11 is information that should originally be supplied to the L2P management module 13. In the memory system 1 of the embodiment, a continuity determination module 12 is interposed between the NAND management module 11 and the L2P management module 13. The continuity determination module 12 has a queue 121 for storing the write address information output from the NAND management module 11. In order to reduce the processing cost of the L2P table 131, the continuity determination module 12 stores the write address information output from the NAND management module 11 in the queue 121, processes it, and supplies the processed write address information to the L2P management module 13. In other words, the memory system 1 of the embodiment can reduce the processing cost of the L2P table 131. This point will be described in detail below.

[0016] First, the structure of the L2P table 131 and the management of the L2P table 131 by the L2P management module 13 will be described with reference to FIG.

[0017] In the memory system 1 of the embodiment, it is assumed that the L2P table 131 has a hierarchical structure, such as a tree structure. The L2P management module 13 stores information indicating a one-to-one correspondence between LBAs and PBAs in a first node at the lowest level in the hierarchical structure of the L2P table 131. FIG. 2A shows an example in which information indicating that PBA "32" is associated with LBA "16" is held in the first node. The L2P management module 13 basically updates the first node based on write address information.

[0018] Furthermore, the L2P management module 13 stores information indicating whether a predetermined number of consecutive PBAs are associated with a predetermined number of consecutive LBAs in a second node higher than the first node in the hierarchical structure of the L2P table 131. Fig. 2(A) shows an example in which a second node is provided for eight first nodes.

[0019] In the example shown in Figure 2(A), eight first nodes subordinate to a certain second node hold information indicating that consecutive PBAs ("32-39") correspond to consecutive LBAs ("16-23"). Therefore, this second node holds information indicating that eight consecutive PBAs correspond to eight consecutive LBAs, together with the first PBA "32".

[0020] Furthermore, for example, if a third node is further provided above a second node, if information indicating that eight consecutive PBAs correspond to eight consecutive LBAs is held in all of a predetermined number of second nodes subordinate to a certain third node, the L2P management module 13 stores information indicating that (predetermined number x 8) consecutive PBAs correspond to (predetermined number x 8) consecutive LBAs in this third node together with the first PBA.

[0021] For example, when a read command is issued from the host 2, the controller 10 acquires the PBA corresponding to the LBA specified in the read command by referring to the L2P table 131. At this time, if information indicating that consecutive PBAs are associated with the third node or second node corresponding to the specified LBA is held, the controller 10 can acquire the target PBA without tracing back to the first node at the bottom.

[0022] Furthermore, if a PBA associated with a certain LBA can be obtained at a third node, nodes lower than the third node are unnecessary. Similarly, if a PBA associated with a certain LBA can be obtained at a second node, nodes lower than the second node are unnecessary. The L2P management module 13 deletes unnecessary nodes as appropriate to reduce the total size of the L2P table 131. FIG. 2B shows an example in which the L2P management module 13 stores information indicating that eight consecutive PBAs, starting from PBA "32," are associated with a second node corresponding to LBA "16-23," and deletes eight first nodes subordinate to this second node. The deletion of terminal nodes, as shown in FIG. 2B, is also referred to as "pruning." Note that terminal nodes are not limited to the lowest-level node (first node).

[0023] Next, the operation of the continuity determination module 12 for improving the efficiency of processing of the L2P table 131 by the L2P management module 13, including this "pruning", will be described.

[0024] FIG. 3 is a diagram for explaining a first example of the operation of the continuity determination module 12. In FIG. 3 shows an example in which write address information (a1) including LBA "128", PBA "32", and Length "4" is input to the queue 121. Hereinafter, write address information including these pieces of information will be expressed as write address information "128, 32, 4". The queue 121 is, for example, a data storage unit of a first-in, first-out (FIFO) type.

[0025] 3 also shows an example in which write address information "128,32,4" (a1) is stored in the queue 121 and write address information "234,10,1" (a2) is newly input to the queue 121. The continuity determination module 12 determines whether the write address information "128,32,4" (a1) stored in the queue 121 and the write address information "234,10,1" (a2) newly input to the queue 121 are consecutive in both LBA and PBA.

[0026] Specifically, the continuity determination module 12 first calculates the next expected LBA and PBA from the write address information "128,32,4" (a1). That is, it calculates the LBA and PBA following the storage area indicated by the write address information accumulated in the queue 121. Here, the continuity determination module 12 calculates LBA "132 (=128+4)" and PBA "36 (=32+4)". Next, the continuity determination module 12 compares the calculated LBA and PBA with the LBA and PBA of the write address information "234,10,1" (a2) to determine whether both the LBA and PBA match.

[0027] In the first example shown in Fig. 3, neither the LBA nor the PBA matches. If either the LBA or the PBA matches, that is, if the LBA and the PBA are not consecutive, the continuity determination module 12 outputs the write address information "128,32,4" (a1) from the queue 121. In other words, the write address information output from the NAND management module 11 is output as is from the continuity determination module 12 to the L2P management module 13. The queue 121 transitions to a state in which the write address information "234,10,1" (a2) is stored.

[0028] Upon receiving this write address information "128,32,4" (a1), the L2P management module 13 updates the L2P table 131 to maintain the correspondence between LBAs "128-131" and PBAs "32-35" for the four first nodes at the lowest level.

[0029] Furthermore, the continuity determination module 12 then calculates the next expected LBA "235 (=234+1)" and PBA "11 (=10+1)" from the write address information "234,10,1" (a2), and waits for new write address information to be input to the queue 121. Note that the calculation of the next expected LBA and PBA may be performed when new write address information is input to the queue 121.

[0030] FIG. 4 is a diagram for explaining a second example of the operation of the continuity determination module 12. In FIG. 4 shows an example in which write address information "128,32,4" (b1) is first input to the queue 121. Also, FIG. 4 shows an example in which write address information "132,36,8" (b2) is newly input to the queue 121 while the write address information "128,32,4" (b1) is stored in the queue 121. As explained in the first example above, the continuity determination module 12 calculates the next expected LBA "132" and PBA "36" from the write address information "128,32,4" (b1), and compares the calculated LBA and PBA with the LBA and PBA of the write address information "132,36,8" (b2) to determine whether both the LBA and PBA match.

[0031] In the second example shown in Figure 4, both the LBA and PBA match. If both the LBA and PBA match, that is, if the LBA and PBA are consecutive, the continuity determination module 12 accumulates the newly input write address information "132,36,8" (b2) in addition to the write address information "128,32,4" (b1) in the queue 121. At this time, the next expected LBA and PBA are LBA "140 (=132+8)" and PBA "44 (=36+8)".

[0032] 4, subsequently, write address information "140,44,4" (b3), in which both the LBA and PBA are consecutive, is newly input to the queue 121. The continuity determination module 12 accumulates the write address information "140,44,4" (b3) in the queue 121 in addition to the write address information "128,32,4" (b1) and the write address information "132,36,8" (b2). At this time, the next expected LBA and PBA are LBA "144 (=140+4)" and PBA "48 (=44+4)".

[0033] 4, write address information "144,48,16" (b4), in which both the LBA and PBA are consecutive, is newly input to the queue 121. The continuity determination module 12 accumulates the write address information "144,48,16" (b4) in the queue 121 in addition to the write address information "128,32,4" (b1), the write address information "132,36,8" (b2), and the write address information "140,44,4" (b3).

[0034] Here, it is assumed that the total length included in the write address information (b1 to b4) accumulated in the queue 121 has reached the corresponding length of the second node above the first node (32 (=4+8+4+16)). Note that while FIG. 2 shows an example in which eight first nodes exist under the second node, FIG. 4 assumes that 32 first nodes exist under the second node. The continuity determination module 12 processes the write address information to combine the write address information (b1 to b4) into write address information "128, 32, 32" (b5), and outputs the write address information "128, 32, 32" (b5) from the queue 121 to the L2P management module 13.

[0035] Upon receiving this write address information "128,32,32" (b5), the L2P management module 13 stores the first PBA "32" for the second node above the 32 first nodes in the lowest layer, stores information indicating that 32 PBAs are consecutive from the PBA "32", and performs "pruning" to delete the eight first nodes subordinate to this second node.

[0036] If the continuity determination module 12 does not exist and the write address information (b1 to b4) output from the NAND management module 11 is individually supplied to the L2P table 131, the L2P table 131 will update itself four times based on the write address information (b1 to b4). Also, if the write address information (b4) is supplied alone, whether or not "pruning" is performed when updating the L2P table 131 based on this write address information (b4) depends on the specifications of the L2P management module 13. When "pruning" is performed, it is necessary to scan whether or not the PBAs are contiguous from the beginning of the 32 first nodes managed by the second node.

[0037] In contrast, in the memory system 1 of the embodiment, the continuity determination module 12 interposed between the NAND management module 11 and the L2P management module 13 processes the write address information as described above, so that the L2P management module 13 can update the L2P table 131 with just one "pruning", thereby reducing the processing cost of the L2P table 131.

[0038] FIG. 5 is a flowchart showing the operation procedure of the continuity determination module 12. The continuity determination module 12 determines whether or not new write address information has been input to the queue 121 (S101). If no new write address information has been input (S101: NO), the continuity determination module 12 waits for input of write address information.

[0039] If new write address information has been input (S101: YES), the continuity determination module 12 determines whether or not the write address information has already been stored in the queue 121 (S102). If the write address information has not been stored (S102: NO), the continuity determination module 12 waits for the input of the next write address information.

[0040] If the write address information has already been stored (S102: YES), the continuity determination module 12 determines whether the LBA and PBA of the newly input write address information in the queue 121 are consecutive with the LBA and PBA of the most recent address information among the write address information already stored in the queue 121 (S103). If they are not consecutive (S103: NO), the continuity determination module 12 outputs the write address information already stored in the queue 121 (S104). At this time, the queue 121 stores only the newly input write address information.

[0041] If the LBAs and PBAs are consecutive (S103: YES), the continuity determination module 12 determines whether the length of consecutive LBAs and PBAs from the write address information initially stored in the queue 121 has reached a certain length (S105). If the certain length has not been reached (S105: NO), the continuity determination module 12 continues to wait for input of the next write address information. If the certain length has been reached (S105: YES), the continuity determination module 12 outputs the write address information newly input to the queue 121 and the write address information already stored in the queue 121 together (S106). After outputting the write address information, the continuity determination module 12 continues to wait for input of write address information.

[0042] In this way, the continuity determination module 12 accumulates the write address information in the queue 121 while the LBAs and PBAs are consecutive, and when the length reaches a length that allows for "pruning," it outputs the accumulated write address information as a single piece. By processing the write address information in this way, the memory system 1 of the embodiment can reduce the processing cost of the L2P table 131.

[0043] 4 shows an example in which write address information (b1 to b4) with consecutive LBAs and PBAs is stored in the queue 121. As shown in FIG. 6, the continuity determination module 12 may combine two pieces of write address information into one piece each time write address information already stored in the queue 121 and new write address information with consecutive LBAs and PBAs are input to the queue 121.

[0044] Specifically, when write address information "128,32,4" (b1) is input to the queue 121 and then write address information "132,36,8" (b2) with consecutive LBAs and PBAs is input, the continuity determination module 12 combines these two as write address information "128,32,12" (b11). Next, when write address information "140,44,4" (b3) is input, the continuity determination module 12 combines the write address information "128,32,12" (b11) and the write address information "140,44,4" (b3) as write address information "128,32,16" (b12). Furthermore, when the write address information "144,48,16" (b4) is input, the continuity determination module 12 combines the write address information "128,32,16" (b12) and the write address information "144,48,16" (b4) into write address information "128,32,32" (b13). This write address information "128,32,32" (b13) corresponds to the write address information "128,32,32" (b5) in FIG. 4. The continuity determination module 12 outputs this write address information "128,32,32" from the queue 121 to the L2P management module 13.

[0045] In this case, the number of write address information pieces stored in the queue 121 can be reduced, and therefore the cost of the memory system 1 can be reduced.

[0046] Furthermore, depending on the embodiment of the memory system 1, there may be cases where the write command of the host 2 cannot be completed until the update of the L2P table 131 is completed. In this case, as shown in FIG. 7 , when new write address information whose LBA and PBA are consecutive to write address information already stored in the queue 121 is input to the queue 121, the continuity determination module 12 may combine the two pieces of write address information into one piece and output the newly input write address information from the queue 121 to the L2P management module 13.

[0047] Specifically, when the write address information "128,32,4" (b1) is first input to the queue 121, the continuity determination module 12 accumulates this write address information "128,32,4" (b1) in the queue 121 and also outputs it to the L2P management module 13.

[0048] Next, when write address information "132,36,8" (b2) in which the LBA and PBA are consecutive is input, the continuity determination module 12 combines these two as write address information "128,32,12" (b11) and outputs the write address information "132,36,8" (b2) to the L2P management module 13.

[0049] Similarly, when the write address information "140,44,4" (b3) is input, the continuity determination module 12 combines the write address information "128,32,12" (b11) and the write address information "140,44,4" (b3) into the write address information "128,32,16" (b12), and outputs the write address information "140,44,4" (b3) to the L2P management module 13.

[0050] When the write address information "144,48,16" (b4) is input, the continuity determination module 12 combines the write address information "128,32,16" (b12) and the write address information "144,48,16" (b4) into write address information "128,32,32" (b13). This write address information "128,32,32" (b13) corresponds to the write address information "128,32,32" (b5) in FIG. 4. The continuity determination module 12 outputs this write address information "128,32,32" (b5) from the queue 121 to the L2P management module 13.

[0051] Since the write address information "128,32,32" (b5) includes the write address information "144,48,16" (b4), the continuity determination module 12 does not need to output the write address information "144,48,16" (b4) to the L2P management module 13. Also, since the write address information "128,32,32" (b5) is write address information of length (32) managed by the second node, all information of the first node managed by the second node is discarded, and information that there are 32 consecutive PBAs is stored in the second node, thereby completing "pruning." If b1 to b4 are each output, the L2P management module 13 needs to confirm at b4 that the PBAs of all first nodes managed by the second node are consecutive.

[0052] Note that, here, as an example of outputting newly input write address information to the L2P management module 13 every time the newly input write address information is input to the queue 121, an example has been shown in which the newly input write address information is output while being aggregated with the write address information accumulated in the queue 121. However, the continuity determination module 12 may be configured to output the newly input write address information while additionally accumulating the newly input write address information in the queue 121, for example, as shown in FIG.

[0053] Furthermore, it is preferable that the continuity determination module 12 divides the write address information input to the queue 121 in accordance with the boundary of the LBA management unit of a second node higher than the first node at the lowest level in the hierarchical structure of the L2P table 131. For example, as shown in FIG. 8A, it is assumed that a certain second node corresponds to LBA "16-23" and a subsequent second node corresponds to LBA "24-31". Under this assumption, it is assumed that write address information "20,36,8" (c1) is input to the queue 121, as shown in FIG. 8B. This write address information "20,36,8" (c1) is information relating to LBA "20-27", and therefore straddles the boundary between the two second nodes shown in FIG. 7A.

[0054] In this case, the continuity determination module 12 divides the write address information "20,36,8" (c1) into write address information "20,36,4" (c11) and write address information "20,40,4" (c12) in accordance with the boundary of the second node. Of the two pieces of write address information after division, the continuity determination module 12 outputs the front write address information "20,36,4" (c11) from the queue 121 to the L2P management module 13. The continuity determination module 12 accumulates only the rear write address information "20,40,4" (c12) in the queue 121.

[0055] When the write address information "20,36,8" (c1) is input to the queue 121, if the write address information is accumulated in the queue 121 and both the LBA and PBA of these two pieces of write address information are consecutive, the continuity determination module 12 combines the write address information accumulated in the queue 121 and the divided write address information (c11) into one piece of write address information and outputs it. If at least one of the LBA and PBA of these two pieces of write address information is not consecutive, the continuity determination module 12 separately outputs the write address information accumulated in the queue 121 and the divided write address information (c11).

[0056] By basing the hierarchical structure boundary of the L2P table 131, efficient queuing of write address information that is suitable for "pruning" without waste is realized.

[0057] However, when write address information including consecutive LBAs and PBAs of a certain length is stored in the queue 121, there may be a case where write address information indicating that a portion of the LBAs has been overwritten is input to the queue 121. In this case, the LBAs and PBAs of the write address information stored in the queue 121 are not consecutive to the LBAs and PBAs of the write address information newly input to the queue 121. Therefore, normally, the continuity determination module 12 first outputs the write address information stored in the queue 121 from the queue 121 to the L2P management module 13. Thereafter, at a certain timing, the continuity determination module 12 outputs the write address information newly input to the queue 121 from the queue 121 to the L2P management module 13.

[0058] However, in this case, the L2P management module 13 that receives this write address information will have to update the LBA of the overwritten portion twice, resulting in unnecessary processing costs for the L2P table 131.

[0059] Therefore, in such a case, the continuity determination module 12 does not output the overwritten portion of the queue 121 to the L2P management module 13, as shown in Figure 9, thereby preventing unnecessary processing costs of the L2P table 131 from occurring in the L2P management module 13.

[0060] 6, when the write address information "128,32,16" (b12) has accumulated in the queue 121, it is assumed that the write address information "132,48,4" (d1) is newly input to the queue 121. The write address information "132,48,4" (d1) indicates that data has been written to update the data in PBA "36-39(36,4)" to the data in PBA "48-51(48,4)" for LBA "132-135(132,4)" within LBA "128-148" indicated by the write address information "128,32,16" (b12).

[0061] In this case, if the write address information "128,32,16" (b12) and the write address information "132,48,4" (d1) are output separately because their LBAs and PBAs are not consecutive, the L2P management module 13 updates the correspondence of LBA "132-135(132,4)" to PBA [36-39(36,4)], and then updates the correspondence again to PBA "48-51(48,4)". Since the double update of LBA "132-135(132,4)" is wasteful, the continuity determination module 12 processes the write entry b12 in the queue 121 before outputting it to avoid this waste.

[0062] Specifically, the continuity determination module 12 first divides the write address information "128,32,16" (b12) stored in the queue 121 into write address information "128,32,4" (b121) and write address information "136,40,8" (b122) so as to remove the overlapping portion with the write address information "132,48,4" (d1), and outputs the information from the queue 121 to the L2P management module 13. Retained.

[0063] In this case, the L2P management module 13 updates the PBAs for LBAs "128-31" and "136-142." This eliminates the need for double updating of LBAs "132-135 (132,4)," and reduces the processing cost for the L2P table 131.

[0064] 1 shows only one continuity determination module 12, but this is not limiting, and multiple continuity determination modules 12 (12A, 12B, 12C) may be provided as shown in Fig. 10. In this case, it is preferable to provide a control module 14 for centrally controlling the multiple continuity determination modules 12.

[0065] The control module 14 performs control to assign the continuity determination module 12 to a logical block (super block) (to be described later) that is in a predetermined state (open state (to be described later)). Here, the logical block will be described.

[0066] FIG. 11 is a diagram showing an example of the configuration of the nonvolatile memory 20. As shown in FIG. As shown in FIG. 11, the nonvolatile memory 20 includes a plurality of NAND chips 21. Each of the plurality of NAND chips 21 includes a memory cell array including a plurality of memory cells capable of storing data in a nonvolatile manner, and a peripheral circuit for controlling the memory cell array. Each NAND chip 21 can operate independently. That is, the NAND chips 21 function as a parallel operation unit. The same number of NAND chips 21 (e.g., four chips per channel) are connected to each of a plurality of channels (e.g., 18 channels Ch.0 to Ch.17). Each of the channels Ch.0 to Ch.17 includes a communication line (memory bus) through which the controller 10 communicates with each NAND chip 21.

[0067] For example, 18 NAND chips 21 connected in parallel to each of channels Ch.0 to Ch.17, i.e., NAND chips #0 to #17, NAND chips #18 to #35, NAND chips #36 to #53, and NAND chips #54 to #71, may each be organized as a bank (Bank0 to Bank3). A bank functions as a unit for operating multiple NAND chips 21 in parallel by bank interleaving. In the configuration example shown in FIG. 11, a maximum of 72 NAND chips 21 can be operated in parallel by bank interleaving using 18 channels and four banks.

[0068] FIG. 12 is a diagram showing an example of the configuration of the NAND chip 21. As shown in FIG. As shown in FIG. 12, a NAND chip 21 includes a plurality of physical blocks 22, each including a plurality of pages 23. Data writing and reading are processed in units of pages 23. On the other hand, data erasure is processed in units of physical blocks 22. Data cannot be overwritten on a page 23 to which data has already been written. Therefore, data is updated by invalidating the original data on a page 23 and writing new data to another page 23. The process of reusing pages 23 in which invalidated data remains in a physical block 22 is called garbage collection or the like.

[0069] FIG. 13 is a diagram showing an example of the configuration of a logical block (superblock) generated by the NAND management module 11. As shown in FIG.

[0070] The NAND management module 11 generates a plurality of logical blocks 24, each including a plurality of physical blocks 22. In the memory system 1 of the embodiment, data is erased in units of these logical blocks 24. Specifically, the data erased in units of the physical blocks 22 is executed collectively for one logical block 24.

[0071] The NAND management module 11, for example, selects one physical block 22 from each of the NAND chips (#0 to #71) 21 and manages a logical block 24 including a total of 72 physical blocks 22. The 18 channels and four bank interleaving allow the NAND chips (#0 to #71) 21 to operate in parallel, so that data can be written to one logical block 24 in units of 72 pages 23. The NAND management module 11 may also manage the logical block 24 by selecting one physical block 22 from fewer than 72 NAND chips 21 (for example, 36 or 18). It is preferable that the combination of NAND chips 21 related to one logical block 24 be made up of NAND chips from different channels and banks. When each NAND chip 21 has a multi-plane (for example, two-plane) configuration, the NAND management module 11 may, for example, select one physical block 22 from each of 144 planes corresponding to the NAND chips (#0 to #71) 21, and generate a logical block 24 including a total of 144 physical blocks 22. The NAND management module 11 manages the PBAs of the nonvolatile memory 20 so that the PBAs in the logical block 24 generated from the multiple physical blocks 22 collected from the multiple NAND chips 21 are contiguous.

[0072] FIG. 14 is a diagram showing an example of the transition of the state of a logical block (superblock) 24 generated by the NAND management module 11.

[0073] A logical block 24 can be in two states: a used state (a1) and an unused state (a2). Used logical blocks 24 are further broadly classified into a state in which data is to be written (open state) and a state in which data writing has been completed (closed state). The number of logical blocks 24 that can be simultaneously open is predetermined as a specification of the memory system 1. Here, the three hatched logical blocks 24 indicated by reference symbol e11 are in the open state. The other logical blocks 24 not hatched, indicated by reference symbol e12, are in the closed state. For example, when multiple application programs are running on the host 2, if the logical blocks 24 to which data is to be written are separated for each application program, response performance can be improved compared to when data from multiple application programs are mixed in a single logical block 24.

[0074] An unused logical block 24 is also called a free block. When an open logical block 24 is filled with write data, the NAND management module 11 transitions the logical block 24 from the open state to the closed state. Next, the NAND management module 11 selects one unused logical block 24 and transitions the logical block 24 from the unused state to the open state.

[0075] As described above, data is updated in the nonvolatile memory 20 by invalidating the original data on a certain page 23 and writing new data to another page 23. This can result in a situation where a large portion of a certain logical block 24 is occupied by unnecessary data (invalid data). The proportion of valid data in a logical block 24 is referred to as the valid cluster ratio. The garbage collection described above is performed, for example, on logical blocks 24 with a small valid cluster ratio.

[0076] Specifically, the NAND management module 11 selects N (N is a natural number equal to or greater than 2) logical blocks 24 in ascending order of valid cluster ratio, for example, and moves valid data from the N logical blocks 24 to less than N logical blocks 24. At this time, the less than N logical blocks 24 transition from an unused state to a used state, while data in the N logical blocks 24 is erased and transitions from a used state to an unused state. As a result, one or more (N - less than N) unused logical blocks 24 are created. In other words, pages 23 equivalent to one or more logical blocks 24 are reused.

[0077] In this way, the logic block 24 cyclically transitions from unused state to used state (open state) to used state (closed state) to unused state, . . .

[0078] The control module 14 cooperates with the NAND management module 11 to assign each of the multiple continuity determination modules 12 (12A, 12B, 12C) to an open logical block 24. Therefore, the number of continuity determination modules 12 is equal to or less than the number of logical blocks 24 that can be simultaneously open, which is predetermined as a specification of the memory system 1. When data is written to a certain logical block 24, the NAND management module 11 outputs write address information to the continuity determination module 12 assigned to that logical block 24.

[0079] As described above, the PBAs in the logical block 24 are managed so as to be contiguous by the NAND management module 11. Therefore, when the continuity determination module 12 accumulates write address information in the queue 121, it only needs to calculate the next expected LBA from this write address information and refer to only the LBA of the LBA and PBA of the write address information newly input to the queue 121.

[0080] FIG. 15 is a diagram showing an example of the operation of the continuity determination module 12 in a state where the logical block 24 has been allocated.

[0081] 15 shows an example in which write address information "128,32,4" (b1) is first input to the queue 121. At this time, the continuity determination module 12 stores the next expected LBA "132 (=128+4)" and the length "4".

[0082] Subsequently, when write address information "132,36,8" (b2) is newly input to the queue 121, the continuity determination module 12 determines whether or not only the LBAs are contiguous. In this case, since they are contiguous, the continuity determination module 12 stores the next expected LBA "140 (=132+8)" and the length "12 (=4+8)".

[0083] Similarly, when write address information "140, 44, 4" (b3) is newly input to the queue 121, the continuity determination module 12 determines whether the LBAs are consecutive or not. Since they are consecutive, the continuity determination module 12 stores the next expected LBA "144 (=140+4)" and the length "16 (=12+4)".

[0084] Furthermore, when write address information "144, 48, 16" (b4) with consecutive LBAs is newly input to the queue 121, the total length (32 (=16+16)) reaches the length corresponding to the second node above the first node. Note that in FIG. 15 as well, it is assumed that there are 32 first nodes under the second node.

[0085] The continuity determination module 12 generates write address information “128,32,32” (b5) including the LBA and PBA of the write address information “128,32,4” (b1) and the total length (32), and outputs it to the L2P management module 13.

[0086] In this way, by allocating the continuity determination module 12 (queue 121) to the logical block 24, it is only necessary to monitor the LBA, and therefore the processing cost related to the L2P table 131 can be further reduced.

[0087] Furthermore, when a logical block 24 in an open state transitions to a closed state, the control module 14 instructs the continuity determination module 12 assigned to that logical block 24 to output the write address information accumulated in the queue 121. When the output of the write address information is completed, the control module 14 cancels the allocation of the continuity determination module 12 to that logical block 24. The control module 14 assigns the continuity determination module 12 to the logical block 24 that has transitioned from an unused state to a used state (open state).

[0088] It should be noted that the allocation of continuity determination modules 12 to logical blocks 24 does not necessarily have to be one-to-one. For example, one continuity determination module 12 may be allocated to a logical block 24 that is predicted to have a high access frequency, and one continuity determination module 12 may be allocated to the other multiple logical blocks 24. In other words, the number of continuity determination modules 12 provided may be less than the number of logical blocks 24 that can be open simultaneously. It should be noted that the method of predicting the access frequency is not limited to a specific method, and various known methods can be applied.

[0089] Furthermore, one of the plurality of continuity determination modules 12 may be assigned to a logical block 24 used for writing data for garbage collection. In this case, the length of time when consecutive PBAs are associated with consecutive LBAs tends to be longer when writing data by garbage collection compared to when writing data by a write command from the host 2. Therefore, the continuity determination module 12 assigned to this logical block 24 may increase the length of the write address information stored in the queue 121.

[0090] Specifically, normally, when the corresponding length of the second node is reached, the write address information is output from the queue 121. However, when the corresponding length of the third node above the second node is reached, the write address information may be output from the queue 121. In other words, the pruning unit may be variable.

[0091] As described above, the memory system 1 of the embodiment can reduce the processing cost of the L2P table 131 by interposing the continuity determination module 12, which appropriately processes the write address information, between the NAND management module 11 and the L2P management module 13.

[0092] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0093] 1...Memory system (SSD), 2...Host, 10...Controller, 11...NAND management module, 12...Continuity determination module, 13...L2P management module, 14...Control module, 20...Non-volatile memory, 21...NAND chip, 22...Physical block, 23...Page, 24...Logical block (superblock), 121...Queue, 131...L2P table

Claims

1. It is able to communicate with the host, a non-volatile memory; a controller that controls the nonvolatile memory; Equipped with the controller manages an address translation table that holds a correspondence between a logical address indicating a logical location by the host and a physical address indicating a physical location on the nonvolatile memory; the address conversion table has a hierarchical structure including at least a first node that holds a one-to-one correspondence between the logical addresses and the physical addresses, and a second node that corresponds to a first number of the first nodes and is higher than the first node and holds information indicating whether or not consecutive logical addresses are associated with consecutive physical addresses for the first number of the first nodes; The controller a queue for storing update information of the address conversion table, the update information including the logical address and the physical address indicating a write start position of data to the nonvolatile memory and a length of data to be written to the nonvolatile memory; when second update information including a first logical address indicating a data write end position obtained from the first update information accumulated in the queue, a second logical address at least one of which is not consecutive to a first physical address corresponding to the first logical address, and a second physical address corresponding to the second logical address is input to the queue, the first update information accumulated in the queue is output from the queue, and the first node is updated based on the output first update information; When third update information including the first logical address, a third logical address consecutive to the first physical address, and a third physical address corresponding to the third logical address is input to the queue, the input third update information is stored in the queue in addition to the first update information stored in the queue; when the sum of the length of the data included in the first update information and the length of the data included in the third update information is a length that extends from the write start position of the data included in the first update information stored in the queue to the boundary of the second node, outputting fourth update information generated from the first update information and the third update information stored in the queue from the queue, and updating the first node or the second node based on the output fourth update information; Memory system.

2. The memory system of claim 1 , wherein the controller, when updating the second node, deletes the first number of the first nodes subordinate to the updated second node.

3. 3. The memory system of claim 1, wherein when the controller accumulates the input third update information in the queue in addition to the first update information accumulated in the queue, the controller generates fifth update information that combines the first update information accumulated in the queue and the input third update information, and accumulates the generated fifth update information in the queue.

4. 4. The memory system of claim 3, wherein when the controller generates the fifth update information, the controller generates the fifth update information including the first logical address and the first physical address of the first update information and a length obtained by adding together the length of the data of the first update information and the length of the data of the third update information.

5. A memory system as described in any one of claims 1 to 4, wherein the controller outputs the first update information from the queue in parallel with storing the input second update information in the queue, and updates the first node based on the output first update information.

6. The memory system according to any one of claims 1 to 5, wherein the controller divides the sixth update information input to the queue into seventh update information and eighth update information based on a boundary of the hierarchical structure of the address conversion table.

7. The controller When dividing the sixth update information, if update information input before the sixth update information is not accumulated in the queue, outputting the seventh update information from the queue, which includes the logical address and the physical address that are the first of the seventh update information and the eighth update information, and updating the first node based on the output seventh update information; When dividing the sixth update information, if ninth update information has been accumulated in the queue, tenth update information is generated by combining the ninth update information accumulated in the queue and the seventh update information that includes the logical address and the physical address that is the first of the seventh update information and the eighth update information, and the tenth update information is output from the queue, and the first node or the second node is updated based on the output tenth update information.

7. The memory system of claim 6.

8. when twelfth update information whose target overlaps with eleventh update information stored in the queue is input to the queue, the controller divides the eleventh update information stored in the queue into thirteenth update information and fourteenth update information corresponding to the non-overlapping portions, and outputs the divided pieces of information from the queue, and updates the first node based on the output thirteenth update information and fourteenth update information. The memory system according to any one of claims 1 to 7.

9. The controller a plurality of said queues; updating the address conversion table for each of the plurality of queues; 9. The memory system according to claim 1.

10. the non-volatile memory includes a plurality of physical blocks; The controller generating a logical block from a plurality of said physical blocks; assigning the queue to the logical block; 10. The memory system of claim 9.

11. The memory system according to claim 10 , wherein the controller allocates the queue to the logical block in a state where data can be written.

12. 12. The memory system of claim 11, wherein when the logical block to which the queue is assigned transitions from a state in which data can be written to a state in which data cannot be written, the controller outputs update information accumulated in the queue from the queue, updates the first node based on the output update information, and releases the queue from the logical block.

13. 13. The memory system of claim 11, wherein the controller assigns a first logical block that is frequently accessed among the logical blocks in a data writable state to a first queue, and assigns one or more logical blocks other than the first logical block among the logical blocks in a data writable state to a second queue.

14. The controller performing garbage collection to move valid data in N (N is a natural number equal to or greater than 2) logical blocks to logical blocks less than N to create one or more unused logical blocks; allocating one queue from the plurality of queues to the logical block used for writing data for the garbage collection; The memory system according to any one of claims 9 to 13.

15. the address conversion table further includes a third node higher than the second node, corresponding to a second number of the second nodes, and holding information indicating whether or not consecutive logical addresses are associated with consecutive physical addresses for the second number of the second nodes; With regard to the queue assigned to the logical block used for writing data for the garbage collection, when the length of data included in the update information accumulated in the queue reaches a length that extends from the write start position of the data included in the update information accumulated in the queue to the boundary of the third node, the controller outputs the update information accumulated in the queue from the queue, and updates the first node, the second node, or the third node based on the output update information.

15. The memory system of claim 14.

16. 1. A method for controlling a non-volatile memory, comprising: a host manages an address translation table that holds a correspondence relationship between a logical address indicating a logical location and a physical address indicating a physical location on the nonvolatile memory, the address translation table having a hierarchical structure including at least a first node that holds a one-to-one correspondence relationship between the logical address and the physical address, and a second node that corresponds to a first number of the first nodes and is higher than the first node and holds information indicating whether or not consecutive logical addresses are associated with consecutive physical addresses for the first number of the first nodes; managing a queue for storing update information of the address conversion table, the update information including the logical address and the physical address indicating a write start position of data to the nonvolatile memory and a length of data to be written to the nonvolatile memory; when second update information including a first logical address indicating a data write end position obtained from the first update information accumulated in the queue, a second logical address at least one of which is not consecutive to a first physical address corresponding to the first logical address, and a second physical address corresponding to the second logical address is input to the queue, the first update information accumulated in the queue is output from the queue, and the first node is updated based on the output first update information; When third update information including the first logical address, a third logical address consecutive to the first physical address, and a third physical address corresponding to the third logical address is input to the queue, the input third update information is stored in the queue in addition to the first update information stored in the queue; when the sum of the length of the data included in the first update information and the length of the data included in the third update information is a length that extends from the write start position of the data included in the first update information stored in the queue to the boundary of the second node, outputting fourth update information generated from the first update information and the third update information stored in the queue from the queue, and updating the first node or the second node based on the output fourth update information; method.

Images