Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device which improves reliability of mounting of the semiconductor device to an electronic device, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 1 includes: a lead frame including a first terminal 202; a semiconductor element arranged on a first surface of the lead frame; and a package member 30 covering the lead frame and the semiconductor element. The first terminal 202 includes: a rear surface section 210 which is arranged on a second surface side facing a first surface and is exposed from the package member 30 in a first direction perpendicular to the first surface; a side surface section 211 which is arranged between the first surface and the rear surface section 210 in the first direction and is exposed from the package member 30 in a second direction parallel to the first surface; and a recess section 215 which is arranged between the rear surface section 210 and the side surface section 211 in the first direction.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] Semiconductor devices are implemented in a variety of electronic devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-261193 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the reliability of mounting of semiconductor devices. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes: a first surface and a plurality of electrodes aligned in a first direction parallel to the first surface; First terminal and, a lead frame including: The aforementioned a semiconductor element provided on a first surface, and a package member covering the lead frame and the semiconductor element, Multiple First terminal Each of is provided on a second surface side of the lead frame opposite to the first surface, and is perpendicular to the first surface. 2 a back surface portion exposed from the package member in the direction of an upper portion provided between the first surface and the back surface in the second direction, the upper portion having a third surface exposed in a third direction parallel to the first surface and intersecting the first direction, and connected to a side surface of the package member; The aforementioned No. 2 In the direction of Top and the back surface portion, The third In the direction Stepping back from the third plane exposed from the package member and has a curved surface extending in the first direction. a side portion that extending in the first direction and spanning the plurality of first terminals in the first direction; The aforementioned In the second and third directions provided between the side surface and the back surface and a second end connected to the curved surface and located closer to the first surface than the first end in the second direction. A recessed portion; a protrusion provided on the other end of the recessed portion and extending in the second direction, wherein the back surface portion is flat on the second surface in a region between the back surface portion and the one end of the recessed portion. Includes. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a bird's-eye view showing an apparatus including a semiconductor device according to an embodiment. [Figure 2] 1 is a bird's-eye view showing a structural example of a semiconductor device according to an embodiment; [Figure 3] 1 is a bird's-eye view showing a structural example of a semiconductor device according to an embodiment; [Figure 4] FIG. 1 is a plan view showing a structural example of a semiconductor device according to an embodiment. [Figure 5] 1 is a cross-sectional view showing a structural example of a semiconductor device according to an embodiment. [Figure 6] 1 is a cross-sectional view showing a structural example of a semiconductor device according to an embodiment. [Figure 7] 1 is a plan view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1 is a plan view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device according to the embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a comparative example of the semiconductor device of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment will be described with reference to FIGS.

[0008] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, elements having the same functions and configurations are designated by the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference symbols with distinguishing numbers / letters at the end do not need to be distinguished from each other, descriptions (reference symbols) with the numbers / letters at the end omitted are used.

[0009] [Embodiment] (1) Structure example FIG. 1 is a schematic diagram illustrating an apparatus including a semiconductor device 1 according to this embodiment.

[0010] 1, the semiconductor device 1 of this embodiment is provided in an electric appliance EA. For example, the electric appliance EA is an industrial machine, a power conversion device, an in-vehicle device, a home appliance device, an audio device, a video device, a communication device, or a computer system.

[0011] The semiconductor device 1 is arranged on a surface (hereinafter also referred to as a mounting surface) of a module substrate (also referred to as a motherboard or printed wiring board) 80 together with one or more other devices (e.g., other semiconductor devices or electronic components) 700, 701.

[0012] The module substrate 80 includes a plurality of wires 71, 72, and 73 and a plurality of terminals 75 and . The multiple wirings 71, 72, 73 are provided on the surface of the module substrate 80 or inside the module substrate 80. Each of the wirings 71, 72, 73 is connected to one or more corresponding terminals of multiple terminals (connectors, sockets, or slots) 75, 76, or to devices 1, 700, 701 on the module substrate 80. Each of the terminals 75, 76 is supplied with a corresponding one of various voltages (for example, power supply voltage or ground voltage) or signals.

[0013] The semiconductor device 1 is connected to a plurality of wirings 71 and 72 on the module substrate 80. For example, on the module substrate 80, the semiconductor device 1 is connected to a terminal 75 via the wiring 71, and is connected to a semiconductor device 700 (or an electronic component 701) via the wiring 72.

[0014] The semiconductor device 700 includes, for example, a semiconductor integrated circuit or a discrete device. The semiconductor device 700 may be a modularized device including multiple semiconductor chips and multiple passive elements. The electronic components 701 are passive elements such as capacitors, inductors, resistors, and switches.

[0015] The semiconductor device 700 and the electronic component 701 are connected to terminals 76 via wiring 73, and are connected to each other via other wiring.

[0016] An example of the structure of the semiconductor device of this embodiment will be described with reference to FIGS.

[0017] 2 and 3 are bird's-eye views showing an example of the structure of the semiconductor device 1 of this embodiment. Fig. 2 shows the example of the structure of the semiconductor device 1 of this embodiment when viewed from the front side of the semiconductor device 1. Fig. 3 shows the example of the structure of the semiconductor device 1 of this embodiment when viewed from the back side of the semiconductor device 1 of this embodiment. Fig. 4 is a plan view showing an example of the structure of the semiconductor device 1 of this embodiment. Fig. 5 is a cross-sectional view showing an example of the structure of the semiconductor device 1 of this embodiment. Fig. 5 shows a cross section taken along line VV in Fig. 4.

[0018] In the following description, in the semiconductor device 1 of this embodiment, the back surface of each component is the surface facing the module substrate 80 on which the semiconductor device 1 is mounted. The front surface of each component is the surface facing the back surface in a direction perpendicular to the back surface.

[0019] As shown in FIGS. 2 to 5, the semiconductor device 1 of this embodiment includes a semiconductor element 10, a lead frame 20, and a package member 30.

[0020] The semiconductor element 10 is mounted on a lead frame 20 within a package member 30 .

[0021] When the semiconductor device 1 of this embodiment is a discrete device, the semiconductor element 10 is a field-effect transistor (e.g., a MOS transistor), a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or a diode. As a more specific example, the semiconductor element 10 is a small-signal transistor. However, the semiconductor element 10 may also be a power device such as a high-voltage transistor (also called a high-voltage transistor).

[0022] The semiconductor element 10 is, for example, a semiconductor chip (bare chip). The semiconductor element 10 includes an element portion 100 and a plurality of pads (also called nodes or terminals) 101, 102, and 103.

[0023] The pad 101 is provided on the back surface side of the element part 100 . If the semiconductor element 10 is a field effect transistor, the pad 101 is connected to the drain of the transistor.

[0024] The pads 102 and 103 are provided on the front surface side of the element section 100 . If the semiconductor element 10 is a field-effect transistor, the pad 102 is connected to the source of the transistor. Hereinafter, the pad 102 will be referred to as a source pad 102. If the semiconductor element 10 is a field-effect transistor, the pad 103 is connected to the gate of the transistor. Hereinafter, the pad 103 will be referred to as a gate pad 103.

[0025] The drain pad 101 is electrically connected to the lead frame 20 using a conductive member 41 such as a conductive paste. The source pad 102 and the gate pad 103 are electrically connected to the lead frame 20 via bonding wires 42 and 43, respectively.

[0026] Depending on the internal configuration of the element section 100, the pad 101 may be used as a source pad, and the pad 102 may be used as a drain pad.

[0027] For example, the element portion 100 includes a semiconductor layer such as silicon, silicon carbide, silicon germanium, gallium nitride, or gallium arsenide, and the pads 101, 102, and 103 include a metal layer such as aluminum or copper.

[0028] A package member (also called a sealing member, mold resin, or package resin) 30 is provided on the semiconductor element 10 and the lead frame 20. The package member 30 covers the semiconductor element 10 on the lead frame 20. The package member 30 includes an insulator such as an insulating organic material (e.g., polyimide). The package member 30 is provided on the front surface of the lead frame 20 and under the back surface of the lead frame 20.

[0029] The lead frame 20 includes a plurality of terminals 200, 201, 202 (202a, 202b, 202c, 202d, 202e, 202f) and a plurality of connecting portions 250 (250a, 250b, 250c, 250d, 250e). The lead frame 20 includes copper.

[0030] The terminals 200 , 201 , and 202 have portions exposed from the package member 30 .

[0031] The terminals 200 and 201 are exposed from the package member 30 on the back surface of the semiconductor device 1. The back surface portions of the terminals 200 and 201 function as external connection portions. The terminal 200 is adjacent to the terminal 201 in the Y direction.

[0032] For example, the terminal 200 is used as an external connection terminal and also functions as a die pad (also called a mounting portion). The semiconductor element 10 is provided on the surface of the terminal 200.

[0033] The terminal 200 is electrically connected to a drain pad 101 on the back surface side of the semiconductor element 10 via a conductive member 41 such as a conductive paste. The terminals 200 are electrically connected to connection portions (wiring or terminals) 82 of the module substrate 80 via conductive members 81 such as solder or conductive paste. The connection portions 82 are provided on a substrate member 800 of the module substrate 80 (or within the substrate member 800).

[0034] The terminal 201 is electrically connected via a bonding wire 42 to a source pad 102 provided in the surface of the semiconductor element 10 .

[0035] The terminals 202a, 202b, and 202c are provided on one end side in the X direction of the semiconductor device 1. The terminals 202a and 202b are adjacent to the terminal 200 on one end side in the X direction of the semiconductor device 1. For example, terminals 202a and 202b are connected to terminal 200 via coupling portions 250a and 250b, respectively.

[0036] The terminal 202c is adjacent to the terminal 201 at one end in the X direction of the semiconductor device 1. The terminal 202c is electrically connected to the terminal 201 via a connecting portion 250c. The terminal 202c is electrically isolated from the terminals 202a, 202b, 202d, 202e, and 202f.

[0037] The terminals 202d, 202e, and 202f are provided on the other end side in the X direction of the semiconductor device 1. The terminals 202d and 202e are adjacent to the terminal 200 on the other end side in the X direction of the semiconductor device 1. For example, the terminals 202d and 202e are connected to the terminal 200 via the connecting portions 250d and 250e, respectively.

[0038] The terminal 202f is adjacent to the terminal 201 on the other end side in the X direction of the semiconductor device 1. The terminal 202f is separated from the terminals 200, 201, 202a, 202b, 202c, 202d, and 202e.

[0039] The terminals 202a, 202b, 202d, and 202e are electrically connected to a drain pad 101 provided on the back surface side of the semiconductor element 10 via a connecting portion 250, a terminal 200, and a conductive member 41. The terminal 202c is electrically connected to a source pad 102 provided on the front surface side of the semiconductor element 10 via a connecting portion 250, a terminal 201, and a bonding wire 42. The terminal 202f is electrically connected to a gate pad 103 provided on the front surface side of the semiconductor element 10 via a bonding wire 43.

[0040] For example, the portions of the terminals 200 , 201 , and 202 that are exposed from the package member 30 include a plating layer 230 .

[0041] The connecting portion 250 is covered by the package member 30 without being exposed from the package member 30 .

[0042] The lead frame 20 (the terminals 200, 201, 202 and the connecting portion 250) includes a metal such as copper or aluminum. The plating layer 230 includes copper.

[0043] 2 to 5, in the semiconductor device 1 of this embodiment, each terminal 202 has a WF (wettable flank) structure. In this embodiment, a recess portion (also called a step portion) 215 is provided in each terminal 202.

[0044] FIG. 6 is a cross-sectional view showing an example of the structure of a terminal 202 having a WF structure in the semiconductor device 1 of this embodiment.

[0045] As shown in FIG. 6, the terminals 202 are exposed on the back surface side of the semiconductor device 1 and also on the side surface of the semiconductor device 1.

[0046] The terminal 202 further includes a back surface portion 210 and a side surface portion (also called a curved portion or a half-cut portion) 211.

[0047] The back surface S1 of the back surface portion 210 of the terminal 202 is flat. For example, the back surface S1 is substantially parallel to the surface of the semiconductor device 1. The back surface portion 210 is exposed from the package member 30 in the Z direction.

[0048] The side surface S2 of the side surface portion 211 of the terminal 202 is curved. For example, the side surface portion 211 has a curved surface (side surface S2) that is quarter-circular (or quarter-elliptical) when viewed from the Y direction. The side surface portion 211 is exposed from the package member 30 in the X direction.

[0049] The terminals 202 are electrically connected to connection portions (wiring or terminals) 88 of the module substrate 80 by conductive members 89 such as solder. For example, the solder 89 covers the back surface 210 and side surface 211 of the terminals 202 via a plating layer 230. The connection portions 88 are provided on (or within) a substrate member 800 of the module substrate 80.

[0050] Of the multiple portions constituting the terminal 202, the portion located closer to the surface of the semiconductor device 1 than the side portion 211 in the Z direction and having a flat surface on the side surface of the semiconductor device 1 is called the upper portion 213. The exposed surface (side surface) of the upper portion 213 is exposed after the plating layer 230 is formed. Therefore, the plating layer 230 is not provided on the exposed surface of the upper portion 213. An oxide layer (not shown) may be formed on the exposed surface of the upper portion 213. For example, the solder 89 is not provided on the exposed surface of the upper portion 213.

[0051] The terminal 202 has a recess 215 in the back surface 210 (and side surface 211) of the terminal 202.

[0052] The recessed portion 215 is provided in the boundary region between the rear portion 210 and the side portion 211 . In the portion where the recessed portion 215 is provided, the terminal 202 is recessed from the back surface side of the semiconductor device 1 toward the front surface side of the semiconductor device 1. The recessed portion 215 has a curved surface in the shape of a quarter circle (or a quarter ellipse) when viewed from the Y direction.

[0053] The recessed portion 215 is provided above the back surface portion 210 (on the front surface side of the semiconductor device 1) in the Z direction.

[0054] The end of the recess 215 on the front surface side of the semiconductor device 1 in the Z direction is located above (on the front surface side of the semiconductor device 1) the back surface 210 of the terminal 202 in the Z direction. Hereinafter, the end of the recess 215 located on the front surface side of the semiconductor device 1 in the Z direction will be referred to as the upper end, and the end of the recess 215 located on the back surface side of the semiconductor device 1 in the Z direction will be referred to as the lower end.

[0055] The upper end of the recessed portion 215 is connected to one end (lower end) of the side surface portion 211. The lower end of the recessed portion 215 is connected to one end of the back surface portion 210.

[0056] For example, when dicing the lead frame 20, a burr 290 may be formed at the boundary between the recessed portion 215 and the side surface portion 211 (at the upper end of the recessed portion 215). The burr 290 extends in the Z direction. The burr 290 protrudes from the recessed portion 215 toward the module substrate 80. For example, the burr 290 is covered with the plating layer 230.

[0057] In this embodiment, the burrs 290 are formed on the upper end side (opposite the back surface) of the recessed portion 215. The burrs 290 in the recessed portion 215 are located closer to the front surface of the semiconductor device 1 than the back surface portion 210. Therefore, the size of the burr 290 protruding from the rear surface S1 of the terminal 202 is smaller than the size of the burr protruding from the rear surface S1 when the burr is formed on the rear surface portion 210.

[0058] As shown in FIG. 5, a burr 291 may be formed at the boundary between the side surface portion 211 and the top portion 213 during the dicing process of the semiconductor device 1.

[0059] (2) Manufacturing method A method for manufacturing the semiconductor device 1 of this embodiment (and a method for manufacturing an apparatus including the semiconductor device 1 of this embodiment) will be described with reference to FIGS.

[0060] 7 and 8 are plan views showing a step in the manufacturing method of the semiconductor device 1 of this embodiment. Each of Figures 9 to 15 is a cross-sectional view showing a step in the manufacturing method of the semiconductor device 1 of this embodiment. In Figures 7 to 15, certain parts of the components used to explain the manufacturing method of the semiconductor device 1 are extracted and illustrated.

[0061] As shown in Fig. 7, a metal plate 2 including a plurality of lead frames 20 is formed. The metal plate 2 includes, for example, copper (or aluminum). Note that Fig. 7 illustrates the structure of the lead frames 20 as viewed from the front surface side.

[0062] The plurality of lead frames 20 are connected to one another by connection portions (excess portions) 270 in the metal plate 2.

[0063] A dicing region (also called a full cut area) 190 surrounds a device region 3 which is a component of the semiconductor device 1. A lead frame 20 is formed within the device region 3.

[0064] The dimension in the width direction of the dicing region 190 corresponds to the width (thickness of the edge of the dicing blade) of the dicing blade used in the full cutting step of the metal plate 2 described later.

[0065] In a process described later, the connection portions 270 of the metal plate 2 are divided along the dicing regions 190, thereby forming a plurality of lead frames 20 that are independent of one another.

[0066] FIG. 8 shows the structure of the lead frame 20 as seen from the back side. 8 and 9, recesses 215 are formed on the rear surface of the metal plate 2 on widthwise (X-direction) ends Eg of half-cut areas 191 in a half-cutting process described below. The half-cut areas 191 extend in the Y direction. Ends Eg of the half-cut areas 191 (hereinafter also referred to as half-cut edges) exist on the terminals 202 of the lead frame 20. The recesses 215 have a semicircular (or semi-elliptical) shape when viewed from the Y direction.

[0067] For example, the recess 215 is formed before the semiconductor element 10 is mounted on the lead frame 20 .

[0068] The recessed portion 215 is formed by etching the metal plate 2 or by pressing the metal plate 2 with a press machine.

[0069] The portion of the metal plate 2 where the recessed portion 215 is formed is recessed relative to other portions of the metal plate 2. The dimension (depth) D1 of the recessed portion 215 in the Z direction is approximately several tens of μm to several hundreds of μm. For example, the depth D1 of the recessed portion 215 is approximately 30 μm to 100 μm.

[0070] It is desirable that the distance D2 between the bottoms (upper ends of the recessed portions 215) of two adjacent recessed portions 215 in the width direction of each half-cut area 191 is substantially equal to the width of the dicing blade used in the half-cut process described below.

[0071] However, as long as each of the two recesses 215 is formed at a position that overlaps with each of the widthwise ends of the dicing blade for the half-cut process, the distance D2 between the bottoms of the recesses 215 does not have to match the width of the dicing blade.

[0072] 10, a semiconductor element 10 is mounted on the surface of a lead frame 20 on a metal plate 2. The semiconductor element 10 is mounted on a terminal (mounting portion) 200 of the lead frame 20. A pad 101 of the semiconductor element 10 is electrically connected to the mounting portion 200 via a conductive member 41. Each of the multiple pads 102, 103 of the semiconductor element 10 is electrically connected to terminals 201, 202 of the lead frame 20 via bonding wires (not shown) by wire bonding.

[0073] After the semiconductor element 10 is electrically connected to the lead frame 20, the semiconductor element 10 is sealed with a package member 30. As a result, the package member 30 is formed on the semiconductor element 10 and the lead frame 20. The back surfaces of the terminals 201, 202, and 203 are exposed on the back surface side of the lead frame 20. The exposed surface of the package member 35 may be recessed by etching.

[0074] When the semiconductor element 10 is sealed, the package member 35 is embedded in the recessed portion 215. However, the package member 35 does not have to be embedded in the recessed portion 215.

[0075] 11, a half-cut process is performed on the metal plate 2 by a dicing blade 90 having a first blade width W1. As a result, a portion of the metal plate 2 within a half-cut area 191 is removed.

[0076] The dicing blade 90 comes into contact with the recessed portions 215. The edges of the dicing blade 90 in the width direction overlap with a certain portion of each recessed portion 215. As a result, a portion of the recessed portion 215 is ground away.

[0077] In this embodiment, the back surface portion 210 does not come into contact with the dicing blade 90.

[0078] The package member 35 in the recessed portion 215 is removed in the half-cut process by contact between the package member 35 and the dicing blade 90 or by the impact of dicing. In addition, if the packaging member 35 is not removed by the half-cutting process, the packaging member 35 may be removed from inside the recessed portion 215 by an ED (Electric deflashing) process or a water jet cleaning process that is performed after the half-cutting process.

[0079] 12, a trench 240 is formed in the metal plate 2 by the half-cut process of Fig. 11. This forms the curved side portion 211 of the terminal 202 with the WF structure.

[0080] A burr 290 may be formed in the area near the boundary between the recess 215 and the trench 240 due to grinding of the metal plate 2 by the dicing blade 90 . Burrs 290 are formed in the depressions of recessed portion 215 at the portions where recessed portion 215 and dicing blade 90 come into contact.

[0081] As described above, the back surface 210 does not come into contact with the dicing blade 90, and therefore no burrs are generated on the back surface 210.

[0082] 13, after the half-cutting step, a plating process is performed on the metal plate 2. As a result, a plating layer 230 is formed on the lead frame 20. The terminals 202 are covered with the plating layer 230.

[0083] For example, the component (material) of the burr 290 is the same as the component (material) of the terminal 202. Therefore, the plating layer 230 is also formed on the burr 290. This increases the size of the burr 290. Depending on the shape of the burr 290, a plating layer 230 thicker than the plating layer 230 on the terminal 202 may be formed on the burr 290.

[0084] 14, a full cut process is performed on the metal plate 2 by a dicing blade 91 having a second blade width W2. The second blade width W2 is smaller than the first blade width W1.

[0085] The metal plate 2 is ground along the dicing region 190. The connection portions 270 in the dicing region 190 are removed from the metal plate 2 by dicing in the full cut process. The metal plate 2 is divided into each device region 3. As a result, the multiple semiconductor devices 1 are separated from one another.

[0086] As a result, a semiconductor device 1 having a terminal 202 with a WF structure is formed.

[0087] 15, the semiconductor device 1 of this embodiment is mounted on a module substrate 80 after various processes. For example, a terminal 202 of the WF structure of the semiconductor device 1 is connected to a connection portion (wiring or terminal) 88 of the module substrate 80 by solder 89.

[0088] Since the terminal 202 has a WF structure, a fillet (side fillet) of the solder 89 is formed on the side surface portion 211 of the terminal 202.

[0089] Thereafter, various inspections such as automated optical inspection (AOI) are performed on the semiconductor device 1 on the module substrate 80 by the test equipment 9.

[0090] For example, AOI is used to inspect the shape of the side fillet of the solder 89 formed on the terminal 202. This allows a determination to be made as to whether the bonding state between the semiconductor device 1 and the module substrate 80 is good or bad.

[0091] After various inspections, the module substrate 80 on which the semiconductor device 1 of this embodiment is mounted, or the equipment EA including the semiconductor device 1 of this embodiment, is shipped to the market or to users.

[0092] (3) Variations FIG. 16 is a cross-sectional view showing a modification of the semiconductor device 1 of this embodiment.

[0093] The structure of the recess 215 provided between the rear surface 210 and the side surface 211 of the terminal 202 is not limited to the above example.

[0094] 16(a), the recessed portion 215A may have a structure in which a plane parallel to the surface of the semiconductor device 1 is connected to a plane perpendicular to the surface of the semiconductor device 1. In this case, a rectangular recess is formed in the metal plate 2 in the step of forming the recessed portion 215 in FIG.

[0095] 16(b), the recessed portion 215B may have a structure formed from a single plane inclined with respect to the surface of the semiconductor device 1 between the back surface portion 210 and the side surface portion 211. In this case, a triangular recess is formed in the metal plate 2 in the step of forming the recessed portion 215 in FIG.

[0096] 16(a) and 16(b), burrs 290 generated during the half-cutting process are formed at the boundaries between the recesses 215A, 215B and the side surface 211. In this way, if the steps 215A, 215B are formed between the rear surface 210 and the side surface 211, substantially the same effect as in the above example can be obtained.

[0097] (4) Summary In the manufacturing process of semiconductor devices, the grinding process of the lead frame with a dicing blade can cause burrs to form at the contact points between the edge of the dicing blade and the lead frame.

[0098] Burrs protruding from the back surface of the semiconductor device increase the gap between the back surface of the semiconductor device and the module substrate. This can cause the height of the semiconductor device to fail to meet standards and specifications. Furthermore, the burrs can peel off from the terminals after the semiconductor device is shipped, resulting in the generation of dust inside the product.

[0099] In semiconductor devices with a WF structure, the occurrence of burrs can make it difficult to form good side fillets in the solder, which can lead to poor mountability of the semiconductor device on the module substrate and make mounting inspection of the semiconductor device difficult.

[0100] In the semiconductor device 1 having the terminal 202 of the WF structure of this embodiment, the recess portion 215 is provided between the back surface portion 210 and the side surface portion 211 of the terminal 202.

[0101] The recessed portion 215 comes into contact with a dicing blade in the half-cutting step for forming the side portion 211 of the WF structure.

[0102] Therefore, in this embodiment, the burrs 290 generated in the half-cut process are formed in the recessed portions 215 located closer to the front surface of the semiconductor device 1 than the back surface 210 of the semiconductor device 1. Therefore, the amount by which the burrs 290 in the recessed portions 215 protrude from the back surface of the semiconductor device 1, using the back surface 210 of the semiconductor device 1 as a reference, is smaller than when the burrs 290 are formed on the back surface of the semiconductor device 1.

[0103] 17 is a diagram for explaining the effects of the semiconductor device 1 of this embodiment. In FIG. 17, the plating layer 230 is omitted for the sake of visibility.

[0104] Fig. 17(a) shows the structure of the terminal 202 of the semiconductor device 1 of this embodiment, and Fig. 17(b) shows the structure of the terminal 202x of the semiconductor device 1X of the comparative example.

[0105] 17(a), the burr 290 occurs in the recess 215 at the boundary between the recess 215 and the side surface 211. The recess 215 has a depth D1 in the Z direction. The burr 290 has a dimension H1 in the Z direction.

[0106] In this case, the size A1 of the burr 290 protruding from the back surface portion 210 is "H1-D1."

[0107] As shown in FIG. 17(b), in a terminal portion 202X of a semiconductor device 1X of the comparative example that does not have a recess portion 215, a side surface portion 211X is continuous with a back surface portion 210X.

[0108] The dicing blade comes into contact with the back surface portion 210 during the half-cutting step.

[0109] Therefore, in the comparative example, the burr 290X is formed on the end of the back surface portion 210 at the boundary between the back surface portion 210 and the side surface portion 211. The burr 290X has a dimension H1 in the Z direction. In this case, the size A2 of the burr 290X protruding from the back surface portion 210X is "H1".

[0110] Thus, even if the dimension H1 of the burr 290 in the Z direction is the same as the dimension H1 of the burr 290X in the Z direction, the protrusion amount A1 of the burr 290 based on the back surface of the semiconductor device 1 of this embodiment is smaller than the protrusion amount A2 of the burr 290X based on the back surface of the semiconductor device 1X of the comparative example, because the burr 290 is formed within the recess portion 215. As a result, in this embodiment, the adverse effects of the burrs 290 when the semiconductor device 1 is mounted on the module substrate 80 are mitigated.

[0111] Therefore, the flatness of the back surface of the semiconductor device 1 of this embodiment is improved, and therefore, a good bond is formed between the semiconductor device 1 of this embodiment and the module substrate 80. Therefore, the semiconductor device 1 of this embodiment improves the quality of mounting on the module substrate 80.

[0112] Furthermore, as a result of improving the flatness of the rear surface of the semiconductor device 1 (reducing the amount of protrusion of burrs), the distance between the rear surface of the semiconductor device 1 and the module substrate 80 becomes smaller.

[0113] This improves the amount of solder 89 that creeps up onto the terminal 202 with the WF structure in the semiconductor device 1 having the terminal 202 with the WF structure. Therefore, side fillets of the solder 89 are more likely to be formed on the terminal 202 with the WF structure.

[0114] As a result, it becomes easier to inspect the mounting state of the semiconductor device 1 by AOI. Therefore, the semiconductor device 1 of this embodiment can improve the inspection accuracy. Therefore, the reliability of the quality of equipment including the semiconductor device 1 of this embodiment is improved.

[0115] As described above, the semiconductor device of this embodiment can improve the reliability of packaging.

[0116] (5) Other The semiconductor device 1 of this embodiment may be a semiconductor integrated circuit, an image sensor, an optical device, or a memory device.

[0117] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0118] 1: semiconductor device, 10: semiconductor element, 20: lead frame, 30: package member, 200, 201, 202: terminal, 215: recess portion.

Claims

1. A lead frame including a first surface and a plurality of first terminals arranged in a first direction parallel to the first surface; a semiconductor element provided on the first surface of the lead frame; a package member covering the lead frame and the semiconductor element; Equipped with Each of the plurality of first terminals includes: a back surface portion provided on a second surface side of the lead frame opposite to the first surface, the back surface portion being exposed from the package member in a second direction perpendicular to the first surface; an upper portion provided between the first surface and the back surface in the second direction, the upper portion having a third surface exposed in a third direction parallel to the first surface and intersecting the first direction, and connected to a side surface of the package member; a side surface portion provided between the top portion and the back surface portion in the second direction, recessed from the third surface in the third direction to be exposed from the package member, and having a curved surface extending in the first direction; a recess portion extending in the first direction, spanning the plurality of first terminals in the first direction, and provided between the side surface portion and the rear surface portion in the second and third directions, the recess portion having one end connected to the rear surface portion and the other end located closer to the first surface than the one end in the second direction and connected to the curved surface; a protrusion provided on the other end of the recess and extending in the second direction; Including, the rear surface is flat on the second surface in a region between the rear surface and the one end of the recessed portion; Semiconductor devices.

2. The semiconductor device further includes a plating layer provided on each of the plurality of first terminals, the plating layer covers the recess portion, the back surface portion, and the side surface portion, but does not cover the third surface; The semiconductor device of claim 1 .

3. Further comprising solder having a fillet covering the side surface portion.

3. The semiconductor device according to claim 1 or 2.

4. Each of the plurality of first terminals has a wettable flank (WF) structure. A semiconductor device according to any one of claims 1 to 3.

5. Forming a plurality of lead frames, each including a plurality of first terminals arranged in a first direction, within a metal plate; forming recess portions extending in the first direction across the plurality of first terminals in boundary regions between half-cut areas of the metal plate extending in the first direction and back surfaces of the plurality of first terminals; grinding the plurality of first terminals along the first direction so that an edge of a first blade having a first width overlaps the recess portion, forming a protrusion extending in a second direction perpendicular to a surface of the metal plate at a contact portion between the first blade and the recess portion, and forming a trench having a curved surface extending in the first direction within the half-cut area of ​​the metal plate; grinding the first terminals in the trenches along the first direction with a second blade having a second width smaller than the first width, and separating the lead frames from one another so that an exposed side portion having the curved surface is formed on each of the first terminals; A method for manufacturing a semiconductor device comprising:

6. connecting a semiconductor element to each of the plurality of lead frames after forming the recessed portion and before forming the trench; forming a package member over the semiconductor device before forming the trench; The method for manufacturing a semiconductor device according to claim 5, further comprising:

7. performing a plating process on the first terminals after forming the trenches and before dividing the lead frames by the second blade; The method for manufacturing a semiconductor device according to claim 5 or 6, further comprising:

8. Mounting a semiconductor device including the lead frame on a substrate so that each of the plurality of first terminals is connected to a connection portion of the substrate via solder; inspecting the semiconductor devices on the substrate by automated visual inspection; 8. The method for manufacturing a semiconductor device according to claim 5, further comprising:

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