Compressed Addressing of Transaction Layer Packets

Abstract

Compressed addressing of the transaction layer packets includes determining, over a first epoch, one or more low-entropy address bits in a plurality of first transaction layer packets, removing one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets, and transmitting the one or more second transaction layer packets.

Description

[Background technology]

[0001] Improvements to the interconnection of transaction layer packets increase bandwidth but at the expense of poor signal integrity. Error correction codes or other data increase signal integrity but impose significant coding overhead, thereby reducing system performance. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an example processor for compressed addressing of transaction layer packets, according to some embodiments. [Figure 2] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. [Figure 3] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. [Figure 4] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. [Figure 5] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. [Figure 6] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. [Figure 7] 1 is a flowchart of an exemplary method for compressed addressing of transaction layer packets, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] In some embodiments, a method for compressed addressing of transaction layer packets includes determining, over a first epoch, one or more low-entropy address bits in a plurality of first transaction layer packets, removing the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets, and transmitting the one or more second transaction layer packets.

[0004] In some embodiments, determining one or more low-entropy address bits in the plurality of first transaction layer packets within the first epoch includes maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining the one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets. In some embodiments, the method further includes storing a bit mask indicative of the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values ​​for the one or more low-entropy bits in a first bit array register. In some embodiments, the method further includes synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a receiver of the one or more second transaction layer packets. In some embodiments, the method further includes regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values ​​indicating the one or more removed low-entropy bits. In some embodiments, the one or more stored values ​​include a second bit mask register that stores a bit mask indicating the one or more low-entropy bits and a second bit array register that stores one or more values ​​for the one or more low-entropy bits. In some embodiments, the method further includes sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include the one or more compressed destination addresses.

[0005] In some embodiments, an apparatus for compressed addressing of transaction layer packets performs steps including determining, over a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets; and transmitting the one or more second transaction layer packets.

[0006] In some embodiments, determining one or more low-entropy address bits in a plurality of first transaction layer packets within a first epoch includes maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining the one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets. In some embodiments, the steps further include storing a bit mask indicative of the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values ​​for the one or more low-entropy bits in a first bit array register. In some embodiments, the steps further include synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a receiver of the one or more second transaction layer packets. In some embodiments, the steps further include regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values ​​indicating the one or more removed low-entropy bits. In some embodiments, the one or more stored values ​​include a second bit mask register that stores a bit mask indicating the one or more low-entropy bits and a second bit array register that stores one or more values ​​for the one or more low-entropy bits. In some embodiments, the steps further include sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include the one or more compressed destination addresses.

[0007] In some embodiments, a system for compressed addressing of transaction layer packets includes an apparatus, the apparatus performing steps including determining, over a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing the one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets; and transmitting the one or more second transaction layer packets.

[0008] In some embodiments, determining one or more low-entropy address bits in a plurality of first transaction layer packets within a first epoch includes maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets, modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets, and determining the one or more low-entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets. In some embodiments, the steps further include storing a bit mask indicative of the one or more low-entropy address bits in a first bit mask register and storing one or more predicted values ​​for the one or more low-entropy bits in a first bit array register. In some embodiments, the steps further include synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a receiver of the one or more second transaction layer packets. In some embodiments, the steps further include regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values ​​indicating the one or more removed low-entropy bits. In some embodiments, the one or more stored values ​​include a second bit mask register that stores a bit mask indicating the one or more low-entropy bits and a second bit array register that stores one or more values ​​for the one or more low-entropy bits. In some embodiments, the steps further include sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include the one or more compressed destination addresses.

[0009] 1 is a block diagram of a non-limiting exemplary system 100. The exemplary system 100 can be implemented in a variety of computing devices, including a mobile device, a personal computer, a peripheral hardware component, a gaming device, a set-top box, etc. The processor 100 includes devices 102a and 102b. The devices 102a / b include hardware devices or components (e.g., of a computing system) communicatively coupled via an interconnect 104. For example, in some embodiments, the devices 102a / b include a central processing unit (CPU), a graphics processing unit (GPU), a memory module, etc. In some embodiments, the interconnect 104 includes a Peripheral Component Interface (PCI) interconnect.

[0010] The devices 102a / b communicate over the interconnect 104 using transaction layer packets (TLP). For example, the device 102a performs a memory access command on the device 102b by sending one or more transaction layer packets to the device 102b. Each transaction layer packet includes a memory address in its header. The memory address is the target address of the memory access command (e.g., a read command, a write command).

[0011] In some embodiments, memory addresses indicated in transaction layer packets have one or more low-entropy bits. In other words, the bits in one or more indices for each transaction layer packet received and / or transmitted within a given time window or epoch will have a low degree of entropy (e.g., the bits in these indices have a low degree of dispersion across transaction layer packets within an epoch). To reduce the number of bits required to represent memory addresses in transaction layer packets, the memory addresses may be "compressed" to remove low-entropy bits before transmitting the transaction layer packets to their recipients. These removed or "reclaimed" bits are then available for other uses. For example, these reclaimed bits may be used to add error correction codes or other data used to ensure data integrity, thereby improving the integrity of communications over the interconnect without increasing the overall size of the transaction layer packets.

[0012] The compression unit 106 of the device 102a determines one or more low-entropy bits in a plurality of first transaction layer packets within a first epoch. The plurality of first transaction layer packets are transaction layer packets received by the device 102a or generated by the device 102a for communication to the device 102b. The first epoch is a time window configured during which the first transaction layer packets are received, generated, or transmitted to the device 102b. The first epoch, and other epochs described herein, include predetermined or configurable durations or time intervals.

[0013] In some embodiments, determining one or more low-entropy bits in the plurality of first transaction layer packets within the first epoch includes maintaining at least one corresponding counter 108 for each address bit in the plurality of first transaction layer packets. In some embodiments, for an n-bit memory address, the compression unit 106 maintains n counters 108. For each address bit in the memory address of the first plurality of transaction layer packets, the compression unit 106 updates the counter 108 corresponding to the address bit index. For example, if the address bit at a given index is “1,” the compression unit 106 increments the counter 108 corresponding to the given index. If the address bit at a given index is “0,” the compression unit 106 decrements the counter 108 corresponding to the given index. In this manner, for each first transaction layer packet, each counter 108 is incremented or decremented based on the value of the corresponding address bit.

[0014] In some embodiments, for an n-bit memory address, the compression unit 106 maintains two sets of n counters 108 each. In other words, each address bit in the transaction layer packet corresponds to two counters 108. For each address bit in the memory address of the first plurality of transaction layer packets, the compression unit 106 updates one of the counters 108 corresponding to the address bit index depending on the value of the address bit. For example, if the address bit at a given index is "1," the compression unit 106 increments the first counter 108 corresponding to the given index. If the address bit at a given index is "0," the compression unit 106 increments the second counter 108 corresponding to the given index. In this way, for each of the first transaction layer packets, either the first or second counter 108 is incremented based on the value of the corresponding address bit.

[0015] The compression unit 106 then determines one or more low-entropy address bits (e.g., at the end of the first epoch) based on the counters 108. For example, in some embodiments in which each address bit corresponds to a single counter 108 that is incremented or decremented based on the value of the corresponding address bit, low-entropy bits are identified by having a counter 108 with an absolute value that exceeds a threshold. That is, low-entropy bits have counters 108 with higher absolute values ​​because the counters 108 are incremented or decremented frequently. Conversely, high-entropy bits have counters 108 that are incremented and decremented to a more similar extent.

[0016] As an example, assume that a t-bit counter 108 is used and a threshold "T" is defined, where 0≦T≦1. The value C of the counter 108 x T * (2 t -1), the corresponding address bit is determined to be a low entropy bit and the bit value is predicted to be "1". x is (1-T) * (2 t If the entropy of the corresponding address bit is less than C −1, the corresponding address bit is determined to be a low entropy bit and the bit value is predicted to be “0”. x ≧(1-T) * (2 t -1), and C x ≦T * (2 t -1), it is determined that there is a corresponding address bit and the value is not predicted.

[0017] As another example, in some embodiments where each address bit corresponds to two counters 108 that are alternately incremented based on the value of the corresponding address bit, a low-entropy bit is identified by one counter 108 value being significantly larger than the other counter 108 value (e.g., the difference between the first counter 108 value and the second counter 108 value exceeds a threshold). Conversely, a high-entropy bit is identified by having similar values ​​for the first and second counters 108.

[0018] In some embodiments, to identify which address bits (e.g., address bit indices) are determined to be low-entropy bits, compression unit 106 stores a bit mask in bit mask register 110a. Those skilled in the art will appreciate that in some embodiments, the bit mask is stored in a non-register portion of allocated memory. For example, if the address bit at index i is determined to be a low-entropy bit, the value of the bit mask at index i is set to “1.” Conversely, if the address bit at index i is determined to be a high-entropy bit, the value of the bit mask at index i is set to “0” or remains unchanged. For example, in some embodiments, compression unit 106 resets or zeroes out bit mask register 110a. Thus, the bit mask indices for high-entropy bits need not be changed from their initialized “0” state.

[0019] In some embodiments, to identify predicted values ​​for address bits (e.g., address bit indices) determined to be low-entropy bits, compression unit 106 stores corresponding values ​​in bit array register 112a. Those skilled in the art will appreciate that in some embodiments, the predicted values ​​are stored in a non-register portion of allocated memory. Furthermore, while bit array register 112a is discussed as storing values ​​in an array, those skilled in the art will appreciate that other non-array data structures can be used. For example, if the value of the low-entropy address bit at index i is predicted to be “1,” the value of the bit array (stored in bit array register 112a) at index i is set to “1.” As another example, if the value of the low-entropy address bit at index i is predicted to be “0,” the value of the bit array (stored in bit array register 112a) at index i is set to “0.” Because no values ​​are predicted for high-entropy address bits, no values ​​need to be set in bit array register 112a. In some embodiments, the bit array register 112a is reset (eg, zeroed out, set to all NULL or a default value) at each epoch.

[0020] Compression unit 106 then removes one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch. For example, a bit mask stored in bit mask register 110a is used to determine which indices of the memory addresses are determined to be low-entropy bits. For each index identified as a low-entropy bit (e.g., having a bit mask value of “1”), the value of bit array register 112a at these indices is compared with the corresponding value of the memory address in the second transaction layer packet. For each index identified as a low-entropy bit, if the corresponding bit in the memory address of the second transaction layer packet matches the corresponding value in bit array register 112a (e.g., if an XOR comparison of each bit in the low-entropy bit index against the memory address and the bit array yields “0”), the low-entropy address bit is then removed from the memory address of the second transaction layer packet.

[0021] In some embodiments, additional data, such as error correction codes or other data integrity data, is encoded into the one or more second transaction layer packets. Device 102a then transmits the one or more second transaction layer packets to device 102b.

[0022] In some embodiments, the above-described approach is repeated every epoch (e.g., at predetermined intervals). For example, compression unit 106 determines low-entropy address bits for multiple first transaction layer packets over a first epoch. For example, during the first epoch, counter 108 is maintained and updated based on the memory addresses of the multiple first transaction layer packets. At the end of the first epoch, low-entropy address bits are identified, and bit mask register 110a and bit array register 112a are updated accordingly. During the second epoch, low-entropy address bits are removed from one or more second transaction layer packets based on the values ​​of bit mask register 110a and bit array register 112a determined from the multiple first transaction layer packets. Counter 108 is also reset and updated based on the memory addresses of the one or more second transaction layer packets. At the end of the second epoch, bit mask register 110a and bit array register 112 are updated based on the low entropy bits identified from the second transaction layer packet. Matching low entropy bits are then removed from the third transaction layer packet over the third epoch, and so on.

[0023] The decompression unit 114 of device 102b regenerates the original, uncompressed memory address for the received transaction layer packet (e.g., the one or more second transaction layer packets from which one or more low-entropy bits have been removed). To facilitate the regeneration of the memory address, in some embodiments, the decompression unit 114 includes a bit mask register 110b and a bit array register 112b synchronized with the bit mask register 110a and the bit array register 112a of the compression unit 106. For example, in some embodiments, after storing a value in the bit mask register 110a and / or the bit array register 112a, the compression unit 106 of device 102a provides a signal indicative of the stored value to the decompression unit 114 of device 102b. Furthermore, in response to removing the one or more low-entropy address bits, the compression unit 106 provides a signal indicative of the one or more second transaction layer packets containing a compressed memory address to the decompression unit 114 of device 102b. In this manner, decompression unit 114 determines, based on the received signal, to regenerate the memory addresses of one or more second transaction layer packets based on the values ​​stored in bit mask register 110 b and bit array register 112 b. Decompression unit 114 may also include one or more counters 116 for synchronizing bit mask register 110 a / b and bit array register 112 a / b.

[0024] While the exemplary system 100 depicts two devices 102a / b, it is understood that the approaches described herein may be implemented in a system having any number of interconnected devices. Additionally, while the exemplary system 100 depicts device 102a as having a compression unit 106 and device 102b as having a decompression unit 114, it is understood that in some embodiments, the devices may include both a compression unit 106 and a decompression unit 114 to facilitate bidirectional transmission of transaction layer packets having compressed memory addresses.

[0025] For further explanation, FIG. 2 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits within a plurality of first transaction layer packets over a first epoch. Each transaction layer packet within the plurality of first transaction layer packets includes a memory address within a header. The memory address is a target address of a memory access command (e.g., a read command, a write command). The one or more low-entropy address bits are indices of bits within the memory address that have a low degree of entropy across each of the plurality of first transaction layer packets.

[0026] The first transaction layer packets are transaction layer packets received by device 102a associated with compression unit 200 or generated by device 102a associated with compression unit 200 for communication to device 102b. The first epoch is a configured time window during which the first transaction layer packets are received, generated, or transmitted to device 102b. The first epoch, and other epochs described herein, include predetermined or configurable durations or time intervals.

[0027] In some embodiments, determining 202 one or more low-entropy address bits includes storing an indication of which bits (e.g., which bit indices) correspond to low address bits. For example, a bit mask is stored in bit mask register 110a or another allocated portion of memory. Each index of the bit mask corresponding to a low-entropy bit index is set to a predetermined value (e.g., “1”). In some embodiments, determining 202 one or more low-entropy address bits includes predicting values ​​of one or more low-entropy address bits and storing an indication of the predicted values. For example, in some embodiments, a bit array or other data structure is stored in bit array register 112a or another allocated portion of memory. Each entry in the bit array corresponding to a low-entropy address bit is set to the predicted value (e.g., “0” or “1”) of that low-entropy address bit.

[0028] 2 also includes removing 204 one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch. For example, a bit mask stored in bit mask register 110a is used to determine which indices of the memory addresses are determined to be low-entropy bits. For each indices identified as low-entropy bits (e.g., having a bit mask value of “1”), the values ​​of bit array register 112a at these indices are compared to the corresponding values ​​of the memory addresses in second transaction layer packet 208. For each index identified as a low-entropy bit, if the corresponding bit in the memory address of the second transaction layer packet matches the corresponding value in bit array register 112a, the low-entropy address bit is removed from the memory address of the second transaction layer packet.

[0029] In some embodiments, additional data, such as error correction codes or other data integrity data, is encoded within one or more second transaction layer packets 208. The method of Figure 2 also includes transmitting 206 one or more second transaction layer packets 208. For example, one or more second transaction layer packets 208 are transmitted via interface 104 to device 102b.

[0030] For further explanation, FIG. 3 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch, removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch, and transmitting 206 the one or more second transaction layer packets 208.

[0031] The method of Figure 3 differs from Figure 2 in that determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch includes maintaining 302 at least one counter 108 corresponding to each address bit in the plurality of first transaction layer packets. In some embodiments, for an n-bit memory address, compression unit 200 maintains n counters 108. In other embodiments, for an n-bit memory address, compression unit 200 maintains two sets of n counters 108 each. In other words, each address bit in a transaction layer packet corresponds to two counters 108.

[0032] 3 also includes step 304 of modifying at least one corresponding counter based on the bit value of each address bit in the plurality of first transaction layer packets. If compression unit 200 maintains n counters 108 for n-bit memory addresses, for each address bit in the memory addresses of the first plurality of transaction layer packets, compression unit 200 updates the counter 108 corresponding to the address bit index. For example, if the address bit at a given index is "1," compression unit 200 increments the counter 108 corresponding to the given index. If the address bit at a given index is "0," compression unit 200 decrements the counter 108 corresponding to the given index. Thus, for each first transaction layer packet, each counter 108 is incremented or decremented based on the value of the corresponding address bit.

[0033] If compression unit 200 maintains 2*n counters 108 for an n-bit memory address, then for each address bit in the memory address of the first plurality of transaction layer packets, compression unit 200 updates one of counters 108 corresponding to the address bit index depending on the value of the address bit. For example, if the address bit at a given index is "1," compression unit 200 increments the first counter 108 corresponding to the given index. If the address bit at a given index is "0," compression unit 200 increments the second counter 108 corresponding to the given index. Thus, for each of the first transaction layer packets, either the first or second counter 108 is incremented based on the value of the corresponding address bit.

[0034] 3 also includes determining 306 one or more low-entropy address bits based on the counter 108 (e.g., at the end of the first epoch). For example, in some embodiments in which each address bit corresponds to a single counter 108 that is incremented or decremented based on the value of the corresponding address bit, low-entropy bits are identified by having a counter 108 with an absolute value that exceeds a threshold. That is, low-entropy bits have counters 108 with higher absolute values ​​because the counters 108 are incremented or decremented frequently. Conversely, high-entropy bits have counters 108 that are incremented and decremented to a more similar extent.

[0035] As an example, assume that a t-bit counter 108 is used and a threshold "T" is defined, where 0≦T≦1. The value C of the counter 108 x T * (2 t -1), the corresponding address bit is determined to be a low entropy bit and the bit value is predicted to be "1". x is (1-T) * (2 t If the entropy of the corresponding address bit is less than C −1, the corresponding address bit is determined to be a low entropy bit and the bit value is predicted to be “0”. x ≧(1-T) * (2 t -1), and C x ≦T * (2 t -1), it is determined that there is a corresponding address bit and the value is not predicted.

[0036] As another example, in some embodiments where each address bit corresponds to two counters 108 that are alternately incremented based on the value of the corresponding address bit, a low-entropy bit is identified by one counter 108 value being significantly larger than the other counter 108 value (e.g., the difference between the first counter 108 value and the second counter 108 value exceeds a threshold). Conversely, a high-entropy bit is identified by having similar values ​​for the first and second counters 108.

[0037] For further explanation, FIG. 4 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch, removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch, and transmitting 206 the one or more second transaction layer packets 208.

[0038] 4 differs from FIG. 2 in that the method of FIG. 4 also includes storing 402 a bit mask 404 indicating one or more low-entropy address bits in a first bit mask register 406. For example, if the address bit at index i is determined to be a low-entropy bit, the value of bit mask 404 at index i is set to “1.” Conversely, if the address bit at index i is determined to be a high-entropy bit, the value of bit mask 404 at index i is set to “0” or remains unchanged. For example, in some embodiments, compression unit 200 resets or zeroes out bit mask register 406 (e.g., every epoch). Thus, bit mask 404 indices for high-entropy bits need not be changed from their initialized “0” state.

[0039] 4 also includes storing 408 one or more predicted values ​​410 for one or more low-entropy bits in a first bit array register 412. For example, if the value of the low-entropy address bit at index i is predicted to be “1,” the value of the bit array (stored in the bit array register 412) at index i is set to “1.” As another example, if the value of the low-entropy address bit at index i is predicted to be “0,” the value of the bit array (stored in the bit array register 412) at index i is set to “0.” For high-entropy address bits, no values ​​are predicted, so no values ​​need to be set in the bit array register 412. In some embodiments, the bit array register 412 is reset (e.g., zeroed out, set to all NULL, or a default value) at each epoch.

[0040] For further explanation, FIG. 5 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch; storing 402 a bit mask 404 indicative of the one or more low-entropy address bits in a first bit mask register 406; storing 408 one or more predicted values ​​for the one or more low-entropy bits in a first bit array register 412; removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch; and transmitting 206 the one or more second transaction layer packets 208.

[0041] 5 differs from FIG. 4 in that the method of FIG. 5 also includes synchronizing 502 first bit mask register 406 and first bit array register 412 with second bit mask registers and second bit array registers of a receiver of one or more second transaction layer packets 208. For example, a decompression unit (e.g., decompression unit 114 of device 102b) includes second bit mask registers and second bit array registers to facilitate regenerating memory addresses from compressed memory addresses of received second transaction layer packets 208. Accordingly, compression unit 200 transmits a message or signal that causes the values ​​of first bit mask register 406 and first bit array register 412 to be stored in the second bit mask register and second bit array register, respectively.

[0042] For further explanation, FIG. 6 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch, removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch, and transmitting 206 the one or more second transaction layer packets 208.

[0043] 6 differs from FIG. 2 in that the method of FIG. 6 also includes sending 602 a signal 604 to one or more receivers 606 of the second transaction layer packets indicating that one or more second transaction layer packets 208 include one or more compressed memory addresses. For example, in some embodiments, sending 602 the signal 604 includes asserting a signal on a bus or other signal path from the compression unit 202 to the receiver 606 device. In other embodiments, sending 602 the signal includes sending a message indicating that the second transaction layer packet 208 includes a compressed memory address. In this way, the receiver 606 device knows to recreate the original memory address of the second transaction layer packet 208 from the compressed memory address.

[0044] For further explanation, FIG. 7 sets forth a flowchart illustrating an exemplary method for compressed addressing of transaction layer packets, including determining 202 (e.g., by compression unit 200) one or more low-entropy address bits in a plurality of first transaction layer packets over a first epoch, removing 204 the one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets 208 associated with a second epoch after the first epoch, and transmitting 206 the one or more second transaction layer packets 208.

[0045] 7 differs from FIG. 2 in that the method of FIG. 7 also includes regenerating 702 (e.g., by decompression unit 702) one or more memory addresses based on one or more compressed memory addresses in one or more second transaction layer packets 208 and one or more stored values ​​indicating the one or more removed low-entropy bits. In some embodiments, the one or more stored values ​​include a bit mask stored in a bit mask register and a bit array stored in a bit array register. For example, the bit mask register and the bit array register of decompression unit 700 are synchronized with another bit mask register and bit array register of compression unit 200. In some embodiments, regenerating 702 one or more memory addresses is performed in response to a signal from compression unit 200 indicating that second transaction layer packet 208 includes a compressed memory address.

[0046] In view of the above discussion, the reader will recognize that compressed addressing of transaction layer packets includes the following advantages: Improved performance of computing systems by reducing the size required to represent memory addresses in transaction layer packets. Improved performance of computing systems by allowing memory address bits reused through memory address compression to be used for other values ​​such as error correcting codes, thereby improving signal integrity without increasing packet size or transport overhead. Improved performance of computing systems by reducing packet transmission resource requirements by reducing the overall size needed to represent memory addresses.

[0047] The advantages and features of the present disclosure may be further described by the following statements.

[0048] Statement 1. A method for compressed addressing of transaction layer packets, the method including: determining one or more low entropy address bits in a plurality of first transaction layer packets over a first epoch; removing one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch; and transmitting the one or more second transaction layer packets.

[0049] Statement 2. The method of statement 1, wherein determining one or more low entropy address bits in the plurality of first transaction layer packets over the first epoch includes: maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets; modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and determining the one or more low entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0050] Statement 3. The method of any of statements 1-2, further including storing, in a first bit mask register, a bit mask indicating one or more low entropy address bits; and storing, in a first bit array register, one or more predicted values ​​for the one or more low entropy bits.

[0051] Statement 4. The method of any of Statements 1-3, further including synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets.

[0052] Statement 5. The method of any of statements 1-4, further including regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and the one or more stored values ​​indicating the one or more removed low entropy bits.

[0053] Statement 6. The method of any of statements 1 to 5, wherein the one or more stored values ​​include a second bit mask register that stores a bit mask indicating one or more low entropy bits, and a second bit array register that stores one or more values ​​for the one or more low entropy bits.

[0054] Statement 7. The method of any of statements 1-6, further comprising sending a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed memory addresses.

[0055] Statement 8. An apparatus for compressed addressing of transaction layer packets, the apparatus configured to perform steps including determining, over a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing the one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch; and transmitting the one or more second transaction layer packets.

[0056] Statement 9. The apparatus of statement 8, wherein determining one or more low entropy address bits in the plurality of first transaction layer packets over the first epoch includes: maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets; altering the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and determining the one or more low entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0057] Statement 10. The apparatus of statement 8 or 9, the step further comprising: storing, in a first bit mask register, a bit mask indicative of one or more low entropy address bits; and storing, in a first bit array register, one or more predicted values ​​for the one or more low entropy bits.

[0058] Statement 11. The apparatus of any of statements 8-10, wherein the step further includes synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of one or more second transaction layer packets.

[0059] Statement 12. The apparatus of any of statements 8-11, wherein the step further includes regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and the one or more stored values ​​indicating the one or more removed low entropy bits.

[0060] Statement 13. The apparatus of any of statements 8-12, wherein the one or more stored values ​​include a second bit mask register that stores a bit mask indicating one or more low entropy bits, and a second bit array register that stores one or more values ​​for the one or more low entropy bits.

[0061] Statement 14. The apparatus of any of statements 8-13, wherein the step further includes transmitting a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed memory addresses.

[0062] Statement 15. A system for compressed addressing of transaction layer packets, comprising: an apparatus configured to perform the steps of: determining, over a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing the one or more low entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch; and transmitting the one or more second transaction layer packets.

[0063] Statement 16. The system of statement 15, wherein determining one or more low entropy address bits in the plurality of first transaction layer packets over the first epoch includes: maintaining at least one corresponding counter for each address bit in the plurality of first transaction layer packets; modifying the corresponding at least one counter based on a bit value of each address bit in the plurality of first transaction layer packets; and determining the one or more low entropy address bits based on the corresponding at least one counter for each address bit in the plurality of first transaction layer packets.

[0064] Statement 17. The system of statement 15 or 16, further comprising: storing, in a first bit mask register, a bit mask indicative of one or more low entropy address bits; and storing, in a first bit array register, one or more predicted values ​​for the one or more low entropy bits.

[0065] Statement 18. The system of any of statements 15-17, wherein the step further includes synchronizing the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets.

[0066] Statement 19. The system of any of statements 15-18, wherein the step further includes regenerating the one or more memory addresses based on the one or more compressed memory addresses in the one or more second transaction layer packets and the one or more stored values ​​indicating the one or more removed low entropy bits.

[0067] Statement 20. The system of any of statements 15-19, wherein the one or more stored values ​​include a second bit mask register that stores a bit mask indicating one or more low entropy bits, and a second bit array register that stores one or more values ​​for the one or more low entropy bits.

[0068] Exemplary embodiments of the present disclosure are described primarily in the context of a fully functional computer system for compressed addressing of transaction layer packets. However, readers skilled in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and others as will occur to those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means is capable of performing the steps of the disclosed methods embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0069] The present disclosure may be a system, a method, and / or a computer program product, which may include a computer-readable storage medium having computer-readable program instructions for causing a processor to perform aspects of the present disclosure.

[0070] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as ridges in grooves with instructions recorded thereon, and any suitable combination of the above. As used herein, a computer-readable storage medium should not be construed as being an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), such as an electric wave or other freely propagating electromagnetic wave, or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0071] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or over a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage.

[0072] The computer-readable program instructions for carrying out the operations of the present disclosure can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can execute completely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to perform aspects of the present disclosure.

[0073] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, result in a machine that generates means for performing the functions / acts specified in the flowchart and / or block diagram blocks. These computer-readable program instructions can be stored on a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in the flowchart and / or block diagram blocks.

[0075] The computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram blocks.

[0076] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

[0077] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. An apparatus for compressed addressing of transaction layer packets, comprising: a first device including a compression unit; the first device includes logic; The logic is: receiving a plurality of first transaction layer packets over a first epoch; maintaining a corresponding counter for each address bit in the plurality of first transaction layer packets, the corresponding counter indicating whether the address bit is a low-entropy address bit having a low degree of variance; removing one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch; transmitting the one or more second transaction layer packets; configured to: Device.

2. The compression unit modifying the corresponding counter based on a bit value of each address bit in the plurality of first transaction layer packets; determining the one or more low-entropy address bits based on the corresponding counters for each address bit in the plurality of first transaction layer packets; and further comprising logic configured to:

10. The apparatus of claim 1.

3. The compression unit storing a bit mask indicative of the one or more low-entropy address bits in a first bit mask register; storing a predicted value for each of the one or more low-entropy address bits in a first bit array register; and further comprising logic configured to:

10. The apparatus of claim 1.

4. The compression unit and logic configured to synchronize the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of a recipient of the one or more second transaction layer packets.

4. The apparatus of claim 3.

5. The method further comprises: a bit mask register that stores a bit mask indicating the one or more low-entropy address bits; and a bit array register that stores a value for each of the one or more low-entropy address bits.

10. The apparatus of claim 1.

6. The compression unit and further comprising logic configured to send a signal to a recipient of the one or more second transaction layer packets indicating that the one or more second transaction layer packets include one or more compressed memory addresses.

10. The apparatus of claim 1.

7. 1. A system for compressed addressing of transaction layer packets, comprising: a first device and a second device, the first device connected to the second device via an interconnect, the first device comprising a compression unit; the first device includes logic; The logic is: receiving a plurality of first transaction layer packets over a first epoch; maintaining a corresponding counter for each address bit in the plurality of first transaction layer packets, the corresponding counter indicating whether the address bit is a low-entropy address bit having a low degree of variance; removing one or more low-entropy address bits from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch; transmitting the one or more second transaction layer packets; configured to: system.

8. The compression unit of the first device comprises: modifying the corresponding counter based on a bit value of each address bit in the plurality of first transaction layer packets; determining the one or more low-entropy address bits based on the corresponding counters for each address bit in the plurality of first transaction layer packets; determining the one or more low entropy address bits in the plurality of first transaction layer packets over the first epoch by using logic that: The system of claim 7.

9. The compression unit of the first device comprises: storing a bit mask indicative of the one or more low-entropy address bits in a first bit mask register; storing a predicted value for each of the one or more low-entropy address bits in a first bit array register; and further comprising logic configured to: The system of claim 7.

10. The compression unit of the first device comprises: and logic configured to synchronize the first bit mask register and the first bit array register with a second bit mask register and a second bit array register of the second device. The system of claim 9.

11. the second device comprises a decompression unit; the decompression unit includes logic; the logic is configured to regenerate the one or more memory addresses based on one or more compressed memory addresses in the one or more second transaction layer packets and one or more stored values ​​indicating the one or more removed low-entropy address bits. The system of claim 7.

12. the one or more stored values ​​include a bit mask register that stores a bit mask indicative of the one or more low-entropy address bits, and a bit array register that stores a value for each of the one or more low-entropy address bits. The system of claim 11.

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