Method for driving semiconductor device

Abstract

To provide a semiconductor device with suppressed breakage caused by current concentration.SOLUTION: A semiconductor device according to an embodiment includes: a transistor region that includes a semiconductor layer having a first surface and a second surface opposed to the first surface, a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer; and an adjacent region adjacent to the transistor region and including the semiconductor layer, and a third transistor having a third gate electrode electrically connected with the second gate electrode and provided on the second surface side of the semiconductor layer. A second conductivity type impurity concentration at a portion opposed to the third gate electrode, of the semiconductor layer is lower than a second conductivity type impurity concentration at a portion opposed to the second gate electrode, of the semiconductor layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An example of a power semiconductor device is an insulated gate bipolar transistor (IGBT). An IGBT has, for example, a p-type collector region, an n-type drift region, and a p-type base region provided on a collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film sandwiched between them. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, reverse-conducting IGBTs (RC-IGBTs), in which an IGBT and a freewheeling diode are formed on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode has the function of passing current in the opposite direction to the on-current of the IGBT. Forming the IGBT and the freewheeling diode on the same semiconductor chip has many advantages, including a reduction in chip size by sharing the termination area and the dispersion of heat-generating areas.

[0004] In an RC-IGBT, a boundary region that does not include the IGBT or diode is provided between the IGBT region containing the IGBT and the diode region containing the diode. The provision of the boundary region prevents interference between the IGBT and the diode, which would otherwise degrade the device characteristics of the RC-IGBT. However, there is a risk that current may concentrate at the edge of the IGBT region due to holes injected from the backside of the boundary region, potentially destroying the IGBT. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5417811 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device in which breakdown due to current concentration is suppressed. [Means for solving the problem]

[0007] Semiconductor device of an embodiment Drive method a transistor region including a semiconductor layer having a first surface and a second surface opposite to the first surface, a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer; and an adjacent region adjacent to the transistor region including the semiconductor layer and a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second surface side of the semiconductor layer. a driving method for a semiconductor device, the driving method including: changing the first transistor from an off state to an on state at a first time; changing the first transistor from an on state to an off state at a second time after the first time; changing the third transistor from an off state to an on state at a predetermined time after the first time, and then changing the second transistor from an off state to an on state; and changing the second transistor and the third transistor to an off state at a third time after the predetermined time and the second time. . [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is an explanatory diagram of a method for driving the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a schematic plan view of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of n-type. + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0011] In this specification, the distribution and absolute value of the impurity concentration in a semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS). The relative magnitude relationship between the impurity concentrations in two semiconductor regions can be determined using, for example, scanning capacitance microscopy (SCM). The distribution and absolute value of the impurity concentration can be measured using, for example, spreading resistance analysis (SRA). SCM and SRA can determine the relative magnitude relationship and absolute value of the carrier concentration in a semiconductor region. By assuming the activation rate of the impurities, the relative magnitude relationship between the impurity concentrations in two semiconductor regions, the distribution of the impurity concentrations, and the absolute value of the impurity concentrations can be determined from the measurement results of SCM and SRA.

[0012] (First embodiment) The semiconductor device of the first embodiment includes a transistor region including a semiconductor layer having a first surface and a second surface opposite to the first surface, a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer, and an adjacent region adjacent to the transistor region including a semiconductor layer and a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second surface side of the semiconductor layer, the third transistor having a threshold voltage whose absolute value is smaller than that of the second transistor.

[0013] The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a free wheel diode are formed on the same semiconductor chip. The RC-IGBT100 is an IGBT with a double-sided gate structure in which gate electrodes are provided on the front and back sides of the semiconductor layer. The following description will be given taking as an example a case in which the first conductivity type is n-type and the second conductivity type is p-type.

[0014] 1A and 1B are schematic plan views of a semiconductor device according to a first embodiment. Fig. 1A is a plan view of the semiconductor layer of an RC-IGBT 100 as seen from the front side. Fig. 1B is a plan view of the semiconductor layer of an RC-IGBT 100 as seen from the back side. Fig. 1 is a diagram showing the layout of the RC-IGBT 100.

[0015] The RC-IGBT 100 includes an IGBT region 100a, a diode region 100b, and a boundary region 100c. The RC-IGBT 100 also includes a first electrode pad 101 and a second electrode pad 102. The IGBT region 100a is an example of a transistor region. The boundary region 100c is an example of an adjacent region.

[0016] A boundary region 100c is provided between the IGBT region 100a and the diode region 100b. The boundary region 100c is adjacent to the IGBT region 100a. The boundary region 100c prevents the performance degradation of the RC-IGBT 100 from occurring due to interference between the operation of the IGBT in the IGBT region 100a and the operation of the diode in the element region.

[0017] The first electrode pad 101 is provided, for example, on the front surface side of the semiconductor layer, and the second electrode pad 102 is provided, for example, on the back surface side of the semiconductor layer.

[0018] 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along the line AA' in FIG.

[0019] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a dummy gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a dummy gate electrode 34, a front interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0020] The IGBT region 100a operates as an IGBT. The diode region 100b operates as a freewheeling diode. The freewheeling diode is, for example, a fast recovery diode (FRD).

[0021] The IGBT region 100a includes a first transistor having a first gate electrode 31 and a second transistor having a second gate electrode 32. The boundary region 100c includes a third transistor having a third gate electrode 33.

[0022] The first transistor is controlled by a voltage applied to a first gate electrode 31. The second transistor is controlled by a voltage applied to a second gate electrode 32. The third transistor is controlled by a voltage applied to a third gate electrode 33.

[0023] The first transistor is provided on the first face P1 side of the semiconductor layer 10. The first transistor has a trench gate structure in which a gate electrode is provided in a trench. The first transistor is an IGBT.

[0024] The second transistor is provided on the second surface P2 side of the semiconductor layer 10. The second transistor has a planar gate structure. The second transistor is a so-called backside transistor. The second transistor is an n-type Metal Oxide Field Effect Transistor (MOSFET) that uses electrons as carriers.

[0025] The third transistor is provided on the second surface P2 side of the semiconductor layer 10. The third transistor has a planar gate structure. The third transistor is a so-called backside transistor. The third transistor is an n-type MOSFET that uses electrons as carriers.

[0026] The first transistor, the second transistor, and the third transistor are not clearly separated from each other in structure. For example, the area surrounded by the dashed line X in FIG. 2 corresponds to one unit of the first transistor. Also, for example, the area surrounded by the dashed line Y in FIG. 2 corresponds to one unit of the second transistor. Also, for example, the area surrounded by the dashed line Z in FIG. 2 corresponds to one unit of the third transistor.

[0027] The semiconductor layer 10 includes a main gate trench 51 (first trench), a dummy gate trench 52, an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first collector region 64 (fourth semiconductor region), a p-type second collector region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78.

[0028] The upper electrode 12 is an example of a first electrode. The lower electrode 14 is an example of a second electrode. The main gate trench 51 is an example of a first trench. The first drain region 60 is an example of a sixth semiconductor region. The second drain region 62 is an example of a seventh semiconductor region. The first collector region 64 is an example of a fourth semiconductor region. The second collector region 66 is an example of a fifth semiconductor region. The drift region 70 is an example of a first semiconductor region. The base region 72 is an example of a second semiconductor region. The emitter region 74 is an example of a third semiconductor region.

[0029] The semiconductor layer 10 has a first surface P1 and a second surface P2 facing the first surface P1. The first surface P1 is the front surface of the semiconductor layer 10, and the second surface P2 is the back surface of the semiconductor layer 10. The semiconductor layer 10 is, for example, single crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0030] In this specification, a direction parallel to the first plane P1 is referred to as the "first direction." A direction parallel to the first plane P1 and perpendicular to the first direction is referred to as the "second direction." In this specification, "depth" is defined as the distance from the first plane P1 toward the second plane P2.

[0031] The upper electrode 12 is provided on the first face P1 side of the semiconductor layer 10. At least a portion of the upper electrode 12 contacts the first face P1 of the semiconductor layer 10.

[0032] The upper electrode 12 functions as an emitter electrode of the first transistor in the IGBT region 100a. The upper electrode 12 functions as an anode electrode of the diode in the diode region 100b. The upper electrode 12 is made of, for example, a metal.

[0033] In the IGBT region 100a, the upper electrode 12 is electrically connected to the emitter region 74. In the IGBT region 100a, the upper electrode 12 is in contact with the emitter region 74.

[0034] In the diode region 100b, the upper electrode 12 is electrically connected to the anode region 78. In the diode region 100b, the upper electrode 12 contacts the anode region 78.

[0035] An emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage is, for example, 0V.

[0036] The lower electrode 14 is provided on the second face P2 side of the semiconductor layer 10. At least a portion of the lower electrode 14 contacts the second face P2 of the semiconductor layer 10.

[0037] The lower electrode 14 functions as a collector electrode of the first transistor in the IGBT region 100a, and as a cathode electrode of the diode in the diode region 100b. The lower electrode 14 is made of, for example, a metal.

[0038] In the IGBT region 100a, the lower electrode 14 is electrically connected to the first collector region 64. In the IGBT region 100a, the lower electrode 14 is in contact with the first collector region 64.

[0039] In the diode region 100b, the lower electrode 14 is electrically connected to the cathode region 76. In the diode region 100b, the lower electrode 14 contacts the cathode region 76.

[0040] The bottom electrode 14 is electrically connected to the second collector region 66 at the boundary region 100c. The bottom electrode 14 contacts the second collector region 66 at the boundary region 100c.

[0041] A collector voltage (Vc) is applied to the lower electrode 14. The collector voltage is, for example, 200V or more and 6500V or less.

[0042] The drift region 70 is an n-type semiconductor region and is provided in the IGBT region 100a, the diode region 100b, and the boundary region 100c.

[0043] The drift region 70 serves as a path for an on-current when the first transistor is in an on-state. The drift region 70 is depleted when the IGBT is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT.

[0044] The drift region 70 serves as a path for an on-current when the diode is in an on-state, and is depleted when the diode is in an off-state, thereby maintaining the breakdown voltage of the diode.

[0045] The base region 72 is a p-type semiconductor region. The base region 72 is provided in the IGBT region 100a and the boundary region 100c. The base region 72 is provided between the drift region 70 and the first plane P1. The p-type impurity concentration of the base region 72 in the boundary region 100c may be the same as or different from the p-type impurity concentration of the base region 72 in the IGBT region 100a. The p-type impurity concentration of the base region 72 in the boundary region 100c may be the same as or different from the p-type impurity concentration of the anode region 78 in the diode region 100b.

[0046] An n-type inversion layer is formed in the region of the base region 72 facing the first gate electrode 31 when the first transistor is in an on-state. The base region 72 functions as a channel region of the first transistor. The base region 72 is electrically connected to the upper electrode 12. The base region 72 contacts the upper electrode 12 at a portion not shown.

[0047] The emitter region 74 is an n-type semiconductor region. The emitter region 74 is provided in the IGBT region 100a. The emitter region 74 is not provided in the diode region 100b or the boundary region 100c.

[0048] The emitter region 74 is provided in the IGBT region 100a between the base region 72 and the first plane P1. The n-type impurity concentration of the emitter region 74 is higher than the n-type impurity concentration of the drift region .

[0049] The emitter region 74 is electrically connected to the upper electrode 12. The emitter region 74 is in contact with the upper electrode 12. The emitter region 74 serves as a source of electrons when the first transistor is in an on state.

[0050] The first collector region 64 is a p-type semiconductor region. The first collector region 64 is provided in the IGBT region 100a. The first collector region 64 is provided between the drift region 70 and the second plane P2. The first collector region 64 is in contact with the second plane P2.

[0051] The first collector region 64 is electrically connected to the bottom electrode 14. The first collector region 64 is in contact with the bottom electrode 14. The first collector region 64 serves as a source of holes when the first transistor is in an on-state.

[0052] A part of the first collector region 64 faces the second gate electrode 32. In the first collector region 64 facing the second gate electrode 32, a channel of a second transistor controlled by the second gate electrode 32 is formed.

[0053] The second collector region 66 is a p-type semiconductor region. The second collector region 66 is provided in the boundary region 100c. The second collector region 66 is provided between the drift region 70 and the second surface P2. The second collector region 66 is in contact with the second surface P2.

[0054] The second collector region 66 is electrically connected to the bottom electrode 14. The second collector region 66 is in contact with the bottom electrode 14. The second collector region 66 serves as a source of holes when the first transistor is in an on-state.

[0055] A part of the second collector region 66 faces the third gate electrode 33. In the second collector region 66 facing the third gate electrode 33, a channel of a third transistor controlled by the third gate electrode 33 is formed.

[0056] The p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32. The collector region spanning the IGBT region 100a and the boundary region 100c may be either the first collector region 64 or the second collector region 66.

[0057] The first drain region 60 is an n-type semiconductor region. The first drain region 60 is provided in the IGBT region 100a. The first drain region 60 is provided between the first collector region 64 and the second plane P2. The first drain region 60 is in contact with the second plane P2.

[0058] A part of the first drain region 60 faces the second gate electrode 32. A part of the first drain region 60 contacts the lower electrode .

[0059] The first drain region 60 functions as the drain of the second transistor. The n-type impurity concentration of the first drain region 60 is higher than the n-type impurity concentration of the drift region 70.

[0060] The second drain region 62 is an n-type semiconductor region. The second drain region 62 is provided in the boundary region 100c. The second drain region 62 is provided between the second collector region 66 and the second face P2. The second drain region 62 is in contact with the second face P2.

[0061] A part of the second drain region 62 faces the second gate electrode 32. A part of the second drain region 62 contacts the lower electrode .

[0062] The second drain region 62 functions as the drain of the third transistor. The n-type impurity concentration of the second drain region 62 is higher than the n-type impurity concentration of the drift region 70.

[0063] The buffer region 68 is an n-type semiconductor region and is provided in the IGBT region 100a, the boundary region 100c, and the diode region 100b.

[0064] The buffer region 68 is provided between the drift region 70 and the first collector region 64. The buffer region 68 is provided between the drift region 70 and the first collector region 64. The buffer region 68 is provided between the drift region 70 and the cathode region 76.

[0065] A part of the buffer region 68 contacts the second plane P2. A part of the buffer region 68 faces the second gate electrode 32. A part of the buffer region 68 faces the third gate electrode 33.

[0066] The n-type impurity concentration of the buffer region 68 is higher than the n-type impurity concentration of the drift region 70 .

[0067] The buffer region 68 has a lower resistance than the drift region 70. By providing the buffer region 68, when the second transistor and the third transistor are turned on, the discharge of electrons from the drift region 70 to the lower electrode 14 via the second transistor and the third transistor is promoted.

[0068] The buffer region 68 also has the function of suppressing the extension of the depletion layer when the RC-IGBT 100 is in the off state. Note that it is also possible to configure the RC-IGBT 100 without providing the buffer region 68.

[0069] The cathode region 76 is an n-type semiconductor region. The cathode region 76 is provided in the diode region 100b. The cathode region 76 is provided between the buffer region 68 and the second face P2.

[0070] The n-type impurity concentration of the cathode region 76 is higher than the n-type impurity concentration of the buffer region 68 .

[0071] The cathode region 76 is electrically connected to the lower electrode 14. The cathode region 76 contacts the lower electrode 14.

[0072] The anode region 78 is a p-type semiconductor region. The anode region 78 is provided in the diode region 100b. The anode region 78 is provided between the drift region 70 and the first plane P1.

[0073] The anode region 78 is electrically connected to the upper electrode 12. The anode region 78 contacts the upper electrode 12.

[0074] The main gate trench 51 is provided in the IGBT region 100a. The main gate trench 51 is provided on the first face P1 side of the semiconductor layer 10 so as to contact the base region 72.

[0075] The main gate trench 51 is a groove provided in the semiconductor layer 10. The main gate trench 51 is a part of the semiconductor layer 10.

[0076] The main gate trench 51 extends in a first direction parallel to the first plane P1 in the first plane P1. The main gate trench 51 has a stripe shape. A plurality of main gate trenches 51 are repeatedly arranged in a second direction perpendicular to the first direction.

[0077] The main gate trench 51 penetrates the base region 72 and reaches the drift region 70 .

[0078] The first gate electrode 31 is provided in the IGBT region 100a. The first gate electrode 31 is provided on the first face P1 side of the semiconductor layer 10. The first gate electrode 31 is provided in the main gate trench 51.

[0079] The first gate electrode 31 is, for example, a semiconductor or a metal. The first gate electrode 31 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The first gate electrode 31 is electrically connected to the first electrode pad 101.

[0080] The first gate insulating film 21 is provided between the first gate electrode 31 and the semiconductor layer 10. The first gate insulating film 21 is provided between the first gate electrode 31 and the drift region 70, between the first gate electrode 31 and the base region 72, and between the first gate electrode 31 and the emitter region 74. The first gate insulating film 21 is in contact with the drift region 70, the base region 72, and the emitter region 74. The first gate insulating film 21 is made of, for example, silicon oxide.

[0081] The dummy gate trench 52 is provided in the boundary region 100c and the diode region 100b. The dummy gate trench 52 is provided on the first face P1 side of the semiconductor layer 10. Note that it is also possible to configure the semiconductor layer 10 so that the dummy gate trench 52 is not provided in the boundary region 100c or the diode region 100b.

[0082] The dummy gate trench 52 is a trench provided in the semiconductor layer 10. The dummy gate trench 52 is a part of the semiconductor layer 10.

[0083] The dummy gate trenches 52 extend in a first direction parallel to the first plane P1 in the first plane P1. The dummy gate trenches 52 have a stripe shape. The multiple dummy gate trenches 52 are repeatedly arranged in a second direction perpendicular to the first direction.

[0084] The dummy gate trench 52 penetrates the base region 72 and reaches the drift region 70. The dummy gate trench 52 penetrates the anode region 78 and reaches the drift region 70.

[0085] The dummy gate electrode 34 is provided in the dummy gate trench 52. The dummy gate electrode 34 is, for example, a semiconductor or a metal. The dummy gate electrode 34 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities.

[0086] The dummy gate electrode 34 is electrically connected to, for example, the upper electrode 12. It is also possible to put the dummy gate electrode 34 in a floating state, in which it is not fixed to a specific potential.

[0087] The dummy gate insulating film 24 is provided between the dummy gate electrode 34 and the semiconductor layer 10. In the boundary region 100c, the dummy gate insulating film 24 is provided between the dummy gate electrode 34 and the drift region 70 and between the dummy gate electrode 34 and the base region 72. In the diode region 100b, the dummy gate insulating film 24 is provided between the dummy gate electrode 34 and the drift region 70 and between the dummy gate electrode 34 and the anode region 78. The dummy gate insulating film 24 is made of, for example, silicon oxide.

[0088] The second gate electrode 32 is provided in the IGBT region 100a. The second gate electrode 32 is provided on the second surface side of the semiconductor layer .

[0089] The second gate electrode 32 is, for example, a semiconductor or a metal. The second gate electrode 32 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 32 is electrically connected to the second electrode pad 102.

[0090] The second gate insulating film 22 is provided between the second gate electrode 32 and the semiconductor layer 10. The second gate insulating film 22 is provided between the second gate electrode 32 and the first collector region 64, between the second gate electrode 32 and the first drain region 60, and between the second gate electrode 32 and the buffer region 68. The second gate insulating film 22 is in contact with the first collector region 64, the first drain region 60, and the buffer region 68. The second gate insulating film 22 is made of, for example, silicon oxide.

[0091] The third gate electrode 33 is provided in the boundary region 100c. The third gate electrode 33 is provided on the second surface side of the semiconductor layer .

[0092] The third gate electrode 33 is, for example, a semiconductor or a metal. The third gate electrode 33 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The third gate electrode 33 is electrically connected to the second electrode pad 102.

[0093] The third gate insulating film 23 is provided between the third gate electrode 33 and the semiconductor layer 10. The third gate insulating film 23 is provided between the third gate electrode 33 and the second collector region 66, between the third gate electrode 33 and the second drain region 62, and between the third gate electrode 33 and the buffer region 68. The third gate insulating film 23 is in contact with the second collector region 66, the second drain region 62, and the buffer region 68. The third gate insulating film 23 is made of, for example, silicon oxide.

[0094] The surface interlayer insulating layer 42 is provided between the first gate electrode 31 and the upper electrode 12. The surface interlayer insulating layer 42 electrically separates the first gate electrode 31 from the upper electrode 12. The surface interlayer insulating layer 42 is made of, for example, silicon oxide.

[0095] The back surface interlayer insulating layer 44 is provided between the second gate electrode 32 and the lower electrode 14. The back surface interlayer insulating layer 44 electrically isolates the second gate electrode 32 from the lower electrode 14. The back surface interlayer insulating layer 44 is provided between the third gate electrode 33 and the lower electrode 14. The back surface interlayer insulating layer 44 electrically isolates the third gate electrode 33 from the lower electrode 14. The back surface interlayer insulating layer 44 is made of, for example, silicon oxide.

[0096] The first electrode pad 101 is provided on the first surface P1 side of the semiconductor layer 10. The first electrode pad 101 is electrically connected to the first gate electrode 31. The first electrode pad 101 and the first gate electrode 31 are connected by, for example, a metal wiring (not shown). A first gate voltage (Vg1) is applied to the first electrode pad 101.

[0097] The second electrode pad 102 is provided on the second surface P2 side of the semiconductor layer 10. The second electrode pad 102 is electrically connected to the second gate electrode 32 and the third gate electrode 33. The second electrode pad 102 is connected to the second gate electrode 32 and the third gate electrode 33 by, for example, metal wiring (not shown). A second gate voltage (Vg2) is applied to the second electrode pad 102.

[0098] The absolute value of the threshold voltage of the third transistor of the RC-IGBT 100 is lower than the threshold voltage of the second transistor. In the RC-IGBT 100, the second transistor and the third transistor are n-type MOSFETs. Therefore, the threshold voltages of the second transistor and the third transistor are positive values. Therefore, the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0099] The threshold voltage of the third transistor having the third gate electrode 33 is, for example, two-thirds or less of the threshold voltage of the second transistor having the second gate electrode 32 .

[0100] The p-type impurity concentration of the second collector region 66 in the portion facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 in the portion facing the second gate electrode 32. Because the p-type impurity concentration of the second collector region 66 in the portion facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 in the portion facing the second gate electrode 32, the threshold voltage of the third transistor becomes lower than the threshold voltage of the second transistor.

[0101] Next, a method for driving the RC-IGBT 100 will be described.

[0102] 3 is an explanatory diagram of a method for driving the semiconductor device of the first embodiment. FIG. 3 is a timing chart of a first gate voltage (Vg1) applied to the first electrode pad 101 and a second gate voltage (Vg2) applied to the second electrode pad 102.

[0103] When the RC-IGBT 100 is in an off state, an emitter voltage (Ve) is applied to the upper electrode 12. For example, at time t0, the emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage (Ve) is, for example, 0 V.

[0104] When the RC-IGBT 100 is in the off state, a collector voltage (Vc) is applied to the lower electrode 14. The collector voltage (Vc) is, for example, not less than 200 V and not more than 6500 V. The collector-emitter voltage (Vce) applied between the lower electrode 14 and the upper electrode 12 is, for example, not less than 200 V and not more than 6500 V.

[0105] The first gate voltage (Vg1) is a voltage based on the emitter voltage (Ve), and the second gate voltage (Vg2) is a voltage based on the collector voltage (Vc).

[0106] First, the timing of change in the first gate voltage (Vg1) applied to the first transistor will be described.

[0107] For example, at time t0, a first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). The first turn-off voltage (Voff1) is a voltage equal to or lower than the threshold voltage at which the first transistor does not turn on.

[0108] The first turn-off voltage (Voff1) is, for example, 0 V or a negative voltage. Fig. 3 illustrates an example in which the first turn-off voltage (Voff1) is 0 V.

[0109] At time t1, a first turn-on voltage (Von1) is applied as a first gate voltage (Vg1). The first turn-on voltage (Von1) is a positive voltage that exceeds the threshold voltage of the first transistor. Figure 3 illustrates an example in which the first turn-on voltage (Von1) is 15V.

[0110] The RC-IGBT 100 is turned on by applying a first turn-on voltage (Von1) to the first transistor. The RC-IGBT 100 is turned on at time t1.

[0111] By applying a first turn-on voltage (Von1) to the first transistor, an n-type inversion layer is formed in the vicinity of the interface between the p-type base region 72 and the first gate insulating film 21. By forming the n-type inversion layer, electrons are injected from the n-type emitter region 74 into the n-type drift region 70 through the n-type inversion layer.

[0112] The electrons injected into the n-type drift region 70 forward bias the pn junctions formed between the n-type buffer region 68 and the p-type first collector region 64, and between the n-type buffer region 68 and the p-type second collector region 66. The electrons reach the bottom electrode 14 and cause holes to be injected from the p-type first collector region 64 and the p-type second collector region 66. Therefore, the RC-IGBT 100 is turned on.

[0113] At time t2, a first turn-off voltage (Voff1) is applied as a first gate voltage (Vg1). By applying the first turn-off voltage (Voff1) to the first transistor, the RC-IGBT 100 is turned off. Between time t1 and time t2, the RC-IGBT 100 is in an on state.

[0114] Next, the timing of change in the second gate voltage (Vg2) applied to the second and third transistors, which are backside transistors, will be described.

[0115] For example, at time t0, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) is a voltage equal to or lower than the threshold voltage at which the second transistor and the third transistor are not turned on.

[0116] The second turn-off voltage (Voff2) is, for example, 0 V or a negative voltage. Fig. 3 illustrates an example in which the second turn-off voltage (Voff2) is 0 V.

[0117] At time tx after time t1, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) is a positive voltage that exceeds the threshold voltages of the second transistor and the third transistor. Figure 3 illustrates an example where the second turn-on voltage (Von2) is 15V.

[0118] Note that time tx may be before time t2 or after time t2. Fig. 3 illustrates the case where time tx is before time t2.

[0119] By applying a second turn-on voltage (Von2) to the second transistor, an n-type inversion layer is formed near the interface between the p-type first collector region 64 and the second gate insulating film 22. Furthermore, by applying a second turn-on voltage (Von2) to the third transistor, an n-type inversion layer is formed near the interface between the p-type second collector region 66 and the third gate insulating film 23.

[0120] The formation of an n-type inversion layer near the interface between the p-type first collector region 64 and the second gate insulating film 22 forms a path for electrons to be discharged from the n-type buffer region 68 of the IGBT region 100a through the n-type inversion layer and the n-type first drain region 60 to the lower electrode 14.

[0121] Furthermore, an n-type inversion layer is formed near the interface between the p-type second collector region 66 and the third gate insulating film 23, thereby forming a path for electrons to be discharged from the n-type buffer region 68 in the boundary region 100c through the n-type inversion layer and the n-type second drain region 62 to the lower electrode 14.

[0122] That is, a state in which the n-type buffer region 68 in the IGBT region 100a and the boundary region 100c and the lower electrode 14 are short-circuited, that is, a so-called anode short occurs.

[0123] The occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 of the IGBT region 100a through the p-type first collector region 64 to the lower electrode 14. This suppresses the injection of holes from the p-type first collector region 64 into the drift region 70 of the IGBT region 100a.

[0124] Similarly, the occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 in the boundary region 100c through the p-type second collector region 66 to the lower electrode 14. This suppresses the injection of holes from the p-type second collector region 66 into the drift region 70 in the boundary region 100c.

[0125] In the RC-IGBT 100 of the first embodiment, the threshold voltage of the third transistor in the boundary region 100c is lower than the threshold voltage of the second transistor in the IGBT region 100a. Therefore, when the second turn-on voltage (Von2) is applied simultaneously to the second gate electrode 32 and the third gate electrode 33 at time tx, the third transistor, which has the lower threshold voltage, turns on before the second transistor.

[0126] Therefore, the injection of holes into the drift region 70 in the boundary region 100c is suppressed prior to the injection of holes into the drift region 70 in the IGBT region 100a. Therefore, the amount of holes in the drift region 70 in the boundary region 100c decreases prior to the amount of holes in the drift region 70 in the IGBT region 100a.

[0127] After that, at time t3, the second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2) to turn off the second transistor and the third transistor.

[0128] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0129] The RC-IGBT 100 of the first embodiment includes a second transistor as a backside transistor on the backside of the semiconductor layer 10 in the IGBT region 100a. When the RC-IGBT 100 is turned off, the second transistor is turned on to suppress the injection of holes into the drift region 70 in the IGBT region 100a. By suppressing the injection of holes into the drift region 70, the turn-off loss is reduced compared to when the backside transistor is not included. This allows the RC-IGBT 100 to reduce its power consumption.

[0130] Furthermore, the RC-IGBT 100 of the first embodiment has a boundary region 100c, which does not include a first transistor or a diode, between the IGBT region 100a and the diode region 100b. The boundary region 100c prevents the operation of the IGBT in the IGBT region 100a from interfering with the operation of the diode in the element region, thereby preventing the deterioration of the characteristics of the RC-IGBT 100. For example, it prevents the recovery loss of the diode from increasing due to the influence of carriers injected from the IGBT region 100a during the recovery operation of the diode.

[0131] When the RC-IGBT 100 is in the on state, an on-current also flows between the upper electrode 12 and the lower electrode 14 in the boundary region 100c. Therefore, when the RC-IGBT 100 is in the on state, carriers also accumulate in the drift region 70 in the boundary region 100c. In other words, when the RC-IGBT 100 is in the on state, carriers spread to the boundary region 100c on the surface where no first transistor exists.

[0132] When the RC-IGBT 100 is turned off, it is necessary to discharge the carriers accumulated in the drift region 70 of the boundary region 100c. However, there is no discharge path for the carriers on the surface side of the boundary region 100c. Therefore, the carriers are concentrated and discharged at the edge of the IGBT region 100a. This causes current concentration at the edge of the IGBT region 100a. This current concentration may cause damage to the RC-IGBT 100.

[0133] The RC-IGBT 100 of the first embodiment includes a third transistor on the back surface side of the semiconductor layer 10 in the boundary region 100c, which has a lower threshold voltage and therefore starts operating before the second transistor. By turning on the third transistor at time tx, the injection of holes into the drift region 70 in the boundary region 100c is suppressed prior to the injection of holes into the drift region 70 in the IGBT region 100a. Therefore, the number of holes in the drift region 70 in the boundary region 100c decreases prior to the decrease in the number of holes in the drift region 70 in the IGBT region 100a.

[0134] This can prevent current concentration from occurring at the end of the IGBT region 100a during the turn-off operation of the RC-IGBT 100. This can prevent the RC-IGBT 100 from being destroyed by current concentration.

[0135] From the viewpoint of suppressing destruction of the RC-IGBT 100 due to current concentration, it is preferable that the threshold voltage of the third transistor having the third gate electrode 33 is not more than two-thirds of the threshold voltage of the second transistor having the second gate electrode 32, and more preferably not more than one-half.

[0136] The first modified example of the semiconductor device of the first embodiment differs from the semiconductor device of the first embodiment in that the thickness of the third gate insulating film 23 is thinner than the thickness of the second gate insulating film 22. In the first modified example of the semiconductor device of the first embodiment, for example, the p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32.

[0137] In the first modified example of the semiconductor device of the first embodiment, the thickness of the third gate insulating film 23 is thinner than the thickness of the second gate insulating film 22, so that the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0138] The second modification of the semiconductor device of the first embodiment differs from the semiconductor device of the first embodiment in that the channel length of the third transistor is shorter than the channel length of the second transistor. Specifically, for example, the distance in the second direction between the second drain region 62 and the buffer region 68 in the boundary region 100c is shorter than the distance in the second direction between the first drain region 60 and the buffer region 68 in the IGBT region 100a. In the second modification of the semiconductor device of the first embodiment, for example, the p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is equal to the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32.

[0139] In the second modification of the semiconductor device of the first embodiment, the channel length of the third transistor is made shorter than the channel length of the second transistor, and the threshold voltage of the third transistor becomes lower than the threshold voltage of the second transistor due to the short channel effect.

[0140] As described above, according to the first embodiment and the modified example, an RC-IGBT in which breakdown due to current concentration is suppressed can be realized.

[0141] (Second embodiment) The semiconductor device of the second embodiment includes a transistor region including a semiconductor layer having a first surface and a second surface opposite to the first surface, a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer, and an adjacent region adjacent to the transistor region including a semiconductor layer and a third transistor electrically connected to the second gate electrode, the third gate electrode having an occupancy rate in a predetermined area higher than the occupancy rate in a predetermined area of ​​the second gate electrode, and the third transistor having a third gate electrode provided on the second surface side of the semiconductor layer.

[0142] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the occupancy rate of the third gate electrode in a predetermined area is higher than the occupancy rate of the second gate electrode in a predetermined area. Hereinafter, some of the content that overlaps with the first embodiment may be omitted.

[0143] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a free wheel diode are formed on the same semiconductor chip. The RC-IGBT200 is an IGBT with a double-sided gate structure in which gate electrodes are provided on the front and back sides of the semiconductor layer. The following description will be given taking as an example a case in which the first conductivity type is n-type and the second conductivity type is p-type.

[0144] Fig. 4 is a schematic cross-sectional view of the semiconductor device of the second embodiment, which corresponds to Fig. 2 of the semiconductor device of the first embodiment.

[0145] The RC-IGBT 200 of the second embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a dummy gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a dummy gate electrode 34, a front interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0146] The semiconductor layer 10 includes a main gate trench 51 (first trench), a dummy gate trench 52, an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first collector region 64 (fourth semiconductor region), a p-type second collector region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78.

[0147] In the RC-IGBT 200, the occupancy rate of the third gate electrodes 33 in the boundary region 100c in a given area is higher than the occupancy rate of the second gate electrodes 32 in the IGBT region 100a in the given area. In other words, the density of the third gate electrodes 33 in the boundary region 100c is higher than the density of the second gate electrodes 32 in the IGBT region 100a. That is, the density of the third transistors in the boundary region 100c is higher than the density of the second transistors in the IGBT region 100a.

[0148] In the RC-IGBT 200, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the occupancy rate of the third gate electrodes 33 in a given area of ​​the boundary region 100c becomes higher than the occupancy rate of the second gate electrodes 32 in the IGBT region 100a in the given area.

[0149] The predetermined area is an area that can include the boundary region 100c on the second surface P2. The predetermined area is, for example, an area of ​​50 μm×50 μm.

[0150] The proportion of the third gate electrode 33 in the boundary region 100c in a given area is, for example, 1.5 times or more the proportion of the second gate electrode 32 in the IGBT region 100a in the given area.

[0151] In the RC-IGBT 200, for example, the threshold voltage of the third transistor and the threshold voltage of the second transistor are the same. In the RC-IGBT 200, for example, the p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is the same as the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32.

[0152] The RC-IGBT 200 is driven by the driving method shown in FIG. 3 of the first embodiment.

[0153] At time tx, a second turn-on voltage (Von2) is applied to the second transistor and the third transistor, causing an anode short circuit, similar to the RC-IGBT 100 of the first embodiment.

[0154] The occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 of the IGBT region 100a through the p-type first collector region 64 to the lower electrode 14. This suppresses the injection of holes from the p-type first collector region 64 into the drift region 70 of the IGBT region 100a.

[0155] Similarly, the occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 in the boundary region 100c through the p-type second collector region 66 to the lower electrode 14. This suppresses the injection of holes from the p-type second collector region 66 into the drift region 70 in the boundary region 100c.

[0156] In the RC-IGBT 200 of the second embodiment, the density of the third transistors in the boundary region 100c is higher than the density of the second transistors in the IGBT region 100a. Therefore, when the second turn-on voltage (Von2) is applied simultaneously to the second gate electrode 32 and the third gate electrode 33 at time tx, the decrease in the amount of holes injected into the drift region 70 in the boundary region 100c becomes larger than the decrease in the amount of holes injected into the drift region 70 in the IGBT region 100a. Therefore, the amount of holes in the drift region 70 in the boundary region 100c decreases before the amount of holes in the drift region 70 in the IGBT region 100a decreases.

[0157] This can prevent current concentration from occurring at the end of the IGBT region 100a during the turn-off operation of the RC-IGBT 200. This can prevent the RC-IGBT 200 from being destroyed by current concentration.

[0158] In order to prevent the destruction of the RC-IGBT 200 due to current concentration, the occupancy rate of the third gate electrode 33 in the boundary region 100c in a given area is preferably, for example, 1.5 times or more, and more preferably 2 times or more, of the occupancy rate of the second gate electrode 32 in the IGBT region 100a in the given area.

[0159] As described above, according to the second embodiment, an RC-IGBT in which breakdown due to current concentration is suppressed can be realized.

[0160] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the semiconductor layer further includes a second trench provided on the second surface side and a third trench provided on the second surface side, the second gate electrode is provided in the second trench, and the third gate electrode is provided in the third trench. Hereinafter, some description of content that overlaps with the first or second embodiment may be omitted.

[0161] The semiconductor device of the third embodiment is an RC-IGBT 300 in which an IGBT and a free wheel diode are formed on the same semiconductor chip. The RC-IGBT 300 is an IGBT with a double-sided gate structure in which gate electrodes are provided on the front and back sides of the semiconductor layer. The following description will be given taking as an example a case in which the first conductivity type is n-type and the second conductivity type is p-type.

[0162] Fig. 5 is a schematic cross-sectional view of a semiconductor device according to a third embodiment, which corresponds to Fig. 2 of the semiconductor device according to the first embodiment.

[0163] The RC-IGBT 300 of the third embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a dummy gate insulating film 24, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a dummy gate electrode 34, a front interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0164] In the semiconductor layer 10, a main gate trench 51 (first trench), a dummy gate trench 52, a first back surface trench 53 (second trench), a second back surface trench 54 (third trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first collector region 64 (fourth semiconductor region), a p-type second collector region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), an n-type cathode region 76, and a p-type anode region 78 are provided.

[0165] The main gate trench 51 is an example of a first trench. The first back surface trench 53 is an example of a second trench. The second back surface trench 54 is an example of a third trench.

[0166] The first transistor is provided on the first face P1 side of the semiconductor layer 10. The first transistor has a trench gate structure in which a gate electrode is provided in a trench. The first transistor is an IGBT.

[0167] The second transistor is provided on the second face P2 side of the semiconductor layer 10. The second transistor has a trench gate structure. The second transistor is a so-called backside transistor. The second transistor is an n-type MOSFET that uses electrons as carriers.

[0168] The third transistor is provided on the second face P2 side of the semiconductor layer 10. The third transistor has a trench gate structure. The third transistor is a so-called backside transistor. The third transistor is an n-type MOSFET that uses electrons as carriers.

[0169] The first transistor, the second transistor, and the third transistor are not clearly separated from each other in structure. For example, the area surrounded by the dashed line X in FIG. 5 corresponds to one unit of the first transistor. Also, for example, the area surrounded by the dashed line Y in FIG. 5 corresponds to one unit of the second transistor. Also, for example, the area surrounded by the dashed line Z in FIG. 5 corresponds to one unit of the third transistor.

[0170] In the RC-IGBT 300, the occupancy rate of the third gate electrode 33 in the boundary region 100c in a given area is higher than the occupancy rate of the second gate electrode 32 in the IGBT region 100a in the given area. That is, the density of the third transistors in the boundary region 100c is higher than the density of the second transistors in the IGBT region 100a.

[0171] In the RC-IGBT 300, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the occupancy rate of the third gate electrodes 33 in a given area of ​​the boundary region 100c becomes higher than the occupancy rate of the second gate electrodes 32 in the IGBT region 100a in the given area.

[0172] The RC-IGBT 300 is driven by the driving method shown in FIG. 3 of the first embodiment.

[0173] In the RC-IGBT 300 of the third embodiment, the density of the third transistors in the boundary region 100c is higher than the density of the second transistors in the IGBT region 100a. Therefore, similar to the RC-IGBT 200 of the second embodiment, current concentration at the end of the IGBT region 100a can be suppressed during the turn-off operation of the RC-IGBT 300. Therefore, damage to the RC-IGBT 300 due to current concentration can be suppressed.

[0174] As described above, according to the third embodiment, an RC-IGBT in which breakdown due to current concentration is suppressed can be realized.

[0175] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the semiconductor device of the fourth embodiment includes a termination region. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0176] The semiconductor device of the fourth embodiment is an IGBT 400 with a double-sided gate structure having gate electrodes on the front and back sides of a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type.

[0177] 6A and 6B are schematic plan views of a semiconductor device according to a fourth embodiment. Fig. 6A is a plan view of the semiconductor layer of the IGBT 400 as seen from the front side. Fig. 6B is a plan view of the semiconductor layer of the IGBT 400 as seen from the back side. Fig. 6A is a diagram showing the layout of the IGBT 400.

[0178] The IGBT 400 includes an IGBT region 400a and a termination region 400b. The termination region 400b surrounds the IGBT region 400a. The termination region 400b is adjacent to the IGBT region 400a.

[0179] The IGBT 400 also includes a first electrode pad 101 and a second electrode pad 102. The first electrode pad 101 is provided, for example, on the front surface side of the semiconductor layer. The second electrode pad 102 is provided, for example, on the back surface side of the semiconductor layer.

[0180] The IGBT region 400a is an example of a transistor region, and the termination region 400b is an example of an adjacent region.

[0181] Fig. 7 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along line BB' in Fig. 6(a).

[0182] The IGBT 400 of the fourth embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a front interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0183] The IGBT region 400a operates as an IGBT. The termination region 400b has a function of suppressing a decrease in breakdown voltage at the end of the IGBT region 400a.

[0184] IGBT region 400a includes a first transistor having a first gate electrode 31 and a second transistor having a second gate electrode 32. Termination region 400b includes a third transistor having a third gate electrode 33.

[0185] The first transistor is controlled by a voltage applied to a first gate electrode 31. The second transistor is controlled by a voltage applied to a second gate electrode 32. The third transistor is controlled by a voltage applied to a third gate electrode 33.

[0186] The first transistor is provided on the first face P1 side of the semiconductor layer 10. The first transistor has a trench gate structure in which a gate electrode is provided in a trench. The first transistor is an IGBT.

[0187] The second transistor is provided on the second surface P2 side of the semiconductor layer 10. The second transistor has a planar gate structure. The second transistor is a so-called backside transistor. The second transistor is an n-type MOSFET that uses electrons as carriers.

[0188] The third transistor is provided on the second surface P2 side of the semiconductor layer 10. The third transistor has a planar gate structure. The third transistor is a so-called backside transistor. The third transistor is an n-type MOSFET that uses electrons as carriers.

[0189] The first transistor, the second transistor, and the third transistor are not clearly separated from each other in structure. For example, the area surrounded by the dashed line X in FIG. 7 corresponds to one unit of the first transistor. Also, for example, the area surrounded by the dashed line Y in FIG. 7 corresponds to one unit of the second transistor. Also, for example, the area surrounded by the dashed line Z in FIG. 7 corresponds to one unit of the third transistor.

[0190] The semiconductor layer 10 includes a main gate trench 51 (first trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first collector region 64 (fourth semiconductor region), a p-type second collector region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), a p-type intermediate region 80, and a p-type guard ring region 82.

[0191] The upper electrode 12 is an example of a first electrode. The lower electrode 14 is an example of a second electrode. The main gate trench 51 is an example of a first trench. The first drain region 60 is an example of a sixth semiconductor region. The second drain region 62 is an example of a seventh semiconductor region. The first collector region 64 is an example of a fourth semiconductor region. The second collector region 66 is an example of a fifth semiconductor region. The drift region 70 is an example of a first semiconductor region. The base region 72 is an example of a second semiconductor region. The emitter region 74 is an example of a third semiconductor region.

[0192] The semiconductor layer 10 has a first surface P1 and a second surface P2 opposite to the first surface P1.

[0193] The upper electrode 12 is provided on the first face P1 side of the semiconductor layer 10. The upper electrode 12 functions as an emitter electrode of the first transistor.

[0194] In the IGBT region 400a, the upper electrode 12 is electrically connected to the emitter region 74. An emitter voltage (Ve) is applied to the upper electrode 12. The emitter voltage is, for example, 0V.

[0195] The lower electrode 14 is provided on the second face P2 side of the semiconductor layer 10. The lower electrode 14 functions as a collector electrode of the first transistor in the IGBT region 400a. The lower electrode 14 is electrically connected to the first collector region 64 in the IGBT region 400a.

[0196] In termination region 400b, bottom electrode 14 is electrically connected to second collector region 66. A collector voltage (Vc) is applied to bottom electrode 14. The collector voltage is, for example, not less than 200V and not more than 6500V.

[0197] The drift region 70 is an n-type semiconductor region and is provided in the IGBT region 400a and the termination region 400b.

[0198] The base region 72 is a p-type semiconductor region and is provided in the IGBT region 400a.

[0199] Emitter region 74 is an n-type semiconductor region. Emitter region 74 is provided in IGBT region 400a. Emitter region 74 is not provided in termination region 400b.

[0200] The emitter region 74 is electrically connected to the upper electrode 12. The emitter region 74 is in contact with the upper electrode 12.

[0201] The first collector region 64 is a p-type semiconductor region and is provided in the IGBT region 400a.

[0202] The first collector region 64 is electrically connected to the lower electrode 14. The first collector region 64 contacts the lower electrode 14.

[0203] A part of the first collector region 64 faces the second gate electrode 32. In the first collector region 64 facing the second gate electrode 32, a channel of a second transistor controlled by the second gate electrode 32 is formed.

[0204] Second collector region 66 is a p-type semiconductor region and is provided in termination region 400b.

[0205] The second collector region 66 is electrically connected to the bottom electrode 14. The second collector region 66 is in contact with the bottom electrode 14.

[0206] A part of the second collector region 66 faces the third gate electrode 33. In the second collector region 66 facing the third gate electrode 33, a channel of a third transistor controlled by the third gate electrode 33 is formed.

[0207] The p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32 .

[0208] The first drain region 60 is an n-type semiconductor region and is provided in the IGBT region 400a.

[0209] Second drain region 62 is an n-type semiconductor region and is provided in termination region 400b.

[0210] The buffer region 68 is an n-type semiconductor region and is provided in the IGBT region 400a and the termination region 400b.

[0211] The p-type intermediate region 80 is provided in the termination region 400b. The intermediate region 80 is provided between the drift region 70 and the first plane P1. The intermediate region 80 surrounds the IGBT region 400a.

[0212] A p-type guard ring region 82 is provided in the termination region 400b. The guard ring region 82 is provided between the drift region 70 and the first plane P1. The guard ring region 82 surrounds the intermediate region 80. For example, a plurality of guard ring regions 82 may be provided.

[0213] By providing intermediate region 80 and guard ring region 82, the electric field strength at the end of termination region 400b is reduced, and a decrease in breakdown voltage when IGBT 400 is in the off state is suppressed.

[0214] The main gate trench 51 is provided in the IGBT region 400a.

[0215] The first gate electrode 31 is provided in the IGBT region 400a. The first gate electrode 31 is provided in the main gate trench 51. The first gate electrode 31 is electrically connected to the first electrode pad 101.

[0216] The first gate insulating film 21 is provided between the first gate electrode 31 and the semiconductor layer 10.

[0217] The second gate electrode 32 is provided in the IGBT region 400a. The second gate electrode 32 is provided on the second surface side of the semiconductor layer 10. The second gate electrode 32 is electrically connected to the second electrode pad 102.

[0218] The second gate insulating film 22 is provided between the second gate electrode 32 and the semiconductor layer 10 .

[0219] The third gate electrode 33 is provided in the termination region 400b. The third gate electrode 33 is provided on the second surface side of the semiconductor layer 10. The third gate electrode 33 is electrically connected to the second electrode pad 102.

[0220] The third gate insulating film 23 is provided between the third gate electrode 33 and the semiconductor layer 10.

[0221] The surface interlayer insulating layer 42 is provided between the first gate electrode 31 and the upper electrode 12 .

[0222] The back surface interlayer insulating layer 44 is provided between the second gate electrode 32 and the lower electrode 14. The back surface interlayer insulating layer 44 is provided between the third gate electrode 33 and the lower electrode 14.

[0223] The first electrode pad 101 is provided on the first surface P1 side of the semiconductor layer 10. The first electrode pad 101 is electrically connected to the first gate electrode 31. The first electrode pad 101 and the first gate electrode 31 are connected by, for example, a metal wiring (not shown). A first gate voltage (Vg1) is applied to the first electrode pad 101.

[0224] The second electrode pad 102 is provided on the second surface P2 side of the semiconductor layer 10. The second electrode pad 102 is electrically connected to the second gate electrode 32 and the third gate electrode 33. The second electrode pad 102 is connected to the second gate electrode 32 and the third gate electrode 33 by, for example, metal wiring (not shown). A second gate voltage (Vg2) is applied to the second electrode pad 102.

[0225] The threshold voltage of the third transistor of the IGBT 400 is lower than the threshold voltage of the second transistor. The threshold voltage of the third transistor having the third gate electrode 33 is lower than the threshold voltage of the second transistor having the second gate electrode 32. The threshold voltage of the third transistor having the third gate electrode 33 is, for example, two-thirds or less of the threshold voltage of the second transistor having the second gate electrode 32.

[0226] The p-type impurity concentration of the second collector region 66 in the portion facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 in the portion facing the second gate electrode 32. Since the p-type impurity concentration of the second collector region 66 in the portion facing the third gate electrode 33 is lower than the p-type impurity concentration of the first collector region 64 in the portion facing the second gate electrode 32, the threshold voltage of the third transistor becomes lower than the threshold voltage of the second transistor.

[0227] Next, a method for driving the IGBT 400 will be described.

[0228] The IGBT 400 is driven by the driving method shown in FIG. 3 of the first embodiment.

[0229] At time tx, a second turn-on voltage (Von2) is applied to the second transistor and the third transistor, causing an anode short circuit, similar to the RC-IGBT 100 of the first embodiment.

[0230] The occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 of the IGBT region 400a through the p-type first collector region 64 to the lower electrode 14. This suppresses the injection of holes from the p-type first collector region 64 into the drift region 70 of the IGBT region 400a.

[0231] Similarly, the occurrence of an anode short prevents electrons from passing from n-type buffer region 68 of termination region 400b through p-type second collector region 66 to bottom electrode 14. This suppresses the injection of holes from p-type second collector region 66 into drift region 70 of termination region 400b.

[0232] The IGBT 400 of the fourth embodiment includes a second transistor as a backside transistor on the backside of the semiconductor layer 10 in the IGBT region 400a. By turning on the second transistor during the turn-off operation of the IGBT 400, the turn-off loss is reduced. Therefore, the power consumption of the IGBT 400 can be reduced.

[0233] Furthermore, the IGBT 400 of the fourth embodiment is provided with a termination region 400b around the IGBT region 400a. The termination region 400b is provided with an intermediate region 80 and a guard ring region 82. By providing the intermediate region 80 and the guard ring region 82, the electric field strength at the end of the IGBT region 400a is reduced, and a reduction in the breakdown voltage when the IGBT 400 is in the off state is suppressed.

[0234] When the IGBT 400 is in the on state, an on-current also flows between the upper electrode 12 and the lower electrode 14 of the termination region 400b. Therefore, when the IGBT 400 is in the on state, carriers also accumulate in the drift region 70 of the termination region 400b. In other words, when the IGBT 400 is in the on state, carriers spread to the termination region 400b, where no first transistor exists on the surface.

[0235] When the IGBT 400 is turned off, it is necessary to discharge the carriers accumulated in the drift region 70 of the termination region 400b. However, there is no carrier discharge path on the surface side of the termination region 400b. As a result, the carriers are concentrated and discharged at the edge of the IGBT region 400a. This causes current concentration at the edge of the IGBT region 400a. This current concentration may cause damage to the IGBT 400.

[0236] The IGBT 400 of the fourth embodiment includes a third transistor on the back surface side of the semiconductor layer 10 in the termination region 400b, which has a lower threshold voltage and therefore starts operating before the second transistor. By turning on the third transistor at time tx, the injection of holes into the drift region 70 in the termination region 400b is suppressed prior to the injection of holes into the drift region 70 in the IGBT region 400a. Therefore, the number of holes in the drift region 70 in the termination region 400b decreases before the number of holes in the drift region 70 in the IGBT region 400a decreases.

[0237] This can prevent current concentration from occurring at the end of the IGBT region 400a during the turn-off operation of the IGBT 400. This can prevent the IGBT 400 from being destroyed by current concentration.

[0238] From the viewpoint of suppressing destruction of the IGBT 400 due to current concentration, it is preferable that the threshold voltage of the third transistor having the third gate electrode 33 is not more than two-thirds of the threshold voltage of the second transistor having the second gate electrode 32, and more preferably not more than one-half.

[0239] It should be noted that by making the thickness of the third gate insulating film 23 thinner than the thickness of the second gate insulating film 22, it is also possible to make the threshold voltage of the third transistor lower than the threshold voltage of the second transistor.

[0240] Furthermore, by making the channel length of the third transistor shorter than the channel length of the second transistor, the threshold voltage of the third transistor can be made lower than the threshold voltage of the second transistor.

[0241] As described above, according to the fourth embodiment, an IGBT in which breakdown due to current concentration is suppressed can be realized.

[0242] (Fifth embodiment) A semiconductor device of a fifth embodiment includes a transistor region including a semiconductor layer having a first surface and a second surface opposite to the first surface, a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, and a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer, and an adjacent region adjacent to the transistor region including a semiconductor layer and a third transistor electrically connected to the second gate electrode, the third gate electrode having an occupancy rate in a predetermined area higher than the occupancy rate in a predetermined area of ​​the second gate electrode, and the third transistor having a third gate electrode provided on the second surface side of the semiconductor layer.

[0243] The semiconductor device of the fifth embodiment differs from the semiconductor device of the fourth embodiment in that the occupancy rate of the third gate electrode in a given area is higher than the occupancy rate of the second gate electrode in a given area. Hereinafter, some of the content that overlaps with the fourth embodiment may be omitted.

[0244] The semiconductor device of the fifth embodiment is an IGBT 500 with a double-sided gate structure having gate electrodes on the front and back sides of a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type.

[0245] The IGBT 500 includes an IGBT region 400a and a termination region 400b, similar to the IGBT 400 of the fourth embodiment. The termination region 400b surrounds the IGBT region 400a. The termination region 400b is adjacent to the IGBT region 400a.

[0246] Fig. 8 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment, which corresponds to Fig. 7 of the semiconductor device of the fourth embodiment.

[0247] The IGBT 500 of the fifth embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first gate insulating film 21, a second gate insulating film 22, a third gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a front interlayer insulating layer 42, a back interlayer insulating layer 44, a first electrode pad 101, and a second electrode pad 102.

[0248] The semiconductor layer 10 includes a main gate trench 51 (first trench), an n-type first drain region 60 (sixth semiconductor region), an n-type second drain region 62 (seventh semiconductor region), a p-type first collector region 64 (fourth semiconductor region), a p-type second collector region 66 (fifth semiconductor region), an n-type buffer region 68, an n-type drift region 70 (first semiconductor region), a p-type base region 72 (second semiconductor region), an n-type emitter region 74 (third semiconductor region), a p-type intermediate region 80, and a p-type guard ring region 82.

[0249] In the IGBT 500, the occupancy rate of the third gate electrodes 33 in the termination region 400b in a given area is higher than the occupancy rate of the second gate electrodes 32 in the IGBT region 400a in the given area. In other words, the density of the third gate electrodes 33 in the termination region 400b is higher than the density of the second gate electrodes 32 in the IGBT region 400a. That is, the density of the third transistors in the termination region 400b is higher than the density of the second transistors in the IGBT region 400a.

[0250] In the IGBT 500, the distance between adjacent third gate electrodes 33 is smaller than the distance between adjacent second gate electrodes 32. By making the distance between adjacent third gate electrodes 33 smaller than the distance between adjacent second gate electrodes 32, the occupancy rate of the third gate electrodes 33 in a given area in the termination region 400b becomes higher than the occupancy rate of the second gate electrodes 32 in the IGBT region 400a in the given area.

[0251] The predetermined area is an area that can include the termination region 400b on the second surface P2. The predetermined area is, for example, an area of ​​50 μm×50 μm.

[0252] The occupancy rate of the third gate electrode 33 in the termination region 400b in a given area is, for example, 1.5 times or more the occupancy rate of the second gate electrode 32 in the IGBT region 400a in the given area.

[0253] In the IGBT 500, for example, the threshold voltage of the third transistor and the threshold voltage of the second transistor are the same. In the IGBT 500, for example, the p-type impurity concentration of the second collector region 66 facing the third gate electrode 33 is the same as the p-type impurity concentration of the first collector region 64 facing the second gate electrode 32.

[0254] The IGBT 500 is driven by the driving method shown in FIG. 3 of the first embodiment.

[0255] At time tx, a second turn-on voltage (Von2) is applied to the second transistor and the third transistor, causing an anode short circuit, similar to the IGBT 400 of the fourth embodiment.

[0256] The occurrence of an anode short prevents electrons from passing from the n-type buffer region 68 of the IGBT region 400a through the p-type first collector region 64 to the lower electrode 14. This suppresses the injection of holes from the p-type first collector region 64 into the drift region 70 of the IGBT region 400a.

[0257] Similarly, the occurrence of an anode short prevents electrons from passing from n-type buffer region 68 of termination region 400b through p-type second collector region 66 to bottom electrode 14. This suppresses the injection of holes from p-type second collector region 66 into drift region 70 of termination region 400b.

[0258] In the IGBT 500 of the fifth embodiment, the density of the third transistors in the termination region 400b is higher than the density of the second transistors in the IGBT region 400a. Therefore, when the second turn-on voltage (Von2) is applied simultaneously to the second gate electrode 32 and the third gate electrode 33 at time tx, the decrease in the amount of holes injected into the drift region 70 in the termination region 400b is greater than the decrease in the amount of holes injected into the drift region 70 in the IGBT region 400a. Therefore, the amount of holes in the drift region 70 in the termination region 400b decreases before the amount of holes in the drift region 70 in the IGBT region 400a decreases.

[0259] This can prevent current concentration from occurring at the end of the IGBT region 400a during the turn-off operation of the IGBT 500. This can prevent the IGBT 500 from being destroyed by current concentration.

[0260] From the viewpoint of suppressing destruction of the IGBT 500 due to current concentration, the occupancy rate of the third gate electrode 33 in the termination region 400b in a given area is preferably, for example, 1.5 times or more, and more preferably 2 times or more, of the occupancy rate of the second gate electrode 32 in the IGBT region 400a in the given area.

[0261] As described above, according to the fifth embodiment, an IGBT in which breakdown due to current concentration is suppressed can be realized.

[0262] In the first to fifth embodiments, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0263] In the first to fifth embodiments, the trenches are arranged in a stripe shape in parallel to one another. However, the present invention can also be applied to trenches in a mesh shape in which trenches intersect, or to trenches in a dot shape.

[0264] In the first to fifth embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type.

[0265] In the first to fifth embodiments, the first transistor has been described as having a trench gate structure, but the first transistor may have a planar gate structure.

[0266] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0267] 10 Semiconductor layer 12 Upper electrode (first electrode) 14 Lower electrode (second electrode) 31 first gate electrode 32 second gate electrode 33 Third gate electrode 51 Main Gate Trench (First Trench) 53 First backside trench (second trench) 54 Second backside trench (third trench) 60 first drain region (sixth semiconductor region) 62 second drain region (seventh semiconductor region) 64 first collector region (fourth semiconductor region) 66 second collector region (fifth semiconductor region) 70 drift region (first semiconductor region) 72 base region (second semiconductor region) 74 Emitter region (third semiconductor region) 100 RC-IGBT (semiconductor device) 100a IGBT area (transistor area) 100b Diode Region 100c Border area (adjacent area) 200 RC-IGBT (semiconductor device) 300 RC-IGBT (semiconductor device) 400 IGBT (semiconductor device) 400a IGBT area (transistor area) 400b Termination area (adjacent area) 500 IGBT (semiconductor device) P1 First side P2 Second side X first transistor Y Second transistor Z Third transistor

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface; a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer; a second transistor having a second gate electrode provided on the second surface side of the semiconductor layer; a transistor region including: the semiconductor layer; a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second surface side of the semiconductor layer; an adjacent region adjacent to the transistor region, A method for driving a semiconductor device comprising: changing the first transistor from an off state to an on state at a first time; After the first time, at a second time, the first transistor is changed from an on state to an off state; after the first time, at a predetermined time, the third transistor is changed from an off state to an on state, and then the second transistor is changed from an off state to an on state; the second transistor and the third transistor are turned off at a third time after the predetermined time and the second time.

2. A method for driving a semiconductor device as described in claim 1, wherein the specified time is before the second time.

3. A method for driving a semiconductor device as described in claim 1 or claim 2, wherein the absolute value of the threshold voltage of the third transistor is smaller than the absolute value of the threshold voltage of the second transistor.

4. A method for driving a semiconductor device described in any one of claims 1 to 3, further comprising a diode region including the semiconductor layer and a diode, with the adjacent region provided between the transistor region.

5. A method for driving a semiconductor device described in any one of claims 1 to 3, wherein the adjacent region surrounds the transistor region.

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