Semiconductor device and display device

Abstract

To provide a driving circuit in which deterioration in a transistor is suppressed.SOLUTION: A plurality of pulse output circuits including a first transistor to a sixth transistor is operated on the basis of a plurality of clock signals that control the respective transistors, a previous-stage signal input from the pulse output circuit in a previous stage, a subsequent-stage signal input from the pulse output circuit in a subsequent stage, and a reset signal. Thus, a degree of characteristic deterioration of the transistors can be reduced.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a driver circuit, or a liquid crystal display device having a driver circuit formed on the same substrate as a pixel portion. The present invention relates to a display device, or to an electronic device equipped with the display device. [Background technology]

[0002] With the spread of large display devices such as LCD TVs, there is a demand for higher value-added products. In particular, the channel region is made of amorphous semiconductor. Using thin film transistors (TFTs), the gate driver and other components are mounted on the same substrate as the pixel section. The technology that configures the drive circuit is being actively developed because it contributes greatly to reducing costs and improving reliability. Development is underway.

[0003] Thin film transistors with channel regions made of amorphous semiconductors have the following problems: an increase in threshold voltage, As the degradation of the thin film transistor progresses, the following problems occur: This causes problems such as the driver circuit becoming difficult to operate and making it impossible to display an image. Patent Document 1 describes a shift register that can suppress the deterioration of transistors. In Patent Document 1, in order to suppress the deterioration of the transistor characteristics, The transistor is connected to the output terminal of the flip-flop and the low power supply potential VSS. The transistor is connected between the wiring to which the current is supplied. By doing this, the time that the transistor is in a conducting state is This allows the transistor characteristics to be reduced to a certain extent. This can suppress deterioration in performance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-050502 Summary of the Invention [Problem to be solved by the invention]

[0005] One aspect of the present invention is to provide a driving circuit capable of reducing the degree of deterioration of characteristics of a thin film transistor. It is an object of the present invention to provide a display device. [Means for solving the problem]

[0006] One aspect of the present invention has a plurality of pulse output circuits, each of which includes a first thin-film transistor. the pulse output circuit includes a first signal line to a seventh signal line; and the first thin film transistor is electrically connected to the first power supply line and the second power supply line. , the first terminal is electrically connected to the first power line, and the second terminal is a gate of the third thin film transistor. , the gate of the fourth thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor the second terminal of the 10th thin film transistor and the first terminal of the 11th thin film transistor, and the gate of the 12th thin film transistor is electrically connected to the second terminal of the 13th thin film transistor and the first terminal of the 14th thin film transistor. 2 signal line, and the second thin film transistor has a first terminal electrically connected to the third thin film transistor; the first terminal of the eighth thin film transistor and the second terminal of the eighth thin film transistor, electrically connected to the gate of the sixth thin film transistor and the gate of the seventh thin film transistor; The gate of the third thin film transistor is electrically connected to the first power line, and the first terminal of the third thin film transistor is electrically connected to the second thin film transistor. the first terminal of the eighth thin film transistor and the second terminal of the eighth thin film transistor; The second terminal is electrically connected to the second power supply line, and the gate is connected to the second terminal of the first thin film transistor, The gate of the fourth thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor a fourth thin film transistor electrically connected to the second terminal and the first terminal of the tenth thin film transistor; a first terminal of the sixth thin film transistor electrically connected to the seventh signal line and the second terminal of the sixth thin film transistor; the second terminal is electrically connected to the second power supply line, and the gate is connected to the second terminal, the gate of the third thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor a second terminal of the 10th thin film transistor and a first terminal of the 5th thin film transistor; The first terminal of the seventh thin film transistor is connected to the sixth signal line, the second terminal of the seventh thin film transistor is connected to the first signal line, and the 1 is electrically connected to the first terminal of the thin film transistor, and the second terminal is electrically connected to the second power line. The gate is connected to the second terminal of the first thin film transistor, the gate of the third thin film transistor, the gate of the fourth thin film transistor, the second terminal of the ninth thin film transistor, and the tenth thin film transistor; the sixth thin film transistor is electrically connected to the first terminal of the sixth thin film transistor; and the sixth thin film transistor is electrically connected to the first signal line; and the second terminal is electrically connected to the seventh signal line and the first terminal of the fourth thin film transistor. the gate is electrically connected to the second terminal of the second thin film transistor and the seventh thin film transistor the seventh thin film transistor has a first terminal electrically connected to the first signal line; , and the second terminal is connected to the sixth signal line, the first terminal of the fifth thin film transistor, and the eleventh thin film transistor a gate electrically connected to the first terminal of the second thin film transistor; , and electrically connected to the gate of the sixth thin film transistor, and the eighth thin film transistor The first terminal is electrically connected to the first power line, and the second terminal is the first terminal of the second thin film transistor; and a gate electrically connected to the first terminal of the third thin film transistor, and a fourth signal line electrically connected to the gate of the third thin film transistor. the ninth thin film transistor has a first terminal electrically connected to the first power line and a second terminal electrically connected to the The terminals are the second terminal of the first thin film transistor, the gate of the third thin film transistor, and the a gate of the fifth thin film transistor, a gate of the tenth thin film transistor, a gate electrically connected to the fifth signal line; a tenth thin-film transistor electrically connected to the fifth signal line; The first terminal of the thin film transistor is the second terminal of the first thin film transistor, the gate of the third thin film transistor, The gate of the fourth thin film transistor, the gate of the fifth thin film transistor, and the gate of the ninth thin film transistor the second terminal of the gate is electrically connected to the fourth signal line, and the eleventh thin film transistor has a first terminal electrically connected to the sixth signal line; electrically connected to the first terminal of the fifth thin film transistor and the second terminal of the seventh thin film transistor; and a driving circuit whose gate is electrically connected to the third signal line.

[0007] One aspect of the present invention has a plurality of pulse output circuits, each of which includes a first thin-film transistor. the pulse output circuit includes a first signal line to a seventh signal line; and a first thin film, electrically connected to the first power line, the second power line, and the third power line. The transistor has a first terminal electrically connected to the first power supply line and a second terminal electrically connected to a third thin film transistor. gate of the fourth thin film transistor, gate of the fifth thin film transistor, gate of the ninth thin film transistor a second terminal of the thin film transistor and a first terminal of the tenth thin film transistor; The second thin film transistor has a gate electrically connected to the second signal line, and a first terminal of the second thin film transistor is connected to the third a first terminal of the thin film transistor and a second terminal of the eighth thin film transistor; , the second terminal is electrically connected to the gate of the sixth thin film transistor and the gate of the seventh thin film transistor; the gate is electrically connected to the third power supply line, and the third thin film transistor is The terminal is electrically connected to the first terminal of the second thin film transistor and the second terminal of the eighth thin film transistor. , the second terminal is electrically connected to the second power supply line, and the gate is connected to the first thin film transistor the second terminal of the fourth thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor the second terminal of the 10th thin film transistor and the first terminal of the 11th thin film transistor; The fourth thin film transistor has a first terminal connected to the seventh signal line, and a second terminal connected to the sixth thin film transistor. the first terminal is electrically connected to the second power supply line, and the gate is electrically connected to the first thin film transistor. a second terminal of the thin film transistor, a gate of the third thin film transistor, a gate of the fifth thin film transistor, electrically connected to the second terminal of the ninth thin film transistor and the first terminal of the tenth thin film transistor; The fifth thin film transistor has a first terminal connected to the sixth signal line, and the seventh thin film transistor has a second terminal connected to the sixth signal line. a terminal electrically connected to the first terminal of the eleventh thin film transistor, and a second terminal electrically connected to the second power supply; the gate is electrically connected to the second terminal of the first thin film transistor, a gate of the fourth thin film transistor; a second terminal of the ninth thin film transistor; The first terminal of the thin film transistor 10 is electrically connected to the first terminal of the thin film transistor 6. the second terminal is electrically connected to the seventh signal line, and the fourth thin film transistor the gate is electrically connected to the second terminal of the second thin film transistor, and the seventh thin film transistor the seventh thin film transistor has a first terminal electrically connected to the gate of the first thin film transistor; The second terminal is electrically connected to the sixth signal line, and the first terminal of the fifth thin film transistor is electrically connected to the sixth signal line. and the first terminal of the eleventh thin film transistor, and the gate of the second thin film transistor a second terminal of the sixth thin film transistor and a gate of the sixth thin film transistor; The transistor has a first terminal electrically connected to the first power supply line and a second terminal electrically connected to the second thin-film transistor. a gate electrically connected to the first terminal of the third thin film transistor and the first terminal of the fourth thin film transistor; The ninth thin film transistor is electrically connected to the signal line, and a first terminal of the ninth thin film transistor is electrically connected to the first power line. The second terminal is connected to the second terminal of the first thin film transistor and the gate of the third thin film transistor. , the gate of the fourth thin film transistor, the gate of the fifth thin film transistor, and the gate of the tenth thin film transistor a gate electrically connected to the fifth signal line; a first terminal of the first transistor; a gate electrically connected to the fifth signal line; The first terminal of the thin film transistor is the second terminal of the first thin film transistor, and the third terminal of the a gate of the fourth thin film transistor, a gate of the fifth thin film transistor, and 9 is electrically connected to the second terminal of the thin film transistor, and the second terminal is electrically connected to the second power line. the gate of the eleventh thin film transistor is electrically connected to the fourth signal line; and the gate of the eleventh thin film transistor is electrically connected to the first terminal the sixth signal line, the first terminal of the fifth thin film transistor, and the second terminal of the seventh thin film transistor; and a drive circuit whose gate is electrically connected to a third signal line.

[0008] In the drive circuit, a reset signal is supplied to the second signal line, and a previous signal is supplied to the fourth signal line. A first signal is supplied to the fifth signal line, a second signal is supplied to the sixth and seventh signal lines, and a third signal is supplied to the sixth and seventh signal lines. The first and second output signals are output to the first signal lines of the pulse output circuits in the odd-numbered stages. , a clock signal is supplied to the third signal line of the odd-numbered stage, and an inverted clock signal is supplied to the third signal line of the odd-numbered stage. An inverted clock signal is supplied to the first signal line of the even-numbered pulse output circuit, The third signal line may be supplied with a clock signal.

[0009] In the driving circuit, the inverted clock signal is a signal delayed by 1 / 2 cycle from the clock signal. It is also possible.

[0010] In the drive circuit, a reset signal is supplied to the second signal line, and a previous signal is supplied to the fourth signal line. A first output signal is supplied to the fifth signal line, a second output signal is supplied to the sixth signal line, and a first output signal is supplied to the seventh signal line. and outputs the second output signal and the second output signal, and the (J-3)th pulse (J is a multiple of 4 or more) The first signal line of the output circuit is supplied with a first clock signal, and the third signal line of the (J-3) stage is The second clock signal is supplied to the (J-2)th stage pulse output circuit. , the second clock signal is supplied, and the third signal line of the (J-2)th stage receives the third clock signal. The third clock signal is supplied to the first signal line of the (J-1)th stage pulse output circuit. The fourth clock signal is supplied to the third signal line of the (J-1)th stage, and the pulse of the Jth stage is The fourth clock signal is supplied to the first signal line of the output circuit, and the third clock signal is supplied to the third signal line of the Jth stage. A single clock signal may be supplied.

[0011] In the drive circuit, the 4th clock signal is a signal delayed by 1 / 4 cycle from the 3rd clock signal. The third clock signal is delayed by a quarter cycle from the second clock signal. The clock signal is a signal delayed by 1 / 4 cycle from the first clock signal, and the first clock signal is It may be a signal delayed by 1 / 4 cycle from the fourth clock signal.

[0012] In the driving circuit, one electrode is connected to the second terminal of the first thin film transistor, the gate of the fourth thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor the second terminal of the 10th thin film transistor and the first terminal of the 11th thin film transistor; The other electrode of the capacitor may be electrically connected to the second power supply line.

[0013] In the driving circuit, the first terminal is connected to the second terminal of the first thin film transistor, the gate of the fourth thin film transistor, the gate of the fifth thin film transistor, the gate of the ninth thin film transistor a second terminal connected to the second terminal of the 10th thin film transistor and the first terminal of the 11th thin film transistor; a twelfth thin-film transistor whose gate is electrically connected to the seventh signal line; The circuit may have a transistor.

[0014] In the driver circuit, the first to eleventh thin film transistors are made of microcrystalline silicon. The channel region may be provided with a gate. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a driver circuit capable of reducing the degree of deterioration of characteristics of a thin film transistor is provided. It can be provided. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a circuit diagram of a drive circuit. [Figure 2] 1 is a circuit diagram of a driving circuit and a timing chart for explaining the operation thereof. [Figure 3] FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 4]FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 5] FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 6] FIG. 2 is a circuit diagram of a drive circuit. [Figure 7] FIG. 2 is a circuit diagram of a drive circuit. [Figure 8] 1A and 1B are a circuit diagram of a driving circuit and a timing chart for explaining the operation thereof; [Figure 9] FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 10] FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 11] FIG. 4 is a schematic diagram for explaining the operation of a drive circuit. [Figure 12] FIG. 1 is a block diagram of a display device. [Figure 13] FIG. 1 is a block diagram of a display device. [Figure 14] 1 is a circuit diagram of a driving circuit and a timing chart for explaining the operation thereof. [Figure 15] 1 is a circuit diagram of a pixel and a timing chart for explaining the operation thereof; [Figure 16] FIG. 2 is a circuit diagram of a pixel. [Figure 17] FIG. 2 is a cross-sectional view illustrating a driving circuit. [Figure 18] FIG. 2 is a cross-sectional view illustrating a driving circuit. [Figure 19] FIG. 2 is a cross-sectional view illustrating a driving circuit. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a driver circuit. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a driver circuit. [Figure 22] 10A to 10C are diagrams illustrating a multi-tone mask that can be applied to a method for manufacturing a driver circuit. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a driver circuit. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a driver circuit. [Figure 25]1A to 1C are cross-sectional views illustrating a method for manufacturing a driver circuit. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 27] 1A and 1B are diagrams illustrating electronic devices having a display device. [Figure 28] FIG. 2 is a circuit diagram of a drive circuit. [Figure 29] FIG. 2 is a circuit diagram of a drive circuit. [Figure 30] FIG. 2 is a circuit diagram of a drive circuit. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope thereof. It will be readily apparent to those skilled in the art that various modifications can be made to the modes and details of the present invention. It should not be construed as being limited to the description of the form. In this regard, parts having the same or similar functions are denoted by common reference numerals in different drawings, and the same parts are A detailed description of the components or components having similar functions will be omitted.

[0018] The size, thickness of layers, and raw signal waveforms of each component shown in the drawings of each embodiment may differ. The dimensions may be exaggerated for clarity. It is not limited to that scale.

[0019] In addition, terms such as "first," "second," and "third" used in this specification do not mean a mixture of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting in number.

[0020] (Embodiment 1) In this embodiment, one mode of a driver circuit and a structure of the thin film transistor will be described. .

[0021] First, the configuration of the drive circuit will be described. It functions as a shift register for use in a light driver, a source driver, or a display device. It is possible.

[0022] For the driver circuit functioning as a shift register, see Figures 1 to 6, 28, and 29. The shift register 100 is configured to output a first pulse from a first pulse output circuit 101_1 to an N-th pulse. The pulse output circuit 101_N (N≧3) is included (see FIG. 1A). The first pulse output circuit 101_1 to the Nth pulse output circuit 101_2 of the shift register 100 Each stage of 1_N receives a clock signal CK from the first wiring 102 and an inverted clock signal CK from the second wiring 103. A clock signal CKB and a reset signal RES are inputted through the third wiring 104. The pulse output circuit of the stage receives a start pulse SP or a signal from the pulse output circuit of the previous stage. (called the previous stage signal Lin) is input to the pulse output circuit of each stage. The signal from the pulse output circuit (called the next stage signal Rin) is input. The circuit outputs a first output signal Gout to be output to a gate line or a data line, etc. and / or a second output signal SRout for input to a subsequent pulse output circuit. The pulse output circuit is a dummy stage that outputs a signal that does not contribute to the display on the display unit. For example, it may be used in a shift register of a gate driver, and In the configuration in which pulses are output sequentially, the number of stages may be n≦N.

[0023] The clock signal CK and the inverted clock signal CKB are connected to the pulse output circuits of the odd-numbered stages and the even-numbered stages. In the pulse output circuit of the second stage, the input terminals are swapped. Specifically, as shown in Figure 1(B), In this way, in the pulse output circuit 101_1 of the odd-numbered stage, the clock signal CK is input to the first terminal. The reset signal RES is input to the second terminal, and the inverted clock signal CKB is input to the third terminal. The first signal Lin is input to the fourth terminal, and the second signal Rin is input to the fifth terminal. A first output signal Gout is output from the sixth terminal, and a second output signal SRo is output from the seventh terminal. When ut is output, the pulse output circuit 101_2 of the even stage is In this case, an inverted clock signal CKB is input to the first terminal, and a reset signal RES is input to the second terminal. is input, the clock signal CK is input to the third terminal, and the previous signal Lin is input to the fourth terminal. The next stage signal Rin is input to the fifth terminal, and the first output signal Gout is output from the sixth terminal. The clock is input, and the second output signal out is output from the seventh terminal. The signal CK and the inverted clock signal CKB alternate between H signal (high power supply potential level) and L signal at regular intervals. The signal (low power supply potential level) is a signal that repeats the clock signal CK and the inverted clock signal CK. The lock signal is delayed by 1 / 2 period.

[0024] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, in this specification, voltage and potential can be interchangeably described.

[0025] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. In FIG. 1D, as an example, the configuration of an odd-numbered pulse output circuit will be described. As mentioned above, the difference between the odd-numbered and even-numbered pulse output circuits is the clock signal The difference is that the terminals to which CK and the inverted clock signal CKB are input are switched.

[0026] The pulse output circuit has a first thin film transistor 111 to an eleventh thin film transistor 121. In addition to the signals input to the first to seventh terminals, FIG. A high power supply potential VDD is supplied from a first power supply line 131, and a low power supply potential VSS is supplied from a second power supply line 132. In FIG. 1(D), the clock signal C is supplied to the first terminal. The wiring for inputting K is the first signal line 151, and the wiring for inputting the reset signal RES to the second terminal is The wiring for inputting the inverted clock signal CKB to the second signal line 152 and the third terminal is connected to the third signal line 15 3. The fourth terminal is connected to the fourth signal line 154 for inputting the previous signal Lin, and the fifth terminal is connected to the next signal line The wiring for inputting Rin is the fifth signal line 155, and the first output signal Gout is output from the sixth terminal. The wiring for outputting the second output signal SRout from the seventh terminal is the sixth signal line 156. It is called the seventh signal line 157.

[0027] The first thin film transistor 111 has a first terminal connected to the first power line 131 and a second terminal connected to the first power line 132. The gate of the third thin film transistor 113, the gate of the fourth thin film transistor 114, the gate of the fifth thin film transistor the gate of the ninth thin film transistor 115, the second terminal of the ninth thin film transistor 119, and the tenth thin film transistor The first terminal of the transistor 120 is connected to the first terminal of the transistor 120 , and the gate of the transistor 120 is connected to the second signal line 152 . The second thin film transistor 112 has a first terminal connected to a first terminal of the third thin film transistor 113, and and the second terminal of the eighth thin film transistor 118 is connected to the sixth thin film transistor and the gate of the seventh thin film transistor 117. The third thin film transistor 113 has a first terminal connected to the second thin film transistor 113. the first terminal of the eighth thin film transistor 112 and the second terminal of the eighth thin film transistor 118; The second terminal is connected to the second power supply line 132, and the gate is connected to the second terminal of the first thin film transistor 111. , the gate of the fourth thin film transistor 114, the gate of the fifth thin film transistor 115, 119 and a first terminal of the tenth thin film transistor 120. The fourth thin film transistor 114 has a first terminal connected to the seventh signal line 157 and a sixth thin film transistor 118. the second terminal of the membrane transistor 116 is connected to the second power supply line 132; The gate is the second terminal of the first thin film transistor 111, and the gate of the third thin film transistor 113. , the gate of the fifth thin film transistor 115, the second terminal of the ninth thin film transistor 119, and The fifth thin film transistor 11 is connected to the first terminal of the tenth thin film transistor 120. 5, the first terminal of which is connected to the sixth signal line 156, the second terminal of the seventh thin film transistor 117, and the first The first terminal of the thin film transistor 121 is connected to the first terminal of the thin film transistor 121, and the second terminal of the thin film transistor 121 is connected to the second power supply line 132. The gate is connected to the second terminal of the first thin film transistor 111 and the gate of the third thin film transistor 113. the gate of the fourth thin film transistor 114; the second terminal of the ninth thin film transistor 119; and the first terminal of the tenth thin film transistor 120. 116 has a first terminal connected to the first signal line 151, a second terminal connected to the seventh signal line 157, and The gate of the fourth thin film transistor 114 is connected to the first terminal of the second thin film transistor 11 2 and the gate of the seventh thin film transistor 117. The transistor 117 has a first terminal connected to the first signal line 151 and a second terminal connected to the sixth signal line 152. 56, the first terminal of the fifth thin film transistor 115, and the second terminal of the eleventh thin film transistor 121 the gate is connected to the second terminal of the second thin film transistor 112 and the sixth thin film transistor The eighth thin film transistor 118 has a first terminal connected to the gate of the eighth thin film transistor 116. The second terminal is connected to the first terminal of the second thin film transistor 112, and the second terminal is connected to the first power supply line 131. The gate of the third thin film transistor 113 is connected to the first terminal of the third thin film transistor 113, and the gate of the third thin film transistor 113 is connected to the fourth signal line 154. The ninth thin film transistor 119 has a first terminal connected to the first power supply line 131 and a second terminal connected to the first power supply line 131. The second terminal is the second terminal of the first thin film transistor 111 and the gate of the third thin film transistor 113. , the gate of the fourth thin film transistor 114, the gate of the fifth thin film transistor 115, and 10 is connected to the first terminal of the thin film transistor 120, and the gate is connected to the fifth signal line 155. The tenth thin film transistor 120 has a first terminal connected to the first thin film transistor 111. The second terminal, the gate of the third thin film transistor 113, and the gate of the fourth thin film transistor 114 , the gate of the fifth thin film transistor 115, and the second terminal of the ninth thin film transistor 119 The second terminal is connected to the second power supply line 132, and the gate is connected to the fourth signal line 154. The eleventh thin film transistor 121 has a first terminal connected to the sixth signal line 156 and a fifth thin film transistor 122. the first terminal of the seventh thin film transistor 115 and the second terminal of the seventh thin film transistor 117; The gate is connected to the third signal line 153 , and the second terminal is connected to the second power supply line 132 .

[0028] The gates of the sixth thin film transistor 116 and the seventh thin film transistor 117 and the second terminal, the sixth thin film transistor 116 and the seventh thin film transistor 117 are connected. A separate capacitance element is provided to perform bootstrap operation by floating the gate. The gate capacitance of the sixth thin film transistor 116 and the seventh thin film transistor If a test strap operation can be performed, the capacitance element can be reduced.

[0029] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can be passed through the drain region, the channel region, and the source region. The source and drain vary depending on the structure and operating conditions of the thin film transistor. It is difficult to determine whether it is the source or the drain. The region that functions as a drain may not be called a source or drain. In this case, for example, they may be referred to as the first terminal and the second terminal, respectively. These may be referred to as the first electrode and the second electrode, respectively. Alternatively, they may be referred to as the first region and the second region. This may be noted.

[0030] The structure of the thin film transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied.

[0031] As another example, a structure in which gate electrodes are arranged above and below the channel region can be applied. In addition, by arranging gate electrodes above and below the channel region, multiple The configuration is such that several thin film transistors are connected in parallel.

[0032] A structure in which a gate electrode is placed above a channel region, and a structure in which a gate electrode is placed below a channel region Structures in which the channel region is divided into multiple regions, such as a positive staggered structure, a reverse staggered structure, and a The structure may be a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series. Furthermore, the source electrode and drain electrode are attached to the channel region (or a part of it). An overlapping structure can also be applied.

[0033] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be modified to include the connection relationships shown in the drawings or text. This also includes matters other than those in charge.

[0034] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements (e.g., switches, thin film transistors, capacitance elements, inductors, resistance elements, One or more diodes may be connected between A and B. When A and B are functionally connected, a circuit (e.g., For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (booster circuit (e.g., a voltage path, a step-down circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current power sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current, etc., operational amplifiers, amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits One or more circuits (such as a control circuit) may be connected between A and B. For example, Even if there is another circuit between A and B, if the signal output from A is transmitted to B, are functionally connected.

[0035] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are directly connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is another When A and B are connected functionally across a circuit, and when A and B are connected directly ( (i.e., when A and B are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that the

[0036] The thin film transistor in this embodiment is made of a microcrystal (microcrystal, nanocrystal, etc.). Thin-film transistors (TFTs) that use amorphous silicon (also called semi-amorphous silicon) as the channel layer Therefore, it is necessary to minimize the degree of deterioration of the characteristics of the thin film transistor. It is possible to provide a driving circuit that can

[0037] The first to third thin film transistors and the eighth to eleventh thin film transistors are thin film transistors. Not only the stator, but also the device that switches between a conductive state (ON state) or a non-conductive state (OFF state) according to the input signal. ) may be a switch that switches between the two.

[0038] The switch may take various forms, for example, an electrical switch. There are various types of switches, such as switches and mechanical switches. In other words, anything that can control the flow of current is sufficient. There is no particular limitation. For example, a transistor (e.g., a bipolar transistor) can be used as a switch. transistors, MOS transistors, etc.), diodes (e.g., PN diodes, P IN diode, Schottky diode, MIM (Metal Insulator Metal diode, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0039] Next, the operation of the shift register shown in FIGS. 1(A) to 1(D) will be explained with reference to FIGS. 2 to 6. For the purpose of explanation, as shown in FIG. 2(A), the second thin film transistor 11 2, the gate of the sixth thin film transistor 116, and the seventh thin film transistor 117 The connection point of the gate is called node A. In order to specifically explain this, the first period shown in the timing chart of FIG. The explanation is divided into T1, the second period T2, the third period T3, the fourth period T4, and the fifth period T5. In the following description, the first thin film transistor 111 to the eleventh thin film transistor The transistor 121 is an N-channel thin film transistor, and the gate-source voltage (Vgs) When the threshold voltage (Vth) is exceeded, the transistor is in a conductive state. In this case, the gate driver is provided with a shift register, and the period 201 is a vertical feedback 2B, the timing shown in FIG. The timing chart shows the clock signal CK, the inverted clock signal CKB, the reset signal RES, The first stage signal Lin, the second stage signal Rin, and the second output signal SRout (for example) at each stage A specific example is shown for the waveform of SRout1) in the first row. The power supply potential level and low power supply potential level are VDD and VSS, respectively, except for node A. The first output signal Gout1 will be described as The waveform shown is the same as that of SRout1, so it is omitted here.

[0040] In the first period T1, the reset signal RES becomes an H signal, and a gate is applied to the second signal line 152. The first thin film transistor 111 connected to the port is turned on. At this time, the clock signal CK is an H signal, the inverted clock signal CKB, the previous stage signal Lin, and the next stage signal Rin are L signals. As shown in FIG. 3(A), the first thin film transistor 111 is conductive, and the second thin film transistor a third thin film transistor 112, a fourth thin film transistor 113, a fifth thin film transistor 114, and a The transistor 115 is turned on. As a result, a current flows as shown by the dotted arrow in FIG. The potential of each wiring in the first period T1 is determined as shown in FIG. T1 is the period during which the potential of each wiring in the pulse output circuit is reset (to VSS). During the first period T1, the second output signal SRout1 outputs an L signal.

[0041] The reset signal RES is input to the gate of the first thin film transistor 111 during a period By performing this every vertical blanking period 201, each node of each thin film transistor is set to VDD Alternatively, the potential of the floating node described in this embodiment can be set to VSS. In dynamic circuits that use a node for driving, initialization (reset) of each node is required. ) can be performed, improving operational reliability and noise resistance to the same level as static circuits. It is possible.

[0042] Next, in the second period T2, the preceding signal Lin becomes an H signal, and a gate is applied to the fourth signal line 154. The eighth thin film transistor 118 and the tenth thin film transistor 120 are conductive. At this time, the inverted clock signal CKB is an H signal, the clock signal CK, and the reset signal RE S and the subsequent signal Rin are L signals. The second thin film transistor 112 is turned on following the first period T1. Then, current flows as shown by the dotted arrow in Figure 3(B). At this time, node A The potential of the first power supply line 131 is supplied to the second terminal of the eighth thin film transistor 118 as a source. The value obtained by subtracting the threshold voltage Vth of the eighth thin film transistor 118 from the potential of When the second terminal of the eighth thin film transistor 118 becomes (VDD-Vth), The thin film transistor 118 is turned off, and the node A is maintained at (VDD-Vth). As shown in FIG. 3B, the sixth thin film transistor 116 and Although the thin film transistor 117 is turned on, the first signal line 151 is VSS. The potential of each wiring during the second period T2 is determined as shown in FIG. 2(B). In this period, the potential of the node A in the pulse output circuit is in a floating state. Therefore, the second output signal SRout1 outputs an L signal.

[0043] Next, in the third period T3, the clock signal CK becomes an H signal. The clock signal CKB, reset signal RES, previous signal Lin, and next signal Rin are L signals. At this time, as shown in FIG. 4(A), the sixth thin film transistor 116 and the seventh thin film transistor The transistor 117 is in a conducting state, i.e., a current flows between the source and the drain (FIG. 4(A) )), and the sixth thin film transistor 116 and the seventh thin film transistor 11 The potential of the second terminal (source side) of the sixth thin film transistor 116 and the sixth thin film transistor 117 begins to rise. 7 Capacitive coupling due to parasitic capacitance exists between the gate and source of the thin film transistor 117. As the potential of the second terminal, which serves as the base, rises, the potential of node A, which is in a floating state, rises. (Bootstrap operation). Eventually, the potential of node A becomes higher than (VDD+Vth). The voltages at the second terminals of the sixth thin film transistor 116 and the seventh thin film transistor 117 are During the third period T3, the second output signal SRout1 is set to an H signal. That is, in the third period T3, the potential of the node A in the floating state is set to a blank. The H signal is output to the first output signal Gout1 and the second output signal Gout2 by the load strap operation. The second output signal SRout1 is output as the signal SRout1. It is input as the pre-stage signal Lin to the second-stage pulse output circuit.

[0044] As shown in FIG. 1(D), the second thin film transistor has a gate to which a high power supply potential VDD is applied. Providing the register 112 has the following advantages.

[0045] If there is no second thin film transistor 112 to which the high power supply potential VDD is applied to the gate, the boot When the potential of the node A rises due to the strap operation, the second The potential of the source terminal rises and becomes higher than the high power supply potential VDD. The source of the eighth thin film transistor 118 is switched to the first terminal side. In the transistor 118, the gate-source and gate-drain During this time, a large bias voltage is applied, which causes a large stress on the thin film transistor. This can be a factor in deterioration of the resistor.

[0046] By providing a second thin film transistor 112 to the gate of which a high power supply potential VDD is applied, Therefore, although the potential of node A rises due to the bootstrap operation, the This prevents the potential of the second terminal of the resistor 118 from rising. By providing the thin film transistor 112, the gate and the source of the eighth thin film transistor 118 are Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By using the circuit configuration of the above form, the gap between the gate and source of the eighth thin film transistor 118 The negative bias voltage applied to the 8th thin-film transistor can also be reduced, so stress can be reduced. This can further suppress the deterioration of the capacitor 118.

[0047] The second thin film transistor 112 is provided at a position corresponding to the eighth thin film transistor 11 8 and the gate of the sixth thin film transistor 116 or the seventh thin film transistor 117 The first terminal and the second terminal may be connected between the gate of the .

[0048] The second thin film transistor 112 has a gate to which a high power supply potential VDD is applied. Therefore, a high voltage is not applied between the gate and source, but the conduction Therefore, when the channel region of a thin film transistor is formed using an amorphous semiconductor, In this case, the degree of deterioration of the thin film transistor becomes significant. A structure in which microcrystalline silicon, a typical example of a microcrystalline semiconductor, is provided in the channel region of each transistor. By using this composition, the effect of reducing the progression of deterioration can be further achieved. The transistor 112 has a multi-gate structure with two or more gate electrodes, making it possible to reduce the thickness Redundancy of the film transistors can be achieved, which further reduces the progression of degradation. This will be the case.

[0049] In FIG. 1D, the potential applied to the gate of the second thin film transistor 112 is a high power supply voltage. However, if a potential that turns on the second thin film transistor 112 is applied, In FIG. 28A, when a high power supply potential VDD is input to the gate of the second thin film transistor 112, A third power supply line 22 that applies a conduction holding potential VCC is provided separately from the first power supply line 131 to which the conduction holding potential VCC is applied. An example is shown in which the power supply is connected to 801. The potential of the conduction holding potential VCC is VSS <VCC≦VD The magnitude relationship of D is sufficient, and the conduction holding potential VCC is set lower than the high power supply potential VDD. Therefore, the degree of deterioration of the second thin film transistor can be reduced.

[0050] In addition to the configuration shown in FIG. 1(D), a twelfth thin film transistor 2802 is provided. The first terminal of the twelfth thin film transistor 2802 may be formed as follows (see FIG. 28(B)). The second terminal of the first thin film transistor 111, the gate of the third thin film transistor 113, The gate of the fifth thin film transistor 115, the gate of the ninth thin film transistor 116, the second terminal of the tenth thin film transistor 119 and the first terminal of the tenth thin film transistor 120; The second terminal is connected to the second power supply line 132, and the gate is connected to the seventh signal line 157. The gate of the thin film transistor 2802 may be connected to the sixth signal line 156. The twelfth thin film transistor 2802 is connected to the seventh signal line 157 (or the sixth signal line 156). By supplying a H signal, the seventh signal line 157 (or the During the third period T3 when the signal line 156 supplies an H signal, the first thin film transistor 111 the second terminal of the third thin film transistor 113, the gate of the fourth thin film transistor 114, the gate of the fifth thin film transistor 115, the second terminal of the ninth thin film transistor 119, and a node to which the first terminal of the tenth thin film transistor 120 is connected and a node to which VSS is supplied; By bringing the second power supply line 132 into a conductive state, the third thin film transistor 113 and the fourth thin film transistor The thin film transistor 114 and the fifth thin film transistor 115 are more reliably turned off. Therefore, malfunction of the drive circuit can be reduced.

[0051] Next, in the fourth period T4, the subsequent signal Rin( 2B) becomes an H signal, and the gate is connected to the fifth signal line 155. The ninth thin film transistor 119 is turned on. At this time, the inverted clock signal CKB is turned on. The clock signal CK, the reset signal RES, and the previous signal Lin are L signals. a fourth thin film transistor 113, a fifth thin film transistor 114, and a The second thin film transistor 112 is turned on. After the third period T3, the sixth thin film transistor 116 and the seventh thin film transistor The potential of the gate of the sixth thin film transistor 116 and the seventh thin film transistor 117 is set to VSS. The thin film transistor 117 is made non-conductive. Then, a current flows as shown by the dotted arrow in FIG. The potential of each wiring in the fourth period T4 is determined as shown in FIG. During the fourth period T4, the L signal is used as the first output signal Gout1 and the second output signal SRout1. The output will be as follows.

[0052] Next, in the fifth period T5, the clock signal CK and the inverted clock signal CKB are alternately inverted. The following will be explained for the periods T5-1 and T5-2, which are input as follows. During the period T5-1, the clock signal CK becomes an H signal, and the inverted clock signal CK B, the reset signal RES, the previous signal Lin, and the next signal Rin are L signals. thin film transistor 111, eighth thin film transistor 118, ninth thin film transistor 119, and and the tenth thin film transistor 120 are non-conductive, The potentials of the gates of the fourth thin film transistor 114 and the fifth thin film transistor are That is, the third thin film transistor 113 and the fourth thin film transistor 114 are in a floating state while maintaining the state. The fifth thin film transistor 114 and the fifth thin film transistor 115 are maintained in a conductive state. Then, the second thin film transistor 112 becomes conductive following the fourth period T4, and the sixth thin film transistor The potential of the gates of the seventh thin film transistor 116 and the seventh thin film transistor 117 is VSS. This makes the sixth thin film transistor 116 and the seventh thin film transistor 117 non-conductive. The eleventh thin film transistor 121 is in a non-conductive state. Current flows as indicated by the dotted arrows, and the potential of each wiring during period T5-1 is determined as shown in Figure 5(A). During the period T5-2, the inverted clock signal CKB becomes an H signal, and the clock signal CK, the reset signal RES, the previous stage signal Lin, and the next stage signal Rin are all L signals. Similarly to T5-1, the first thin film transistor 111, the eighth thin film transistor 118, the ninth thin film transistor The third thin film transistor 119 and the tenth thin film transistor 120 are turned off. The gates of the thin film transistor 113, the fourth thin film transistor 114, and the fifth thin film transistor The potential of the third thin film gate is in a floating state while maintaining the state of the fourth period. The fourth thin film transistor 113, the fourth thin film transistor 114, and the fifth thin film transistor 115 are The second thin film transistor 112 maintains the conductive state during the fourth period T 4, and the sixth thin film transistor 116 and the seventh thin film transistor 117 are turned on. By setting the potential of the gate to VSS, the sixth thin film transistor 116 and the seventh thin film transistor The eleventh thin film transistor 117 is made non-conductive, and the eleventh thin film transistor 121 is made conductive. Then, current flows as shown by the dotted arrows in Figure 5(B), and the potential of each wiring during period T5-2 2B. That is, in the fifth period T5, the L signal is converted into the first output signal G out1 and the second output signal SRout1.

[0053] In addition to the structure shown in FIG. 1D, a capacitor 2901 may be provided. (See FIG. 29). One electrode of the capacitor 2901 is connected to the second thin film transistor 111. a terminal, a gate of the third thin film transistor 113, a gate of the fourth thin film transistor 114, the gate of the fifth thin film transistor 115, the second terminal of the ninth thin film transistor 119, and the first The other electrode is connected to the second power supply line 132. The capacitor element 2901 is connected to the second terminal of the first thin film transistor 111 and the third thin film transistor 112. the gate of the fourth thin film transistor 113, the gate of the fifth thin film transistor 114, the gate of the ninth thin film transistor 115, the second terminal of the ninth thin film transistor 119, and the tenth thin film transistor The potential of the node to which the first terminal of the seventh signal 120 is connected is maintained. During a fifth period T5 in which the output of the line 157 (or the sixth signal line) is held at an L signal, The thin film transistor 113, the fourth thin film transistor 114, and the fifth thin film transistor 11 5 can be held at a potential that ensures that the transistor 5 is in a conductive state, thereby preventing malfunction of the drive circuit. This can reduce the amount of work required.

[0054] The shift register shown in this embodiment outputs a first output signal Gout and a second output signal SRo. A sixth signal line 156 and a seventh signal line 157 for outputting ut are separately provided. As a result, the load of the elements connected to the subsequent stages of the sixth signal line 156 and the seventh signal line 157 is reduced. Therefore, the sixth thin film transistor and the seventh thin film transistor are different in size. This allows the delay in the rise of the potential of each signal to be reduced. The thin film transistor size is the W / L (W: channel width, L: channel) of the thin film transistor. As shown in FIG. 6A, the sixth signal line 156 and the seventh signal line 157 are integrated, and the first output signal Gout and the second output signal SRo are output from the same signal line 166. ut may be output. The eleventh thin film transistor may also be omitted. The sixth signal line 156 and the seventh signal line 157 are integrated to obtain the same output signal. By omitting 11 thin film transistors, the number of thin film transistors can be reduced, and the inverted clock signal This allows for the reduction of wiring for inputting the shift register, which makes it possible to miniaturize the shift register. can.

[0055] In the circuit configuration of the pulse output circuit shown in this embodiment, the eleventh thin film transistor 12 11. By providing the eleventh thin film transistor 121, , the fall time of the potential of the first output signal Gout on the sixth signal line 156 can be shortened. On the other hand, the circuit configuration of the pulse output circuit shown in this embodiment mode can be the same as that shown in FIGS. For example, as shown in the figure, the first power supply line 131 and / or the 2. A plurality of power supply lines 132 are provided to supply a plurality of high power supply potentials and / or a plurality of low power supply potentials. For example, as shown in FIG. 6B, The wiring is divided into a plurality of power supply lines 171 and 172, and a first high power supply potential VDD1 and a second high The power supply potential VDD2 may be supplied to the eleventh thin film transistor 121. This sufficiently shortens the fall time of the potential of the first output signal Gout on the sixth signal line 156. In this case, the fifth thin film transistor 115 controls the potential of the first output signal Gout on the sixth signal line 156. Therefore, the fall time of the power supply line 171 in FIG. 6(B) is not required to be shortened. By setting the first high power supply potential VDD1 lower than the second high power supply potential VDD2 of the power supply line 172, As a result, the third thin film transistor 113, the fourth thin film transistor 114, and The threshold shift of the fifth thin film transistor 115 can be reduced.

[0056] Next, the structure of the thin film transistor that constitutes the pulse output circuit will be described. The field effect mobility of carriers is higher in n-type transistors than in p-type transistors. In this embodiment, the structure of an n-type thin film transistor will be described.

[0057] (Structure 1) FIG. 17 is a cross-sectional view of one mode of a thin film transistor. 1101, a gate electrode 1103, a microcrystalline semiconductor layer 1115a, and a mixed layer 1115b are formed on a substrate 1101. 15b, the layer 1129c containing an amorphous semiconductor, the gate electrode 1103, and the microcrystalline semiconductor layer The gate insulating layer 1105 and the layer 1129c containing an amorphous semiconductor are provided between the gate insulating layer 1105 and the layer 1115a. an impurity semiconductor layer 1127 which functions as a source region and a drain region in contact with the The wiring 1125 is in contact with the semiconductor layer 1127 .

[0058] The substrate 1101 may be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of this manufacturing process. A plastic substrate or the like having sufficient heat resistance can be used. When this is not required, an insulating layer is provided on the surface of a metal substrate such as a stainless steel alloy. The glass substrate may be, for example, barium borosilicate glass or aluminoborose glass. It is preferable to use a non-alkali glass substrate such as an alkali-containing glass or an aluminosilicate glass. The substrate 1101 may be a 3rd generation (for example, 550 mm x 650 mm) or 3.5th generation (e.g., 600mm x 720mm, or 620mm x 750mm), 4th generation (e.g., 680mm x 880mm or 730mm x 920mm), 5th generation (e.g., 1 100mm x 1300mm), 6th generation (e.g., 1500mm x 1850mm), 7th generation Generation (e.g., 1870mm x 2200mm), 8th generation (e.g., 2200mm x 24 00mm), 9th generation (e.g., 2400mm x 2800mm), 10th generation (e.g., A glass substrate such as a substrate having a size of 2850 mm x 3050 mm can be used.

[0059] The gate electrode 1103 is made of molybdenum, titanium, chromium, tantalum, tungsten, or aluminum. Metallic materials such as tungsten, copper, neodymium, scandium, etc., or alloy materials containing these as the main components The insulating layer can be formed by using a single layer or a stacked layer of a material. A semiconductor layer such as doped polycrystalline silicon or an AgPdCu alloy may also be used. .

[0060] The two-layer structure of the gate electrode 1103 is a molybdenum layer stacked on an aluminum layer. two-layer structure with a molybdenum layer on a copper layer; two-layer structure with a titanium nitride layer on a copper layer or The two-layer structure is made up of a tantalum nitride layer, or a titanium nitride layer and a molybdenum layer. The three-layer structure of the gate electrode 1103 is preferably a tungsten Tungsten nitride or tungsten nitride and aluminum and silicon alloy or aluminum It is preferable to use a structure in which a titanium alloy and a titanium nitride or titanium layer are laminated. A metal layer that functions as a barrier layer is stacked on a layer with low electrical resistance, The diffusion of metal elements from the metal layer to the semiconductor layer can be prevented.

[0061] In order to improve the adhesion between the gate electrode 1103 and the substrate 1101, the above-mentioned metal material is preferably nitrided. A nitride layer may be provided between the substrate 1101 and the gate electrode 1103 .

[0062] The gate insulating layer 1105 is a silicon oxide layer formed by using a CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer; It can be formed as follows.

[0063] In this specification, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The content is high, and preferably, the Rutherford backscattering method (RBS) is used. Ford Backscattering Spectrometry) and hydrogen forward Using the hydrogen forward scattering (HFS) method When measured, the composition range was 50 to 70 atomic % oxygen, 0.5 to 15 atomic % nitrogen, It refers to a material containing 25 to 35 atomic % silicon and 0.1 to 10 atomic % hydrogen. Silicon nitride oxide is a material whose composition contains more nitrogen than oxygen. Therefore, preferably, the composition range is 50% oxygen or less when measured using RBS and HFS. ~30 atomic %, nitrogen 20~55 atomic %, silicon 25~35 atomic %, hydrogen 10~3 0 atomic %. However, silicon oxynitride or silicon oxynitride When the total number of atoms constituting silicon is 100 atomic %, the content of nitrogen, oxygen, silicon and hydrogen is The ownership ratio shall be within the above range.

[0064] The microcrystalline semiconductor forming the microcrystalline semiconductor layer 1115a has an amorphous structure and a crystalline structure (single crystal, polycrystalline, etc.). It is a semiconductor with an intermediate structure between the crystalline and noncrystalline semiconductors. A semiconductor having a third state, which is a crystalline semiconductor with short-range order and lattice distortion. The crystal grain size is 2 nm or more and 200 nm or less, preferably 10 nm or more and 80 nm or less. More preferably, columnar or needle-shaped crystals of 20 nm to 50 nm are formed on the substrate surface. Therefore, at the interface between the columnar or needle-like crystals, there are grain boundaries. may also be formed.

[0065] Microcrystalline silicon, a typical example of a microcrystalline semiconductor, has a Raman spectrum that is similar to that of single-crystal silicon. Indicates 520cm -1 The wave number is shifted to the lower side than that of single crystal silicon. 520cm -1 and 480 cm, which indicates amorphous silicon -1 Between the microcrystalline silicon It also shows the peaks in the Mann spectrum. It contains at least 1 atomic % or more of hydrogen or halogen. The lattice distortion is further reduced by adding rare gas elements such as fluorine, argon, krypton, or neon. By promoting this, the stability is increased and a good microcrystalline semiconductor can be obtained. Such a description is disclosed, for example, in US Pat. No. 4,409,134.

[0066] In addition, oxygen and nitrogen contained in the microcrystalline semiconductor layer 1115a were analyzed by secondary ion mass spectrometry. The concentration measured is 1×10 18 atoms / cm 3 By making it less than This is preferable because it can increase the crystallinity of the layer 1115a.

[0067] The layer 1129c containing an amorphous semiconductor has an amorphous structure. The grain size is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. In this case, compared to conventional amorphous semiconductor layers, the CPM (Constant Phase Modulation) photocurrent method) and photoluminescence spectroscopy. A semiconductor layer with a low energy Urbach edge and a small defect absorption spectrum is The amorphous semiconductor layer 1129c is a layer containing an amorphous semiconductor. The orderly structure has a low level and a steep slope of the tail of the level at the edge of the valence band. The high-temperature semiconductor layer is referred to as a layer 1129c containing an amorphous semiconductor. 9c has a steep slope of the tail of the level at the edge of the valence band, The gap widens, making it difficult for tunnel current to flow.

[0068] The amorphous semiconductor of the layer 1129c containing an amorphous semiconductor is typically an amorphous silicon. It's Recon.

[0069] The layer 1129c containing the amorphous semiconductor may also contain nitrogen or an NH group.

[0070] FIG. 18 shows the gate insulating layer 1105 of FIG. 17 and the insulating layers 1102 functioning as source and drain regions. 11 shows an enlarged view of the impurity semiconductor layer 1127, and particularly shows the mixed layer 1115b in detail. vinegar.

[0071] As shown in FIG. 18A, the mixed layer 1115b is a layer including a microcrystalline semiconductor layer 1115a and an amorphous The mixed layer 1115b is provided between the layers 1129c containing a semiconductor. The region 1108a and the amorphous semiconductor region filled between the microcrystalline semiconductor regions 1108a Specifically, the microcrystalline semiconductor layer 1115a has a protruding region 1108b. The semiconductor region 1108a and the layer 1129c containing an amorphous semiconductor are formed of the same semiconductor. The amorphous semiconductor region 1108b is formed of the mixed layer 1115b. The semiconductor region 1108b is provided with a particle size of 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. The following semiconductor grains may also be included:

[0072] The microcrystalline semiconductor region 1108a is formed by the gate insulating layer 1105 to the layer 112 containing an amorphous semiconductor. The gate insulating film is a microcrystalline semiconductor with a convex or pyramidal shape that narrows toward the tip. A convex or pyramidal shape whose width increases from the edge layer 1105 toward the layer 1129c containing the amorphous semiconductor. It may be a microcrystalline semiconductor.

[0073] In the mixed layer 1115b, the microcrystalline semiconductor region 1108a is In the case where the tip of the convex portion narrows toward the layer 1129c containing the amorphous semiconductor, the microcrystalline semiconductor layer The microcrystalline semiconductor region on the 1115a side is larger than the amorphous semiconductor-containing layer 1129c side. This is because the ratio of the microcrystalline semiconductor region 1115a to the surface of the microcrystalline semiconductor layer 1115b is high. The 08a grows in the film thickness direction, but the source gas contains nitrogen or the source gas The flow rate of hydrogen to silane is adjusted based on the deposition conditions of the microcrystalline semiconductor layer. When the amount of the crystalline semiconductor is reduced, the growth of the semiconductor crystal grains in the microcrystalline semiconductor region 1108a is suppressed, and the cone-shaped This is because semiconductor crystal grains are formed and amorphous semiconductor is eventually deposited.

[0074] The microcrystalline semiconductor region 1108a included in the mixed layer 1115b is The mixed layer 1115b is a semiconductor of substantially the same quality as the amorphous semiconductor region 1115a. The layer 108b is a semiconductor of substantially the same quality as the layer 1129c containing an amorphous semiconductor. The interface between the crystalline semiconductor layer and the layer containing the amorphous semiconductor is the microcrystalline semiconductor region 110 in the mixed layer. 8a and the amorphous semiconductor region 1108b. It can also be said that the interface of the semiconductor-containing layer is uneven.

[0075] In the mixed layer 1115b, the cone-shaped microcrystalline semiconductor region 1108a is included, and thus the vertical direction Resistance in the film thickness direction, that is, the resistance between the microcrystalline semiconductor layer 1115a and the source region or the drain region It is possible to reduce the resistance between the impurity semiconductor layers 1127 which function as in-regions.

[0076] Therefore, the channel region is formed of the microcrystalline semiconductor layer 1115a, and the channel region and the source region are formed of the microcrystalline semiconductor layer 1115b. A cone-shaped microcrystalline semiconductor layer is formed between the impurity semiconductor layer 1127 which functions as a drain region and a drain region. The mixed layer 1115b has a bulk region 1108a and a low-defect, valence band edge. Amorphous semiconductors are formed in highly ordered semiconductor layers with steeply sloped tails of the levels By providing the layer 1129c including a conductor, the off-state current of the thin film transistor can be reduced. Furthermore, it is possible to increase the on-current and field-effect mobility.

[0077] As shown in FIG. 18B, the mixed layer 1115b is a microcrystalline semiconductor layer 1115a and a The mixed layer 1115b is provided between the impurity semiconductor layer 1127. In some cases, the layer 1129c containing an amorphous semiconductor is not formed between the first and second semiconductor layers. In this structure, the ratio of the microcrystalline semiconductor region 1108a to the amorphous semiconductor region 1108b is As a result, the off-state current of the thin film transistor can be reduced. In addition, in the mixed layer 1115b, the resistance in the vertical direction (thickness direction) and the source region It is possible to reduce the resistance between the drain region and the thin film transistor, thereby increasing the on-current. It is possible to do this.

[0078] The mixed layer 1115b preferably contains nitrogen, typically an NH group or an NH2 group. This is because the interface of the semiconductor crystal grains included in the microcrystalline semiconductor region 1108a or the microcrystalline At the interface between the crystalline semiconductor region 1108a and the amorphous semiconductor region 1108b, nitrogen, typically When an NH or NH2 group bonds with a dangling bond of a silicon atom, a defect occurs. For this reason, the nitrogen concentration is reduced to 1×10 20 cm -3 〜1×10 21 cm -3 By this, the dangling bonds of silicon atoms are crosslinked with nitrogen, preferably with NH groups. The semiconductor atoms at the interface become more easily dissociated, and carriers flow more easily. The dangling bonds are terminated with NH2 groups, and the defect level disappears. As a result, the on state Resistance in the vertical direction (thickness direction) when a voltage is applied between the source electrode and the drain electrode That is, the field effect mobility and on-current of the thin film transistor are increased.

[0079] In addition, by reducing the oxygen concentration in the mixed layer 1115b, the microcrystalline semiconductor region 1108a and the The carriers at the interface with the amorphous semiconductor region 1108b and the interface between the semiconductor crystal grains Defects that impede movement can be reduced.

[0080] Note that the microcrystalline semiconductor layer 1115a here refers to a region having a substantially uniform thickness. The interface between the crystalline semiconductor layer 1115a and the mixed layer 1115b is a microcrystalline semiconductor region 1115a. At the flat portion at the interface with the amorphous semiconductor region 1108b, the gate insulating layer 1105 The area is an extension of the nearest area.

[0081] The total thickness of the microcrystalline semiconductor layer 1115a and the mixed layer 1115b, that is, the gate insulating layer 11 The distance from the interface of the semiconductor substrate 1105 to the tip of the protruding microcrystalline semiconductor region 1108a is 3 nm or more and 80 nm or less. nm or less, preferably 5 nm to 50 nm, The flow can be reduced.

[0082] The impurity semiconductor layer 1127 is made of amorphous silicon doped with phosphorus, The thin film transistor is formed of microcrystalline silicon or the like. When a transistor is formed, the impurity semiconductor layer 1127 is made of microcrystalline silicon doped with boron. The mixed layer 1115b is formed of amorphous silicon or amorphous silicon doped with boron. Alternatively, the layer 1129c containing an amorphous semiconductor and the wiring 1125 may be in ohmic contact. In this case, the impurity semiconductor layer 1127 does not need to be formed.

[0083] The impurity semiconductor layer 1127 is made of microcrystalline silicon doped with phosphorus or microcrystalline silicon doped with boron. When the mixed layer 1115b is formed of microcrystalline silicon containing an amorphous semiconductor, A microcrystalline semiconductor layer, typically a microcrystalline By forming a silicon layer, the interface characteristics can be improved. The interface between the semiconductor layer 1127 and the mixed layer 1115b or the layer 1129c containing an amorphous semiconductor As a result, the resistance occurring in the source region of the thin film transistor, a crystalline semiconductor layer 1115a, a mixed layer 1115b, and a layer 1129c containing an amorphous semiconductor; It is possible to increase the amount of current flowing through the drain region, thereby increasing the on-current and field effect mobility. do.

[0084] The wiring 1125 shown in FIG. 19 is made of aluminum, copper, titanium, neodymium, scandium, molybdenum, Formed in a single layer or laminated with ribdenum, chromium, tantalum, tungsten, etc. Alternatively, an aluminum alloy containing an anti-hillock element (such as a gate electrode) can be used. The electrode 1103 may be made of an Al-Nd alloy or the like. The layer on the side in contact with the body layer 1127 is made of titanium, tantalum, molybdenum, tungsten or It is formed by nitrides of these elements, and aluminum or aluminum alloy is formed on it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be laminated. The surface is coated with titanium, tantalum, molybdenum, or tungsten, or with the nitrides of these elements. It may also have a laminated structure in which the material is sandwiched between oxides.

[0085] The thin film transistors shown in FIGS. 18 and 19 have reduced off-state current and reduced on-state current. It is possible to increase the field effect mobility. In addition, the channel region is formed of a microcrystalline semiconductor layer. Therefore, there is little deterioration and the reliability of the electrical characteristics is high. Compared to thin-film transistors that use amorphous silicon for the channel region, It is possible to reduce the area of ​​the thin film transistor, i.e., the area occupied by the thin film transistor. This allows for high integration of the devices.

[0086] (Structure 2) FIG. 19 is a cross-sectional view of one mode of a thin film transistor. A gate electrode 1103 is provided on a substrate 1101, and a gate insulating layer 1103 is provided to cover the gate electrode 1103. 1105, and a microcrystalline semiconductor layer that is in contact with the gate insulating layer 1105 and functions as a channel region. a pair of layers 1132 containing an amorphous semiconductor on the microcrystalline semiconductor layer 1131; and the amorphous semiconductor layer 1132 is in contact with the amorphous semiconductor layer 1132 and functions as a source region and a drain region. The impurity semiconductor layer 1127 has a function of forming a wiring 1. The wiring 1125 functions as a source electrode and a drain electrode. A first insulating layer 1135a is formed on the surface of the crystalline semiconductor layer 1131. The second insulating layer 1132 is formed on the surface of the amorphous semiconductor-containing layer 1132 and the impurity semiconductor layer 1127. A third insulating layer 1135e is formed on the surface of the wiring 1125. will be done.

[0087] The first microcrystalline semiconductor layer 1131 is in contact with the gate insulating layer 1105. and a second microcrystalline semiconductor layer 1131a having a plurality of pyramidal protrusions (convex portions). It has.

[0088] The microcrystalline semiconductor layer 1131 has a microcrystalline structure similar to that of the microcrystalline semiconductor layer 1115a described in Embodiment 1. The second microcrystalline semiconductor layer 1131b is formed of a mixed layer 1131a shown in Embodiment 1. The microcrystalline semiconductor region 1108 can be formed in the same manner as the microcrystalline semiconductor region 1108a included in 115b.

[0089] The pair of layers 1132 containing an amorphous semiconductor are the same as the layer 11 containing an amorphous semiconductor described in Embodiment 1. Similar to 29c, it has fewer defects and a valence band edge compared to conventional amorphous semiconductor layers. It can be formed in a highly ordered semiconductor with a steep slope of the tail of the level at Cut.

[0090] The first insulating layer 1135a is an oxide layer obtained by oxidizing the microcrystalline semiconductor layer 1131, a microcrystalline semiconductor a nitride layer obtained by nitriding the layer 1131; an oxynitride layer obtained by nitriding and oxidizing the microcrystalline semiconductor layer 1131; The first insulating layer 1135a is typically formed of an oxide or nitride layer. Examples of the layer include a silicon layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer.

[0091] The second insulating layer 1135c is formed by a pair of the amorphous semiconductor layer 1132 and the impurity semiconductor layer 1133. The oxide layer 127 is oxidized, the pair of amorphous semiconductor-containing layers 1132 is formed, and the impurity semiconductor layer 1 a nitride layer obtained by nitriding 127, a pair of layers 1132 containing amorphous semiconductors, and an impurity semiconductor layer 1 The second insulating layer is formed of an oxynitride layer or a nitride oxide layer obtained by nitriding and oxidizing the first insulating layer 127. Representative examples of the layer 1135c include a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the insulating layer may be an insulating layer in which phosphorus or boron is added. There is a marginal layer.

[0092] The third insulating layer 1135e is an oxide layer formed by oxidizing the wiring 1125, and a nitride layer formed by nitriding the wiring 1125. The nitride layer is formed of an oxynitride layer or a nitride oxide layer obtained by nitriding and oxidizing the wiring 1125. Here, the third insulating layer 1135e is formed on the upper surface and side surfaces of the wiring 1125. However, if the wiring 1125 is formed only on the side surface of the wiring 1125 and not on the top surface of the wiring 1125, Representative examples of the third insulating layer 1135e include a metal oxide layer, a metal nitride layer, a metal The metal layer may be an oxynitride layer, a metal nitride oxide layer, etc. The metal layer may be a gold layer shown as the wiring 1125. It is a group element.

[0093] The layer 1132 containing an amorphous semiconductor has a weak n-type conductivity because it contains an amorphous semiconductor. The density of the amorphous semiconductor layer is lower than that of the microcrystalline semiconductor layer 1131. The second insulating layer 1135c, which is made of silicon or nitride, is a low density, sparse insulating layer and has poor insulating properties. However, in the thin film transistor described in this embodiment, a microcrystalline semiconductor is formed on the back channel side. The first insulating layer 1135a is formed by oxidizing the conductor layer 1131. The microcrystalline semiconductor layer is Since the density is higher than that of the amorphous semiconductor layer, the first insulating layer 1135a also has a high density and insulating properties. Furthermore, the second microcrystalline semiconductor layer 1131b has a plurality of pyramidal protrusions (convex portions). Therefore, the surface is uneven. These factors contribute to reducing the off-state current of thin film transistors. can.

[0094] The thin film transistor described in this embodiment has a fine crystal structure in which a channel region has a plurality of cone-shaped protrusions. a pair of amorphous semiconductor layers in contact with the microcrystalline semiconductor layer; Therefore, compared with thin film transistors having an amorphous semiconductor in the channel region, and a thin-film transistor having a microcrystalline semiconductor in the channel region. The off-state current of the thin film transistor can be reduced compared to that of the conventional thin film transistor.

[0095] The thin film transistors that make up the pulse output circuit are configured as shown in (Structure 1) and (Structure 2) above. By using a thin film transistor with a microcrystalline semiconductor in the channel region, The degree of degradation of transistor characteristics can be reduced, suppressing the degree of degradation of display quality. In addition, when a microcrystalline semiconductor is used for a semiconductor layer of a thin film transistor, Since productivity can be improved, it is possible to increase the size of display devices, reduce costs, or increase yields. It is possible to improve things.

[0096] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0097] (Embodiment 2) In this embodiment mode, one mode of a driver circuit having a different structure from that of the above embodiment modes will be described. .

[0098] The driving circuit functioning as a shift register will be described with reference to FIGS. 7 to 10 and 30. The shift register 700 includes a first pulse output circuit 701_1 to a J-th pulse output circuit 701_2. The power circuit 701_J (where J is preferably a multiple of 4 or greater) is included (see FIG. 7A). Unlike the above embodiment, the first pulse output of the shift register 700 shown in FIG. Each stage of the pulse output circuit 701_1 to the J-th pulse output circuit 701_J is connected to a first wiring 702. A first clock signal CK1 is transmitted through the first wiring 701, a second clock signal CK2 is transmitted through the second wiring 702, and a third clock signal CK3 is transmitted through the third wiring 703. A third clock signal CK3 is transmitted from a wiring 704, and a fourth clock signal C is transmitted from a fourth wiring 705. A reset signal RES is input from K4 and the fifth wiring 706. Also, the pulse output of each stage The circuit receives a start pulse SP or a signal from the previous stage pulse output circuit (previous stage signal L In addition, the pulse output circuit of each stage is connected to the pulse output circuit of the next stage. The signal from the path (called the next stage signal Rin) is input. Also, from the pulse output circuit of each stage a first output signal Gout for outputting to a gate line or a data line, etc., ... Alternatively, a second output signal SRout is output to be input to a pulse output circuit at a subsequent stage. The pulse output circuit is provided with a dummy stage that outputs a signal that does not contribute to the display on the display unit. For example, it is used in the shift register of a gate driver, and pulses are sequentially sent to n gate lines. In a configuration in which the signal is output, the number of stages may be n≦J.

[0099] The first clock signal CK1 to the fourth clock signal CK2 are generated from the first stage pulse output circuit. Specifically, the (J-3) clock The clock signal CK1 and the (J-2)th clock signal CK2 are in a 1 / 4 cycle advanced relationship. The (J-2)th clock signal CK2 and the (J-1)th clock signal CK3 are 1 / 4 cycle apart. The (J-1)th clock signal CK3 and the Jth clock signal CK4 are in a phase-advanced relationship. are in a 1 / 4 period advanced relationship, and the Jth clock signal CK4 and the (J-3)th clock The signal is advanced by 1 / 4 period. As shown in FIG. 7B, the pulse output circuit 701_1 has a first terminal to which a clock signal CK _N (where N is 1) is input, the reset signal RES is input to the second terminal, and the third terminal and one of the first to fourth clock signals different from the clock signal input to the first terminal. The previous signal Lin is input to the 4th terminal, and the 5th terminal The subsequent signal Rin is input to the sixth terminal, the first output signal Gout is output from the seventh terminal, and The second output signal SRout is output from the second output terminal. The second pulse output circuit 701_2 receives a clock signal CK_N (where N is 2) at its first terminal. ) is input to the second terminal, the reset signal RES is input to the third terminal, and the input to the first terminal Any one of the first to fourth clock signals (here, CK3 and CK4) different from the clock signal to be used The previous signal Lin is input to the fourth terminal, and the next signal Rin is input to the fifth terminal. A first output signal Gout is output from the sixth terminal, and a second output signal Gout is output from the seventh terminal. The signal SRout is output. Also, the third stage pulse output circuit, which is an example of the (J-1) stage, A clock signal CK_N (where N is 3) is input to a first terminal of the circuit 701_3, and a clock signal CK_N (where N is 3) is input to a second terminal of the circuit 701_3. The reset signal RES is input to the terminal, and the clock signal input to the first terminal is input to the third terminal. Any one of the first to fourth clock signals (here, CK3) different from the above is input, The previous signal Lin is input to the fourth terminal, the next signal Rin is input to the fifth terminal, and the sixth terminal The first output signal Gout is output from the terminal 1, and the second output signal SRout is output from the seventh terminal. In addition, the fourth-stage pulse output circuit 701_4, which is an example of the J-th stage, has a first terminal The clock signal CK_N (where N is 4) is input to the first terminal, and the reset signal RES is input to the second terminal. and a third terminal receives one of the first to fourth clock signals different from the clock signal input to the first terminal. One of the clock signals (CK4 in this case) is input, and the previous signal Lin is input to the fourth terminal. is input to the fifth terminal, the next stage signal Rin is input to the fifth terminal, and the first output signal Gou is output from the sixth terminal. t is output from the first clock terminal, and the second output signal SRout is output from the seventh terminal. The clock signals CK1 to CK4 are set to H signals (high power supply potential levels) at regular intervals. It is a signal that alternates between a high (low) signal and an L signal (low power supply potential level).

[0100] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. FIG. 7C shows the configuration of the pulse output circuit at the (J-3) stage as an example. The following explanation will be given assuming that the pulse output circuits of each stage are the same as those of the previous examples. The terminals to which the first clock signal CK1 to the fourth clock signal CK4 are input are different. The circuit configuration of the pulse output circuit is as shown in FIG. This is the same as the pulse output circuit shown in FIG. 1(D) of the first embodiment, and the above description is incorporated herein. do.

[0101] Next, the operation of the shift register shown in FIGS. 7(A) to 7(C) will be explained with reference to FIGS. 8 to 11. For the sake of explanation, as shown in FIG. 8(A), similarly to the first embodiment, , the second terminal of the second thin film transistor 112, the gate of the sixth thin film transistor 116, and The connection point of the seventh thin film transistor 117 is referred to as node A. To specifically explain the operation of the register, the timing chart of FIG. , a first period T1, a second period T2, a third period T3, a fourth period T4, and a fifth period T5. In the following description, the first thin film transistor 111 to the third thin film transistor 112 will be described separately. The thin film transistor 121 is an N-channel thin film transistor, and the gate and source When the voltage (Vgs) between the gate and the gate exceeds the threshold voltage (Vth), the gate is in a conductive state. In FIG. 8B, the gate driver is provided with a shift register. The period 201 is a vertical blanking period, and the period 202 is a gate selection period. In the timing chart shown in B), the first clock signal CK1, the second clock signal C K2, the third clock signal CK3, the fourth clock signal CK4, the reset signal RES, The stage signal Lin, the subsequent stage signal Rin, and the second output signal SRout (for example, A specific example of the waveform of SRout1) in the first row is shown. The power supply potential level and the low power supply potential level are assumed to be VDD and VSS, respectively. The waveform of the first output signal Gout1 is the same as that of the second output signal SRout1. Since the waveform is the same as that shown in

[0102] The configuration shown in this embodiment differs from that of the first embodiment in that the clock signals (first to The first to fourth clock signals CK1 to CK4 are in a cycle of repeating charge and discharge. In comparison with the clock signal CK and the inverted clock signal CKB, in the configuration of this embodiment, This reduces the number of times the clock signal is charged and discharged by half. This reduces the number of pixels and power consumption, especially when driving large display devices. In the circuit, the parasitic capacitance of each wiring and the gate capacitance become large. By reducing the number of times the clock signal is charged and discharged, the signal for charging and discharging each wiring can be reduced. The rising edge (switching from VSS to VDD) or the falling edge (switching from VDD to V This reduces the time required for the image to be displayed (switching to SS). The driving circuit for a display device can perform the above-described operations.

[0103] In the first period T1, the reset signal RES becomes an H signal, and a gate is applied to the second signal line 152. The first thin film transistor 111 to which the second clock signal is connected is turned on. The first clock signal CK2, the first clock signal CK1, the previous signal Lin, and the next signal Rin are L signals. Then, as shown in FIG. 9(A), the first thin film transistor 111 becomes conductive, and the second thin film transistor a third thin film transistor 112, a fourth thin film transistor 113, and a 9A, the fifth thin film transistor 115 is turned on. A current flows, and the potential of each wiring in the first period T1 is determined as shown in FIG. The first period T1 is a period in which the potential of each wiring in the pulse output circuit is reset (to VSS). In the first period T1, the second output signal SRout1 is output as an L signal. become.

[0104] The reset signal RES is input to the gate of the first thin film transistor 111 during a period By performing this every vertical blanking period 201, the potential of each thin film transistor is set to VSS. Therefore, as described in this embodiment, the floating node is used for driving. In a so-called dynamic circuit, each node can be initialized (reset). Therefore, it is possible to improve the operational reliability and noise resistance to the same level as static circuits.

[0105] Next, in the second period T2, the preceding signal Lin becomes an H signal, and the fourth signal line 154 is gated. The eighth thin film transistor 118 and the tenth thin film transistor 120 to which the port is connected are conductive. At this time, the first clock signal CK1, the second clock signal CK2, and the reset signal RES and the subsequent signal Rin are L signals. The second thin film transistor 112 is turned on for the first period T1. Then, current flows as shown by the dotted arrow in Figure 9(B). The potential of the node A is supplied to the first power line 1 through the second terminal of the eighth thin film transistor 118 as the source. The value obtained by subtracting the threshold voltage Vth of the eighth thin film transistor 118 from the potential of the When the second terminal of the eighth thin film transistor 118 becomes (VDD-Vth), The eighth thin film transistor 118 is turned off, and the node A maintains (VDD-Vth). As shown in FIG. 9B, the sixth thin film transistor 116 and and the seventh thin film transistor 117 are conductive, the first signal line 151 is VSS, The potential of each wiring in the second period T2 is determined as shown in FIG. The second period is a period during which the potential of node A in the pulse output circuit is in a floating state. At T2, the second output signal SRout1 outputs an L signal.

[0106] Next, in the third period T3, the first clock signal CK1 becomes an H signal. A second clock signal CK2, a reset signal RES, a front-stage signal Lin, and a rear-stage signal Rin is an L signal. At this time, as shown in FIG. 10(A), the sixth thin film transistor 116 and and the seventh thin film transistor 117 is in a conducting state, that is, a state in which a current flows between the source and the drain. 10(A)), and the sixth thin film transistor 116 and the seventh thin film transistor The potential of the second terminal (source side) of the transistor 117 starts to rise. The capacitance coupling due to parasitic capacitance occurs between the gate and source of the seventh thin film transistor 116 and the seventh thin film transistor 117. When the potential of the second terminal (source) rises, the floating state of node A The potential of the gate rises (bootstrap operation). Eventually, the potential of node A rises to ( VDD+Vth), the sixth thin film transistor 116 and the seventh thin film transistor The potential of the second terminal of the inverter 117 becomes VDD. Then, during the third period T3, the potential of the second output signal S In other words, the third period T3 is a floating state. The potential of node A is raised by the bootstrap operation, and the H signal is output as the first output signal Go The second output signal SRout1 is output as the second output signal SRout1. The signal SRout1 is input as a pre-stage signal Lin to the second-stage pulse output circuit.

[0107] As shown in FIG. 8B, the second thin film transistor, to whose gate a high power supply potential VDD is applied, Providing the register 112 has the following advantages.

[0108] If there is no second thin film transistor 112 to which the high power supply potential VDD is applied to the gate, the boot When the potential of the node A rises due to the strap operation, the second The potential of the source terminal rises and becomes higher than the high power supply potential VDD. The source of the eighth thin film transistor 118 is switched to the first terminal side. In the transistor 118, the gate-source and gate-drain During this time, a large bias voltage is applied, which causes a large stress on the thin film transistor. This can cause deterioration of the resistor.

[0109] By providing a second thin film transistor 112 to the gate of which a high power supply potential VDD is applied, Therefore, although the potential of node A rises due to the bootstrap operation, the This prevents the potential of the second terminal of the resistor 118 from rising. By providing the thin film transistor 112, the gate and the source of the eighth thin film transistor 118 are Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By configuring the circuit in this form, the voltage applied between the gate and source of the thin film transistor Since the negative bias voltage applied to the eighth thin film transistor 118 can be reduced, the stress-induced Deterioration can be further suppressed.

[0110] The second thin film transistor 112 is provided at a position corresponding to the eighth thin film transistor 11 8 and the gate of the sixth thin film transistor 116 or the seventh thin film transistor 117 The first terminal and the second terminal may be connected between the gate of the .

[0111] As in the first embodiment, the third voltage supply VCC shown in FIG. 28(A) is supplied to the conduction holding voltage Vcc. It may be configured to be connected to a power line 2801. Also, the 12th thin film transistor shown in FIG. A resistor 2802 may be provided.

[0112] Next, in the fourth period T4, the subsequent signal Rin( 2B) becomes an H signal, and the gate is connected to the fifth signal line 155. The ninth thin film transistor 119 is turned on. At this time, the second clock signal CK2 is turned on as an H signal. The first clock signal CK1, the reset signal RES, and the previous stage signal Lin are L signals. The third thin film transistor 113, the fourth thin film transistor 114, and the fifth thin film transistor The second thin film transistor 115 and the eleventh thin film transistor 121 are conductive. 112 is conductive following the third period T3, and the sixth thin film transistor 116 and the seventh thin film transistor The potential of the gate of the transistor 117 is set to VSS, so that the sixth thin film transistor 116 , and the seventh thin film transistor 117 is made non-conductive. The current flows as shown in FIG. 8B, and the potential of each wiring in the fourth period T4 is determined as shown in FIG. 8B. That is, in the fourth period T4, the L signal is input to the first output signal Gout1 and the second output signal S It will be output as Rout1.

[0113] In the fourth period T4, the signal ( Here, by supplying a second clock signal CK2, a sixth clock signal Gout is output. This makes it possible to make the potential of the signal line 156 fall sharper, thereby reducing malfunctions. In addition, the third thin film transistor 113 and the fourth thin film transistor Therefore, the loads of the fifth thin film transistor 114 and the fifth thin film transistor 115 can be reduced. As shown in FIG. 30, the deterioration of the 11th thin film transistor can be reduced. The transistor 121 is a plurality of eleventh thin film transistors 121_1 to 121_3. , respectively, are clock signals (herein, Then, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 ) from the third signal lines 153_1 to 153_3 to control the conductive state or non-conductive state. By connecting the third thin film transistor 113 and the fourth thin film transistor The loads of the fifth thin film transistor 114 and the fifth thin film transistor 115 are reduced, This can reduce the deterioration of the transistor.

[0114] Next, in the fifth period T5, the H signals of the first clock signal CK1 and the third clock signal CK3 are The following will be explained in the periods T5-1 and T5-2 in which the L signal and the L signal are input in combination. First, the period T5-1 will be described. During the period T5-1, the first clock signal CK1 becomes a H signal or a L signal, and the third clock signal CK3, the reset signal RES, the previous stage signal The first thin film transistor 111, the eighth thin film transistor 112, and the subsequent signal Rin are L signals. a transistor 118, a ninth thin film transistor 119, and a tenth thin film transistor 120; When the third thin film transistor 113, the fourth thin film transistor 114, and the The potential of the gate of the fifth thin film transistor is kept in a floating state while maintaining the state of the fourth period. That is, the third thin film transistor 113, the fourth thin film transistor 114, and the fifth thin film transistor 115 are connected to each other. The thin film transistor 115 is maintained in a conductive state. The sixth thin film transistor 116 and the seventh thin film transistor 112 are conductive following the fourth period T4. By setting the potential of the gate of the thin film transistor 117 to VSS, the sixth thin film transistor 1 The eleventh thin film transistor 117 is turned off. 121 is in a non-conducting state. Then, a current flows as shown by the dotted arrow in FIG. 11(A), The potential of each wiring in the period T5-1 is determined as shown in FIG. 11(A). The first clock signal CK1 is an H signal or an L signal, and the third clock signal CK3 is an H signal. The reset signal RES, the preceding signal Lin, and the following signal Rin are L signals. As in the period T5-1, the first thin film transistor 111, the eighth thin film transistor 118, When the ninth thin film transistor 119 and the tenth thin film transistor 120 are turned off, a third thin film transistor 113, a fourth thin film transistor 114, and a fifth thin film transistor The potential of the gate of the third thin film transistor is in a floating state while maintaining the state of the fourth thin film transistor. a first thin film transistor 113, a fourth thin film transistor 114, and a fifth thin film transistor 115 The second thin film transistor 112 maintains the conductive state. The sixth thin film transistor 116 and the seventh thin film transistor 117 are turned on after the interval T4. By setting the potential of the gate of the sixth thin film transistor 116 to VSS, The eleventh thin film transistor 121 is in a conductive state. Then, current flows as shown by the dotted arrows in FIG. 11(B), and the current flows through each wiring during period T5-2. The potential is determined as shown in FIG. 8B. That is, in the fifth period T5, the L signal is applied to the first output The output signals are output as the signal Gout1 and the second output signal SRout1.

[0115] Note that, similar to the configuration shown in FIG. 29 of Embodiment 1, a capacitor 2901 is provided separately. You may do so.

[0116] The thin film transistors constituting the pulse output circuit shown in this embodiment are As explained in (Structure 1) and (Structure 2) of Embodiment 1, the channel region is made of a microcrystalline semiconductor. By using a thin film transistor, the degree of deterioration of the characteristics of the thin film transistor can be reduced. This makes it possible to suppress the degree of deterioration of display quality. When a microcrystalline semiconductor is used as the conductive layer, productivity can be improved, and therefore, the display device This allows for the enlargement of the device, reduction in costs, and improvement in yield.

[0117] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0118] (Embodiment 3) In this embodiment mode, a display element, a display device which is a device having a display element, a light-emitting element, a light-emitting element, An example of a light-emitting device having a display element will be described. Display devices, which are devices that emit light, and light-emitting devices, which are devices that have light-emitting elements, are available in various forms. For example, a display element, a display device, a light-emitting element, etc. As a light-emitting device, EL (electroluminescence) elements (organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green color LED, blue LED, etc.), transistors that emit light according to the current, electron emission elements, liquid crystal Devices, electronic ink, electrophoretic devices, grating light valves (GLV), plasma displays Display panels (PDP), digital micromirror devices (DMD), piezoelectric ceramics contrast due to electromagnetic effects, such as black displays and carbon nanotubes The EL element can have a display medium whose brightness, reflectance, transmittance, etc. change. An example of a display device using an electron-emitting device is an EL display, and an example of a display device using an electron-emitting device is a flash display. Field Emission Display (FED) and SED Flat Panel Display (SED :Surface-conduction Electron-emitter Dis ply), and other display devices that use liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays). Play, Transflective LCD, Reflective LCD, Direct View LCD and projection type liquid crystal displays), and electronic ink and electrophoretic element-based display devices include electronic There is paper.

[0119] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. 12(A). The liquid crystal display device includes a circuit 5361, a source driver 5362, a gate driver 5363, and a _1, a gate driver 5363_2, a pixel portion 5364, a circuit 5365, and a lighting device 53 66. In the pixel portion 5364, a plurality of wirings 5371 are connected from the source driver 5362 to the A plurality of wirings 5372 are arranged to connect the gate driver 5363_1 and the gate driver The wirings 5371 and 5372 are arranged extending from the driver 5363_2. In the intersecting area with the line 5372, pixels 5367 each having a display element such as a liquid crystal element are formed. They are arranged in a trix shape.

[0120] The circuit 5361 drives a source driver 5362 and a gate driver 5363 in response to a video signal 5360. 5363_1, the gate driver 5363_2, and the circuit 5365. It has the function of supplying current, etc., and is equipped with a controller, control circuit, timing generator, power supply In this embodiment, the circuit 53 functions as a 61 is a signal line driver circuit start signal (SSP) for the source driver 5362, a signal line Clock signal for driver circuit (SCK), inverted clock signal for signal line driver circuit (SCKB), It shall supply data (DATA) for video signals and latch signals (LAT). The circuit 5361 includes, for example, a gate driver 5363_1 and a gate driver 5363_2. 63_2 is the start signal for the scanning line driving circuit (GSP), the clock signal for the scanning line driving circuit (GCK), and the clock signal for the inverted scanning line driver circuit (GCKB) shall be supplied. Alternatively, the circuit 5361 may supply a backlight control signal (BLC) to the circuit 5365. However, the circuit 5361 is not limited to this, and various other signals, various Voltages or various currents are supplied to the source driver 5362, the gate driver 5363_1, It can be supplied to the gate driver 5363_2 and the circuit 5365.

[0121] The source driver 5362 receives signals (for example, SSP, SCK) supplied from the circuit 5361. , SCKB, DATA, LAT) to output video signals to a plurality of wirings 5371. The gate driver 5363_1 and the gate The driver 5363_2 receives signals (GSP, GCK, GCKB) supplied from the circuit 5361. ) and has a function of outputting scan signals to a plurality of wirings 5372, and serves as a scan line driver circuit. The circuit 5365 functions in response to the signal (BLC) supplied from the circuit 5361. By controlling the amount of power or time supplied to the lighting device 5366, the lighting device 5 It has the function of controlling the brightness (or average brightness) of 366 and can function as a power supply circuit. It is Noh.

[0122] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wirings 53 can function as lines, video signal lines, source lines, or the like. When a scanning signal is input to 72, the plurality of wirings 5372 are signal lines, scanning lines, or gate lines. It functions as a line.

[0123] The same signal is output to the gate driver 5363_1 and the gate driver 5363_2. When input is made from the line 5361, the gate driver 5363_1 outputs to multiple wirings 5372. The gate driver 5363_2 outputs scanning signals to a plurality of wirings 5372. Therefore, the timing of the gate driver 53 is often roughly the same. This can reduce the loads driven by the gate drivers 63_1 and 5363_2. Therefore, the display device can be made larger. Alternatively, the display device can be made higher in resolution. Alternatively, the gate driver 5363_1 and the gate driver 5363_2 have Since the channel width of the thin film transistor can be reduced, a display device with a narrow frame can be obtained. However, the circuit 5361 is not limited to this, and may include a gate driver 5363_ It is possible to supply separate signals to the gate driver 5363_1 and the gate driver 5363_2.

[0124] Note that one of the gate drivers 5363_1 and 5363_2 can be omitted. It is possible to do this.

[0125] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, the gate driver 5363_1 or the gate driver 5363_2 may be A similar circuit is newly added, and this newly added circuit transmits the scanning signal to the newly added wiring. It is possible to output signals such as:

[0126] The pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 12(B), the display element can emit light, so that the circuit 5 365 and the lighting device 5366 can be omitted. In order to supply power, a plurality of wirings 5373 that can function as power supply lines are provided in the pixel portion 53 64. The circuit 5361 distributes a power supply voltage called voltage (ANO). The wiring 5373 is connected to each color element of the pixel. It can be connected to all pixels in common.

[0127] Note that in FIG. 12B, as an example, the circuit 5361 includes a gate driver 5363_1 and a An example of supplying different signals to the gate driver 5363_1 and the gate driver 5363_2 is shown. is the start signal for the scanning line driving circuit (GSP1), the clock signal for the scanning line driving circuit (GC K1), and the clock signal for the inverted scanning line driver circuit (GCKB1) are sent to the gate driver. The circuit 5361 supplies a start signal for the scanning line driver circuit to the driver 5363_1. (GSP2), clock signal for the scanning line driver circuit (GCK2), and for the inversion scanning line driver circuit A signal such as a clock signal (GCKB2) is supplied to the gate driver 5363_2. In this case, the gate driver 5363_1 only drives the odd-numbered wirings among the multiple wirings 5372. The gate driver 5363_2 scans only the even-numbered wirings among the multiple wirings 5372. Therefore, the gate driver 5363_1 and the gate driver Since the drive frequency of the bus 5363_2 can be reduced, power consumption can be reduced. Alternatively, the area in which one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 12A, the circuit 5361 can be The same signal is output to the gate driver 5363_1 and the gate driver 5363_2. is possible.

[0128] 12(B), the circuit 5361 in FIG. 12(A) is also a gate driver. It is possible to supply separate signals to the gate driver 5363_1 and the gate driver 5363_2. do.

[0129] The above is an example of a system block of a display device.

[0130] Next, an example of the configuration of a display device will be described with reference to FIGS. 13(A), (B), (C), and (D). This will be explained in light of the above.

[0131] In FIG. 13A, a circuit (for example, a source driver 5362, gate driver 5363_1, and gate driver 5363_2, etc. ) is formed on the same substrate 5380 as the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Alternatively, the number of signals or voltages input to the substrate 5380 can be reduced. This reduces the number of connections between the substrate 5380 and external components, thereby improving reliability. Alternatively, the yield can be improved.

[0132] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta Flexible PCB (Flexible Printed Circuit) Alternatively, the substrate may be , the pixel part 5364 is mounted on the same substrate 538 by the COG (Chip on Glass) method. It is possible to implement it in 0.

[0133] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is formed on a single crystal semiconductor. Therefore, it is possible to form a transistor using the substrate. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0134] A signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0135] In FIG. 13(B), a circuit with a low driving frequency (for example, a gate driver 5363_1, a gate The gate driver 5363_2 is formed on the same substrate 5380 as the pixel section 5364. The circuit 5361 and the source driver 5362 are formed on a substrate different from that of the pixel portion 5364. Thus, a transistor using a single crystal semiconductor (also called a MOS transistor) The thin film transistor formed on the substrate 5380 has a smaller field effect mobility than the Therefore, it is possible to configure a circuit in which the thin film transistor channel region is Therefore, it is possible to increase the size of a display device and reduce the number of steps. This can reduce the number of parts, reduce costs, or improve yields.

[0136] As shown in FIG. 13C, a part of the source driver 5362 (the source driver 53 62a) is formed on the same substrate 5380 as the pixel section 5364, and the remaining source driver 536 2 (source driver 5362b) can be formed on a substrate separate from the pixel section 5364. The source driver 5362a is a thin film transistor with low field effect mobility. It has configurable circuits (e.g., shift registers, selectors, switches, etc.) The source driver 5362b has high field effect mobility and characteristic variations. It is preferable to use MOS transistors with low resistance (e.g., shift When the device has a register, latch circuit, buffer circuit, DA conversion circuit, AD conversion circuit, etc. By doing so, the channel region of the thin film transistor is It is possible to use microcrystalline semiconductors as a semiconductor region, and it is also possible to reduce the number of external components. can.

[0137] In FIG. 13D, a part of the circuit 5361 (circuit 5361a) is formed on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a has a field effect mobility higher than that of a MOS transistor. Circuits that can be constructed using thin film transistors with small capacitance (e.g., switches, selectors) The circuit 5361b is a field effect It is preferable to use MOS transistors with high mobility and small variations. circuits (e.g., shift registers, timing generators, oscillators, regulators, In many cases, the device has a built-in analog buffer.

[0138] 13(A) to 13(C), the circuit 5361a is mounted on the same substrate as the pixel section 5364. The circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0139] Here, the gate driver 5363_1 and the gate driver 5363_2 are It is possible to use the shift register of the first embodiment or the second embodiment. The gate driver 5363_1, the gate driver 5363_2 and the pixel section are formed on the same substrate. By this, the polarity of all thin film transistors formed on the substrate can be made to be the same conductivity type. Therefore, it is possible to reduce the number of processes, improve yield, and improve reliability. Or, costs can be reduced. All thin film transistors are N-channel type. In some cases, a microcrystalline semiconductor can be used as the semiconductor layer of a thin film transistor. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yields. In addition, by using a microcrystalline semiconductor for the semiconductor layer, deterioration of the characteristics of a thin film transistor can be suppressed. Since the amount of light emitted can be controlled, the life of the display device can be extended.

[0140] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0141] (Fourth embodiment) In this embodiment, an example of a source driver will be described.

[0142] An example of a source driver will be described with reference to FIG. A plurality of circuits 602_1 to 602_N (N is a natural number), a circuit 600, and a circuit 6 01. Each of the circuits 602_1 to 602_N includes a thin film transistor 60 It has multiple thin film transistors, numbered 3_1 to 603_k (k is a natural number). The registers 603_1 to 603_k are the pulse outputs of the shift registers described in the above embodiment. It is assumed that the conductive type is the same as that of the thin film transistors that make up the circuit.

[0143] The connection relationship of the source driver will be explained using the circuit 602_1 as an example. The first terminals of the thin film transistors 603_1 to 603_k are connected to the wiring 605_1. The second terminals of the thin film transistors 603_1 to 603_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 603_1 to 603_k are connected to the wirings 604_1 to 604_k, respectively. For example, a first terminal of the thin film transistor 603_1 is connected to a wiring 605_1. A second terminal of the thin film transistor 603_1 is connected to the wiring S1. The gate of the first transistor 603_1 is connected to a wiring 604_1.

[0144] The circuit 600 transmits signals to circuits 602_1 to 602_k via wirings 604_1 to 604_k. N, and can function as a shift register, decoder, etc. This signal is often a digital signal and can function as a selection signal. The wirings 604_1 to 604_k can function as signal lines. be.

[0145] The circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and is a video signal generator. For example, the circuit 601 can function as a At the same time, a signal is supplied to the circuit 602_1 via the wiring 605_2. The signal is often an analog signal and functions as a video signal. The wirings 605_1 to 605_N can function as signal lines. It is possible to do this.

[0146] The circuits 602_1 to 602_N select the wiring to which the output signal of the circuit 601 is to be output. For example, the circuit 602 has a function of selecting a _1 indicates which of the wirings S1 to Sk the signal output from the circuit 601 to the wiring 605_1 is connected to. It has the function to select whether to output to

[0147] The thin film transistors 603_1 to 603_N are arranged in accordance with the output signal of the circuit 600. The line 605_1 has a function of controlling the conduction state between the wirings S1 to Sk, and functions as a switch. It works.

[0148] Next, the operation of the source driver in FIG. 14(A) will be explained with reference to the timing chart in FIG. 14(B). 14B, a signal 614_1 input to a wiring 604_1 is , a signal 614_2 input to the wiring 604_2, a signal 614_k input to the wiring 604_k, _k, a signal 615_1 input to the wiring 605_1, and a signal 615_2 input to the wiring 605_2. An example of No. 615_2 is shown below.

[0149] The operating period of the source driver corresponds to one gate selection period in the display device. The gate selection period is a period during which pixels belonging to a certain row are selected and a video signal is written to the selected pixels. This refers to the period during which it is possible to

[0150] One gate selection period is divided into periods T0, T1, and Tk. is a period for simultaneously applying a precharge voltage to pixels belonging to a selected row. The periods T1 to Tk can function as precharge periods. This is the period for writing video signals to pixels belonging to the selected row, and functions as a write period. It is possible to do this.

[0151] For convenience, the operation of the source driver will be explained using the operation of the circuit 602_1 as an example.

[0152] First, in a period T0, the circuit 600 applies an H-level signal to the wirings 604_1 to 604_k. Then, the voltages between the sources and drains of the thin film transistors 603_1 to 603_k are Since the wiring 605_1 is electrically connected to the wirings S1 to Sk, the wiring 605_1 and the wirings S1 to Sk are electrically connected to each other. The circuit 601 supplies a precharge voltage Vp to the wiring 605_1. The voltage Vp is applied to the wirings S1 to Sk via the thin film transistors 603_1 to 603_k. The precharge voltage Vp is written to the pixels belonging to the selected row. As the signal is input, the pixels belonging to the selected row are precharged.

[0153] Next, in the period T1, the circuit 600 outputs an H-level signal to the wiring 604_1. Then, the source and drain of the thin film transistor 603_1 are electrically connected, and the wiring 6 Then, the wiring 605_1 and the wiring S2 to Sk are electrically connected. At this time, the circuit 601 outputs the signal Data (S1) to the wiring 605_1. If the signal Data (S1) is output, the signal Data (S1) is output via the thin film transistor 603_1. In this way, the signal Data (S1) is output to the pixel connected to the line S1. The pixel data is written to the pixels belonging to the selected row among the pixels.

[0154] Next, in a period T2, the circuit 600 outputs an H-level signal to the wiring 604_2. Then, the source and drain of the thin film transistor 603_2 are electrically connected, and the wiring 6 The wiring 605_2 and the wiring S2 are electrically connected. The wiring 605_1 and the wiring S1 are electrically disconnected. In this state, the wiring 605_1 and the wirings S3 to Sk remain in a non-conductive state. If the circuit 601 outputs the signal Data (S2) to the wiring 605_1, the signal D The ata (S2) is output to the wiring S2 via the thin film transistor 603_2. The signal Data(S1) is output from the pixels connected to the line S1 and belonging to the selected row. The pixel is written to.

[0155] After that, until the period Tk, the circuit 600 outputs a high-level signal to the wirings 604_1 to 604_k. Since the signals are output in sequence, the signals are output in the same manner as in the periods T1 and T2, from the period T3 to the period Tk. 00 outputs a high-level signal to the wirings 604_3 to 604_k in order. The sources and drains of the transistors 603_3 to 603_k are sequentially conductive, so that the thin film The sources and drains of the transistors 603_1 to 603_k are sequentially brought into conduction. Therefore, the signal output from the circuit 601 is output to the wirings S1 to Sk in order. Signals can then be written in order to the pixels belonging to the selected row.

[0156] An example of the source driver has been described above. Since the circuit has a function as a connector, the number of signals or the number of wirings can be reduced. Furthermore, before writing a video signal to the pixel (period T0), a voltage for precharging is applied. is written to the pixel, the time required to write the video signal can be shortened. This allows for larger display devices and higher resolution display devices. It is possible to omit period T0 and not precharge the pixels.

[0157] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so it is preferable that k≦6. More preferably, k≦3. Further preferably, k=2. It's nice.

[0158] In particular, if the color components of a pixel are divided into n (n is a natural number), it is possible to set k=n. For example, if the color components of a pixel are divided into three components, red (R), green (G), and blue (B), , k=3. In this case, one gate selection period includes a period T0, a period T1, , period T2, and period T3. In periods T1, T2, and T3, It is possible to write video signals to red (R), green (G), and blue (B) pixels. However, the order of the periods T1, T2, and T3 is not limited to this, and can be set arbitrarily. It is possible to do this.

[0159] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, then k=n. In this case, one gate selection period is the period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible to do this.

[0160] In addition, since the driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are often low, The circuit 600 and the circuits 602_1 to 602_N may be formed on the same substrate as the pixel portion. In this way, it is possible to reduce the number of connections between the substrate on which the pixel section is formed and the external circuit. Therefore, it is possible to improve the yield or reliability.

[0161] The circuit 600 may be implemented using the shift register of the first or second embodiment. In this case, the polarity of all thin film transistors in the circuit 600 is N-channel. In the case of a panel type, a microcrystalline semiconductor is used as the semiconductor layer of the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yields. Furthermore, by using a microcrystalline semiconductor as a semiconductor layer, the characteristics of a thin film transistor can be improved. Since deterioration can be suppressed, the life of the display device can be extended.

[0162] It should be noted that not only the circuit 600 but also all the thin-film transistors included in the circuits 602_1 to 602_N The polarity of the transistors can be the same conductivity type. When 02_1 to 602_N are formed on the same substrate as the pixel section, the number of processes can be reduced and the yield can be improved. In addition, when a microcrystalline semiconductor is used as a semiconductor layer, the semiconductor layer can be formed using a semiconductor material. This can suppress the deterioration of the thin film transistor characteristics, thereby extending the life of the display device. It can be made longer.

[0163] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0164] (Embodiment 5) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0165] 15A shows an example of a pixel. The pixel 5420 includes a thin film transistor 5321, a liquid crystal display (LCD), and a The thin film transistor 5321 includes an element 5422 and a capacitor 5423. The first terminal of the thin film transistor 5321 is connected to the wiring 5431, and the second terminal of the thin film transistor 5321 is connected to the liquid crystal element One electrode of the thin film transistor 5422 and one electrode of the capacitor element 5423 are connected to each other. The gate of the liquid crystal element 5321 is connected to a wiring 5432. The other electrode of the liquid crystal element 5422 is connected to a The other electrode of the capacitor 5423 is connected to a wiring 5433 .

[0166] A liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystals. It is composed of a pair of electrodes and liquid crystal. Controlled by the electric field applied to the crystal (including the horizontal electric field, the vertical electric field, or the diagonal electric field) The liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, smectic Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, Polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, Examples include side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALCs), and banana-shaped liquid crystals. The liquid crystal driving method is Twisted Nematic (TN). mode, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, MVA (Multi-domain Vertical Alignment gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr systal mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, guest host mode, Blue Phase mode etc. can be used.

[0167] For example, a video signal is input to the wiring 5431. For example, a A scanning signal, a selection signal, or a gate signal is input to the wiring 5433. , a constant voltage is supplied to the electrode 5434. As an example, a constant voltage is supplied to the electrode 5434. However, this is not limiting, and the wiring 5431 may be supplied with a precharge voltage. The time required for writing the video signal can be shortened by using the wiring 5433. By inputting a signal, it is possible to control the voltage applied to the liquid crystal element 5422. Alternatively, a signal is input to the electrode 5434 to perform frame inversion driving. It is possible to achieve this.

[0168] The wiring 5431 functions as a signal line, a video signal line, or a source line. The wiring 5432 functions as a signal line, a scanning line, or a gate line. The electrode 5434 functions as a common electrode or a counter electrode. However, without being limited to this, when a voltage is supplied to the wiring 5431 and the wiring 5432, The wiring 5433 functions as a power supply line. 5433 functions as a signal line.

[0169] The thin film transistor 5421 is electrically connected to the wiring 5431 and one electrode of the liquid crystal element 5422. By controlling the state of the pixel, it is possible to control the timing of writing a video signal to the pixel. The capacitor 5423 can function as a switch. A potential difference is maintained between one electrode and the wiring 5433, and a potential is applied to the liquid crystal element 5422. It has the function of keeping the voltage constant and functions as a storage capacitor. However, it is not limited to this. stomach.

[0170] FIG. 15B is a timing chart for explaining the operation of the pixel of FIG. 15A. 15B shows an example of a signal 5442_j (j is a natural number), a signal 5442_j+1 , a signal 5441_i (i is a natural number), a signal 5441_i+1, and a voltage 5442 are shown. FIG. 15(B) shows the k-th (k is a natural number) frame and the k+1-th frame. Note that the signals 5442_j, ​​5442_j+1, 5441_i, and 5441_i +1 and a voltage 5442 are signals input to the wiring 5432 in the jth row, and the j+1th row a signal input to the wiring 5432 in the i-th column, a signal input to the wiring 5431 in the i+1-th column, 5 is an example of a signal input to the wiring 5431 and a voltage supplied to the wiring 5432.

[0171] The operation of the pixel 5420 belonging to the jth row and the ith column will be described. When the voltage Vcc is 0, the source and drain of the thin film transistor 5421 are electrically connected. Since the wiring 5431 in the column and one electrode of the liquid crystal element 5422 are electrically connected, the signal 54 41_j is input to one electrode of a liquid crystal element 5422 via a thin film transistor 5421. The capacitor 5423 is connected to the potential of one electrode of the liquid crystal element 5422 at this time. The potential difference with the potential of the wiring 5433 is maintained. The voltage applied to the liquid crystal element 5422 is constant until the voltage reaches the level. 5422 expresses a gray scale according to the applied voltage.

[0172] In FIG. 15B, positive and negative polarity signals are alternately arranged for each row selection period. This shows an example of input to the line 5431. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A negative signal is a signal whose potential is higher than the reference value. (for example, the potential of the electrode 5434). The signal input to the wiring 5431 can have the same polarity during one frame period. do.

[0173] In addition, in FIG. 15(B), the polarity of the signal 5441_i and the polarity of the signal 5441_i+1 are different. However, the present invention is not limited to this example, and the polarity and The polarity of signal 5441_i+1 may be the same.

[0174] 15B shows a period in which the signal 5442_j is at H level and a period in which the signal 5442_j is at H level. This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 15C, there is a period in which the signal 5442_j is at H level and a period in which the signal 5442_j is at H level. 42_j+1 is at H level. In this case, the period when the wiring 543 It is preferable that signals of the same polarity are supplied to all the inputs during one frame. By using the signal 5441_j written to the pixel in the jth row, the pixel in the j+1th row is This allows the time required to write a video signal to the pixel to be shortened. Therefore, the display device can be made high-definition. Alternatively, the same wiring 5431 can be used in one frame period. Since a polarity signal is input, power consumption can be reduced.

[0175] It should be noted that the pixel configuration of FIG. 16(A) and the timing chart of FIG. 15(C) can be combined. In this way, dot inversion driving can be realized. The pixel 5420(i, j) is connected to the wiring 5431_i. j+1) is connected to the wiring 5431_i+1. In this way, the i-th row is connected to the wiring 5431_i and the wiring 5431_i+1 alternately. The pixels belonging to the eye are written with positive and negative polarity signals alternately, row by row. However, the present invention is not limited to this, and the dot inversion driving can be realized. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 5431_i and the wiring 5431 _i+1.

[0176] It should be noted that a sub-pixel structure can be used as the pixel configuration. (C) shows a configuration in which a pixel is divided into two sub-pixels. Figure 16(B) shows a subpixel structure called 1S+2G, and Figure 16(C) shows a subpixel structure called 2S+1 The subpixel structure shown is called G. Subpixel 5420A and subpixel 5420B are This corresponds to the pixel 5420. corresponds to the thin film transistor 5421. The liquid crystal elements 5422A and 5422B corresponds to the liquid crystal element 5422. The capacitors 5423A and 5423B are capacitors The wiring 5431A and the wiring 5431B correspond to the wiring 5431. The wiring 5432A and the wiring 5432B correspond to the wiring 5432.

[0177] Here, when the pixel of this embodiment is combined with each of the configurations of the first to fourth embodiments, For example, as a pixel, When using this structure, the number of signals required to drive the display device increases. As a result, the number of gate lines or source lines on the substrate on which the pixel portion is formed increases. However, if the number of gate lines increases, the number of connections to external circuits may increase significantly. However, as shown in Embodiment 3, the scanning line driver circuit can be formed on the same substrate as the pixel portion. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be significantly increased. Alternatively, the number of source lines can be increased, and a pixel with a sub-pixel structure can be used. In addition, by using the source driver of the fourth embodiment, the number of source lines can be reduced. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be significantly increased. Therefore, pixels with a sub-pixel structure can be used without the need for a pixel shifter.

[0178] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0179] (Embodiment 6) In this embodiment mode, a manufacturing method of the thin film transistor shown in Embodiment 1 will be described with reference to FIGS. This will be explained with reference to FIG.

[0180] Here, if all thin film transistors formed on the same substrate are unified to the same polarity, the process Therefore, in this embodiment, the number of n-type thin film transistors can be reduced. The method for manufacturing the capacitor will be described below.

[0181] (Method 1) First, the manufacturing process of the thin film transistor shown in FIG. 17 will be described with reference to FIG. As shown in (A), a gate electrode 1103 is formed on a substrate 1101. Next, After forming a gate insulating layer 1105 that covers the electrode 1103, a first semiconductor layer 1106 is formed. Complete.

[0182] The gate electrode 1103 is formed on the substrate 1101 by sputtering or vacuum deposition. A conductive layer is formed using the material shown in Embodiment Mode 1, and a photolithography method or Alternatively, a mask is formed by an ink-jet method or the like, and the conductive layer is etched using the mask. In addition, conductive nanopaste such as silver, gold, or copper can be formed by inkjet printing. Alternatively, the substrate 11 may be formed by discharging the film on the substrate by a baking method and baking the film. A conductive layer is formed on the substrate, and etching is performed using a resist mask formed using a photomask. Then, the gate electrode 1103 is formed.

[0183] In the photolithography process, the resist may be applied to the entire surface of the substrate. After printing the resist in the area where the resist mask is to be formed, the resist is exposed to light. It is possible to save on resist and reduce costs. Instead of exposing the resist, the resist may be exposed by a laser beam direct writing device.

[0184] In addition, the side surface of the gate electrode 1103 is tapered, so that the surface of the gate electrode 1103 This can reduce wiring breakage at the step of the semiconductor layer and wiring layer formed on the substrate. In order to make the side surface of the gate electrode 1103 tapered, the resist mask is recessed. Etching can be performed while

[0185] In addition, in the process of forming the gate electrode 1103, the gate wiring (scanning line) and the capacitance wiring are also formed at the same time. The scanning line is a line for selecting a pixel, and the capacitance line is a line for selecting a pixel. However, it is not limited to this and may also refer to a gate wiring. Either or both of the line and the capacitor wiring and the gate electrode 1103 may be formed in separate steps.

[0186] The gate insulating layer 1105 is formed by the CVD method, the sputtering method, or the like, as in the first embodiment. The gate insulating layer 1105 can be formed using the materials shown in the above. It may be formed using a microwave plasma CVD apparatus (1 GHz or higher). When the gate insulating layer 1105 is formed using a plasma CVD apparatus, the gate electrode and the drain This improves the breakdown voltage between the source and source electrodes, resulting in a highly reliable thin-film transistor. In addition, organic silane gas is used as the gate insulating layer 1105. By forming a silicon oxide layer using the CVD method, the crystallization of the microcrystalline semiconductor layer to be formed later is minimized. Since it is possible to improve the crystallinity, the on-current and field effect mobility of thin film transistors can be improved. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(O C2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethyl Trimethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OM CTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2 Silicon compounds such as tris(dimethylamino)silane (SiH(N(CH3)2)3) and tris(dimethylamino)silane (SiH(N(CH3)2)3) A containing compound can be used.

[0187] The first semiconductor layer 1106 may be made of microcrystalline silicon, microcrystalline silicon germanium, or microcrystalline silicon. The first semiconductor layer 1106 is formed using crystalline germanium or the like. The thickness of the first semiconductor layer 1106 is 3 to 10 nm. By thinning the second semiconductor layer to 100 nm, preferably 3 to 5 nm, the second semiconductor layer to be formed later will be The length of multiple pyramidal protrusions (convex portions) formed from microcrystalline semiconductors is controlled to form thin-film transistors. The on-current and off-current of the capacitor can be controlled.

[0188] The first semiconductor layer 1106 is formed by depositing silicon or silicon nitride in a reaction chamber of a plasma CVD apparatus. A deposition gas containing ruthenium is mixed with hydrogen and formed by glow discharge plasma. Alternatively, a deposition gas containing silicon or germanium, hydrogen, helium, neon, It is formed by mixing rare gases such as krypton with silicon and using glow discharge plasma. The flow rate of hydrogen is preferably 10 to 2000 times the flow rate of the deposition gas containing germanium. It is usually diluted 10 to 200 times to produce microcrystalline silicon, microcrystalline silicon germanium, and microcrystalline silicon. Form germanium, etc.

[0189] Representative examples of deposition gases containing silicon or germanium include SiH4, Si2H6 , GeH4, Ge2H6, etc.

[0190] The raw material gas for the first semiconductor layer 1106 is helium, argon, neon, krypton, By using a rare gas such as xenon, the deposition rate of the first semiconductor layer 1106 is increased. The increased film formation rate reduces the amount of impurities mixed into the first semiconductor layer 1106. Therefore, the crystallinity of the first semiconductor layer 1106 can be improved. The on-current and field effect mobility of the thin film transistor are increased, and the productivity of the thin film transistor is improved. This can be done.

[0191] When forming the first semiconductor layer 1106, the glow discharge plasma is generated at a frequency of 3 MHz to 3 0MHz, typically 13.56MHz, 27.12MHz HF band high frequency power, is the high frequency power in the VHF band, which is greater than 30MHz and up to about 300MHz, typically 6 It is also possible to apply microwave power of 1 GHz or higher. In addition, by using high frequency power in the VHF band or microwave, film formation It is possible to increase the speed. Furthermore, the high frequency power in the HF band and the high frequency power in the VHF band By overlapping the plasma, it is possible to reduce plasma unevenness and improve uniformity even on large substrates. This makes it possible to increase the film formation rate.

[0192] Before forming the first semiconductor layer 1106, the gas inside the processing chamber of the CVD apparatus must be exhausted. However, a deposition gas containing silicon or germanium is introduced to remove impurity elements in the processing chamber. By removing the insulating layer 1105 and the first insulating layer 1106 of the thin film transistor to be formed later, It is possible to reduce the amount of impurities in the semiconductor layer 1106, and the electric potential of the thin film transistor can be improved. The thermal characteristics can be improved.

[0193] Next, as shown in FIG. 20(B), a semiconductor layer is deposited on the first semiconductor layer 1106. Next, an impurity semiconductor layer 1107 is formed on the second semiconductor layer 1107. A resist mask 1109 and a conductive layer 1111 are formed on the conductive layer 1111. Form 113

[0194] The first semiconductor layer 1106 is used as a seed crystal, and a microcrystalline semiconductor is grown under the conditions for partial crystal growth. A second semiconductor layer 1107a, a mixed layer 1107b, and a layer 1107c containing an amorphous semiconductor. Here, for convenience, the second semiconductor layer 1107 is formed with the first The structure also includes the semiconductor layer 1106, that is, the first semiconductor layer 1106 is a microcrystalline semiconductor layer 1107. The structure contained in a is shown.

[0195] The second semiconductor layer 1107 is formed by depositing silicon or silicon nitride in the processing chamber of the plasma CVD apparatus. A deposition gas containing ruthenium is mixed with a gas containing hydrogen and nitrogen, and the mixture is heated in a glow discharge plasma. The nitrogen-containing gases are ammonia, nitrogen, nitrogen fluoride, and nitrogen chloride. etc.

[0196] At this time, the flow rate ratio of the deposition gas containing silicon or germanium to hydrogen is set to 1 / 2. The same conditions as for the semiconductor layer 1106 are used to form a microcrystalline semiconductor layer, and nitrogen is included in the source gas. By using a gas, the conditions for reducing crystal growth can be achieved more effectively than the conditions for forming the first semiconductor layer 1106. As a result, in the second semiconductor layer 1107, the mixed layer 1107b and there are few defects, and the slope of the tail of the level at the edge of the valence band is steep. The layer 1107c containing an amorphous semiconductor is formed of a semiconductor layer having a high degree of order. can.

[0197] Here, a typical example of the conditions for forming the second semiconductor layer 1107 is silicon or germanium. The flow rate of hydrogen is 10 to 2000 times, preferably 10 to 2000 times, the flow rate of hydrogen containing deposition gas. A typical example of the conditions for forming a normal amorphous semiconductor layer is silicon or The flow rate of hydrogen is 0 to 5 times the flow rate of the deposition gas containing germanium.

[0198] The source gas for the second semiconductor layer 1107 may be helium, neon, argon, xenon, Alternatively, the film formation rate can be increased by introducing a rare gas such as krypton.

[0199] In the initial stage of deposition of the second semiconductor layer 1107, the first semiconductor layer 1106 is used as a seed crystal. A microcrystalline semiconductor layer is deposited on the entire first semiconductor layer 1106 (initial deposition stage). Since the raw material gas contains nitrogen, the crystal growth is partially suppressed, and the cone-shaped microcrystals are formed. As the crystalline semiconductor region grows, an amorphous semiconductor region is formed (middle stage of deposition). The crystal growth of the pyramidal-shaped microcrystalline semiconductor region stops, and a layer containing an amorphous semiconductor is formed ( late deposition).

[0200] For this reason, the microcrystalline semiconductor layer 1115a shown in FIGS. 17 and 18 is The first semiconductor layer 1106 and the second semiconductor layer 1107 are formed in the initial stage of deposition. This corresponds to the semiconductor layer, that is, the microcrystalline semiconductor layer 1107a shown in FIG.

[0201] 17 and 18. The mixed layer 1115b shown in FIG. 17 and FIG. 18 is the second semiconductor layer shown in FIG. 20(B). The cone-shaped microcrystalline semiconductor regions formed during the middle of the deposition of 1107 and the amorphous semiconductor filling the gaps This corresponds to the layer having the conductive region, that is, the mixed layer 1107b.

[0202] 17 and 18. The layer 1129c containing an amorphous semiconductor shown in FIG. This corresponds to the layer 1107c containing an amorphous semiconductor formed in the later stage of deposition of the second semiconductor layer 1107. do.

[0203] The second semiconductor layer 1107 formed by this method was analyzed by secondary ion mass spectrometry. The nitrogen concentration measured by the method is measured at the boundary between the microcrystalline semiconductor layer 1107a and the mixed layer 1107b. The peak concentration is near the surface, and the mixed layer 1107b and the layer 1107c containing the amorphous semiconductor are stacked. The density is constant in the product direction.

[0204] The impurity semiconductor layer 1109 is formed by depositing silicon in the reaction chamber of the plasma CVD apparatus. The volatile gas, hydrogen, and phosphine (diluted with hydrogen or silane) are mixed and glow discharged. The deposition gas containing silicon is diluted with hydrogen and phosphorus is added. The silicon dioxide is doped with phosphorus to form amorphous silicon or microcrystalline silicon doped with phosphorus.

[0205] The conductive layer 1111 can be formed using a material similar to that of the wiring 1125 shown in FIG. The conductive layer 1111 is formed by using a CVD method, a sputtering method, or a vacuum deposition method. The conductive layer 1111 is formed by screen printing using conductive nanopaste such as silver, gold, or copper. The conductive layer may be formed by discharging the conductive layer by a method such as a liquid crystal display or an ink jet method, and then baking the conductive layer.

[0206] The second resist mask 1113 is formed by a photolithography process. The resist mask 1113 has regions of different thicknesses. By using a multi-tone mask, the photomask to be used can be formed. This is preferable because it reduces the number of masks and the number of manufacturing steps. The step of forming a pattern of the semiconductor layer 1107 and the step of separating the source region and the drain region are also performed. In this step, a multi-tone mask can be used.

[0207] A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity. Representative examples include: Exposure is performed with three levels of light intensity: exposed area, semi-exposed area, and unexposed area. By doing so, a single exposure and development process can be performed to produce a film having multiple (typically two) thicknesses. A resist mask can be formed. Therefore, by using a multi-tone mask, This allows reducing the number of masks required.

[0208] 22(A-1) and 22(B-1) show cross-sectional views of a typical multi-tone mask. 2(A-1) shows a gray-tone mask 1180, and FIG. 22(B-1) shows a half-tone mask. The mask 1185 is shown.

[0209] The gray-tone mask 1180 shown in FIG. 22(A-1) is formed on a light-transmitting substrate 1181. a light-shielding portion 1182 formed by a light-shielding layer, and a diffraction grating formed by a pattern of the light-shielding layer. It is composed of a lattice portion 1183.

[0210] The diffraction grating section 1183 has slits spaced at intervals equal to or less than the resolution limit of the light used for exposure. By providing dots or meshes, the light transmittance can be controlled. The slits, dots or meshes provided in 83 may be periodic or non-periodic. It may also be periodic.

[0211] The light-transmitting substrate 1181 can be made of quartz or the like. The light-shielding layer constituting the diffraction grating portion 1183 is made of chromium or chromium oxide. .

[0212] When the gray-tone mask 1180 is irradiated with light for exposure, the pattern shown in FIG. 22(A-2) appears. As shown in the figure, the light transmittance in the area overlapping the light-shielding portion 1182 is 0%, and the light transmittance in the area overlapping the light-shielding portion 1182 is 0%. Alternatively, the light transmittance in the area where the diffraction grating portion 1183 is not provided is 100%. The light transmittance of the diffraction grating portion 1183 is generally in the range of 10 to 70%. This can be adjusted by adjusting the spacing of the slits, dots or mesh.

[0213] The halftone mask 1185 shown in FIG. 22(B-1) is formed on a light-transmitting substrate 1186. The semi-transparent portion 1187 is formed by a semi-transparent layer, and the light-shielding portion 1188 is formed by a light-shielding layer. It consists of 88.

[0214] The semi-transparent portion 1187 is made of MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. The light-shielding portion 1188 can be formed using the same light-shielding layer as the gray-tone mask. The material may be any of the above, and is preferably chromium or chromium oxide. do.

[0215] When the halftone mask 1185 is irradiated with light for exposure, the pattern shown in FIG. 22(B-2) appears. As shown in the figure, the light transmittance in the area overlapping the light-shielding portion 1188 is 0%, and the light transmittance in the area overlapping the light-shielding portion 1188 is 0%. The light transmittance in the area where the semi-transparent portion 1187 is not provided is 100%. The light transmittance of the semi-transparent portion 1187 is generally in the range of 10 to 70%. It can be adjusted by the type or thickness of the film to be formed.

[0216] By using a multi-tone mask and then performing exposure and development, a resist mask with regions of different thickness can be produced. A mask can be formed.

[0217] Next, using a second resist mask 1113, the second semiconductor layer 1107 and the impurity semiconductor The layer 1109 and the conductive layer 1111 are etched. This process removes the second semiconductor layer 1 107, the impurity semiconductor layer 1109 and the conductive layer 1111 are separated for each element, and a second semiconductor layer A second semiconductor layer 1115, an impurity semiconductor layer 1117, and a conductive layer 1119 are formed. The semiconductor layer 1115 includes a microcrystalline semiconductor layer 1115a, a mixed layer 1115b, and an amorphous semiconductor. The layer 1115c includes a layer 1115b (see FIG. 20(C)).

[0218] Next, the second resist mask 1113 is retracted to leave a separated third resist mask 1113. The resist mask is recessed by ashing using oxygen plasma. Here, a second resist mask 1113 is formed on the gate electrode so as to separate the gate electrode. By this etching, a third resist mask 1123 can be formed (FIG. 21(A) )reference).

[0219] Next, the conductive layer 1111 is etched using the third resist mask 1123, and a source electrode is formed. Wirings 1125 that function as a lead and drain electrode are formed (see FIG. 21(B)). The conductive layer 1111 is preferably etched by wet etching. The etching is performed to etch the conductive layer isotropically. The wiring 1125 is formed inward from the gate 1123. The gate electrode may function as a gate or drain electrode as well as a signal line. The signal line, the source electrode, and the drain electrode may be provided separately.

[0220] Next, the layer 1115c containing an amorphous semiconductor and The impurity semiconductor layer 1117 is partially etched. Here, dry etching is used. Up to this step, the layer 1129c including the amorphous semiconductor having the recessed portion on the surface, the source An impurity semiconductor layer 1127 which functions as a gate region and a drain region is formed. The resist mask 1123 is then removed (see FIG. 21(C)).

[0221] Here, the conductive layer 1111 is wet-etched to remove the amorphous semiconductor-containing layer 111 5c and the impurity semiconductor layer 1117 were partially dry-etched. 1119 is isotropically etched, and the side surface of the wiring 1125 and the impurity semiconductor layer 1127 are The side surfaces of the impurity semiconductor layer 1127 are not aligned, and the side surfaces of the impurity semiconductor layer 1127 are formed outside the side surfaces of the wiring 1125. The shape becomes

[0222] After the third resist mask 1123 is removed, the impurity semiconductor layer 1117 and the amorphous Part of the semiconductor-containing layer 1115c may be etched. The impurity semiconductor layer 1117 is etched using 125. The side surfaces of the semiconductor layer 1127 are roughly aligned.

[0223] Next, after removing the third resist mask 1123, dry etching may be performed. The dry etching conditions are set so that the exposed amorphous semiconductor-containing layer 1129c is not damaged. The etching rate for the layer 1129c containing the amorphous semiconductor is low. In other words, the exposed surface of the layer 1129c containing the amorphous semiconductor is hardly damaged. The thickness of the exposed amorphous semiconductor-containing layer 1129c is hardly reduced. The etching gas typically used is Cl2, CF4, or N2. The etching method is not particularly limited, and an inductively coupled plasma (ICP) Inductively Coupled Plasma) method, Capacitively Coupled Plasma ( CCP (Capacitively Coupled Plasma) method, electronic cycle Electron Cyclotron Resonance Plasma (ECR) ce) method, reactive ion etching (RIE) ng) method, etc. can be used.

[0224] Next, the surface of the layer 1129c containing the amorphous semiconductor is treated with water plasma, ammonia plasma, or nitrogen plasma. Plasma or the like may also be irradiated.

[0225] Water plasma treatment is a process in which a gas whose main component is water, such as water vapor (H2O vapor), is introduced into a reaction space. This can be done by introducing a gas between the gas and generating plasma.

[0226] As described above, after the impurity semiconductor layer 1127 is formed, the amorphous semiconductor-containing layer 112 Further dry etching was performed under conditions that did not damage 9c, revealing the exposed amorphous Impurities such as residues present on the semiconductor-containing layer 1129c can be removed. Dry etching is followed by water plasma treatment to remove the resist mask residue. Furthermore, by performing water plasma treatment, the source region and the drain region can be This ensures insulation between the layers, reducing the off-state current of the completed thin film transistor. Therefore, the variation in electrical characteristics can be reduced.

[0227] By the above steps, a thin film in which a channel region is formed of a microcrystalline semiconductor layer can be formed using a small number of masks. In addition, a transistor having a low off-state current and a low on-state current and a low field-effect transition can be manufactured. It is possible to fabricate thin film transistors with high mobility.

[0228] (Method 2) Regarding a method for manufacturing a thin film transistor different from the above (Method 1), FIGS. 20, 23, and 24 are shown. 24 is used.

[0229] Similarly to the above (Method 1), a gate electrode 1103 is formed on a substrate 1101. A gate insulating layer 1105 and a first semiconductor layer 1106 are formed to cover the gate electrode 1103 (see FIG. Next, in the same manner as in the above (Method 1), crystal growth is performed from the first semiconductor layer 1106. The second semiconductor layer 1107 (the microcrystalline semiconductor layer 1107a, the mixed layer 1107b, and the non-crystalline semiconductor layer 1107b) is formed by extending the Next, a layer containing an amorphous semiconductor (1107c) is formed on the second semiconductor layer (1107). A semiconductor layer 1109 is formed (see FIG. 23(A)). A resist mask (not shown) is formed thereon.

[0230] Next, the second semiconductor layer 1107 and the impurity semiconductor layer 1109 are formed using a resist mask. By this process, the second semiconductor layer 1107 and the impurity semiconductor layer 1109 The second semiconductor layer 1115 (microcrystalline semiconductor layer 1115a, mixed layer 111 5b, a layer containing an amorphous semiconductor 1115c, and an impurity semiconductor layer 1117 are formed (FIG. 23(B)).

[0231] Next, a gate insulating layer 1105, a second semiconductor layer 1115, and an impurity semiconductor layer 1117 are formed on the gate insulating layer 1105, the second semiconductor layer 1115, and the impurity semiconductor layer 1117. A conductive layer 1111 is formed on the insulating film 1114 (see FIG. 23C).

[0232] Next, a resist mask (not shown) is formed over the conductive layer 1111. The conductive layer 1111 is etched using a A wiring 1133 is formed (see FIG. 24(A)).

[0233] Next, the impurity semiconductor layer 1117 is etched to form a layer that functions as a source region and a drain region. The impurity semiconductor layer 1127 is formed. Then, etching is performed to form a layer 1129c containing an amorphous semiconductor (see FIG. 24B).

[0234] Through the above steps, a thin film transistor can be manufactured.

[0235] After the wiring 1133 is formed, the layer 11 containing the amorphous semiconductor is formed without removing the resist mask. After removing the resist mask, the impurity semiconductor layer 1 The layer 117 and the layer 1129c containing the amorphous semiconductor may be partially etched. The impurity semiconductor layer 1117 is etched using the wiring 1133 as a mask. The side surfaces of the wiring 1133 and the impurity semiconductor layer 1127 are generally aligned with each other.

[0236] Next, after removing the resist mask, dry etching is preferably performed. The condition is that the exposed layer 1129c containing the amorphous semiconductor is not damaged and the amorphous semiconductor is The etching rate of the layer 1129c containing the semiconductor is low. The exposed amorphous semiconductor layer 1129c is not damaged, and the exposed amorphous semiconductor layer 1129c is not damaged. The conditions are such that the thickness of the layer 1129c containing the amorphous semiconductor is hardly reduced.

[0237] Next, the surface of the layer 1129c containing the amorphous semiconductor is treated with water plasma, ammonia plasma, or nitrogen plasma. Plasma or the like may also be irradiated.

[0238] Water plasma treatment is a process in which a gas whose main component is water, such as water vapor (H2O vapor), is introduced into a reaction space. This can be done by introducing a gas between the gas and generating plasma.

[0239] As described above, after the layer 1129c containing an amorphous semiconductor is formed, Further dry etching is performed under conditions that do not damage the layer 1129c, thereby forming an amorphous Impurities such as residues present on the semiconductor-containing layer 1129c can be removed. Dry etching is followed by water plasma treatment to remove the resist mask residue. By performing water plasma treatment, the insulation between the source and drain regions can be improved. This can ensure the edge, reduce the off-current of the thin film transistor, and improve the electrical characteristics. Variation can be reduced.

[0240] (Method 3) Next, a manufacturing method of the thin film transistor shown in FIG. 19 will be described with reference to FIGS. 20, 21, and 25. It is shown using

[0241] As in the above (Method 1), the wiring 112 is connected via FIGS. 20, 21(A), and 21(B). After forming the impurity semiconductor layer 1117, the impurity semiconductor layer 1127 is formed. The layer 1115c containing the amorphous semiconductor is etched to form a pair of amorphous semiconductor layers. A layer 1132 including a body is formed (see FIG. 25(A)).

[0242] Here, the layer containing the amorphous semiconductor is formed by wet etching or dry etching. The condition for selectively etching the second microcrystalline semiconductor layer 1115c and exposing the second microcrystalline semiconductor layer 1131b is An etchant capable of selectively wet etching an amorphous semiconductor layer is used as appropriate. Typical examples of such compounds include hydrazine, potassium hydroxide, or ethylenediamine-containing etchants. An etchant containing a mixed solution of hydrofluoric acid and nitric acid can also be used. It can also be used as tetramethylammonium hydroxide (TMAH). ) aqueous solution can be used.

[0243] In addition, as an etching gas capable of selectively dry etching an amorphous semiconductor layer, For example, hydrogen can be used. Alternatively, a gas containing chlorine, bromine, or iodine can be used as the etching gas. The hydrogen chloride, hydrogen bromide, or hydrogen iodide can be used as the hydrogen chloride gas. hydrogen, silicon tetrachloride, phosphorus trichloride, or boron trichloride. A gas containing tetrafluoromethane, hexafluoromethane, etc. can be used as an etching gas. Sulfur fluoride, nitrogen trifluoride, silicon tetrafluoride, boron trifluoride, xenon difluoride, Also, a mixture of tetrafluoromethane and oxygen, or sulfur hexafluoride and A chlorine mixed gas can be used as the etching gas.

[0244] After that, the resist mask is removed, and the second microcrystalline semiconductor layer 1131b and the pair of amorphous semiconductor layers The surfaces of the layer 1132 containing the impurity, the impurity semiconductor layer 1127, and the wiring 1125 are oxidized, or A nitriding plasma treatment 1140 is performed to form the first insulating layer 1135a shown in FIG. 25(C), A second insulating layer 1135c and a third insulating layer 1135e are formed.

[0245] The layer 1132 containing an amorphous semiconductor has a weak n-type conductivity because it contains an amorphous semiconductor. The density of the amorphous semiconductor layer 1132 is lower than that of the microcrystalline semiconductor layer. The second insulating layer 1135c, which is oxidized or nitrided, is a low density, loose insulating layer, and has insulating properties. However, the thin film transistor shown in FIG. 19 has a microcrystalline semiconductor on the back channel side. The first insulating layer 1135a is formed by oxidizing the conductor layer 1131. The microcrystalline semiconductor layer is Since the density is higher than that of the amorphous semiconductor layer, the first insulating layer 1135a also has a high density and insulating properties. Furthermore, the second microcrystalline semiconductor layer 1131b has a plurality of pyramidal protrusions (convex portions). Therefore, the surface is uneven. These factors contribute to reducing the off-state current of thin film transistors. can.

[0246] Here, after the wiring 1125 is formed, the layer 1115c containing the amorphous semiconductor is etched. The second microcrystalline semiconductor layer 1131b was exposed by etching. After the wiring 1125 was formed, The resist mask is removed, and the impurity semiconductor layer 1117 and the layer 1115c containing an amorphous semiconductor are removed. Each of them is partially dry-etched, and the surface of the second microcrystalline semiconductor layer 1131b is further oxidized. Alternatively, a plasma treatment 1140 for nitridation may be performed. In this case, the wiring 1125 is masked. As a result, the impurity semiconductor layer 1127 and the layer 1115c containing an amorphous semiconductor are etched. Therefore, the side of the wiring 1125 and the impurity semiconductors that function as the source and drain regions are The side surface of the conductive layer 1127 is roughly aligned with the side surface of the conductive layer 1127 .

[0247] As described above, the second microcrystalline semiconductor layer 1131b having the pyramidal protrusions (convex portions) is exposed. After that, an insulating layer is formed on the surface of the second microcrystalline semiconductor layer 1131b by plasma treatment. This makes it possible to increase the distance of the leakage path between the source and drain regions. In addition, a highly insulating layer can be formed. These features result in low off-state current, low on-state current, and low field effect transition. It is possible to fabricate thin film transistors with high mobility. Thin film transistors formed from the organic layers can be fabricated.

[0248] (Method 4) The following describes a method for manufacturing the second semiconductor layer 1107 that can be applied to (Method 1) to (Method 3). Here, a gas containing nitrogen is used as a source gas for the second semiconductor layer 1107. Instead, a nitrogen-containing layer is formed in the processing chamber of the plasma CVD apparatus, and then a second semiconductor The second semiconductor layer 1107 is formed to supply nitrogen to the second semiconductor layer 1107. do.

[0249] After the first semiconductor layer 1106 is formed, the substrate is removed from the processing chamber of the plasma CVD apparatus. Next, a layer containing nitrogen is formed in the processing chamber of the plasma CVD apparatus. Next, after the substrate is carried into the processing chamber, a second silicon nitride layer is formed as the layer containing the silicon nitride. The source gas used for depositing the semiconductor layer 1107 is introduced into the processing chamber, and the second semiconductor layer 1107 Here, a deposition gas containing silicon or germanium is used as a source gas. The nitrogen-containing layer formed on the inner wall of the processing chamber is exposed to the plasma. As a result, a part of the nitrogen-containing layer dissociates, and N is released, or an NH group is generated. As a result, the second semiconductor layer 1107 contains nitrogen, and as shown in FIG. 18(A), The mixed layer 1107b is composed of a crystalline semiconductor layer 1107a, a mixed layer 1107b, and a layer 1107c containing an amorphous semiconductor. 18B, the second semiconductor layer 1107 is formed. A second semiconductor layer 1107 consisting of a first semiconductor layer 1107a and a mixed layer 1107b can be formed. Cut.

[0250] The second semiconductor layer 1107 formed by this method was analyzed by secondary ion mass spectrometry. The nitrogen concentration measured by the method is measured above the microcrystalline semiconductor layer 1107a or above the microcrystalline semiconductor layer 1107b. The second semiconductor layer 1107a has a peak concentration near the interface between the second semiconductor layer 1107a and the mixed layer 1107b. 107 deposition direction.

[0251] Through the above steps, the second semiconductor layer 1107 can be formed.

[0252] (Method 5) The following describes a method for manufacturing the second semiconductor layer 1107 that can be applied to (Method 1) to (Method 3). Here, a gas containing nitrogen is used as a source gas for the second semiconductor layer 1107. Instead, nitrogen is added to the processing chamber of the CVD apparatus before the second semiconductor layer 1107 is formed. After the gas is introduced, the second semiconductor layer 1107 is formed. The present invention is characterized in that nitrogen is supplied to the

[0253] After the first semiconductor layer 1106 is formed, the surface of the first semiconductor layer 1106 is irradiated with a nitrogen-containing gas. The plasma CVD equipment is exposed to nitrogen gas (called flash processing here) in the processing chamber. Nitrogen is supplied. Gases containing nitrogen include ammonia, nitrogen, nitrogen fluoride, and nitrogen chloride. In addition, hydrogen may be contained in any of the nitrogen-containing gases. Nitrogen is provided by exposing the surface of layer 1106 to ammonia.

[0254] Next, after introducing a source gas used for depositing the second semiconductor layer 1107 into the processing chamber, A semiconductor layer 1107 is formed. Here, silicon or germanium is used as a source gas. A deposition gas containing and hydrogen is used.

[0255] In the process of forming the second semiconductor layer 1107, the The nitrogen-containing gas, in this case ammonia, is decomposed by the plasma discharge, and N is released. Alternatively, NH groups are generated. As a result, nitrogen is contained in the second semiconductor layer 1107, and As shown in FIG. 18(A), the microcrystalline semiconductor layer 1107a, the mixed layer 1107b, and the amorphous semiconductor layer 1107b are The second semiconductor layer 1107 is made up of a layer 1107c including a conductor, or As shown in FIG. 1, the second semiconductor layer 1107 is composed of the microcrystalline semiconductor layer 1107a and the mixed layer 1107b. Layer 1107 can be formed.

[0256] The second semiconductor layer 1107 formed by this method was analyzed by secondary ion mass spectrometry. The nitrogen concentration measured by the method is measured above the microcrystalline semiconductor layer 1107a or above the microcrystalline semiconductor layer 1107b. The peak concentration is near the interface between the layer 1107a and the mixed layer 1107b. The concentration decreases in the deposition direction of the layer 1107c containing the amorphous semiconductor.

[0257] Through the above steps, the second semiconductor layer 1107 can be formed.

[0258] In this embodiment, an example of a method for manufacturing a thin film transistor included in a display device is described. The above structure is combined with the shift registers of the first to fifth embodiments. The channel region of a thin film transistor is made of a microcrystalline semiconductor. In this case, it is possible to increase the size of the display device, reduce costs, or improve yields. In addition, by using a microcrystalline semiconductor as the channel region, the deterioration of the characteristics of thin film transistors can be suppressed. Since the amount of light emitted can be controlled, the life of the display device can be extended.

[0259] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0260] (Embodiment 7) In this embodiment mode, a cross-sectional structure of a liquid crystal display device as one mode of the display device will be described with reference to FIG. Specifically, the following description will be made with reference to the TFT substrate, the counter substrate, and the counter substrate and the TFT substrate. The structure of a liquid crystal display device having a liquid crystal layer sandwiched between the liquid crystal layer and the substrate will be described. 26(A) is a top view of the liquid crystal display device. 26(B) shows a cross-sectional view of a substrate 1601 having a microcrystalline semiconductor layer in a channel region. It has a structure in which an inverted staggered thin-film transistor is formed using a conductor layer, and the display method is MVA. (Multi-domain Vertical Alignment) LCD display FIG.

[0261] The liquid crystal display device shown in FIG. 26(A) has a pixel portion 1603, a first scanning line 1604, a second scanning line 1605, a first scanning line 1606, a second scanning line 1607, a first scanning line 1608, a second scanning line 1609, a second scanning line 1610, a third scanning line 1611, a fourth scanning line 1612, a fourth scanning line 1613, a fifth A driver circuit 1605a, a second scanning line driver circuit 1605b, and a signal line driver circuit 1607 The pixel portion 1603, the first scanning line driver circuit 1605a, the second scanning line driver circuit 1605b, and the The circuit 1605b and the signal line driver circuit 1607 are attached to the substrate 16 by a sealing material 1609. The FPC161 is sealed between the FPC161 and the substrate 1611. 3 and an IC chip 1615 are disposed on the substrate 1601.

[0262] The cross-sectional structure taken along line CD in FIG. 26(A) will be described with reference to FIG. 26(B). Here, a pixel portion 1603 and a part of its peripheral driving circuit portion formed on a substrate 1601 are shown. 16 shows a second scanning line driver circuit 1605b and a terminal portion 1617.

[0263] A thin film transistor 1621 provided in a scanning line driver circuit 1605b is provided on a substrate 1601. A thin film transistor 1623 is formed in the pixel portion 1603. Insulating layers 1625 and 1627 are formed on the transistors 1621 and 1623. The source electrode or drain electrode of the thin film transistor 1621 is connected to the opening 1625. a wiring 1629 connected to the source electrode or drain electrode of the thin film transistor 1623; A pixel electrode 1631 is formed to connect the insulating layer 1627, the wiring 1629, and the pixel electrode 1631. An insulating layer 1635 is formed on the element electrode 1631 .

[0264] The structures and manufacturing methods of the thin film transistors 1621 and 1623 are described in Embodiment Mode 1 and The sixth embodiment can be applied as appropriate.

[0265] The insulating layer 1625 and the insulating layer 1627 are formed using an inorganic insulating layer, an organic resin layer, or the like. The inorganic insulating layer can be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, or a DLC layer. Carbon layers such as diamond-like carbon (DLC) can be used. For the oil layer, acrylic resin, epoxy resin, polyimide, polyamide, polyvinyl phenol The resin may be a siloxane polymer, a benzocyclobutene resin, or the like. It can be used.

[0266] The insulating layer 1625 and the insulating layer 1627 are formed by a CVD method, a sputtering method, a printing method, a coating method, or the like. It can be formed by appropriately using a slit coating method or the like.

[0267] At least one of the insulating layer 1625 and the insulating layer 1627 is formed using an organic resin layer. This makes it possible to improve the flatness, and control the orientation of the liquid crystal molecules in the liquid crystal layer 1649. It becomes easier.

[0268] The wiring 1629 and the pixel electrode 1631 are made of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten, indium oxide containing titanium oxide, titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, or acid containing tungsten The insulating film can be formed using indium tin oxide or the like to which silicon dioxide is added.

[0269] The wiring 1629 and the pixel electrode 1631 are made of a conductive polymer (conductive polymer) having light-transmitting properties. The wiring 1629 and the conductive film 1628 can be formed using a conductive composition containing a conductive material. The pixel electrode 1631 has a sheet resistance of 10000Ω / □ or less and a wavelength of 550 nm. The light transmittance at 1000 nm is preferably 70% or more. The sheet resistance is preferably lower. In addition, the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable.

[0270] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples of the polymerizable compound include ethylenediamine or a derivative thereof, and a copolymer of two or more of these.

[0271] When the pixel electrode 1631 functions as a reflective electrode, the wiring 1629 and the pixel electrode 1631 As 631, aluminum, silver, or alloys thereof can be used. , titanium, molybdenum, tantalum, chromium, tungsten, and aluminum are laminated. The two-layer structure is made of aluminum and titanium, molybdenum, tantalum, chromium, tungsten, etc. A three-layer laminate structure sandwiched between any metals may be used.

[0272] An opening is formed in the pixel electrode 1631. The opening formed in the conductive film allows liquid crystal molecules to pass through. Since it is possible to give the surface an inclination, it can play the same role as the protrusions in the MVA method. Cut.

[0273] The insulating layer 1635 functions as an alignment film.

[0274] The periphery of the pixel portion 1603, or the periphery of the pixel portion 1603 and its peripheral driver circuit portion A sealing material 1609 is formed on the conductive layer 1641 by ink jetting or the like. A substrate 1611 on which an insulating layer 1643 and a protrusion 1645 are formed, and a substrate 1601 are bonded together with a seal material 1609 via a spacer 1647, and liquid is A crystal layer 1649 is disposed on the substrate 1611. The substrate 1611 functions as an opposing substrate.

[0275] The spacers 1647 may be provided by scattering particles of several μm in size, or by forming a resin layer on the entire surface of the substrate. After that, the resin layer may be etched to form the insulating layer.

[0276] The conductive layer 1641 functions as a counter electrode. The insulating layer 1643 can be made of the same material as the pixel electrode 1631. It functions as:

[0277] A connection terminal 1659 is formed in the terminal portion 1617. The connection terminal 1659 is The pixel portion 1603 and the wiring 1655 of the peripheral driver circuit portion are electrically connected. 1659 is the same as the pixel electrode 1631 of the pixel portion 1603 and the wiring 1629 of the peripheral driving circuit portion. It is formed in the same way.

[0278] Here, the thin film transistors 1621 and 1623 are formed by a process using a multi-tone mask. Therefore, a thin film transistor is formed between the wiring 1655 and the substrate 1601. The microcrystalline semiconductor layer 1651 formed at the same time as the microcrystalline semiconductor layer of the source region and the drain region An impurity semiconductor layer 1653 is formed at the same time as the drain region.

[0279] The FPC 1613 is disposed on the connection terminal 1659 via the anisotropic conductive layer 1657. In addition, an IC chip 161 is mounted on the FPC 1613 via an anisotropic conductive layer 1661. 5 are arranged. That is, the FPC 1613, the anisotropic conductive layers 1657, 1661, and and IC chip 1615 are electrically connected.

[0280] The anisotropic conductive layers 1657 and 1661 are made of anisotropic conductive film (ACF). Conductive Film) and Anisotropic Conductive Paste (ACP (Anisotropic Conductive Film) Adhesive materials such as otropic conductive paste are used. The anisotropic conductive layers 1657 and 1661 can be made of silver paste, copper paste, or the like. Alternatively, a conductive adhesive such as carbon paste or solder joints may be used.

[0281] The IC chip 1615 forms functional circuits (memory and buffers) and The product can be used effectively.

[0282] Although FIG. 26B is a cross-sectional view of the MVA display system, However, PVA (Patterned Vertical Alignment) method is also acceptable. In the case of the PVA method, a slit is provided in the conductive layer 1641 on the substrate 1611. The liquid crystal molecules can be tilted by forming a protrusion on the conductive layer having slits. A raised portion 1645 (also called an alignment control protrusion) may be provided to tilt the alignment of the liquid crystal molecules. In addition, the LCD driving method is not limited to the MVA method or the PVA method, but can also be TN ( Twisted Nematic mode, IPS (In-Plane Switching ng) mode, FFS (Fringe Field Switching) mode, AS M(Axially Symmetric aligned Micro-cell) model OCB (Optical Compensated Birefringence) ) mode, FLC (Ferroelectric Liquid Crystal) mode AFLC (AntiFerroelectric Liquid Crystal) etc. can be used.

[0283] The liquid crystal panel of FIG. 26(A) and FIG. 26(B) includes a first scanning line driver circuit 1605a, a second scanning line driver circuit 1605b, and a When the scanning line driver circuit 1605b and the signal line driver circuit 1607 are formed on the substrate 1601, 13B, the signal line driver circuit 1607 is connected to the The corresponding drive circuit is a driver IC, and is mounted on the LCD panel using a COG method or similar. By using a driver IC as the signal line driver circuit 1607, power saving can be achieved. In addition, by using semiconductor chips such as silicon wafers for the driver IC, the LCD panel This allows for higher speed operation and lower power consumption.

[0284] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and the shift registers of the first to fifth embodiments can be combined. When a microcrystalline semiconductor is used for a channel region of a transistor, the size of a display device increases, In addition, the microcrystalline semiconductor can be used as the semiconductor layer. By using it as a thin film transistor, it is possible to suppress the deterioration of its characteristics, and it is therefore suitable for display devices. This can extend the life of the device.

[0285] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0286] (Embodiment 8) In this embodiment, an example of an electronic device will be described.

[0287] The display device according to the above embodiment can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, electronic paper, digital cameras, digital Cameras such as video cameras, digital photo frames, mobile phones (mobile phones, mobile phones devices), portable game machines, personal digital assistants, sound reproducing devices, large game machines such as pachinko machines, etc. Examples include a gaming machine.

[0288] The electronic paper, which is one type of display device according to the above-described embodiment, displays information. If it is possible to use it in electronic devices in a wide range of fields, , electronic books (e-books), posters, in-car advertisements on trains and other vehicles, credit cards, etc. The electronic device can be applied to the display of various cards. show.

[0289] Fig. 27(A) shows an example of an electronic book. The electronic book shown in Fig. 27(A) has a housing 1 The housing 1700 and the housing 1701 are two housings. are integrated by a hinge 1704 and can be opened and closed. This configuration allows it to operate like a book.

[0290] A display unit 1702 is incorporated in the housing 1700, and a display unit 1703 is incorporated in the housing 1701. The display unit 1702 and the display unit 1703 are also configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 1702 in FIG. 27(A)), and the left table An image can be displayed on the display unit (display unit 1703 in FIG. 27A).

[0291] FIG. 27A shows an example in which an operation unit and the like are provided in a housing 1700. The body 1700 is provided with a power input terminal 1705, operation keys 1706, a speaker 1707, etc. The operation keys 1706 can be used to turn pages. It may also be configured to include a keyboard, a pointing device, etc. External connection terminals (earphone terminal, USB terminal, various cables such as USB cable) are installed on the front and side. The device may be configured to include a terminal that can be connected to a cable, a recording medium insertion section, etc. The electronic book shown in 27(A) may be configured to have the function of an electronic dictionary.

[0292] The electronic book shown in FIG. 27(A) may be configured to be capable of transmitting and receiving information wirelessly. By wireless communication, you can purchase and download the desired book data from the e-book server. It is also possible to configure it as follows.

[0293] FIG. 27(B) shows a digital display using a display device such as electronic paper, a liquid crystal display device, or a light-emitting display device. For example, the digital photo frame shown in FIG. The frame has a display unit 1712 built into a housing 1711. The display unit 1712 can display various It is possible to display images, for example, image data taken by a digital camera, etc. By displaying it, it can function just like a regular photo frame.

[0294] The digital photo frame shown in FIG. 27(B) has an operation unit, an external connection terminal (USB terminals that can be connected to various cables such as USB cables, etc.), a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a display on the surface of a digital photo frame as this improves the design. Insert a memory that stores image data taken with a digital camera into the recording media insertion section to record images. The data can be imported and the imported image data can be displayed on the display unit 1712.

[0295] The digital photo frame shown in FIG. 27(B) is configured to be able to send and receive information wirelessly. It is also possible to wirelessly import and display desired image data. Cut.

[0296] FIG. 27(C) shows a television set using a display device such as a liquid crystal display device or a light emitting display device. 27C shows an example of a television device including a display unit 1721 and a television receiver 1722. The display unit 1722 is capable of displaying images. In addition, here, a configuration is shown in which the housing 1721 is supported by a stand 1723. The display device described in the above embodiment can be applied to the portion 1722.

[0297] The television device shown in FIG. 27C is operated by an operation switch provided on the housing 1721, This can be done using a separate remote control. The channel and volume can be controlled, and the video displayed on the display unit 1722 can be controlled. In addition, the information output from the remote control device can be displayed on the remote control device. A display unit for displaying the same may be provided.

[0298] The television device shown in FIG. 27(C) includes a receiver, a modem, and the like. The receiver can receive general television broadcasts, and can also receive wired or By connecting to a wireless communication network, It is also possible to carry out two-way information communication (between sender and receiver, or between receivers, etc.). be.

[0299] FIG. 27(D) shows a mobile phone using a display device such as an electronic paper, a liquid crystal display device, or a light-emitting display device. The mobile phone shown in FIG. 27(D) is built in a housing 1731. In addition to the display unit 1732, an operation button 1733, an operation button 1737, an external connection port 1 734, a speaker 1735, and a microphone 1736.

[0300] In the mobile phone shown in FIG. 27D, the display portion 1732 is a touch panel, and By touching the screen, the display contents of the display unit 1732 can be operated. Or, creating an email or the like can be performed by touching the display portion 1732 with a finger or the like.

[0301] The screen of the display unit 1732 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0302] For example, when making a call or creating an email, the display unit 1732 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. In this case, most of the screen of the display unit 1732 is used to display a keyboard or number buttons. It is preferable.

[0303] In addition, the mobile phone shown in FIG. 27(D) has a gyro, an acceleration sensor, etc., inside to detect the tilt. By providing a detection device equipped with a sensor that detects the orientation of the mobile phone (portrait or landscape), Therefore, the display information on the display unit 1732 can be automatically switched.

[0304] The screen mode can be switched by touching the display unit 1732 or by pressing the operation button on the housing 1731. This is done by operating the button 1737. Also, depending on the type of image displayed on the display unit 1732, For example, if the image signal to be displayed on the display unit is video data, If it is data, it can be switched to display mode, and if it is text data, it can be switched to input mode.

[0305] In the input mode, the optical sensor of the display unit 1732 detects a signal and displays it. If there is no input by touch operation of the part 1732 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0306] The display unit 1732 can also function as an image sensor. 32 with your palm or fingers, and the image sensor captures your palm print and fingerprint, allowing you to authenticate your identity. In addition, the display unit may be provided with a backlight that emits near-infrared light or a display that emits near-infrared light. By using a sensing light source, it is possible to capture images of finger veins, palm veins, etc.

[0307] In the above embodiment, an example of an electronic device including the display device described in the above embodiment is described. The electronic device has a drive circuit that includes the shift lever of the first embodiment or the second embodiment. The display device includes a thin film transistor that constitutes a shift register. When a microcrystalline semiconductor is used for a channel region, it is possible to increase the size of a display device, reduce costs, or It is also possible to improve yields by using microcrystalline semiconductors as the channel of thin film transistors. By using it as a gate region, it is possible to suppress the deterioration of the characteristics of thin film transistors. The life of the display device can be extended.

[0308] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate. [Explanation of symbols]

[0309] 100 Shift Registers 101 Pulse output circuit 102 Wiring 103 Wiring 104 Wiring 106 Semiconductor layer 111 Thin-film transistor 112 Thin-film transistor 113 Thin-film transistor 114 Thin-film transistor 115 Thin-film transistor 116 Thin-film transistor 117 Thin-film transistor 118 Thin-film transistor 119 Thin-film transistor 120 Thin-film transistor 121 Thin-film transistor 131 Power line 132 Power line 151 Signal Line 152 signal line 153 Signal Line 154 Signal Line 155 Signal Line 156 Signal Line 157 Signal Line 166 Signal Line 171 Power line 172 Power line 201 period 540 pixels 600 circuits 601 circuits 602 circuits 603 Thin Film Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 700 Shift Registers 701 Pulse output circuit 702 Wiring 703 Wiring 704 Wiring 705 Wiring 706 Wiring 1101 Circuit Board 1103 Gate electrode 1105 Gate insulating layer 1106 Semiconductor layer 1107 Semiconductor layer 1109 Impurity semiconductor layer 1111 Conductive layer 1113 Resist mask 1115 Semiconductor layer 1117 Impurity semiconductor layer 1119 Conductive layer 1123 Resist mask 1125 Wiring 1127 Impurity semiconductor layer 1131 Microcrystalline semiconductor layer 1132 layers 1133 Wiring 1140 Plasma treatment 1180 Gray Tone Mask 1181 Circuit Board 1182 Light blocking part 1183 Diffraction grating section 1185 Halftone Mask 1186 PCB 1187 Semi-transparent part 1188 Light blocking part 1601 PCB 1603 Pixel section 1607 Signal line driver circuit 1609 Sealing material 1611 PCB 1613 FPC 1615 IC chip 1617 Terminal section 1621 Thin-film transistor 1623 Thin-film transistor 1625 Insulation layer 1627 Insulation layer 1629 Wiring 1631 pixel electrode 1635 Insulation layer 1641 Conductive layer 1643 Insulation Layer 1645 Protrusion 1647 Spacer 1649 Liquid crystal layer 1651 Microcrystalline semiconductor layer 1653 Impurity semiconductor layer 1655 Wiring 1657 Anisotropic conductive layer 1659 connection terminal 1661 Anisotropic Conductive Layer 1700 chassis 1701 Case 1702 Display section 1703 Display section 1704 Hinge 1705 Power input terminal 1706 Operation Key 1707 Speaker 1711 Case 1712 Display section 1721 Case 1722 Display section 1723 Stand 1731 Case 1732 Display section 1733 Operation button 1734 External connection port 1735 Speaker 1736 Mike 1737 Operation button 2801 Power line 2802 Thin-film transistor 2901 Capacitor element 5321 Thin-film transistor 5360 video signal 5361 Circuit 5362 Source Driver 5363 Gate Driver 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 input terminal 5420 pixels 5421 Thin-film transistor 5422 Liquid crystal element 5423 Capacitor 5431 Wiring 5432 Wiring 5433 Wiring 5434 Electrode 5441 Signal 5442 Voltage 1107a Microcrystalline semiconductor layer 1107b mixed layer 1107c layer 1108a Microcrystalline semiconductor region 1108b Amorphous semiconductor region 1115a Microcrystalline semiconductor layer 1115b mixed layer 1115c layer 1129a layer 1129c layer 1131a Microcrystalline semiconductor layer 1131b Microcrystalline semiconductor layer 1135a Insulating layer 1135c insulating layer 1135e Insulation layer 1605a Scanning line driver circuit 1605b Scanning line driver circuit 5361a circuit 5361b circuit 5362a Source Driver 5362b source driver 5420A Subpixel 5420B subpixel 5421A Thin-Film Transistor 5421B Thin Film Transistor 5422A Liquid Crystal Element 5422B Liquid Crystal Element 5423A Capacitive Element 5423B Capacitive Element 5431A Wiring 5431B Wiring 5432A Wiring 5432B Wiring

Claims

1. having first to eighth transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the first power supply line; the other of the source and the drain of the second transistor is always electrically connected to the output signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the gate of the third transistor is always electrically connected to the second power supply line; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the third transistor; one of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the second power supply line; one of the source and the drain of the seventh transistor is always electrically connected to the second power supply line; the other of the source and the drain of the seventh transistor is always electrically connected to the one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the first signal line; the other of the source and the drain of the eighth transistor is always electrically connected to the first power supply line; the gate of the eighth transistor is always electrically connected to the second signal line; A third signal is input to the gate of the sixth transistor.

2. The semiconductor device includes first to eighth transistors and a capacitor, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the first power supply line; the other of the source and the drain of the second transistor is always electrically connected to the output signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the gate of the third transistor is always electrically connected to the second power supply line; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the third transistor; one of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the second power supply line; one of the source and the drain of the seventh transistor is always electrically connected to the second power supply line; the other of the source and the drain of the seventh transistor is always electrically connected to the one of the source and the drain of the eighth transistor; the gate of the seventh transistor is always electrically connected to the first signal line; the other of the source and the drain of the eighth transistor is always electrically connected to the first power supply line; the gate of the eighth transistor is always electrically connected to the second signal line; one electrode of the capacitance element is always electrically connected to the first power supply line; the other electrode of the capacitance element is always electrically connected to the gate of the second transistor; A third signal is input to the gate of the sixth transistor.

3. A semiconductor device according to claim 1 or 2, and a pixel, the pixel is connected to the output signal line, The pixel has a liquid crystal element, The display device wherein the driving mode of the liquid crystal element is an IPS mode.

Images