Semiconductor Devices

Abstract

To solve a problem in a semiconductor device in which a threshold voltage is lowered in a boundary region adjacent to a diode portion of a transistor portion.SOLUTION: A semiconductor device includes a semiconductor substrate having an active region and a peripheral region. The active region has a transistor portion and a diode portion. The outer peripheral region has a current sensing portion. A lifetime control region including a lifetime killer is provided over the diode portion and at least a part of the transistor portion. The current sensing portion has a sense transistor non-irradiated region in which the lifetime control region is not provided and a sense transistor irradiation region in which the lifetime control region is provided.SELECTED DRAWING: Figure 3B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in a semiconductor device in which a transistor section such as an insulated gate bipolar transistor (IGBT) and a diode section are formed on the same substrate, a technique is known in which a particle beam such as helium ions is irradiated at a predetermined depth position in the semiconductor substrate to provide a lifetime control region including a lifetime killer (see, for example, Patent Document 1). Also known are semiconductor devices having a current sensing section (see, for example, Patent Documents 2 and 3). Patent Document 1: JP 2017-135339 A Patent Document 2: International Publication No. 2014 / 013618 Patent Document 3: JP 2018-67624 A Summary of the Invention [Problem to be solved by the invention]

[0003] In such a semiconductor device, there is a problem that the threshold voltage decreases in the boundary region of the transistor section adjacent to the diode section. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device comprising a semiconductor substrate having an active region and a peripheral region, the active region having a transistor portion and a diode portion, the peripheral region having a current sense portion, a lifetime control region including a lifetime killer extending from the diode portion to at least a portion of the transistor portion, and the current sense portion having a sense transistor non-irradiated region where the lifetime control region is not provided and a sense transistor irradiated region where the lifetime control region is provided.

[0005] The area ratio between the sense transistor irradiated region and the sense transistor non-irradiated region may be equal to the area ratio between the boundary region in which the lifetime control region is provided and the non-boundary region in the transistor section.

[0006] The semiconductor device further includes a gate metal layer provided above the front surface of the semiconductor substrate, an emitter electrode provided above the front surface of the semiconductor substrate, and a plurality of trench portions provided on the front surface side of the semiconductor substrate in the transistor portion, the diode portion, and the current sense portion, the plurality of trench portions including gate trench portions electrically connected to the gate metal layer and dummy trench portions electrically connected to the emitter electrode, and the ratio of the number of gate trench portions to the number of dummy trench portions per unit length in the current sense portion may be equal to the ratio in the transistor portion.

[0007] The current sense section has a first region extending along one of the opposing ends of the current sense section and a second region extending along the other end, and the first and second regions may be either a sense transistor non-irradiated region or a sense transistor illuminated region.

[0008] The current sensing section may further have an ineffective region between the sense transistor non-irradiation region and the sense transistor irradiation region.

[0009] The ineffective region may be provided with a trench portion set to the emitter potential.

[0010] In the ineffective region, the top surface of the mesa portion between the plurality of trench portions provided on the front surface side of the semiconductor substrate does not need to be in contact with the emitter electrode.

[0011] The transistor section and the current sensing section have an emitter region of the first conductivity type provided on the front surface of the semiconductor substrate, and no emitter region may be provided in the ineffective region.

[0012] The ineffective region may be provided with an isolation region of the second conductivity type.

[0013] The transistor section and the diode section have a base region of a second conductivity type provided on the front surface of the semiconductor substrate, and the invalid region has a well region of the second conductivity type provided on the front surface of the semiconductor substrate, and the doping concentration of the well region may be higher than the doping concentration of the base region.

[0014] The semiconductor device may further include a passivation layer above the front surface of the semiconductor substrate, the passivation layer covering the current sensing portion, the passivation layer having an opening positioned above the sensing transistor illumination region.

[0015] The opening may be arranged so that its edge overlaps with the edge of the sense transistor irradiation region, or so that it covers the entire sense transistor irradiation region.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a diagram showing an example of the top surface of the semiconductor device 100. [Figure 2A] FIG. 2 is an enlarged top view of an area A in FIG. [Figure 2B] FIG. 2B is a diagram showing a cross section taken along line aa' in FIG. 2A. [Figure 3A] 2 is an enlarged top view of the current sensing unit 210 and its vicinity. FIG. [Figure 3B] FIG. 3B is a diagram showing a cross section taken along aa' in FIG. 3A. [Figure 3C] FIG. 3B is a diagram showing a cross section taken along the line bb' in FIG. 3A. [Figure 4A] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4B] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4C]10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4D] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4E] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4F] FIG. 4B is a diagram showing an example of a cross section taken along aa' in FIG. 4E. [Figure 4F-1] FIG. 4B is a diagram showing an example of a cross section taken along aa' in FIG. 4E. [Figure 4F-2] FIG. 4B is a diagram showing an example of a cross section taken along aa' in FIG. 4E. [Figure 4F-3] FIG. 4B is a diagram showing an example of a cross section taken along aa' in FIG. 4E. [Figure 4F-4] FIG. 4B is a diagram showing an example of a cross section taken along aa' in FIG. 4E. [Figure 4G] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 4H] FIG. 4C is a diagram showing a cross section taken along line aa' of FIG. 4G. [Figure 5A] 10 is a diagram for explaining an example of the arrangement of a sense transistor non-irradiation region 218 and a sense transistor irradiation region 220. FIG. [Figure 5B] FIG. 5B is a view showing a cross section taken along the line cc' in FIG. 5A. [Figure 5C] FIG. 5B is a diagram showing a cross section taken along the line dd' in FIG. 5A. [Figure 6A] 2 is an enlarged top view of the current sensing unit 210 and its vicinity. FIG. [Figure 6B] FIG. 6B is a diagram showing the ee' cross section of FIG. 6A. [Figure 6C] FIG. 6B is a diagram showing the ff' cross section of FIG. 6A. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "top" or "front" and the other side as the "bottom" or "back." Of the two main surfaces of a substrate, layer, or other member, one is referred to as the front surface and the other as the back surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0020] In this specification, technical matters may be explained using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is mentioned without specifying positive or negative, it means the +Z-axis and -Z It means the direction parallel to the axis.

[0021] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0022] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0023] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0024] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A This becomes:

[0025] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as donors that supply electrons.

[0026] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0027] In this specification, chemical concentration refers to the concentration of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently larger than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration.

[0028] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0029] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0030] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0031] Fig. 1 is a diagram showing an example of the top surface of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0032] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has an edge 102 in a top view. In this specification, the term "top view" simply refers to a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edge 102 that face each other in a top view. In FIG. 1, the X-axis and Y-axis are parallel to one of the edge 102. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0033] Semiconductor substrate 10 has an active region 160, a peripheral region 180, and an edge termination region 190. Active region 160 is a region through which a main current flows in the depth direction between the front and back surfaces of semiconductor substrate 10 when semiconductor device 100 is in operation. An emitter electrode is provided above active region 160, but is not shown in FIG.

[0034] The active region 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor sections 70 and the diode sections 80 are arranged in alternating stripes along a predetermined arrangement direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10. In another example, the active region 160 may have the diode sections 80 arranged in a lattice pattern within the transistor section 70.

[0035] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction.

[0036] The width of the transistor section 70 in the X-axis direction is greater than the width of the diode section 80 in the X-axis direction. In addition, the width of the transistor section 70 in the X-axis direction may be the same as the width of the diode section 80 in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0037] The diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, an extension region in which the diode section 80 is extended in the Y-axis direction to a gate runner, which will be described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region.

[0038] The transistor section 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the front surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0039] The semiconductor device 100 includes a gate runner 48 that electrically connects the conductive portion of the gate trench portion to the gate pad. The gate runner 48 is disposed between the active region 160 and the edge 102 of the semiconductor substrate 10 in a top view. In this example, the gate runner 48 surrounds the active region 160 in a top view. The area surrounded by the gate runner 48 in a top view may be the active region 160, and the area from the gate runner 48 toward the edge 102 may be the peripheral region 180.

[0040] The gate runner 48 is disposed above the semiconductor substrate 10. In this example, the gate runner 48 may be formed of polysilicon doped with impurities or the like. The gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0041] The peripheral region 180 surrounds the active region 160. The peripheral region 180 may have one or more pads provided above the semiconductor substrate 10. As an example, the semiconductor device 100 has pads such as an anode pad, a cathode pad, and a current detection pad. Each pad may be connected to an external circuit via wiring such as a wire.

[0042] The peripheral region 180 has a current sense unit 210. The current sense unit 210 detects the current flowing through the transistor unit 70. The peripheral region 180 may further have a temperature sense unit which is a PN junction diode formed of polysilicon or the like. A current sense emitter electrode 53 is provided above the current sense unit 210, but is omitted in FIG. 1.

[0043] In this example, edge termination region 190 is disposed between periphery region 180 and edge 102. Edge termination region 190 alleviates electric field concentration on the front surface side of semiconductor substrate 10.

[0044] Edge termination region 190 may include guard ring 92. Guard ring 92 is a P-type region that contacts the front surface of semiconductor substrate 10. Note that although edge termination region 190 in this example includes multiple guard rings 92, only one guard ring 92 is shown in FIG. 1 . By providing multiple guard rings 92, the depletion layer on the upper surface side of active region 160 can be extended outward, improving the breakdown voltage of semiconductor device 100. Edge termination region 190 may further include at least one of a field plate and a resurf annularly disposed around peripheral region 180.

[0045] A passivation layer 230 is provided above the semiconductor substrate 10, but is omitted in Fig. 1. The passivation layer 230 is a protective film formed of polyimide or the like, and covers the entire front surface side of the semiconductor substrate 10. The passivation layer 230 may have openings at positions corresponding to pads, wires, and the like provided in the peripheral region 180.

[0046] Fig. 2A is an enlarged top view of region A in Fig. 1. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0047] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the front surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0048] The semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The gate metal layer 50 and the emitter electrode 52 are provided separately from each other. The gate metal layer 50 and the emitter electrode 52 are electrically insulated from each other.

[0049] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate 10, but is not shown in FIG. 2A. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In FIG. 2A, each contact hole is hatched with diagonal lines.

[0050] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via contact holes 54.

[0051] The emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate via an insulating film such as an interlayer insulating film and a dummy insulating film in the dummy trench portion 30.

[0052] The gate metal layer 50 is electrically connected to the gate runner 48 through a contact hole 49. The gate runner 48 may be formed of impurity-doped polysilicon or the like. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52.

[0053] The gate runner 48 and the emitter electrode 52 are electrically isolated by an insulating material such as an interlayer insulating film and an oxide film. The gate runner 48 in this example is provided from below the contact hole 49 to the end of the gate trench portion 40. At the end of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate and is connected to the gate runner 48.

[0054] The emitter electrode 52 and the gate metal layer 50 are formed of a conductive material containing metal, such as aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal layer made of titanium, a titanium compound, or the like beneath the region made of aluminum or the like.

[0055] Each electrode may have a plug formed of tungsten or the like in a contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, with tungsten buried so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0056] The plug is provided in a contact hole that contacts the contact region 15 or the base region 14. A P++ type plug region is formed under the contact hole of the plug, and has a higher doping concentration than the contact region 15. This can improve the contact resistance between the barrier metal and the contact region 15. The depth of the plug region is approximately 0.1 μm or less, which is 10% or less of the depth of the contact region 15.

[0057] The plug region improves the contact resistance, thereby improving the latch-up resistance in the operation of the transistor section 70. On the other hand, in the operation of the diode section 80, increases in conduction loss and switching loss can be suppressed.

[0058] The well region 11 extends from the gate runner 48, overlapping with the peripheral region 180, and is provided in a ring shape in top view. The well region 11 also extends to the active region 160 inside the gate runner 48 by a predetermined width, and is provided in a ring shape in top view. In this example, the well region 11 is provided in a range that is farther toward the gate runner 48 than the end of the contact hole 54 in the Y-axis direction. The well region 11 is a region of the second conductivity type that has a doping concentration higher than that of the base region 14. The doping concentration of the well region 11 may be the same as or lower than the doping concentration of the contact region 15. The gate runner 48 is electrically insulated from the well region 11.

[0059] In this example, the base region 14 is P- type, and the well region 11 is P+ type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of the base region 14. The base region 14 is provided in contact with the well region 11 in the transistor section 70 and the diode section 80. The well region 11 is electrically connected to the emitter electrode 52.

[0060] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction.

[0061] The gate trench portion 40 in this example may have two extension portions 41 (portions of the trench that are linear along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0062] At least a part of the connection portion 43 may be curved in top view. The connection portion 43 connects the ends of the two extension portions 41 in the Y-axis direction to the gate runner 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the connection portion 43 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 43 were completed at the extension portion 41.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each extension section 41 of the gate trench section 40. In the example of Fig. 2A, two dummy trench sections 30 are provided between each extension section 41, but one dummy trench section 30 may be provided, or more than two dummy trench sections 30 may be provided.

[0064] Furthermore, the dummy trench portion 30 does not have to be provided between the extension portions 41, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-state voltage.

[0065] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have an extension portion 31 and a connection portion 33, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2A has only dummy trench portions 30 having connection portions 33 arranged therein, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have connection portions 33.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a top view. That is, at the ends of the trench portions in the Y-axis direction, negative The bottom of each trench portion (side) is covered with the well region 11. This can reduce the electric field concentration at the bottom of each trench portion.

[0067] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0068] The mesa portion in this example is sandwiched between adjacent trench portions in the X-axis direction and is provided on the front surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trenches. As will be described later with reference to FIG. 2B , in this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to refers to both the mesa portion 60 and the mesa portion 61.

[0069] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0070] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0071] The contact regions 15 and emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0072] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0073] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80.

[0074] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (X-axis direction) of the mesa portions.

[0075] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the rear surface of the semiconductor substrate. A P+ type collector region 22 may be provided in a region of the rear surface of the semiconductor substrate where the cathode region 82 is not provided. In Figure 2A, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0076] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby suppressing hole injection from the well region 11 and reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0077] 2B is a diagram showing the a-a' cross section of Fig. 2A. The a-a' cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0078] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 has a contact hole 54, as described with reference to FIG. 2A.

[0079] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 through a contact hole 54 in the interlayer insulating film 38. A plug (not shown) such as tungsten (W) may be embedded inside the contact hole 54 via a barrier metal film. A plug region 17 may be provided in the surface layer of the semiconductor substrate 10 where the contact hole 54 is opened. The plug region 17 is of P type. The doping concentration of the plug region 17 is higher than the doping concentration of the contact region 15.

[0080] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing a metal or a laminated film thereof.

[0081] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0082] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0083] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0084] The accumulation region 16 in this example is N-type. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0085] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21. The emitter region 12 is provided in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0086] The diode section 80 is provided with a base region 14 exposed on the front surface 21. The base region 14 of the diode section 80 operates as an anode.

[0087] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0088] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0089] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a freewheeling current in the reverse direction when the transistor section 70 is turned off.

[0090] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0091] The gate trench portion 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be located in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of impurity-doped polysilicon or the like.

[0092] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0093] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench further than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0094] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered on the front surface 21 with an interlayer insulating film 38. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0095] In the diode section 80, a lifetime control region including a lifetime killer is locally provided in the drift region 18. The lifetime killer is a crystal defect formed at a predetermined depth in the semiconductor substrate 10 by implanting, for example, helium ions, hydrogen ions (protons, deuterons), etc. The lifetime control region promotes recombination between holes generated in the base region 14 and electrons injected from the cathode region 82 when the diode section 80 is turned off, and suppresses peak current during reverse recovery.

[0096] The lifetime control region 85 may be formed by irradiating the semiconductor substrate 10 with protons or helium from the front surface 21 or the back surface 23 using a mask. As an example, the transistor section 70 and the diode section 80 are irradiated with protons or helium through openings in the mask, with the regions where the lifetime control region 85 is not to be formed being shielded by the mask. The regions shielded by the mask are not irradiated with protons or helium.

[0097] 2B, the peak position in the Z-axis direction of the lifetime killer concentration distribution is indicated by an "x" symbol. In this example, the peak position in the Z-axis direction of lifetime control region 85 may be the same as the position in the Z-axis direction of the lower surface of well region 11, or may be located lower than the position in the Z-axis direction of the lower surface of well region 11. Furthermore, lifetime control region 85 may be formed so that the lifetime killer concentration distribution has multiple peaks in the Z-axis direction.

[0098] In this example, the lifetime control region 85 is provided continuously from the diode portion 80 to at least a portion of the transistor portion 70. In the transistor portion 70, the region where the lifetime control region 85 is provided is referred to as the boundary region 75. When the diode portion is conductive, a hole current is generated not only in the base region 14 of the diode portion 80 but also from the base region 14 of the transistor portion 70 toward the cathode region 82. The transistor portion 70 has the boundary region 75 where the lifetime control region 85 is provided, which promotes carrier annihilation and reduces reverse recovery loss during turn-off.

[0099] However, in the trench portion of the boundary region 75, when helium or protons are irradiated from the front surface 21 or the back surface 23 of the semiconductor substrate 10, damage occurs in the gate insulating film 42, and the interface state changes. When a gate voltage is applied to the irradiated gate insulating film 42, an inversion layer is more likely to form in the adjacent base region 14 than in the unirradiated gate insulating film 42. Therefore, the threshold voltage in the boundary region 75 is lower than in the region of the transistor portion 70 other than the boundary region 75.

[0100] 3A is an enlarged top view of the current sensing unit 210 and its vicinity. The current sensing unit 210 of this example is surrounded by well regions 11a and 11b. Between the well region 11a surrounding the current sensing unit 210 and the well region 11b surrounding the well region 11a, a region in which the drift region 18 is exposed on the front surface 21 is formed, separating the well region 11a from the well region 11b. The well region 11a is connected to the same potential as a current sense emitter electrode 53 (described later), and the well region 11b is connected to the same potential as an emitter electrode 52.

[0101] In this example, an opening 232 in the passivation layer 230 is provided so as to overlap the current sensing section 210. In Fig. 3A, the area of ​​the passivation layer 230 other than the opening 232 is hatched with oblique lines.

[0102] The current sensing section 210 has an emitter arrangement region 216 and a non-emitter arrangement region 214. The emitter arrangement region 216 is a region in which the emitter regions 12 are periodically arranged in a top view. For example, in the emitter arrangement region 216, as shown in FIG. 2A etc., the emitter regions 12 and the contact regions 15 are arranged. Y The emitter arrangement region 216 may be a region that includes the center of the current sensing section 210 when viewed from above.

[0103] The non-emitter region 214 is a region where the emitter region 12 is not provided. A P-type region may be exposed on the upper surface of the non-emitter region 214. The P-type region may have the same doping concentration as the contact region 15, the same doping concentration as the base region 14, or a different doping concentration.

[0104] The current sense unit 210 of this example has a similar structure to the transistor unit 70, and thus simulates the current flowing through the transistor unit 70 at a ratio according to the channel area ratio when viewed from above. The area of ​​the current sense unit 210 when viewed from above is smaller than the area of ​​the transistor unit 70. The area of ​​the current sense unit 210 may be smaller than the area of ​​each pad, such as the gate pad 208, arranged on the upper surface of the semiconductor substrate 10.

[0105] In this specification, the current sensing section 210 may refer to only the emitter region 216, excluding the emitter-free region 214 that does not operate as a transistor.

[0106] The emitter-free region 214 is provided to surround the emitter-placement region 216 in a top view. As an example, the emitter-placement region 216 and the emitter-free region 214 have rectangular shapes in a top view. The emitter-free region 214 is surrounded by the well region 11a in a top view. Furthermore, the well region 11a is surrounded by the well region 11b with the drift region 18 sandwiched therebetween in a top view.

[0107] A plurality of trenches and mesa portions are arranged in the emitter-location region 216 and the emitter-free region 214. In FIG. 3A, some of the trenches are indicated by dashed lines. Each trench extends in the Y-axis direction. The plurality of trenches includes a gate trench 40. The plurality of trenches may further include a dummy trench 30. The gate trench 40 and the dummy trench 30 have the same structure as the gate trench 40 and the dummy trench 30 provided in the transistor section 70.

[0108] When the emitter-location region 216 and the non-emitter region 214 are arranged side by side in the Y-axis direction, the trench portion may be provided continuously across the emitter-location region 216, the non-emitter region 214, and the well region 11a. The end of the gate trench portion 40 in the Y-axis direction may be provided inside the well region 11a. This makes it possible to alleviate electric field concentration at the end of the gate trench portion 40.

[0109] The well region 11a may be provided with a trench portion extending in the Y-axis direction. The emitter region 12 is not provided in the well region 11a.

[0110] 3A, the end of the opening 232 in top view is disposed along the outer periphery of the emitter-free region 214. In another example, the end of the opening 232 may be disposed above the emitter-free region 214 or along the outer periphery of the emitter-containing region 216. Alternatively, the end of the opening 232 may expose the emitter-free region 214, the well regions 11a and 11b, or the drift region 18 in top view. Furthermore, the emitter-free region 214 does not have to be provided at the end of the current sensing section 210 in the X-axis direction.

[0111] Figure 3B is a diagram showing the a-a' cross section of Figure 3A. The a-a' cross section is an XZ plane passing through the emitter region 12 of the current sense section 210. The current sense section 210 of this example has a sense transistor non-irradiated region 218 in which the lifetime control region 85 is not provided, and a sense transistor irradiated region 220 in which the lifetime control region 85 is provided.

[0112] Moreover, a current sense emitter electrode 53 is provided above the current sensing section 210. The current sense emitter electrode 53 is electrically insulated from the emitter electrode 52 provided above the active region 160.

[0113] The trench portion, impurity layer, electrodes, etc. in the current sensing portion 210 may be provided by the same process as the process for providing the transistor portion 70. In the current sensing portion 210, the lifetime control region 85 may be provided by the same process as the process for providing the lifetime control region 85 in the active region 160.

[0114] The sense transistor non-irradiated region 218 and the sense transistor irradiated region 220 are both regions in which the emitter region 12 is provided, and are included in the emitter-disposed region 216. In the example of FIG. 3B , the emitter non-disposed region 214 has a contact region 15 provided adjacent to the trench portion.

[0115] The area ratio between the sense transistor irradiated region 220 and the sense transistor non-irradiated region 218 is equal to the area ratio between the boundary region 75 and the region other than the boundary region 75 in the transistor section 70 .

[0116] In this way, in the current sensing section 210, by matching the area ratio of the region where the lifetime control region 85 is provided to that of the transistor section 70, the threshold voltages can be made uniform.

[0117] In this example, the value G / E obtained by dividing the number G of gate trench portions 40 included in a unit length in the arrangement direction of each trench portion by the number E of dummy trench portions 30 is referred to as the gate-emitter ratio. The gate-emitter ratio in the current sense portion 210 is equal to the gate-emitter ratio in the transistor portion 70.

[0118] That is, in the current sense section 210, the gate trench sections 40 are arranged at the same density as in the transistor section 70. The gate-emitter ratio of the current sense section 210 may be calculated from the number of all trench sections arranged in the X-axis direction in the current sense section 210. The gate-emitter ratio of the transistor section 70 may also be calculated from the number of all trench sections arranged in the X-axis direction in the transistor section 70.

[0119] Figure 3C is a diagram showing the bb' cross section of Figure 3A. The bb' cross section is a cross section in the Y-axis direction passing through the gate trench portion 40 of the current sense unit 210, and shows the vicinity of the end portion on the Y-axis negative side of the current sense unit 210, i.e., the edge termination region 190 side.

[0120] The current sensing section 210 of this example is surrounded by the well region 11. The current sensing section 210 and the well region 11 are separated by a drift region 18 exposed on the front surface 21. negative The end portion of the gate trench portion 40 is located below the lower end of the gate trench portion 40 (in the Z-axis direction). negative Located on the side.

[0121] 3C, the end of the gate trench portion 40 of the current sensing section 210 on the positive side in the Y-axis direction (the active region 160 side) may be provided at a position overlapping with the gate runner 48. This allows the gate trench portion 40 and the gate runner 48 to be easily connected to each other.

[0122] In this example, the gate trench portions 40 and the dummy trench portions 30 are shown in a striped pattern, but they may also be in a lattice pattern. Also, the gate trench portions 40 and the dummy trench portions 30 may be a combination of a striped pattern and a lattice pattern, and these patterns can be changed as appropriate.

[0123] 4A to 4E are diagrams illustrating examples of the arrangement of the sense transistor non-irradiated region 218 and the sense transistor irradiated region 220. In FIGS. 4A to 4E, the edge of the opening 232 in the passivation layer 230 is arranged along the edge of the emitter non-arrangement region 214 of the current sense section 210 in a top view. In this example, the edge of the current sense section 210 refers to the edge of the emitter arrangement region 216. In FIGS. 4A to 4E, the region of the passivation layer 230 other than the opening 232 is hatched with diagonal lines.

[0124] 4A to 4E, the edge of the opening 232 in the passivation layer 230 does not have to be arranged along the edge of the emitter-free region 214 of the current sensing section 210 in top view. The opening 232 in the passivation layer 230 may expose the emitter-placement region 216, the well regions 11a and 11b, or the drift region 18 in top view.

[0125] 4A to 4E, the emitter non-location region 214 is provided on the outer periphery of the emitter location region 216. The edge of the opening 232 in the passivation layer 230 may be arranged along the edge of the emitter location region 216 of the current sensing section 210 in a top view.

[0126] The emitter arrangement region 216 has a pair of opposing end portions 216X extending in the X-axis direction and a pair of opposing end portions 216Y extending in the Y-axis direction. In the example of Fig. 4A, the current sensing section 210 has a sense transistor non-irradiated region 218 extending along one of the end portions 216Y, a sense transistor non-irradiated region 218 extending along the other of the end portions 216Y, and a sense transistor irradiated region 220 extending in the Y-axis direction between these sense transistor non-irradiated regions 218.

[0127] In the example of Figure 4B, the current sensing section 210 has a sense transistor non-irradiated region 218 extending along one of the ends 216X, a sense transistor non-irradiated region 218 extending along the other end 216X, and a sense transistor irradiated region 220 extending in the X-axis direction between these sense transistor non-irradiated regions 218.

[0128] In this way, by arranging the sense transistor irradiation region 220 between the sense transistor non-irradiation regions 218 while extending in the X-axis or Y-axis direction, even if the position of the opening of the resist mask used during irradiation is shifted in the X-axis or Y-axis direction and the position of the sense transistor irradiation region 220 is shifted, the area occupied by the sense transistor irradiation region 220 in the current sense section 210 does not change. Therefore, in the current sense section 210, the area ratio of the region where the lifetime control region 85 is provided can be easily adjusted to that of the transistor section 70.

[0129] In the example of Figure 4C, the current sensing section 210 has a sense transistor illuminated region 220 extending along one side of the end 216Y, a sense transistor illuminated region 220 extending along the other side of the end 216Y, and a sense transistor non-illuminated region 218 extending in the Y-axis direction between these sense transistor illuminated regions 220.

[0130] 4C shows an example in which the sense transistor non-irradiation region 218 and the sense transistor irradiated region 220 are interchanged in the example of FIG. 4A. Similarly, the sense transistor non-irradiation region 218 and the sense transistor irradiated region 220 may be interchanged in the example of FIG. 4B. Even in this case, the area ratio of the region in which the lifetime control region 85 is provided in the current sense section 210 can be easily adjusted to match that of the transistor section 70.

[0131] In the example of FIG. 4D, the current sensing section 210 has a sense transistor non-irradiated region 218 arranged along the ends 216X and 216Y, and a sense transistor illuminated region 220 surrounded by the sense transistor non-irradiated region 218.

[0132] In this way, by arranging the sense transistor irradiation region 220 so that it is surrounded by the sense transistor non-irradiation region 218, even if the position of the opening of the resist mask used during irradiation is shifted in the X-axis or Y-axis direction and the position of the sense transistor irradiation region 220 is shifted, the area occupied by the sense transistor irradiation region 220 in the current sense section 210 does not change. Therefore, in the current sense section 210, the area ratio of the region where the lifetime control region 85 is provided can be easily adjusted to that of the transistor section 70.

[0133] In the examples shown in FIGS. 4A to 4D, even if the position of the opening of the resist mask used during irradiation is shifted in the X-axis or Y-axis direction, the emitter-free region 214 can absorb the shift in the irradiated region.

[0134] In the example of FIG. 4E, the current sensing section 210 further includes an ineffective region 222 between the sense transistor non-irradiated region 218 and the sense transistor illuminated region 220.

[0135] The invalid region 222 is a region provided between the region where the sense transistor non-irradiation region 218 is provided and the region where the sense transistor irradiation region 220 is provided. The invalid region 222 reduces the influence on the change in threshold voltage when the position of the opening of the resist mask used during irradiation is shifted and the position of the sense transistor irradiation region 220 is shifted.

[0136] In the invalid region 222, a plurality of trench portions are provided on the front surface 21 side of the semiconductor substrate 10, similar to the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220. The trench portions provided in the invalid region 222 may be electrically connected to the current sense emitter electrode 53.

[0137] Alternatively, the top surface of the mesa portion between the multiple trench portions provided in the ineffective region 222 may not be in contact with the current sense emitter electrode 53. In other words, the top surface of the mesa portion in the ineffective region 222 may be covered with the interlayer insulating film 38.

[0138] Alternatively, the emitter region 12 may not be provided in the ineffective region 222. For example, the ineffective region 222 has a well region 11a provided on the front surface 21 of the semiconductor substrate 10. Since no channel is formed in the ineffective region 222, even if the lifetime control region 85 is formed, it does not affect the reduction in the threshold voltage.

[0139] 4E, the sense transistor non-irradiation region 218, the sense transistor irradiation region 220, and the invalid region 222 are all provided to extend in the Y-axis direction, but this is not limiting. The invalid region 222 only needs to be provided to separate the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220.

[0140] 4E, the sense transistor non-irradiation region 218 and the sense transistor irradiated region 220 are provided extending along the respective end portions 216Y, but this is not limiting. The sense transistor non-irradiation region 218 and the sense transistor irradiated region 220 may be arranged as shown in FIGS. 4A to 4D.

[0141] Fig. 4F is a diagram showing an example of the aa' cross section of Fig. 4E. In Fig. 4F, the emitter region 12 is not provided in the ineffective region 222, and the trench portion is electrically connected to the current sense emitter electrode 53.

[0142] Here, if the position of the opening of the resist mask used during irradiation is shifted to the negative side in the X-axis direction, the lifetime control region 85 is also formed in the invalid region 222. However, since no channel is formed in the invalid region 222, the lifetime control region 85 formed in the invalid region 222 does not affect the threshold. In other words, since the invalid region 222 does not function as a transistor, even if the lifetime control region 85 is formed in the invalid region 222, the position of the end of the sense transistor irradiation region 220 on the invalid region 222 side (the position in the X-axis direction in FIG. 4F) does not change.

[0143] 4F-1 is a diagram showing an example of the a-a' cross section of FIG. 4E. In FIG. 4F-1, the contact hole 54 is not formed in the interlayer insulating film 38 of the ineffective region 222. The trench portion of the ineffective region 222 may be a dummy trench portion 30, and the trench portion may be electrically connected to the current sense emitter electrode 53. Furthermore, the emitter region 12 and the plug region 17 may not be provided in the ineffective region 222.

[0144] FIG. 4F-2 is a diagram showing an example of the a-a' cross section of FIG. 4E. The example of FIG. 4F-2 differs from the example of FIG. 4F-1 in that the accumulation region 16 is not provided in the invalid region 222. FIG. 4F-3 is a diagram showing an example of the a-a' cross section of FIG. 4E. The example of FIG. 4F-3 differs from the example of FIG. 4F-2 in that the base region 14 is not provided in the invalid region 222. According to the examples of FIG. 4F-1, FIG. 4F-2, and FIG. 4F-3, it is possible to obtain the same effect as the example of FIG. 4F.

[0145] 4F-4 is a diagram showing an example of the a-a' cross section of FIG. 4E. In the example of FIG. 4F-4, an isolation region 93 is provided on the front surface 21 side of the semiconductor substrate 10 in the invalid region 222. In the X-axis direction of FIG. 4F-4, a contact hole 54 and a dummy trench portion 30a may be provided on the isolation region 93 on the sense transistor non-irradiation region 218 side. A plug region 17 is provided in the surface layer of the isolation region 93 exposed by the contact hole 54. Note that the contact hole 54 and the plug region 17 do not necessarily have to be provided in the invalid region 222.

[0146] 4F-4, a contact hole 54 and a dummy trench portion 30b may also be provided on the sense transistor irradiation region 220 side of the isolation region 93. No trench portion may be provided between the dummy trench portion 30a and the dummy trench portion 30b.

[0147] The isolation region 93 is P-type. The doping concentration of the isolation region 93 may be the same as the doping concentration of the contact region 15, the doping concentration of the plug region 17, or the doping concentration of the well region 11. The isolation region 93 may be electrically connected to the well region 11a. The bottom surface of the isolation region 93 may be shallower than, the same as, or deeper than the bottom end of the trench portion, and may be at the same depth position as the bottom surface of the well region 11. The example of FIG. 4F-4 can achieve the same effect as the example of FIG. 4F.

[0148] FIG. 4G is a diagram illustrating an example of the arrangement of the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220. The arrangement of the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220 shown in FIG. 4G is the same as the example of FIG. 4E. In FIG. 4G, the end of the opening 232 in the passivation layer 230 is arranged to overlap with the end of the emitter non-location region 214 provided on the outer periphery of the sense transistor irradiation region 220 in the X-axis direction. Furthermore, the end of the opening 232 in the passivation layer 230 is arranged to overlap with the end of the emitter non-location region 214 provided on the outer periphery of the sense transistor irradiation region 220 in the Y-axis direction. Furthermore, the end of the opening 232 is arranged to overlap with the boundary between the invalid region 222 and the sense transistor irradiation region 220.

[0149] 4G。 As shown in FIG. 4H, the end of the opening 232 in the passivation layer 230 and the end of the sense transistor irradiation region 220 are at the same position (the X-axis position in FIG. 4H). In other words, the opening 232 in the passivation layer 230 and the opening in the resist mask are arranged to overlap in a top view.

[0150] Here, if the position of the opening in the resist mask is shifted toward the negative side of the X-axis direction with respect to the opening 232 in the passivation layer 230, some of the helium or protons irradiated through the opening in the resist mask will pass through the passivation layer 230. The range of the helium or protons that have passed through the passivation layer 230 will be shorter than when they have passed through the opening 232, and therefore, a lifetime control region 85 will be formed below the passivation layer 230 at a position closer to the front surface 21 of the semiconductor substrate 10 than below the opening 232. In FIG. 4G, the area below the passivation layer 230 is the ineffective region 222, and therefore, as described above, the formation of the lifetime control region 85 will not affect the change in the threshold voltage.

[0151] Alternatively, the opening 232 in the passivation layer 230 may be arranged to cover the entire sense transistor irradiation region 220. In this case, a part of the ineffective region 222 is located below the opening 232 in addition to the sense transistor irradiation region 220. As described above, even if the lifetime control region 85 is formed in the ineffective region 222, it does not affect the change in the threshold voltage.

[0152] In this example, an example is shown in which no emitter region 12 is provided in the ineffective region 222 and the trench portion is electrically connected to the current sense emitter electrode 53, but the same effect can be obtained in the examples shown in Figures 4F-1 to 4F-4.

[0153] 5A is a diagram illustrating an example of the arrangement of the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220. In this example, an invalid region 222 is provided between the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220. Separate emitter non-arrangement regions 214 are provided on the outermost peripheries of the sense transistor non-irradiation region 218 and the sense transistor irradiation region 220.

[0154] The example of FIG. 5A is different from the example of FIG. 5A in that a sense transistor non-irradiation area 218 and a sense transistor irradiation area 220 are provided separately with an ineffective area 222 interposed therebetween. 4 This is different from example A. The edge of the opening 232 in the passivation layer 230 is arranged along the edge of the emitter-free region 214 in the sense transistor irradiation region 220 in a top view. The opening 232 in the passivation layer 230 may be arranged to cover the entire sense transistor irradiation region 220.

[0155] 5B is a diagram showing the c-c' cross section of FIG. 5A. As shown in FIG. 5B, well region 11c is provided on the periphery of sense transistor non-irradiated region 218, and well region 11d is provided on the periphery of sense transistor irradiated region 220. Well region 11b is provided between adjacent well regions 11c and 11d. Well region 11b, well region 11c, and well region 11d are separated by drift region 18.

[0156] The edge of the opening 232 in the passivation layer 230 and the edge of the sense transistor irradiation region 220 are at the same position (the X-axis direction position in FIG. 5B). That is, the opening 232 in the passivation layer 230 and the opening of the resist mask used during irradiation are arranged to overlap in top view.

[0157] The well region 11c provided on the periphery of the sense transistor non-irradiation region 218 includes a dummy trench portion 30a. An interlayer insulating film 38 is provided on the upper surface of the well region 11c provided on the periphery of the sense transistor non-irradiation region 218. A contact hole 54 is provided in the interlayer insulating film 38, and a plug region 17 may be provided in the surface layer of the well region 11c where the contact hole 54 is opened. The well region 11c may include the contact hole 54 on the sense transistor non-irradiation region 218 side, and the dummy trench portion 30a on the well region 11b side.

[0158] A dummy trench portion 30b is provided in the well region 11d provided on the periphery of the sense transistor irradiation region 220. An interlayer insulating film 38 is provided on the upper surface of the well region 11d provided on the periphery of the sense transistor irradiation region 220. A contact hole 54 is provided in the interlayer insulating film 38, and a plug region 17 may be provided in the surface layer of the well region 11d where the contact hole 54 is opened. The well region 11d may have the contact hole 54 on the sense transistor irradiation region 220 side, and the dummy trench portion 30b on the well region 11b side.

[0159] Well regions 11b, 11c, and 11d are provided in the invalid region 222. The invalid region 222 also includes a drift region 18 that separates the well regions 11b, 11c, and 11d.

[0160] Figure 5C is a diagram showing the dd' cross section of Figure 5A. The dd' cross section is a Y-axis cross section passing through gate trench portion 40 of sense transistor non-irradiated region 218, and shows the vicinity of the end on the Y-axis negative side of sense transistor non-irradiated region 218, i.e., the edge termination region 190 side.

[0161] In this example, the sense transistor non-irradiation region 218 is surrounded by the well region 11c. The sense transistor non-irradiation region 218 and the well region 11c are separated by the drift region 18 exposed on the front surface 21. The lower end (in the Z-axis direction) of the well region 11c negative The end portion of the gate trench portion 40 is located below the lower end of the gate trench portion 40 (in the Z-axis direction). negative Located on the side.

[0162] Although not shown in Fig. 5C, the dummy trench portion 30 also has a similar cross-sectional shape. The sense transistor irradiation region 220 also has a similar cross section. The sense transistor irradiation region 220 differs from Fig. 5C in that the gate trench portion 40 and the dummy trench portion 30 are surrounded by the well region 11d, and a lifetime control region 85 is provided below the gate trench portion 40 and the dummy trench portion 30.

[0163] Although the gate trench portion 40 and the dummy trench portion 30 in FIG. 5C are shown in a striped pattern, they may also be in a lattice pattern. Furthermore, a combination of a striped pattern and a lattice pattern may also be used, and these can be modified as appropriate. This example also provides the same effect as that shown in FIG. 4E.

[0164] 6A is an enlarged top view of the current sense section 210 and its vicinity. The current sense section 210 of this example is surrounded by a region in which dummy trenches 30c are arranged and a region in which dummy trenches 30d are arranged. A region in which the drift region 18 is exposed on the front surface 21 is formed between the region in which dummy trenches 30c are arranged and the region in which dummy trenches 30d are arranged. The dummy trenches 30c are connected to the same potential as the current sense emitter electrode 53, and the dummy trenches 30d are connected to the same potential as the emitter electrode 52.

[0165] In this example, the opening 232 in the passivation layer 230 is provided to overlap the current sensing portion 210. Also, this example differs from FIG. 3A in that the current sensing portion 210 is separated from the active region 160 by a region in which the dummy trench portion 30c and the dummy trench portion 30d are arranged.

[0166] 6A, the area of ​​the passivation layer 230 other than the opening 232 is hatched with diagonal lines. Note that the edge of the opening 232 in the passivation layer 230 shown in Fig. 6A is arranged along the edge of the emitter-free region 214 of the current sensing section 210 in top view. The opening 232 in the passivation layer 230 exposes the emitter-free region 216 and the emitter-free region 214 in top view.

[0167] The emitter non-placement region 214 is surrounded by a region in which dummy trench portions 30c are arranged, and the region in which dummy trench portions 30c are arranged is surrounded by a region in which dummy trench portions 30d are arranged, sandwiching a region in which the drift region 18 is exposed on the front surface 21.

[0168] The current sensing section 210 has an emitter-placement region 216 and a non-emitter region 214. The emitter-placement region 216 and the non-emitter region 214 are the same as the current sensing section 210, the emitter-placement region 216, and the non-emitter region 214 shown in FIG. 3A, and therefore a description thereof will be omitted.

[0169] In top view, the emitter non-location region 214 is provided to surround the emitter location region 216. As an example, the emitter location region 216 and the emitter non-location region 214 have rectangular outer shapes in top view. In top view, the emitter non-location region 214 is surrounded by a region in which the dummy trench portions 30c are arranged and a region in which the dummy trench portions 30d are arranged.

[0170] A plurality of trenches and mesa portions are arranged in the emitter-location region 216 and the emitter-free region 214. In FIG. 6A, some of the trenches are indicated by dashed lines. Each trench extends in the Y-axis direction. The plurality of trenches includes a gate trench 40. The plurality of trenches may further include a dummy trench 30. The gate trench 40 and the dummy trench 30 have the same structure as the gate trench 40 and the dummy trench 30 provided in the transistor section 70.

[0171] 6A are formed in a stripe shape. The ends of the gate trenches 40 and the dummy trenches 30 are provided in the drift region 18.

[0172] Furthermore, lattice-shaped dummy trenches 30c and dummy trenches 30d are provided in the drift region 18 around the current sensing section 210. A predetermined distance is provided between the dummy trenches 30c and 30d, which reduces electric field concentration at the ends of the gate trenches 40.

[0173] Figure 6B is a diagram showing the e-e' cross section of Figure 6A. The e-e' cross section is an XZ plane passing through the emitter region 12 of the current sense section 210. The current sense section 210 of this example has a sense transistor non-irradiated region 218 in which the lifetime control region 85 is not provided, and a sense transistor irradiated region 220 in which the lifetime control region 85 is provided.

[0174] Moreover, a current sense emitter electrode 53 is provided above the current sensing section 210. The current sense emitter electrode 53 is electrically insulated from the emitter electrode 52 provided above the active region 160.

[0175] The trench portion, impurity layer, electrodes, etc. in the current sensing portion 210 may be provided by the same process as the process for providing the transistor portion 70. In the current sensing portion 210, the lifetime control region 85 may be provided by the same process as the process for providing the lifetime control region 85 in the active region 160.

[0176] The sense transistor non-irradiated region 218 and the sense transistor irradiated region 220 are both regions in which the emitter region 12 is provided, and are included in the emitter-disposed region 216. In the example of FIG. 6B , similar to the example of FIG. 3B , the emitter non-disposed region 214 has a contact region 15 provided adjacent to the trench portion.

[0177] The area ratio between the sense transistor irradiated region 220 and the sense transistor non-irradiated region 218 is equal to the area ratio between the boundary region 75 and the region other than the boundary region 75 in the transistor section 70 .

[0178] In this way, in the current sensing section 210, the threshold voltages can be made uniform by matching the area ratio of the region where the lifetime control region 85 is provided to that of the transistor section 70. Note that the gate-emitter ratio is the same as in the examples of Figures 3A to 3C, and therefore a description thereof will be omitted.

[0179] In the X-axis direction, in the drift region 18 on the periphery of the current sensing section 210, dummy trenches 30c adjacent to the emitter-free region 214 and dummy trenches 30d spaced a predetermined distance from the dummy trenches 30c are provided in a lattice pattern.

[0180] A contact hole 57 is provided in the interlayer insulating film on the upper surface of the dummy trench portion 30c. The dummy trench portion 30c is electrically connected to a current sense emitter electrode 53 provided on the upper surface of the interlayer insulating film .

[0181] Furthermore, a contact hole 58 is provided in the interlayer insulating film on the upper surface of the dummy trench portion 30d. The dummy trench portion 30d is electrically connected to an emitter electrode 52 provided on the upper surface of the interlayer insulating film .

[0182] The current sense emitter electrode 53 and the emitter electrode 52 are covered with a passivation layer 230. Openings are provided at predetermined locations in the passivation layer 230. The current sense emitter electrode 53 is electrically insulated from the emitter electrode 52.

[0183] Plugs made of tungsten or the like may be provided in the contact holes 57 and 58. The plugs may have a barrier metal on the semiconductor substrate 10 side, and tungsten may be embedded so as to be in contact with the barrier metal.

[0184] FIG. 6C is a diagram showing the f-f' cross section of FIG. 6A. The f-f' cross section is a Y-axis cross section passing through the gate trench portion 40 of the current sense portion 210, and shows the vicinity of the end portion on the Y-axis negative side of the current sense portion 210, i.e., the edge termination region 190 side. The dummy trench portion 30c and the dummy trench portion 30d each include a dummy insulating film 32 and a dummy conductive portion 34. A contact hole 57 is provided on the dummy conductive portion 34 of the dummy trench portion 30c. A contact hole 58 is provided on the dummy conductive portion 34 of the dummy trench portion 30d.

[0185] In this example, the current sensing section 210 is surrounded by the drift region 18 and the dummy trench portion 30d. The current sensing section 210 and the dummy trench portion 30c are separated from the active region 160 by the drift region 18 exposed on the front surface 21.

[0186] In the Y-axis direction, in the drift region 18 on the periphery of the current sensing section 210, dummy trenches 30c adjacent to the emitter-free region 214 and dummy trenches 30d spaced a predetermined distance from the dummy trenches 30c are provided in a lattice pattern.

[0187] 6C, the end of the gate trench portion 40 of the current sensing section 210 on the positive side in the Y-axis direction (the side of the active region 160) may be provided at a position overlapping with the gate runner 48. This allows the gate trench portion 40 and the gate runner 48 to be easily connected to each other.

[0188] In this way, the current sensing section 210 has the sense transistor irradiation region 220, so that the threshold voltage can be made the same as that of the transistor section .

[0189] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0190] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0191] 10...semiconductor substrate, 11, 11a, 11b, 11c, 11d...well region, 12...emitter region, 14...base region, 15...contact region, 16...accumulation region, 17...plug region, 18...drift region, 20...buffer region, 21...front surface, 22...collector region, 23...back surface, 24...collector electrode, 25...connection portion, 30, 30a, 30b, 30c , 30d... dummy trench portion, 31... extension portion, 32... dummy insulating film, 33... connection portion, 34... dummy conductive portion, 38... interlayer insulating film, 40... gate trench portion, 41... extension portion, 42... gate insulating film, 43... connection portion, 44... gate conductive portion, 48... gate runner, 49... contact hole, 50... gate metal layer, 52... emitter electrode, 53... Current sense emitter electrode, 54...contact hole, 56...contact hole, 57...contact hole, 58...contact hole, 60...mesa portion, 61...mesa portion, 70...transistor portion, 75...boundary region, 80...diode portion, 82...cathode region, 85...lifetime control region, 92...guard ring, 93...isolation region, 100...semiconductor device, 1 02 edge, 160 active region, 180 peripheral region, 190 edge termination region, 210 current sensing section, 214 non-emitter region, 216 emitter region, 216a edge, 216b edge, 218 sense transistor non-irradiated region, 220 sense transistor irradiated region, 222 invalid region, 230 passivation layer, 232 opening

Claims

1. a semiconductor substrate having an active region and a peripheral region; the active region has a transistor portion and a diode portion; the outer peripheral region has a current sensing section, a lifetime control region including a lifetime killer is provided from the diode section to at least a part of the transistor section; the current sensing section has a sense transistor non-irradiation region in which the lifetime control region is not provided and a sense transistor irradiation region in which the lifetime control region is provided, The area ratio between the sense transistor irradiated area and the sense transistor non-irradiated area is equal to the area ratio between the boundary area in which the lifetime control area is provided and the non-boundary area in the transistor section. Semiconductor device.

2. a semiconductor substrate having an active region and a peripheral region; the active region has a transistor portion and a diode portion; the outer peripheral region has a current sensing section, a lifetime control region including a lifetime killer is provided from the diode section to at least a part of the transistor section; the current sensing section has a sense transistor non-irradiation region in which the lifetime control region is not provided and a sense transistor irradiation region in which the lifetime control region is provided, a gate metal layer disposed above the front surface of the semiconductor substrate; an emitter electrode provided above the front surface of the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate in the transistor section, the diode section, and the current sense section; Furthermore, the plurality of trench portions include a gate trench portion electrically connected to the gate metal layer and a dummy trench portion electrically connected to the emitter electrode, The ratio of the number of the gate trench portions to the number of the dummy trench portions per unit length in the current sense portion is equal to the ratio in the transistor portion. Semiconductor device.

3. a gate metal layer disposed above the front surface of the semiconductor substrate; an emitter electrode provided above the front surface of the semiconductor substrate; a plurality of trench portions provided on the front surface side of the semiconductor substrate in the transistor portion, the diode portion, and the current sense portion; Furthermore, the plurality of trench portions include a gate trench portion electrically connected to the gate metal layer and a dummy trench portion electrically connected to the emitter electrode, The ratio of the number of the gate trench portions to the number of the dummy trench portions per unit length in the current sense portion is equal to the ratio in the transistor portion. The semiconductor device according to claim 1 .

4. The current sense section has a first region extending along one of opposing ends of the current sense section and a second region extending along the other end, and the first and second regions are either a non-irradiated region of the sense transistor or an illuminated region of the sense transistor. The semiconductor device according to claim 1 .

5. The current sensing unit further includes an invalid area between the non-irradiated area of ​​the sense transistor and the illuminated area of ​​the sense transistor.

4. The semiconductor device according to claim 2.

6. The ineffective region is provided with a trench portion set to the emitter potential. The semiconductor device according to claim 5 .

7. In the ineffective region, the upper surface of a mesa portion between a plurality of trench portions provided on the front surface side of the semiconductor substrate is not in contact with the emitter electrode.

7. The semiconductor device according to claim 5.

8. the transistor section and the current sensing section each have an emitter region of a first conductivity type provided on a front surface of the semiconductor substrate; The emitter region is not provided in the ineffective region. The semiconductor device according to claim 5 .

9. The ineffective region is provided with an isolation region of the second conductivity type. The semiconductor device according to claim 5 .

10. the transistor section and the diode section each have a base region of a second conductivity type provided on the front surface of the semiconductor substrate; The invalid region has a well region of a second conductivity type provided on the front surface of the semiconductor substrate, and the doping concentration of the well region is higher than the doping concentration of the base region. The semiconductor device according to claim 5 .

11. a passivation layer covering the current sensing unit above the front surface of the semiconductor substrate; The passivation layer has an opening positioned over the sense transistor illumination area. The semiconductor device according to claim 1 .

12. The opening is disposed so that an edge thereof overlaps an edge of the sense transistor irradiation region or so as to cover the entire sense transistor irradiation region. The semiconductor device according to claim 11.

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