Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device suppressed in the occurrence of latch-up.SOLUTION: A semiconductor device 100 includes: a first conductivity type drift region 18 provided on the semiconductor substrate 10; a second conductivity type base region 14 provided above the drift region; a first conductivity type emitter region 12 provided over the base region; a second conductivity type contact region 15 provided above the base region and having a higher doping concentration than the base region; a plurality of trench portions 30, 40 stretched in a predetermined stretch direction on a front face 21 side of the semiconductor substrate; and an interlayer insulating film 38 provided above the semiconductor substrate and having a first contact hole portion and a second contact hole portion 62. The contact region and the emitter region are provided alternately in the stretch direction. The first contact hole portion and the second contact hole portion are provided alternately in the stretch direction. The lower end of the first contact hole portion is provided at a depth different from the depth of the lower end of the second contact hole portion.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 describes a semiconductor device that includes an N-type emitter region and a P-type contact region in a semiconductor substrate. [Prior art document] [Patent documents] Patent Document 1: International Publication No. 2018 / 052099 Patent Document 2: JP 2013-065724 A Patent Document 3: JP 2021-012995 A

[0003] A semiconductor device that suppresses the occurrence of latch-up is preferable. Summary of the Invention

[0004] A first aspect of the present invention provides a semiconductor device including: a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first conductivity type emitter region provided above the base region; a second conductivity type contact region provided above the base region and having a higher doping concentration than the base region; a plurality of trenches extending in a predetermined extension direction on the front surface side of the semiconductor substrate; and an interlayer insulating film provided above the semiconductor substrate and having first contact holes and second contact holes. The contact regions and the emitter regions may be alternately provided in the extension direction. The first contact holes may be alternately provided with the second contact holes in the extension direction. The lower ends of the first contact holes may be provided at a different depth from the lower ends of the second contact holes.

[0005] The first contact hole portion and the second contact hole portion may be arranged alternately in the extension direction so that the first contact hole portion is arranged at a position corresponding to the emitter region and the second contact hole portion is arranged at a position corresponding to the contact region.

[0006] An emitter region may be provided below the first contact hole, and a contact region may be provided below the second contact hole.

[0007] The first contact hole portion and the second contact hole portion may be provided in the same contact hole.

[0008] The bottom end of the first contact hole portion may be shallower than the bottom end of the second contact hole portion.

[0009] The difference between the bottom end of the first contact hole portion and the bottom end of the second contact hole portion may be 0.03 μm or more.

[0010] The thickness of the contact region below the second contact hole may be 0.3 μm or more and 1.0 μm or less.

[0011] The semiconductor device may include a plug contact region of a second conductivity type that is provided below the second contact hole portion and has a doping concentration higher than that of the base region.

[0012] The semiconductor device may include a trench contact portion provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions.

[0013] The semiconductor device may include a first metal layer filled in the first contact hole, and a base region may be provided below the first metal layer.

[0014] The semiconductor device may include a first metal layer filled in the first contact hole, and a lower end of the first metal layer may be in contact with the emitter region.

[0015] The ratio α of the depth from the front surface of the semiconductor substrate to the bottom end of the first contact hole portion to the difference in the depth direction of the semiconductor substrate between the bottom end of the first contact hole portion and the bottom end of the second contact hole portion may be 0.01 or more and 1.0 or less.

[0016] The semiconductor device may include a plug contact region of a second conductivity type provided below the trench contact portion and having a doping concentration higher than that of the base region, and the width of the plug contact region in the arrangement direction of the plurality of trench portions may be larger than the width of the bottom surface of the trench contact portion.

[0017] The plug contact region may be provided below both the first contact hole portion and the second contact hole portion.

[0018] The plug contact region below the first contact hole portion may be provided shallower than the plug contact region below the second contact hole portion.

[0019] The plug contact region may be provided below the second contact hole portion, but may not be provided below the first contact hole portion.

[0020] A contact region may be provided below the second contact hole portion.

[0021] The semiconductor device may include a second metal layer filled in the second contact hole portion. The contact region may be in contact with a lower end of the second metal layer. The contact region may be provided below the plug contact region.

[0022] The width of the first contact hole portion in the arrangement direction of the plurality of trench portions may be smaller than the width of the second contact hole portion in the arrangement direction.

[0023] The semiconductor device may include a transistor portion and a diode portion.

[0024] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including the steps of: forming a drift region of a first conductivity type in a semiconductor substrate; forming a base region of a second conductivity type above the drift region; forming an emitter region of the first conductivity type above the base region; forming a contact region of the second conductivity type above the base region, the contact region having a doping concentration higher than that of the base region; forming a plurality of trenches extending in a predetermined extension direction on the front surface side of the semiconductor substrate; and forming an interlayer insulating film above the semiconductor substrate, the interlayer insulating film having first contact holes above the emitter regions and second contact holes above the contact regions. The contact regions and the emitter regions may be alternately provided in the extension direction. The lower ends of the first contact holes may be provided at a different depth from the lower ends of the second contact holes.

[0025] The method for manufacturing a semiconductor device may include a step of annealing a semiconductor substrate to form an emitter region and a contact region, and after the annealing step, a step of etching an interlayer insulating film to form a first contact hole portion and a second contact hole portion.

[0026] The etching for forming the first contact hole portion and the etching for forming the second contact hole portion may be performed in the same etching process.

[0027] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0028] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1B] 1B shows an example of a cross section taken along the line aa' in FIG. 1A. [Figure 1C] 1B shows an example of a cross section taken along the line bb' in FIG. 1A. [Figure 1D]1B shows an enlarged view of the front surface 21 of the semiconductor device 100 shown in FIG. 1A. [Figure 1E] 1B shows an example of a cross section taken along the line cc' in FIG. 1A. [Figure 2A] 1B shows a modified example of the cross section bb' in FIG. 1A. [Figure 2B] 1B shows a modified example of the cc' cross section in FIG. 1A. [Figure 3A] 1 shows a top view of a modified example of the semiconductor device 100. FIG. [Figure 3B] 3B shows an example of a cross section taken along the line dd' in FIG. 3A. [Figure 3C] 3B shows an example of a cross section taken along the line ee' in FIG. 3A. [Figure 3D] 3B shows an enlarged view of the front surface 21 of the semiconductor device 100 shown in FIG. 3A. [Figure 3E] 3B shows an example of a cross section taken along line ff' in FIG. 3A. [Figure 4A] 3B shows a modified example of the cross section dd' in FIG. 3A. [Figure 4B] 3B shows a modified example of the cross section dd' in FIG. 3A. [Figure 4C] 3B shows a modified example of the cross section dd' in FIG. 3A. [Figure 4D] 3B shows a modified example of the cross section dd' in FIG. 3A. [Figure 5A] 3B shows a modified example of the ee' cross section in FIG. 3A. [Figure 5B] 3B shows a modified example of the ee' cross section in FIG. 3A. [Figure 6A] A modified example of the semiconductor device 100 is shown. [Figure 6B] A modified example of the semiconductor device 100 is shown. [Figure 6C] A modified example of the semiconductor device 100 is shown. [Figure 7A] 1 shows a top view of a modified example of the semiconductor device 100. FIG. [Figure 7B] 1 shows a cross section taken along line gg' of a modified example of the semiconductor device 100. [Figure 8A] 1 is a flowchart showing an example of a method for manufacturing the semiconductor device 100. [Figure 8B]10 is a flowchart showing a modified example of the method for manufacturing the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0030] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0031] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0032] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0033] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0035] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0036] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0037] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0038] As used herein, chemical concentration refers to the atomic density of an impurity measured regardless of its electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as the value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0039] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0040] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0041] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0042] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70.

[0043] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may also be another transistor such as a MOSFET.

[0044] FIG. 1A shows the region around the chip edge, which is the edge side of semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the region on the negative side of semiconductor device 100 in the Y-axis direction in this example. The edge termination structure reduces electric field concentration on the upper surface side of semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of semiconductor device 100.

[0045] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. Note that in this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10.

[0046] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0047] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0048] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0049] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. Contact holes 55, 56, and 60 are provided to penetrate the interlayer insulating film 38.

[0050] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug metal layer made of tungsten or the like may be formed.

[0051] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug metal layer made of tungsten or the like may be formed.

[0052] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0053] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending in an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0054] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0055] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0056] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0057] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and no dummy trench portions 30.

[0058] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0059] The contact holes 60 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 60 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 60 are formed in the interlayer insulating film. The one or more contact holes 60 may be provided extending in the extension direction.

[0060] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0061] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0062] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0063] The emitter region 12 is a region of a first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 60.

[0064] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0065] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is of P+ type, for example. In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 60.

[0066] 1B shows an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0067] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0068] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.

[0069] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0070] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0071] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0072] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0073] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0074] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1.0E12 cm -2 More than 1.0E13cm -2 The ion implantation dose of the accumulation region 16 may be 3.0E12 cm -2 Above, 6.0E12cm -2 By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced. Note that E represents a power of 10, and for example, 1.0E12 cm -2 is 1.0 x 10 12 cm -2 means.

[0075] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0076] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0077] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0078] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0079] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 60 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. That is, the interlayer insulating film 38 has an opening 39. The contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, a phosphosilicate glass (PSG) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0080] The first contact hole portion 61 is an example of a contact hole 60 provided in the interlayer insulating film 38. The first contact hole portion 61 is provided above the emitter region 12. The emitter region 12 below the first contact hole portion 61 may have a depression 161 on its surface. The first contact hole portion 61 will be described later.

[0081] A first lifetime control region 151 may be formed in the transistor section 70. The first lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the first lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. By providing the first lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0082] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect formed by a vacancy or a divacancy and an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. An electron beam may be used to form the lattice defect.

[0083] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0084] The first lifetime control region 151 is provided on the back surface 23 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The first lifetime control region 151 of this example is provided in the buffer region 20. The first lifetime control region 151 of this example is provided on the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The first lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the first lifetime control region 151 is 0.5E10 cm -2More than 1.0E13cm -2 Even if it is less than 5.0E10cm -2 Above, 5.0E11cm -2 It may be the following:

[0085] Furthermore, first lifetime control region 151 in this example is formed by implantation from the back surface 23 side. This makes it possible to avoid any influence on the front surface 21 side of semiconductor device 100. For example, first lifetime control region 151 is formed by irradiating helium from the back surface 23 side. Here, whether first lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by obtaining the state of the front surface 21 side by the SR method or by measuring leakage current.

[0086] 1C shows an example of the bb' cross section in FIG. 1A. The bb' cross section is an XZ plane passing through the contact region 15 in the transistor section 70.

[0087] The second contact hole portion 62 is an example of a contact hole 60 provided in the interlayer insulating film 38. The second contact hole portion 62 is provided above the contact region 15. The contact region 15 below the second contact hole portion 62 may have a recess 162 on its surface. The depth position of the bottom surface of the recess 162 may be deeper than the depth position of the bottom surface of the recess 161. The second contact hole portion 62 will be described later.

[0088] FIG. 1D is an enlarged view of the front surface 21 of the semiconductor device 100 shown in FIG. 1A. This figure shows the front surface 21 of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40. The contact hole 60 has a first contact hole portion 61 and a second contact hole portion 62. The dashed line of the contact hole 60 indicates the sidewall of the interlayer insulating film 38 at the contact hole 60 above the front surface 21. That is, the dashed line of the contact hole 60 is the opening portion 39 of the interlayer insulating film 38. The opening portion 39 of the interlayer insulating film 38 may have a constant width regardless of the emitter region 12 and the contact region 15 formed in the underlying layer (the surface of the semiconductor substrate 10). The solid line of the contact hole 60 indicates a recess 161 or a recess 162 formed in the surface of the semiconductor substrate 10 below the front surface 21, and indicates the sidewall of the semiconductor substrate 10 in which the recess 161 or the recess 162 is formed. That is, the contact hole 60 may also include the recess 161 or the recess 162 formed by the surface of the semiconductor substrate 10 exposed in the opening 39 of the interlayer insulating film 38 being recessed downward.

[0089] The first contact hole portion 61 and the second contact hole portion 62 are an example of a contact hole 60 provided in the interlayer insulating film 38. The first contact hole portion 61 and the second contact hole portion 62 in this example are provided in the same contact hole 60. That is, the first contact hole portion 61 and the second contact hole portion 62 may be connected to each other to form one contact hole 60.

[0090] The first contact hole portions 61 may be provided alternately with the second contact hole portions 62 in the extension direction. The first contact hole portions 61 and the second contact hole portions 62 may be provided in the extension direction such that the first contact hole portions 61 are provided at positions corresponding to the emitter regions 12, and the second contact hole portions 62 are provided at positions corresponding to the contact regions 15.

[0091] "The first contact hole portion 61 is provided at a position corresponding to the emitter region 12" means, for example, that the emitter region 12 and the first contact hole portion 61 are provided at the same position in the extension direction within the mesa portion 71. Alternatively, "the first contact hole portion 61 is provided at a position corresponding to the emitter region 12" may mean that the first contact hole portion 61 is provided above the emitter region 12. Alternatively, "the first contact hole portion 61 is provided at a position corresponding to the emitter region 12" may mean that the emitter region 12 is provided below the first contact hole portion 61. Furthermore, "the first contact hole portion 61 is provided at a position corresponding to the emitter region 12" may mean that a portion of the interlayer insulating film 38 that contacts the first contact hole portion 61, i.e., an edge portion 166 of the interlayer insulating film 38 with the first contact hole portion 61, is provided above the emitter region 12 or contacts the emitter region 12.

[0092] "The second contact hole portion 62 is provided at a position corresponding to the contact region 15" means, for example, that the contact region 15 and the second contact hole portion 62 in the mesa portion 71 are provided at the same position in the extension direction. Alternatively, "the second contact hole portion 62 is provided at a position corresponding to the contact region 15" may mean that the second contact hole portion 62 is provided above the contact region 15. Alternatively, "the second contact hole portion 62 is provided at a position corresponding to the contact region 15" may mean that the contact region 15 is provided below the second contact hole portion 62. Furthermore, "the second contact hole portion 62 is provided at a position corresponding to the contact region 15" may mean that a portion of the interlayer insulating film 38 that contacts the second contact hole portion 62, i.e., an edge portion 167 of the interlayer insulating film 38 with the second contact hole portion 62, is provided above the contact region 15 or contacts the contact region 15.

[0093] The first contact hole portion 61 has a recess 161 at least a part of which is formed by etching the emitter region 12. For example, the lower end of the first contact hole portion 61 is formed by etching the emitter region 12. The first contact hole portion 61 of this example is provided in contact with the emitter region 12. The first contact hole portion 61 of this example is provided so as to be sandwiched between the emitter regions 12 in the arrangement direction when viewed from above.

[0094] The second contact hole portion 62 has a recess 162 at least a part of which is formed by etching the contact region 15. For example, the lower end of the second contact hole portion 62 is formed by etching the contact region 15. The second contact hole portion 62 of this example is provided in contact with the contact region 15. The second contact hole portion 62 of this example is provided between the contact regions 15 in the arrangement direction when viewed from above.

[0095] Here, the first contact hole portion 61 and the second contact hole portion 62 may have different shapes due to the difference between the etching rate of the emitter region 12 and the etching rate of the contact region 15. For example, if the etching rate of the contact region 15 is higher than the etching rate of the emitter region 12, the width of the first contact hole portion 61 in the arrangement direction will be smaller than the width of the second contact hole portion 62 in the arrangement direction. Furthermore, if the etching rate of the contact region 15 is higher than the etching rate of the emitter region 12, the depth position of the lower end of the depression 161 of the first contact hole portion 61 will be shallower than the depth position of the lower end of the depression 162 of the second contact hole portion 62. As a result, the sidewall of the contact hole 60 below the front surface 21 is provided with unevenness corresponding to the first contact hole portion 61 and the second contact hole portion 62.

[0096] Above the front surface 21, there is no difference in etching rate of the interlayer insulating film 38 between the first contact hole portion 61 and the second contact hole portion 62. Therefore, above the front surface 21, the sidewall of the contact hole 60 does not have any irregularities, and a flat shape is formed along the extension direction (for example, a linear sidewall connecting the dashed line of the first contact hole portion 61 and the dashed line of the second contact hole portion 62 in top view).

[0097] The width Wm is the width of the mesa portion 71 in the arrangement direction. The width Wm may be 0.5 μm or more and 1.5 μm or less. For example, the width Wm is 0.8 μm.

[0098] The width Wt is the width of the trench portion in the arrangement direction. The width Wt of the dummy trench portion 30 and the gate trench portion 40 may be the same or different. The width Wt may be 0.6 μm or more and 2.0 μm or less. For example, the width Wt is 1.1 μm.

[0099] The width Wc is the width of the contact hole 60 in the arrangement direction. The width Wc is the width of the opening 39 provided in the interlayer insulating film 38 above the front surface 21. The width Wc may be 0.1 μm or more and 0.6 μm or less. For example, the width Wc is 0.35 μm. The width Wc may be 20% or more, or 30% or more, of the width Wm. The width Wc may be 70% or less, or 60% or less of the width Wm.

[0100] The width Ws indicates the size of the step between the sidewalls of the first contact hole portion 61 and the second contact hole portion 62. In other words, the width Ws indicates the difference in the arrangement direction between the sidewalls of the first contact hole portion 61 and the sidewalls of the second contact hole portion 62 on the front surface 21. The width Ws may be 0.01 μm or more and 0.04 μm or less. In this example, the width Ws is 0.02 μm. The width Ws may be 0.1% or more and 10% or less of the width Wc, or 1% or more and 5% or less.

[0101] Fig. 1E shows an example of the cc' cross section in Fig. 1A. The cc' cross section is a YZ plane passing through the contact hole 60 in the transistor section 70.

[0102] The lower end of the first contact hole portion 61 is provided at a different depth than the lower end of the second contact hole portion 62. That is, the lower end of the metal layer filled in the first contact hole portion 61 is provided at a different depth than the lower end of the metal layer filled in the second contact hole portion 62. The lower end of the first contact hole portion 61 is shallower than the lower end of the second contact hole portion 62. The metal layer filled in the first contact hole portion 61 and the second contact hole portion 62 may be the metal material that forms the emitter electrode 52 described above, or may be a plug metal layer formed of tungsten, titanium, a titanium alloy, titanium silicide, or the like.

[0103] In this way, the lower end of the second contact hole portion 62 may be formed deeper than the lower end of the first contact hole portion 61 due to over-etching when opening the interlayer insulating film 38. Also, the emitter region 12 at the lower end of the first contact hole portion 61 may be etched by over-etching when opening the interlayer insulating film 38. The upper end of the emitter region 12 after etching may be flush with the front surface 21, or may be deeper than the front surface 21. In this example, the upper end of the emitter region 12 is deeper than the front surface 21, and a recess 162 is formed.

[0104] The thickness Ds in the depth direction indicates the difference between the bottom end of the first contact hole portion 61 and the bottom end of the second contact hole portion 62. The thickness Ds in the depth direction indicates the size of the step caused by the difference in etching rate between the emitter region 12 and the contact region 15. The thickness Ds in the depth direction may vary depending on the depth of the contact hole 60. The thickness Ds in the depth direction may be larger than the width Ws, which is the step in the arrangement direction.

[0105] The thickness Ds in the depth direction may be 0.01 μm or more, or 0.03 μm or more. The thickness Ds in the depth direction may be 0.08 μm or less, or 0.06 μm or less. For example, the thickness Ds in the depth direction is 0.03 μm.

[0106] The depth direction thickness De indicates the depth direction thickness from the front surface 21 to the upper end of the emitter region 12. The depth direction thickness De is also the depth of the recess 161 from the front surface 21. The depth direction thickness De may be 0.005 μm or more, or 0.01 μm or more. The depth direction thickness De may be 0.05 μm or less, or 0.03 μm or less. For example, the depth direction thickness De is 0.01 μm.

[0107] The depth D12 indicates the thickness in the depth direction from the front surface 21 to the lower end of the emitter region 12. The depth D12 may be 0.1 μm or more and 1.0 μm or less, or 0.2 μm or more and 0.6 μm or less. For example, the depth D12 is 0.3 μm.

[0108] The depth D15 indicates the thickness in the depth direction from the front surface 21 to the bottom end of the contact region 15. The depth D15 may be 0.5 μm or more and 1.5 μm or less. For example, the depth D15 is 1.0 μm.

[0109] The depth Dp indicates the depth from the bottom of the second contact hole 62 to the bottom of the contact region 15. In this example, the depth Dp indicates the thickness of the contact region 15 below the second contact hole 62. Reducing the depth Dp makes it easier to extract holes. The depth Dp may be 0.1 μm or more and 1.2 μm or less, or 0.3 μm or more and 1.0 μm or less. For example, the depth Dp is 0.6 μm.

[0110] In the semiconductor device 100 of this example, the step between the first contact hole portion 61 and the second contact hole portion 62 can shorten the distance that holes travel through the contact region 15 to the emitter electrode 52. This improves the extraction of holes to the emitter electrode 52, making it easier to suppress latch-up.

[0111] 2A shows a modified example of the b-b' cross section in FIG. 1A. Fig. 2A differs from Fig. 1C in that a plug contact region 19 is formed to cover the recess 162. The plug contact region 19 is a region of the second conductivity type that has a doping concentration higher than that of the base region 14 and the contact region 15.

[0112] 2B shows a modified example of the c-c' cross section in FIG. 1A. It differs from FIG. 1E in that a plug contact region 19 is provided on the surface of the contact region 15. The plug contact region 19 is a region of the second conductivity type that has a higher doping concentration than the base region 14 and the contact region 15. The plug contact region 19 in this example is provided below the second contact hole portion 62. The plug contact region 19 does not have to be provided below the first contact hole portion 61.

[0113] 3A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG.

[0114] The trench contact portion 65 is provided on the front surface 21 side of the semiconductor substrate 10 between two adjacent trench portions among the multiple trench portions. In this example, the trench contact portion 65 is provided extending in the extension direction. The trench contact portion 65 has a contact hole 60 and a metal layer filled inside the contact hole 60. The inside of the contact hole 60 may be filled with the same material as the emitter electrode 52, or may be filled with a material different from the emitter electrode 52.

[0115] FIG. 3B shows an example of the d-d' cross section in FIG. 3A. The d-d' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. The trench contact section 65 in this example is a groove provided in the semiconductor substrate 10 exposed through the contact hole 60, and is deeper than the recesses described in FIGS. 1A to 1E. Specifically, the depth of the bottom surface of the trench contact section 65 from the front surface 21 of the semiconductor substrate 10 may be 0.05 μm or more, or may be 0.2 μm or more. The groove of the trench contact section 65 may have sidewalls that are perpendicular to the front surface 21 in the depth direction and may have sidewalls that form a predetermined angle θ with respect to the front surface 21. In the example of FIG. 3B, the angle θ is 90° or more. The trench contact portion 65 may be a groove provided in the semiconductor substrate 10 exposed by the contact hole 60, with the bottom surface being 0.2 μm or more from the front surface 21 of the semiconductor substrate 10 and having sidewalls that form a predetermined angle θ with respect to the front surface 21. An edge portion 166 of the sidewall of the interlayer insulating film 38 may also be formed at an angle θ with respect to the surface of the interlayer insulating film 38.

[0116] The trench contact portion 65 in this example is provided to penetrate the emitter region 12 in the depth direction, but it does not have to penetrate the emitter region 12. The semiconductor device 100 in this example includes an accumulation region 16 below the trench contact portion 65, but it does not have to include the accumulation region 16. A plug metal layer 68 is formed in the trench contact portion 65 in this example. As described above, the plug metal layer 68 may be filled with tungsten, titanium, a titanium alloy, titanium silicide, or the like.

[0117] Width A1 is the width of the trench contact portion 65 in the arrangement direction on the front surface 21. Width B1 is the width of the trench contact portion 65 at the lower end in the arrangement direction. The trench contact portion 65 in this example has a tapered XZ cross section. Width A1 is larger than width B1. Width A1 may be 0.25 μm or more and 0.5 μm or less. Width B1 may be 0.15 μm or more and 0.4 μm or less. For example, width A1 is 0.35 μm and width B1 is 0.2 μm, but is not limited to these.

[0118] 3C shows an example of the e-e' cross section in FIG. 3A. The e-e' cross section is an XZ plane passing through the contact region 15 in the transistor section 70. The trench contact portion 65 of this example is provided without penetrating the contact region 15 in the depth direction.

[0119] The width A2 is the width of the trench contact portion 65 in the arrangement direction on the front surface 21. The width B2 is the width of the trench contact portion 65 at the lower end in the arrangement direction. The trench contact portion 65 in this example has a tapered XZ cross section. The width A2 is larger than the width B2. The width A2 of the second contact hole portion 62 may be larger than the width A1 of the first contact hole portion 61. The width B2 of the second contact hole portion 62 may be larger than the width B1 of the first contact hole portion 61. For example, the width A2 is 0.37 μm and the width B2 is 0.22 μm, but is not limited to this.

[0120] 3D is an enlarged view of the front surface 21 of the semiconductor device 100 shown in FIG. 3A. This figure shows the front surface 21 of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40. The trench contact portion 65 has a first contact hole portion 61 and a second contact hole portion 62 as the contact hole 60. The dashed line of the contact hole 60 indicates the sidewall of the interlayer insulating film 38 in the contact hole 60 above the front surface 21. In other words, the dashed line of the contact hole 60 is the opening portion 39 of the interlayer insulating film 38. The opening portion 39 of the interlayer insulating film 38 may have a constant width regardless of the trench contact portion 65, the emitter region 12, and the contact region 15 formed in the underlying layer (the surface of the semiconductor substrate 10). The solid line of the contact hole 60 indicates a recess 261 or a recess 262 formed in the bottom surface of the trench contact portion 65 below the front surface 21, and indicates the sidewall of the semiconductor substrate 10 in which the recess 261 or the recess 262 is formed. In other words, the recess 261 or the recess 262, which is formed by the bottom surface of the trench contact portion 65 exposed in the opening portion 39 of the interlayer insulating film 38 being recessed downward, may also be included in the contact hole 60.

[0121] The width Wst indicates the size of the step between the sidewalls of the first contact hole portion 61 and the second contact hole portion 62 provided in the trench contact portion 65. In other words, the width Wst indicates the difference in the arrangement direction between the sidewalls of the first contact hole portion 61 and the sidewalls of the second contact hole portion 62 provided in the trench contact portion 65 on the front surface 21. The width Wst may be 0.01 μm or more and 0.06 μm or less. In this example, the width Wst is 0.03 μm. The width Wst may be 0.1% or more and 10% or less of the width Wc, or 1% or more and 5% or less.

[0122] The trench contact portion 65 is formed by etching the front surface 21, including the emitter region 12 and the contact region 15. Therefore, compared to when the trench contact portion 65 is not provided as shown in FIG. 1D, the trench contact portion 65 is more susceptible to the etching rate difference because the amount of etching of the emitter region 12 and the contact region 15 is greater. Therefore, the step between the first contact hole portion 61 and the second contact hole portion 62 on the sidewall of the trench contact portion 65 becomes larger. In other words, the width Wst may be larger than the width Ws without the trench contact portion 65.

[0123] 3A. The f-f' cross section is a YZ plane passing through the trench contact portion 65 in the transistor portion 70. The semiconductor device 100 of this example includes a plug contact region 19 below the trench contact portion 65.

[0124] The first contact hole portion 61 of this example is provided so as to penetrate through the emitter region 12. Therefore, the emitter region 12 is not provided below the first contact hole portion 61 in the ff' cross section.

[0125] The second contact hole portion 62 in this example is provided without penetrating the contact region 15. That is, the lower end of the second contact hole portion 62 is shallower than the lower end of the contact region 15. The contact region 15 is provided below the second contact hole portion 62. The contact region 15 in this example is provided separated from the lower end of the metal layer filled in the second contact hole portion 62 by a plug contact region 19. The contact region 15 is provided below the plug contact region 19 that is in contact with the lower end of the metal layer filled in the second contact hole portion 62.

[0126] The plug contact region 19 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. In this example, the plug contact region 19 is provided on the entire surface below the trench contact portion 65. That is, the plug contact region 19 is provided below both the first contact hole portion 61 and the second contact hole portion 62. In this example, the plug contact region 19 is provided in contact with the lower end of the metal layer filled in the trench contact portion 65. The lower end of the plug contact region 19 may be in contact with the emitter region 12 below the first contact hole portion 61. The lower end of the plug contact region 19 may be in contact with the contact region 15 below the second contact hole portion 62. The depth position of the upper end of the plug contact region 19 may be located closer to the front surface 21 than the bottom surface of the trench contact portion 65. That is, the plug contact region 19 may be provided to cover the bottom surface of the trench contact portion 65.

[0127] Here, the plug contact region 19 is formed by forming the trench contact portion 65 and then implanting ions into the bottom surface of the trench contact portion 65. The depth at which the plug contact region 19 is formed is affected by the step between the first contact hole portion 61 and the second contact hole portion 62. Therefore, the plug contact region 19 below the first contact hole portion 61 is provided shallower than the plug contact region 19 below the second contact hole portion 62. The bottom surface of the plug contact region 19 may be provided in a wavy shape along the depth of the bottom surface of the trench contact portion 65. The bottom surface of the plug contact region 19 may be provided in a wavy shape according to the depth of the bottom surface of the trench contact portion 65.

[0128] The depth direction thickness D1 indicates the depth direction thickness from the front surface 21 to the bottom end of the first contact hole portion 61. It is equal to the shallowest depth from the front surface 21 to the bottom surface of the trench contact portion 65. The depth direction thickness D1 may be 0.05 μm or more, 0.2 μm or more and 1.0 μm or less, or 0.3 μm or more and 0.6 μm or less. For example, the depth direction thickness D1 is 0.35 μm.

[0129] The thickness Dst in the depth direction indicates the magnitude of the step between the first contact hole portion 61 and the second contact hole portion 62 in the depth direction. In other words, the thickness Dst in the depth direction indicates the difference in the depth direction of the semiconductor substrate 10 between the bottom end of the first contact hole portion 61 and the bottom end of the second contact hole portion 62. The thickness Dst in the depth direction may be 0.01 μm or more and 0.1 μm or less. For example, the thickness Dst in the depth direction is 0.03 μm.

[0130] The ratio α of the depth direction thickness Dst to the depth direction thickness D1 may be 0.01 or more and 1.0 or less, 0.05 or more and 0.5 or less, or 0.07 or more and 0.2 or less.

[0131] The depth D19 indicates the depth of the plug contact region 19. The depth D19 may be 0.005 μm or more and 0.2 μm or less. For example, the depth D19 of the plug contact region 19 is 0.01 μm.

[0132] The depth direction thickness Dpt indicates the depth direction thickness from the bottom end of the second contact hole portion 62 to the bottom end of the contact region 15. In this example, the depth direction thickness Dpt corresponds to the sum of the depth direction thicknesses of the plug contact region 19 and the contact region 15 provided below the second contact hole portion 62. Reducing the depth direction thickness Dpt makes it easier to extract holes. The depth direction thickness Dpt may be 0.1 μm or more and 1.2 μm or less, or may be 0.3 μm or more and 1.0 μm or less. For example, the depth direction thickness Dpt is 0.6 μm.

[0133] Providing the plug contact region 19 so as to cover the bottom surface of the trench contact portion 65 has the effect of enhancing the suppression of latch-up. As in the present embodiment, by providing the recess 261 and recess 262 on the bottom surface of the trench contact portion 65, with recess 262 being deeper than recess 261, it is possible to prevent holes flowing from the back surface 23 toward the front surface 21 from concentrating toward the emitter region 12. This makes it possible to suppress the occurrence of latch-up when the transistor portion is turned off.

[0134] Fig. 4A shows a modified example of the dd' cross section in Fig. 3A. The trench contact portion 65 of this example differs from that of Fig. 3B in that it does not penetrate the emitter region 12 in the depth direction.

[0135] FIG. 4B shows a modified example of the d-d' cross section in FIG. 3A. The trench contact portion 65 of this example penetrates the emitter region 12 in the depth direction, as in FIG. 3B, but differs from FIG. 3B in that a plug contact region 19 is provided to cover the bottom surface of the trench contact portion 65. The plug contact region 19 is a region of the second conductivity type that has a higher doping concentration than the base region 14 and the contact region 15. The plug contact region 19 will be described later. In the arrangement direction, the width of the plug contact region 19 may be larger than the width of the bottom surface of the trench contact portion 65. This figure corresponds to an XZ cross section of the position where the second contact hole portion 62 is provided in FIG. 3E.

[0136] 4C shows a modified example of the dd' cross section in FIG. 3A. The trench contact portion 65 of this example differs from that of FIG. 4A in that a plug contact region 19 is provided to cover the bottom surface of the trench contact portion 65. The lower end of the plug contact region 19 of this example is deeper than the lower end of the emitter region 12.

[0137] Fig. 4D shows a modified example of the d-d' cross section in Fig. 3A. The trench contact portion 65 of this example differs from that of Fig. 4A in that it includes a plug contact region 19 that covers the bottom surface of the trench contact portion 65, and differs from that of Figs. 4B and 4C in that the lower end of the emitter region 12 is deeper than the lower end of the plug contact region 19.

[0138] Fig. 5A shows a modified example of the e-e' cross section in Fig. 3A. Fig. 5A differs from Fig. 3C in that a plug contact region 19 is provided so as to cover the bottom surface of the trench contact portion 65. This figure corresponds to an XZ cross section of the position where the second contact hole portion 62 is provided in Fig. 3E.

[0139] 5B shows a modified example of the e-e' cross section in FIG. 3A. FIG. 5B differs from FIG. 5A in that the lower end of the trench contact portion 65 is deeper than the lower end of the contact region 15. The lower end of the trench contact portion 65 is located deeper than the upper end of the base region 14. The plug contact region 19 in this example contacts the base region 14.

[0140] FIG. 6A shows a modified example of the semiconductor device 100. This figure shows a YZ plane passing through the trench contact portion 65. In this example, the trench contact portion 65 is provided so as to penetrate the emitter region 12, but the plug contact region 19 is selectively provided below the trench contact portion 65, which is different from the embodiment of FIG. 3E. In this example, differences from the embodiment of FIG. 3E will be particularly described, and the rest may be the same as the embodiment of FIG. 3E. In other words, FIG. 6A of this example corresponds to the examples of FIG. 3B and FIG. 5A.

[0141] The first contact hole portion 61 is provided to penetrate the emitter region 12, and the lower end of the first contact hole portion 61 is deeper than the lower end of the emitter region 12. In other words, the emitter region 12 is not provided below the first contact hole portion 61. The lower end of the metal layer filled in the first contact hole portion 61 contacts the base region 14.

[0142] The plug contact region 19 is not provided over the entire area below the trench contact portion 65, but is provided in a portion below the trench contact portion 65. In this example, the plug contact region 19 is provided below the second contact hole portion 62, and is not provided below the first contact hole portion 61. However, a portion of the plug contact region 19 may be provided below the first contact hole portion 61 by diffusion. The lower end of the metal layer filled in the first contact hole portion 61 is in contact with the base region 14. Note that a portion of the lower end of the metal layer filled in the first contact hole portion 61 may be in contact with the contact region 15 or the plug contact region 19.

[0143] FIG. 6B shows a modified example of the semiconductor device 100. This figure shows a YZ plane passing through the trench contact portion 65. In this example, the plug contact region 19 is provided over the entire surface below the trench contact portion 65, but differs from the embodiment of FIG. 3E in that the trench contact portion 65 is provided without penetrating the emitter region 12. In this example, differences from the embodiment of FIG. 3E will be particularly described, and the rest may be the same. That is, FIG. 6B of this example corresponds to the examples of FIG. 4D and FIG. 5A.

[0144] The first contact hole portion 61 is provided without penetrating the emitter region 12, and the lower end of the first contact hole portion 61 is shallower than the lower end of the emitter region 12. In other words, the emitter region 12 is provided below the first contact hole portion 61. The lower end of the metal layer filled in the first contact hole portion 61 is in contact with the plug contact region 19.

[0145] FIG. 6C shows a modified example of the semiconductor device 100. This figure shows a YZ plane passing through the trench contact portion 65. In this example, the trench contact portion 65 is provided without penetrating the emitter region 12, but the plug contact region 19 is selectively provided below the trench contact portion 65, which is different from the embodiment of FIG. 6B. In this example, differences from the embodiment of FIG. 6B will be particularly described, and the rest may be the same. That is, FIG. 6C of this example corresponds to the examples of FIGS. 4A and 5A.

[0146] The first contact hole portion 61 is provided without penetrating the emitter region 12, and the lower end of the first contact hole portion 61 is shallower than the lower end of the emitter region 12. That is, the emitter region 12 is provided below the first contact hole portion 61. Furthermore, the plug contact region 19 is not provided below the first contact hole portion 61. As a result, the lower end of the metal layer filled in the first contact hole portion 61 is in contact with the emitter region 12.

[0147] Even when a step is provided between the first contact hole portion 61 and the second contact hole portion 62 in this way, the semiconductor device 100 may have various structures in terms of the relationship between the emitter region 12 and the contact region 15. Furthermore, the semiconductor device 100 may be provided with a plug contact region 19 at the lower end of the contact hole 60 as appropriate.

[0148] 7A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0149] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0150] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. In this example, the boundary portion 90 does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0151] The contact holes 60 are provided above the base region 14 in the diode section 80. The contact holes 60 are provided above the contact region 15 in the boundary section 90. None of the contact holes 60 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0152] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0153] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0154] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0155] 7B shows a cross section taken along line gg' of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a first lifetime control region 151 and a second lifetime control region 152.

[0156] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0157] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0158] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0159] The first lifetime control region 151 is provided in both the transistor portion 70 and the diode portion 80. This allows the semiconductor device 100 of this example to speed up recovery in the diode portion 80 and further improve switching loss. The first lifetime control region 151 may be formed by a method similar to that used for the first lifetime control region 151 of the other embodiments.

[0160] The second lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the second lifetime control region 152 is provided in the drift region 18. The second lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The second lifetime control region 152 may be formed by implanting impurities from the front surface 21 side, or may be formed by implanting impurities from the back surface 23 side. The second lifetime control region 152 is provided in the diode section 80 and the boundary section 90, and may not be provided in a part of the transistor section 70.

[0161] The second lifetime control region 152 may be formed by any method among the methods for forming the first lifetime control region 151. The elements and doses used to form the first lifetime control region 151 and the second lifetime control region 152 may be the same or different.

[0162] The first contact hole portion 61 and the second contact hole portion 62 may be provided in the transistor portion 70 in this example, just as they are provided in the transistor portion 70 in other examples. The diode portion 80 in this example does not have the emitter region 12 and the contact region 15, so the first contact hole portion 61 and the second contact hole portion 62 may not be provided. However, if materials with different etching rates are formed in the diode portion 80, the first contact hole portion 61 and the second contact hole portion 62 may be formed. In this example, the first contact hole portion 61 and the second contact hole portion 62 are the examples in FIGS. 4C and 5A.

[0163] 8A is a flowchart showing an example of a method for manufacturing the semiconductor device 100. In step S100, ions are implanted into the semiconductor substrate 10 to form the emitter region 12. The emitter region 12 may be ion-implanted using an N-type dopant such as arsenic or phosphorus. For example, the doping concentration of the emitter region 12 is 1E19 / cm 3 Above, 1E20 / cm 3 In step S100, for example, a resist mask formed in a predetermined pattern may be used to implant a dopant. In step S102, ions are implanted into the semiconductor substrate 10 to form the contact region 15. The contact region 15 may be formed by implanting a dopant such as boron. For example, the doping concentration of the contact region 15 may be 1E18 / cm 3 . 3 Above, 1E19 / cm 3 In step S102, for example, a P-type dopant may be ion-implanted using a resist mask formed in a predetermined pattern. In step S104, the semiconductor substrate 10 is annealed to form the emitter region 12 and the contact region 15. The annealing temperature in step S104 is, for example, 900° C. or higher and 1000° C. or lower.

[0164] In step S106, an interlayer insulating film 38 is formed above the semiconductor substrate 10 by film formation such as low-pressure CVD. The interlayer insulating film 38 may be BPSG, PSG, HTO, or a composite film of these. In step S108, the interlayer insulating film 38 is annealed. The annealing temperature in step S108 is, for example, 900° C. or higher and 950° C. or lower.

[0165] In step S110, the interlayer insulating film 38 is etched in a predetermined pattern to form the first contact hole portion 61 and the second contact hole portion 62. In this example, a mask such as a photoresist may be formed above the interlayer insulating film 38 to form the contact hole 60 in the interlayer insulating film 38. In step S110 of this example, the etching for forming the first contact hole portion 61 and the etching for forming the second contact hole portion 62 are performed in the same etching process. That is, the first contact hole portion 61 and the second contact hole portion 62 may be formed using the same mask.

[0166] In step S110, even after the surface of the semiconductor substrate 10 is exposed by etching the interlayer insulating film 38, etching is continued for a predetermined time to etch the exposed surface of the semiconductor substrate 10 (over-etching). In this case, by using reactive etching such as a chlorine-based gas for etching the interlayer insulating film 38, a difference in etching rate between the emitter region 12 and the contact region 15 is likely to occur. Because the etching rate of the contact region 15 is faster than the etching rate of the emitter region 12, the second contact hole portion 62 is likely to be formed deeper than the first contact hole portion 61.

[0167] In this example, the first contact hole portion 61 and the second contact hole portion 62 are formed after step S104, in which the semiconductor substrate 10 is annealed to form the emitter region 12 and the contact region 15. By performing annealing in advance in step S104 to form the emitter region 12 and the contact region 15, a difference in etching rate between the emitter region 12 and the contact region 15 becomes more likely. This makes it easier to form a step (recess) between the lower end of the first contact hole portion 61 and the lower end of the second contact hole portion 62.

[0168] The trench contact portion 65 may be formed in step S110 by overetching the interlayer insulating film 38, or may be formed by additional etching using the interlayer insulating film 38 as a mask.

[0169] 8B is a flowchart showing a modified example of the method for manufacturing the semiconductor device 100. This figure shows a method for manufacturing the semiconductor device 100 having the trench contact portion 65 and the plug contact region 19. In this example, differences from the manufacturing method shown in FIG. 8A will be particularly described. Steps S100 to S108 may be the same as the manufacturing method shown in FIG. 8A.

[0170] In step S110, first contact hole portions 61 and second contact hole portions 62 are formed. In this example, in order to form trench contact portions 65 in the semiconductor substrate 10, contact holes 60 are formed in the depth direction of the semiconductor substrate 10 beyond the front surface 21. In step S112, ion implantation is performed to form the plug contact regions 19. In step S112, ions may be implanted into the first contact hole portions 61 and the second contact hole portions 62, which are openings in the interlayer insulating film 38, using the interlayer insulating film 38 as a mask. Alternatively, selective ion implantation may be performed into the first contact hole portions 61 and the second contact hole portions 62 using a resist mask formed in a predetermined pattern. In step S114, the semiconductor substrate 10 is annealed to form the plug contact regions 19.

[0171] In this example, the first contact hole portion 61 and the second contact hole portion 62 are formed by the same etching process, but the steps may be formed by using different etching processes for each. That is, the first contact hole portion 61 and the second contact hole portion 62 may be formed by etching using different masks. In this case, the first contact hole portion 61 and the second contact hole portion 62 may be etched under different etching conditions. The plug metal layer 68 may be formed after step S114.

[0172] In this example, the transistor section is an IGBT, but as mentioned above, the transistor section may also be a MOSFET. With a configuration similar to this example, even in an avalanche breakdown mode where a high current flows, holes, which are generated as minority carriers, can be efficiently collected in the trench contact section 65, improving the avalanche resistance.

[0173] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0174] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0175] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 plug contact region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 opening portion, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 gate metal layer, 52 Emitter electrode, 55 contact hole, 56 contact hole, 60 contact hole, 61 first contact hole portion, 62 second contact hole portion, 65 trench contact portion, 68 plug metal layer, 70 transistor portion, 71 mesa portion, 80 diode portion, 81 mesa portion, 82 cathode region, 90 boundary portion, 91 mesa portion, 100 semiconductor device, 151 first lifetime control region, 152 second lifetime control region, 161 recess, 162 recess, 166 edge portion, 167 edge portion, 261 recess, 262 recess

Claims

1. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; a plurality of trench portions extending in a predetermined extension direction on a front surface side of the semiconductor substrate; an interlayer insulating film provided above the semiconductor substrate and having a first contact hole portion and a second contact hole portion; Equipped with the contact regions and the emitter regions are alternately provided in the extension direction, the first contact hole portions are provided alternately with the second contact hole portions in the extending direction, The lower end of the first contact hole portion is provided at a depth different from that of the lower end of the second contact hole portion. Semiconductor device.

2. The first contact hole portion and the second contact hole portion are alternately provided in the extension direction such that the first contact hole portion is provided at a position corresponding to the emitter region, and the second contact hole portion is provided at a position corresponding to the contact region. The semiconductor device according to claim 1 .

3. the emitter region is provided below the first contact hole portion, The contact region is provided below the second contact hole.

3. The semiconductor device according to claim 1.

4. The first contact hole portion and the second contact hole portion are provided in the same contact hole. The semiconductor device according to claim 1 .

5. The lower end of the first contact hole is shallower than the lower end of the second contact hole. The semiconductor device according to claim 1 .

6. The difference between the bottom end of the first contact hole and the bottom end of the second contact hole is 0.03 μm or more. The semiconductor device according to claim 1 .

7. The thickness of the contact region below the second contact hole is 0.3 μm or more and 1.0 μm or less. The semiconductor device according to claim 1 .

8. a plug contact region of a second conductivity type provided below the second contact hole and having a doping concentration higher than that of the base region; The semiconductor device according to claim 1 .

9. a trench contact portion provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; The semiconductor device according to claim 1 .

10. a first metal layer filled in the first contact hole portion; The base region is provided below the first metal layer. The semiconductor device according to claim 9 .

11. a first metal layer filled in the first contact hole portion; The lower end of the first metal layer is in contact with the emitter region. The semiconductor device according to claim 9 .

12. a ratio α of the depth from the front surface of the semiconductor substrate to the bottom end of the first contact hole portion to the difference in depth between the bottom end of the first contact hole portion and the bottom end of the second contact hole portion in the semiconductor substrate is 0.01 or more and 1.0 or less The semiconductor device according to claim 9 .

13. a plug contact region of a second conductivity type provided below the trench contact portion and having a doping concentration higher than that of the base region; In the arrangement direction of the plurality of trench portions, the width of the plug contact region is larger than the width of the bottom surface of the trench contact portion. The semiconductor device according to claim 9 .

14. The plug contact region is provided below both the first contact hole portion and the second contact hole portion. The semiconductor device according to claim 13.

15. The plug contact region below the first contact hole portion is provided shallower than the plug contact region below the second contact hole portion. The semiconductor device according to claim 14.

16. The plug contact region is provided below the second contact hole portion and is not provided below the first contact hole portion. The semiconductor device according to claim 13.

17. The contact region is provided below the second contact hole. The semiconductor device according to claim 13 .

18. a second metal layer filled in the second contact hole portion; the contact region contacts the lower end of the second metal layer; The contact region is provided below the plug contact region.

18. The semiconductor device according to claim 17.

19. The width of the first contact hole portion in the arrangement direction of the plurality of trench portions is smaller than the width of the second contact hole portion in the arrangement direction. The semiconductor device according to claim 1 .

20. It has a transistor section and a diode section The semiconductor device according to claim 1 .

21. forming a drift region of a first conductivity type in a semiconductor substrate; forming a base region of a second conductivity type above the drift region; forming an emitter region of a first conductivity type above the base region; forming a contact region of a second conductivity type above the base region, the contact region having a doping concentration higher than that of the base region; forming a plurality of trenches extending in a predetermined extension direction on a front surface side of the semiconductor substrate; forming an interlayer insulating film above the semiconductor substrate, the interlayer insulating film having a first contact hole portion above the emitter region and a second contact hole portion above the contact region; Equipped with the contact regions and the emitter regions are alternately provided in the extension direction, A method for manufacturing a semiconductor device, wherein a lower end of the first contact hole portion is provided at a different depth from a lower end of the second contact hole portion.

22. annealing the semiconductor substrate to form the emitter region and the contact region; after the annealing step, etching the interlayer insulating film to form the first contact hole portion and the second contact hole portion; Equipped with The method for manufacturing a semiconductor device according to claim 21.

23. The etching for forming the first contact hole portion and the etching for forming the second contact hole portion are performed in the same etching process. The method for manufacturing a semiconductor device according to claim 22.

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