Semiconductor memory device and method for controlling semiconductor memory device

Abstract

To provide a power-saving semiconductor storage device which prevents reliability deterioration and a semiconductor storage device control method.SOLUTION: A memory cell 100 holds data. Bit lines Bit and / Bit are connected to the memory cell 100 and reduces a reference voltage to thereby invert the data held by the memory cell 100. A step-down circuit 102 reduces a bit line voltage at a first predetermined value equal to or lower than the reference voltage. A Vdd dependence generation circuit 103 detects a voltage change based on a first output provided from an inverter chain 131 having delay voltage dependence and a second output provided from an inverter chain 132 whose delay voltage dependence is greater than that of the inverter chain 131, and controls the amount of a bit line voltage reduced by the step-down circuit 102 in accordance with the amount of voltage change detected.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a method for controlling the semiconductor memory device. [Background technology]

[0002] As semiconductors become smaller, the manufacturing variability of memory cells becomes larger relative to the nominal voltage. As a result, in memory cells used in processors that utilize DVFS (Dynamic Voltage and Frequency Scaling), the write margin deteriorates at low voltages, resulting in a higher incidence of write failures. This is particularly true in low-power devices that operate at low power supply voltages, resulting in a lower yield of memory cells.

[0003] DVFS is a technique for dynamically changing the operating frequency and power supply voltage of a processor depending on the processing load. A memory cell used in a processor using DVFS is, for example, an SRAM (Static Random Access Memory) memory cell.

[0004] Therefore, various write assist circuits have been proposed as a countermeasure against the deterioration of margins at low voltages. For example, a write assist circuit is a negative bit line type circuit that assists writing to a memory cell by lowering the bit line potential to a negative potential.

[0005] In recent years, an increasing number of processors have adopted DVFS to improve processor performance per watt. As a result, the operating voltage required for memory cells has expanded from the minimum voltage of the technology to higher voltages. Furthermore, from the perspective of performance competition, memory cells are required to operate at the maximum voltage at which degradation over time is tolerated.

[0006] Here, we will explain the negative bit line type write assist circuit. To write data to a memory cell, the potential of one of the bit lines, which is precharged to the H level, is changed from the H level to the L level. This forces the data retention node on one side of the latch that makes up the cell to be pulled down to L via a transfer gate, inverting the entire latch and completing the write. However, if there is a large variation in the manufacturing process of the transistors that make up the memory cell, a defect may occur in which the retained data is not inverted even when one of the bit lines changes completely from the H level to the L level. Memory cells often use CMOS (Complementary Metal Oxide Semiconductor), and the occurrence of such defects increases at low voltages.

[0007] Therefore, in a negative bit line write assist circuit, a write assist circuit is connected to the path extending from the bit line pair to Vdd. The write assist circuit then disconnects the bit line pair and its connection node from Vss, leaving them in a floating state. A buffer built into the write assist circuit then drives the coupling capacitance with the connection node, lowering the potential of one of the bit lines that is pulled to the L level to a negative potential even lower than Vss, thereby assisting in the inversion of the data held in the memory cell. The magnitude of the negative potential is determined by the capacitance ratio between the bit line parasitic capacitance and the coupling capacitance.

[0008] However, in the method described here, when increasing the voltage, a voltage with a negative potential magnitude added to the positive voltage is applied between the gate and source of the memory cell's transfer gate. This can have a negative impact on transistor reliability. In particular, when using the DVFS method, which dynamically changes the power supply voltage and operating frequency to improve the power efficiency of LSIs (Large Scale Integrators), the memory cell is only applied a voltage up to the maximum rated voltage minus the negative potential, which can limit high-speed operation.

[0009] To address these issues, a technology has been proposed that replaces the capacitance of the boost circuit with a variable capacitance that decreases as the power supply voltage increases, and another technology has been proposed that simultaneously operates the step-down circuit and the step-up circuit when the Vdd detector detects a high voltage, thereby mitigating the potential drop of the bit line. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-257554 Summary of the Invention [Problem to be solved by the invention]

[0011] In technology that replaces the capacitance of the boost circuit with a variable capacitance that decreases as the power supply voltage increases, several structures have been proposed for this variable capacitance element, claiming that using a voltage-dependent variable capacitance can mitigate the potential drop in the bit line. However, there is no variable capacitance that has a capacitance of 0 when the maximum rated voltage is applied. This limits the upper limit of the voltage that can be applied to the LSI, which in turn reduces the operating frequency that can be achieved by applying a high voltage. In addition, assist operation occurs even in high voltage ranges where assist is not required, resulting in wasted power.

[0012] Furthermore, a technology that simultaneously operates a step-down circuit and a step-up circuit to mitigate potential drops on the bit line makes it possible to set the bit line so that it does not drop below Vss in the high-voltage range. However, this requires doubling the number of capacitance elements that occupy a large area of ​​the assist circuit, resulting in a larger area for the assist circuit. Furthermore, as in the first embodiment, assist operation is performed even in the high-voltage range where assist is not required, and the simultaneous operation of the step-down circuit and the step-up circuit results in a significant amount of wasted power.

[0013] The disclosed technology has been made in view of the above, and aims to provide a semiconductor memory device and a method for controlling a semiconductor memory device that prevent a decrease in reliability and saves power. [Means for solving the problem]

[0014] In one aspect of the semiconductor memory device and the control method for the semiconductor memory device disclosed herein, a memory element holds data. A bit line is connected to the memory element and inverts the data held by the memory element by dropping to a reference voltage. A first step-down circuit drops a bit line voltage, which is a voltage applied to the bit line, to a first predetermined value below the reference voltage. A control unit detects a voltage change based on a first output from a first inverter having a voltage-dependent generation delay and a second output from a second inverter having a voltage-dependent generation delay greater than that of the first inverter, and controls the amount of voltage drop of the bit line voltage by the first step-down circuit according to the detected amount of voltage change. [Effects of the Invention]

[0015] In one aspect, the present invention can prevent a decrease in reliability of memory cells and reduce power consumption. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a schematic diagram of an LSI. [Figure 2] FIG. 2 is a diagram illustrating the configuration of an SRAM according to an embodiment. [Figure 3] FIG. 3 is a diagram showing the voltage dependency of the gate delay when the voltage threshold value of the transistor is changed. [Figure 4] FIG. 4 is a diagram showing the relationship between the height of Vdd and the width of a negative pulse. [Figure 5] FIG. 5 is a diagram illustrating the operation waveforms of the signals in the SRAM according to the first embodiment. [Figure 6] FIG. 6 is a flowchart of a data rewrite process in the low voltage range in the SRAM according to the first embodiment. [Figure 7] FIG. 7 is a flowchart of a data rewrite process in the high voltage range in the SRAM according to the first embodiment. [Figure 8]FIG. 8 is a configuration diagram of an SRAM according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing an example of a dynamic gate. [Figure 10] FIG. 10 is a diagram showing the operating waveforms of the dynamic gate. [Figure 11] FIG. 11 is a diagram illustrating the operation waveforms of the signals in the SRAM according to the second embodiment. [Figure 12] FIG. 12 is a configuration diagram of an SRAM according to the third embodiment. [Figure 13] FIG. 13 is a diagram illustrating an operation waveform of the Vdd dependency generating circuit according to the third embodiment. [Figure 14] FIG. 14 is a diagram illustrating an operation waveform of the SRAM according to the third embodiment. [Figure 15] FIG. 15 is a configuration diagram of an SRAM according to the fourth embodiment. [Figure 16] FIG. 16 is a circuit diagram of the selector. [Figure 17] FIG. 17 is a configuration diagram including an LSI tester, a test circuit, and a pulse width setting circuit according to the fifth embodiment. [Figure 18] FIG. 18 is a configuration diagram of a test circuit according to the fifth embodiment. [Figure 19] FIG. 19 is a diagram showing an example of a circuit configuration of a flip-flop mounted on a test circuit. [Figure 20] FIG. 20 is a diagram showing an example of a test pattern in the fifth embodiment. [Figure 21] FIG. 21 is a timing diagram of a test pattern in the fifth embodiment. [Figure 22] FIG. 22 is a diagram showing an example of the test results in Example 5. [Figure 23] FIG. 23 is a diagram showing an example of the configuration of a pulse width setting circuit. [Figure 24] FIG. 24 is a flowchart of the operation of the test circuit and the pulse width setting circuit according to the fifth embodiment. [Figure 25] FIG. 25 is a configuration diagram of a pulse width setting circuit according to the sixth embodiment. [Figure 26]FIG. 26 is a flowchart of the operation of the test circuit and the pulse width setting circuit according to the sixth embodiment. [Figure 27] FIG. 27 is a diagram showing an example of the test results obtained in Example 6. [Figure 28] FIG. 28 is a configuration diagram of a pulse width setting circuit according to the seventh embodiment. [Figure 29] FIG. 29 is a flowchart of the operation of the test circuit and the pulse width setting circuit according to the seventh embodiment. [Figure 30] FIG. 30 is a configuration diagram including a test circuit and a pulse width setting circuit according to the eighth embodiment. [Figure 31] FIG. 31 is a diagram showing the configuration of the test and pulse width setting circuit. [Figure 32] FIG. 32 is a diagram showing an example of a pulse loss setting detection pattern. [Figure 33] FIG. 33 is a timing diagram of the pulse loss setting pattern. [Figure 34] FIG. 34 is a diagram showing changes in internal signals when a pulse loss detection pattern is run. [Figure 35] FIG. 35 is a flowchart of the test and operation of the pulse width setting circuit according to the eighth embodiment. [Figure 36] FIG. 36 is a flowchart of the operation of a system equipped with an SRAM according to the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the semiconductor memory device and the control method of the semiconductor memory device disclosed in the present application will be described in detail with reference to the drawings. Note that the semiconductor memory device and the control method of the semiconductor memory device disclosed in the present application are not limited to the following embodiments. [Example]

[0018] FIG. 1 is a schematic diagram of an LSI. LSI 1 is, for example, a processor. LSI 1 has multiple cores 2 and an L (Level) 2 cache 4. Core 2 is equipped with an L1 cache 3. L1 cache 3 and L2 cache 4 are equipped with multiple SRAMs 10. SRAM 10 is a semiconductor memory device. As shown in FIG. 1, SRAM 10 has a memory cell array 5. Furthermore, SRAM 10 has a work driver, a write / sense amplifier, and a decoder.

[0019] 2 is a diagram showing the configuration of an SRAM according to an embodiment. The SRAM 10 includes a memory cell 100, a write amplifier 101, a step-down circuit 102, and a Vdd dependency generating circuit 103. The SRAM 10 also includes a bit line Bit and a bit line / Bit. The bit line Bit and the bit line / Bit are connected to a connection node a via transistors T3 and T4, respectively. The SRAM 10 also includes a word line WL, input paths for a write enable signal WE and a write data signal WD, and an NMOS transistor T5. The drain of the NMOS transistor T5 is connected to the connection node a, and the source is connected to Vss.

[0020] The memory cell 100 is a storage element, and a plurality of memory cells 100 are mounted in the memory cell array 5 shown in Fig. 1. The memory cell 100 has transfers T1 and T2, a CMOS inverter INV2 having an output node D, and a CMOS inverter INV1 having an output node / D.

[0021] The output node / D of the CMOS inverter INV1 is connected to the transfer T1, and is connected to the bit line Bit via the transfer T1. The output node D of the CMOS inverter INV2 is connected to the transfer T2, and is connected to the bit line / Bit via the transfer T2. The input node of the CMOS inverter INV1 is connected to the output node D of the CMOS inverter INV2. Conversely, the input node of the CMOS inverter INV2 is connected to the output node / D of the CMOS inverter INV1.

[0022] The gates of the transfer transistors T1 and T2 are connected to the word line WL. Furthermore, the terminal opposite to the connection terminal of the CMOS inverter INV1 of the transfer transistor T1 is connected to the bit line Bit. Furthermore, the terminal opposite to the connection terminal of the CMOS inverter INV2 of the transfer transistor T2 is connected to the bit line / Bit.

[0023] The write amplifier 101 also includes AND circuits G1 and G3, an inverter G2, and NMOS transistors T3 and T4.

[0024] The NMOS transistor T3 has a source connected to the bit line Bit and a drain connected to the connection node a. The gate of the NMOS transistor T3 is connected to the output node of the AND circuit G1. The NMOS transistor T4 has a drain connected to the bit line / Bit and a source connected to the connection node a. The gate of the NMOS transistor T4 is connected to the output node of the AND circuit G3.

[0025] A write enable signal WE is input to one input terminal of each of the AND circuits G1 and G3. A write data signal WD is input to the other input terminal of the AND circuit G1. The output terminal of the inverter G2 is connected to the other input terminal of the AND circuit G3. The input terminal of the inverter G2 is also connected to the write data signal WD.

[0026] The step-down circuit 102 includes a buffer G4 and a coupling capacitor C1. The step-down circuit 102 is an example of a "first step-down circuit."

[0027] The input terminal of buffer G4 is connected to an ASSIST ENX terminal that outputs an assist signal for dropping the voltages of bit lines Bit and / Bit to a negative potential. The output terminal of buffer G4 is connected to coupling capacitor C1. The ASSIST ENX terminal is also connected to the gate of NMOS transistor T5.

[0028] The coupling capacitor C1 is connected to the path connecting the output terminal of the buffer G4 and the connection node a with the NMOS transistor T5.

[0029] The Vdd dependency generating circuit 103 includes an inverter chain 131, an inverter chain 132, and a NAND circuit 133. The inverter chain 131 is an example of a "first inverter." The inverter chain 132 is an example of a "second inverter."

[0030] One input terminal of the NAND circuit 133 is connected to the EN' terminal, which is the output terminal of the inverter chain 131. The other input terminal of the NAND circuit 133 is connected to the ENX' terminal, which is the output terminal of the inverter chain 132. The EN_NPLS terminal, which is the output terminal of the NAND circuit 133, is connected to the ASSIST ENX terminal.

[0031] Inverter chain 131 has gates whose delay has small voltage dependency arranged in series in an even number of stages. A small voltage dependency of delay means that the amount of delay that decreases as the voltage increases is small. Conversely, a large voltage dependency of delay means that the amount of delay that decreases as the voltage increases is large. Inverter chain 132 has gates whose gate delay has large voltage dependency arranged in series in an odd number of stages.

[0032] The voltage dependence of gate delay can be changed by, for example, the voltage threshold of a transistor, a circuit configuration such as stacking transistors, or a combination of these. Figure 3 shows the voltage dependence of gate delay when the voltage threshold of a transistor is changed. The horizontal axis of Figure 3 represents the power supply voltage (Vdd), and the vertical axis represents the delay variation. Graph 11 represents the delay variation of a transistor with a small delay voltage threshold. Graph 13 represents the delay variation of a transistor with a large delay voltage threshold. Graph 12 represents the delay variation of a transistor with a delay voltage threshold between those of Graphs 11 and 13.

[0033] As shown in graph 13, a transistor with a large voltage threshold has a large delay variation and is highly voltage-dependent. Conversely, as shown in graph 11, a transistor with a small voltage threshold has a small delay variation and is highly voltage-dependent.

[0034] Therefore, for example, in the inverter chain 131, by arranging many transistors with small voltage thresholds as shown in Fig. 3 in stages, the voltage dependency of the delay becomes small. Also, in the inverter chain 132, by arranging many transistors with large voltage thresholds as shown in Fig. 3 in stages, the voltage dependency of the delay becomes large.

[0035] When Vdd is in the low voltage range, the delay of inverter chain 132 is larger than the delay of inverter chain 131, and on the other hand, when Vdd is in the high voltage range, the number of gate stages is set so that the delay of inverter chain 132 is the same as or smaller than the delay of inverter chain 131.

[0036] Furthermore, a write enable signal WE is input to the EN terminals which are input terminals of the inverter chains 131 and 132.

[0037] When Vdd is in the low voltage range, the delay of the inverter chain 132 is larger than the delay of the inverter chain 131, so a negative pulse is generated from the EN_NPLS terminal when the EN terminal changes from L, which is the Vss level, to H, which is the Vdd level. Conversely, when Vdd is in the high voltage range, the delay of the inverter chain 132 is the same as or smaller than the delay of the inverter chain 131, so no negative pulse is generated from the EN_NPLS terminal even when the EN terminal changes from L, which is the Vss level, to H, which is the Vdd level.

[0038] FIG. 4 is a diagram showing the relationship between the magnitude of Vdd and the width of a negative pulse. Graphs 151 to 153 each show voltage on the vertical axis and time on the horizontal axis. Graph 151 shows the operating waveforms of each signal when Vdd is in the low voltage range. Graph 152 shows the operating waveforms of each signal when Vdd is in the medium voltage range between the low and high voltage ranges. Graph 153 shows the operating waveforms of each signal when Vdd is in the high voltage range. The relationship between the magnitude of Vdd and the negative pulse generated at the EN_NPLS terminal will now be described with reference to FIG. 4.

[0039] A waveform 161 represents a voltage change at the EN terminal of the Vdd dependency generation circuit 103. A waveform 162 represents a voltage change at the EN' terminal of the inverter chain 131. A waveform 163 represents a voltage change at the ENX' terminal of the inverter chain 132. A waveform 164 represents a voltage change at the EN_NPLS terminal of the NAND circuit 133.

[0040] The case where Vdd is in the low voltage region will be described. As shown in graph 151, at timing T11, the EN terminal changes from L to H. Thereafter, at timing T12, after a period T18, which is the delay of the inverter chain 131, has elapsed since timing T11, the EN' terminal changes from L to H, causing the EN_NLPS terminal of the NAND circuit 133 to change from H to L (step S1). In more detail, before timing T12, the EN' terminal is L and the ENX' terminal is H, so the EN_NLPS terminal of the NAND circuit 133 becomes H. Then, after timing T12, both the EN' terminal and the ENX' terminal are H, so the EN_NLPS terminal of the NAND circuit 133 becomes L.

[0041] In this case, the period T19, which is the delay from timing T11 of the inverter chain 132 with high voltage dependency, is longer than the period T18, which is the delay from timing T11 of the inverter chain 132 with low voltage dependency. Therefore, at timing T13, which is after timing T12 and after the period T19 has elapsed since timing T11, the ENX' terminal changes from H to L (step S2). This generates a negative pulse that is output from the EN_NLPS terminal. The processes represented by arrows in graphs 152 and 153 also correspond to the processes shown in graph 151.

[0042] When Vdd rises from the low voltage range to the medium voltage range, the delay times of both inverter chains 131 and 132 become shorter, as shown in graph 152. As a result, EN' changes from L to H at timing T14, which is before timing T12. Also, ENX' changes from H to L at timing T15, which is before timing T13. However, because the inverter chain 132 has a higher voltage dependency than the inverter chain 131, the delay of the inverter chain 132 is shortened to a greater extent than the delay of the inverter chain 131. Therefore, the interval between timing T14 and timing T15 becomes shorter than the interval between timing T12 and timing T13. In other words, the width of the negative pulse output from the EN_NLPS terminal becomes shorter.

[0043] If the voltage further increases and Vdd enters the high-voltage region, the delay time of both inverter chains 131 and 132 becomes even shorter, as shown in graph 153. As a result, the EN' terminal changes from L to H at timing T16, which is before timing T14. Also, the ENX' terminal changes from H to L at timing T17, which is before timing T15. However, the interval between timing T16 and timing T17 is even shorter than the interval between timing T14 and timing T15. In this case, the EN_NLPS terminal returns to H before it has completely fallen from H to L. For this reason, no negative pulse is generated, as shown in graph 153.

[0044] Continuing the explanation, returning to Fig. 2, the voltage at which no negative pulse is generated can be adjusted by changing the number of gate stages and the combination of voltage dependencies in the inverter chains 131 and 132.

[0045] Next, the operation of the SRAM 10 when writing data will be described. Before writing to the memory cell 100, the bit lines Bit and / Bit are precharged to H. The word line WL is L, and the write enable signal WE is L. The ASSIST EXT terminal is H. At this time, the outputs of the AND circuits G1 and G3 are L, the NMOS transistors T3 and T4 are off, and the NMOS transistor T5 is on. The connection node a then becomes L.

[0046] Data is written to memory cell 100 by changing the word line WL from L to H to turn on transistors T1 and T2 of memory cell 100, and then transitioning the write enable signal WE from L to H. At this time, NMOS transistor T3 or NMOS transistor T4 turns on depending on the data input by the write data signal WD, and either the bit line Bit or / Bit is pulled down to Vss. This forces the internal node of memory cell 100 to L, completing normal writing. For example, if the write data signal WD is set to H, NMOS transistor T3 turns on and the bit line Bit is pulled down to Vss.

[0047] When the write enable signal WE transitions from L to H, the EN terminal common to the inverter chains 131 and 132 of the Vdd dependency generating circuit 103 simultaneously transitions from L to H.

[0048] When Vdd is in the low voltage range, for example, around 0.5 V, the delay at the EN' terminal of the inverter chain 131 is faster than the delay at the ENX' terminal of the inverter chain 132, so an opposite-phase signal corresponding to the difference in delay is input to the NAND circuit 133. As a result, a negative pulse is generated at the ASSIST_ENX terminal, which is equal to the output of the EN_NPLS terminal of the NAND circuit 133. This negative pulse is generated with a delay of the delay time of the inverter chain 131 relative to the write enable signal WE. During the delay time of this negative pulse relative to the write enable signal WE, the normal write is completed by lowering the above-mentioned Bit to Vss.

[0049] The negative pulse generated at the ASSIST_EN terminal turns off the NMOS transistor T5 connecting the bit line Bit to Vss for the period during which the negative pulse keeps the voltage at L. As a result, the bit line Bit and the connection node a are disconnected from Vss while remaining at L, becoming floating and reaching the initial potential of 0V.

[0050] Next, immediately after turning off the NMOS transistor T5, the negative pulse drives the coupling capacitance C1 from H to L through the buffer G4. This causes the floating bit line Bit, which is at 0 V, to drop to a negative potential that is a predetermined voltage α (V) lower than Vss. That is, the bit line Bit receives the leading edge of the negative pulse and is boosted to a negative potential, which continues to pull the bit line Bit down to a negative potential for the duration of the pulse. This causes the internal nodes of the memory cell 100 to drop more strongly, allowing the SRAM 10 to ensure a write margin for the memory cell 100. The predetermined voltage α is determined by the capacitance ratio between the parasitic capacitances of the bit lines Bit and / Bit and the coupling capacitance C1. Then, the bit line Bit changes from L to H due to the trailing edge of the negative pulse and is reset to Vss.

[0051] The above describes operation in a low-voltage range, such as 0.5V. Next, we will explain what happens when the voltage increases from the low-voltage range. The voltage dependence of the delay of the inverter chain 132 is greater than that of the inverter chain 131. Therefore, as the voltage increases, the delay difference between the inverter chains 131 and 132 decreases. That is, the assist period, which is equal to the width of the negative pulse generated at the ASSIST ENX terminal, becomes shorter. Then, once the voltage reaches a certain level, the ASSIST ENX terminal no longer generates a negative pulse and remains fixed at H, eliminating the assist. Without the assist, the Vdd dependency generating circuit 103 and the step-down circuit 102 do not operate, so the bit line Bit never drops below Vss. Therefore, no negative pulse is generated at the ASSIST ENX terminal in a voltage range where assist is unnecessary, such as 0.9V. This prevents stress greater than the power supply voltage from being applied to the transfer T1 of the memory cell 100. Furthermore, unnecessary power consumption due to the assist can be reduced.

[0052] In the case of high voltage, unlike in the case of low voltage, the write operation margin is rarely insufficient even in CMOS, so the probability of memory cell 100 failure can be maintained at a low value without lowering the bit line Bit to a negative potential.

[0053] Fig. 5 is a diagram showing the operation waveforms of each signal in the SRAM according to the first embodiment. Next, with reference to Fig. 5, a description will be given of voltage changes of each signal when data is written in the semiconductor memory device according to the first embodiment. In this case as well, an example will be described in which data is written by setting the write data signal WD to H, turning on the NMOS transistor T3, and pulling down the bit line Bit to Vss.

[0054] Graphs 211 to 213 in Fig. 5 each represent voltage on the vertical axis and time on the horizontal axis. Graph 211 represents the operating waveforms of each signal when Vdd is in the low voltage range. Graph 212 represents the operating waveforms of each signal when Vdd is in the medium voltage range between the low and high voltage ranges. Graph 213 represents the operating waveforms of each signal when Vdd is in the high voltage range.

[0055] In Figure 5, waveform 201 represents the voltage change of the write enable signal WE. Waveform 202 represents the voltage change at the ASSIST ENX terminal. Waveform 203 represents the voltage change of the bit line Bit. Waveform 204 represents the voltage change of the output node D. Waveform 205 represents the voltage waveform of the output node / D. Potential 200 represents Vss, which is the reference for each node of the bit line Bit, output node D, and output node / D.

[0056] The operating waveforms of each signal when Vdd is in the low voltage range, as shown in graph 211, will be described. When writing data, the write enable signal WE changes from L to H, as shown in waveform 201 (step S3). In response, the bit line Bit changes from H to L, as shown in waveform 203 (step S4). When the bit line Bit changes to L, the output node D, which is an internal node of the cell, is pulled down to L, as shown in waveform 204 (step S5).

[0057] At this time, as shown in waveform 202, the ASSIST ENX terminal changes from H to L (step S6). Then, during period L1, the ASSIST ENX terminal is L and then changes to H (step S7). This voltage change at the ASSIST ENX terminal generates a negative pulse with a pulse width of period L1. The bit line Bit receives the leading edge of the negative pulse and is boosted to a negative potential α as shown in waveform 203 (step S8). This more strongly pulls down the internal node of the memory cell 100. The bit line Bit maintains a negative potential for the pulse width period L1. Then, the bit line Bit changes from L to H due to the trailing edge of the negative pulse and is reset to Vss (step S9). Then, the D signal returns from the negative voltage state to Vss (step S10) and maintains L. This completes the data write to the memory cell 100.

[0058] Furthermore, as shown in graph 212, when Vdd rises from the low voltage range to the medium voltage range, the delay difference between inverter chain 131 and inverter chain 132 is reduced. This shortens assist period L1, which is the width of the negative pulse generated at the ASSIST ENX terminal. Although assist period L1 is shortened, in this case too, the bit line Bit is pulled down to a negative potential α, as shown in waveform 203 of graph 212, and accordingly, the output node D, which is an internal node of the cell, is also pulled down to a negative potential α, as shown in waveform 204 of graph 212. This allows for more powerful programming of memory cell 100.

[0059] In contrast, as shown in graph 213, when Vdd enters the high voltage range, the delay difference between inverter chain 131 and inverter chain 132 becomes smaller. As a result, as shown in waveform 202 of graph 213, the assist period L1, which is the width of the negative pulse generated at the ASSIST ENX terminal, disappears. Furthermore, when Vdd becomes higher, the voltage drop that occurred in waveform 202 also disappears, and the ASSIST ENX terminal is fixed at H. In this case, as shown in waveform 203 of graph 213, the bit line Bit falls to Vdd, but is not pulled down to a lower negative potential.

[0060] In this way, Vdd dependency generating circuit 103 is an example of a "control unit" that detects the power supply voltage based on the first output from a first inverter having a voltage-dependent generation delay and the second output from a second inverter having a voltage-dependent generation delay greater than that of the first inverter, and controls the amount by which the bit line voltage is lowered by the first step-down circuit according to the detected amount of power supply voltage. More specifically, Vdd dependency generating circuit 103 causes step-down circuit 102 to lower the bit line to a negative potential α, which is a first predetermined value, for a period corresponding to the difference between the timing of the first output in response to input of a predetermined signal to the EN terminal and the timing of the second output in response to input of the same predetermined signal.

[0061] 6 is a flowchart of a data rewrite process in a low voltage range in the SRAM according to the first embodiment. Next, the flow of a data rewrite process in a low voltage range in the SRAM 10 according to the present embodiment will be described with reference to FIG. 6. Here, the case where writing is performed by lowering the voltage of the bit line Bit will be described.

[0062] The word line WL changes from L to H, and the transfers T1 and T2 of the memory cell 100 are turned on (step S101).

[0063] Then, the write enable signal WE transitions from L to H (step S102).

[0064] Next, data is input by the write data signal WD (step S103).

[0065] In response to the input of the write data signal WD, the NMOS transistor T3 is turned on, and the bit line Bit is pulled down to Vss (step S104).

[0066] When the write enable signal WE transitions from L to H, the EN terminal common to the inverter chains 131 and 132 of the Vdd dependency generating circuit 103 simultaneously transitions from L to H (step S105).

[0067] Next, the EN' terminal of the inverter chain 131 transitions from L to H (step S106).

[0068] Next, the EN_NPLS terminal changes from H to L, and the leading edge of a negative pulse is generated at the ASSIST_EN terminal (step S107).

[0069] The negative pulse generated at the ASSIST_EN terminal turns off the NMOS transistor T5 connecting the bit line Bit to Vss. Furthermore, the negative pulse drives the coupling capacitor C1 from H to L through the buffer G4. As a result, the bit line Bit, which is floating at 0 V, is further pulled down to a negative potential that is a predetermined voltage lower than Vss (step S108).

[0070] Thereafter, the ENX' terminal transitions from H to L with a delay corresponding to the difference in delay between the inverter chain 131 and the inverter chain 132 (step S109).

[0071] Next, the EN_NPLS terminal transitions from L to H, and a trailing edge of a negative pulse occurs at the ASSIST_EN terminal (step S110).

[0072] Then, the bit line Bit is reset to Vss upon receiving a change from L to H due to the trailing edge of the negative pulse (step S111).

[0073] 7 is a flowchart of a data rewrite process in a high voltage range in the SRAM according to the first embodiment. Next, the flow of a data rewrite process in a high voltage range in the SRAM 10 according to the present embodiment will be described with reference to FIG. 7. Here, too, a case where writing is performed by lowering the voltage of the bit line Bit will be described.

[0074] The word line WL changes from L to H, and the transfers T1 and T2 of the memory cell 100 are turned on (step S121).

[0075] Then, the write enable signal WE transitions from L to H (step S122).

[0076] Next, data is input by the write data signal WD (step S123).

[0077] In response to the input of the write data signal WD, the NMOS transistor T3 is turned on, and the bit line Bit is pulled down to Vss (step S124).

[0078] When the write enable signal WE transitions from L to H, the EN terminal common to the inverter chains 131 and 132 of the Vdd dependency generating circuit 103 simultaneously transitions from L to H (step S125).

[0079] Next, the EN' terminal of the inverter chain 131 transitions from L to H (step S126).

[0080] In the high voltage region, the difference in delay between the inverter chain 131 and the inverter chain 132 is small, so the ENX' terminal transitions from H to L before the EN_NPLS terminal transitions from H to L (step S127). As a result, the bit line Bit is not lowered to a negative potential and remains at Vss.

[0081] As described above, in the semiconductor memory device of this embodiment, when Vdd is a low voltage, the voltage of the bit line is dropped to a negative potential lower than Vss when writing data, and when Vdd is a high voltage, the voltage of the bit line is dropped to Vss when writing data.

[0082] For example, in a technology that replaces the capacitance of a boost circuit with a variable capacitance that decreases as the power supply voltage increases, the assist circuit operates in any voltage range, so wasteful power is generated in areas where no defects occur even without assistance. Also, when the maximum rated voltage is applied to a memory cell, the assist circuit applies a voltage above the maximum rated voltage to the memory cell, causing performance degradation and reliability problems.

[0083] In contrast, with the semiconductor memory device according to this embodiment, write assist is automatically and completely canceled at high voltages, thereby reducing degradation of memory cells. Furthermore, with the semiconductor memory device according to this embodiment, the operating voltage can be freely set as long as it is equal to or lower than the maximum rated voltage. Therefore, by using the semiconductor memory device according to this embodiment, the operating speed range can be maximized in the DVFS method, and the power efficiency of the LSI can be improved. Furthermore, it is possible to reduce wasted power due to unnecessary assist.

[0084] Furthermore, in a technology that alleviates the potential drop of the bit line by simultaneously operating a voltage step-down circuit and a voltage step-up circuit, it is possible to completely cancel write assist in the high voltage range, but to achieve this, the voltage step-down circuit and the voltage step-up circuit are operated simultaneously.

[0085] In contrast, in the semiconductor memory device according to this embodiment, the step-down circuit can be stopped, so the capacitance element that occupies most of the area of ​​the assist circuit can be kept small, and the wasted power required to cancel the assist in the high-voltage range can be reduced. Furthermore, in the semiconductor memory device according to this embodiment, the amount of assist can be automatically changed in stages, so the increase in power due to the assist can be minimized.

[0086] Furthermore, although it is possible to control the write assist circuit of the installed memory from a processor or the like, this increases the development costs for the logic design, implementation, signal distribution, and timing design required for this. In contrast, in the case of the semiconductor memory device according to this embodiment, by using memory cells with built-in write assist, LSI designers can freely set DVFS and the like while keeping development costs down. [Example]

[0087] 8 is a configuration diagram of an SRAM according to a second embodiment. The SRAM 10 according to this embodiment differs from the first embodiment in that the SRAM 10 maintains the assist of dropping the bit line Bit to a negative potential for a certain period of time. The SRAM 10 according to this embodiment further includes an inverter G5 and a dynamic gate 104. In the following description, the functions of the same parts as those in the first embodiment will not be described.

[0088] A write enable signal WE is input to an EN terminal, which is an input terminal, of the Vdd dependency generating circuit 103. Also, an EN_NPLS terminal, which is an output terminal of a negative pulse, of the Vdd dependency generating circuit 103 is connected to the input of an inverter G5.

[0089] The inverter G5 generates a trg signal by converting the negative pulse output from the Vdd dependency generating circuit 103 into a positive pulse. The inverter G5 then inputs the trg signal to the EN terminal of the dynamic gate 104.

[0090] The dynamic gate 104 has two input terminals, a PC terminal and an EN terminal, and an output terminal, an OUT terminal. The PC terminal of the dynamic gate 104 is connected to a precharge line PC to which a control command is output. The OUT terminal of the dynamic gate 104 is connected to an ASSIST ENX terminal.

[0091] 9 is a circuit diagram showing an example of a dynamic gate. The PC terminal of the dynamic gate 104 extends from the gate of a P-channel FET switch connected to Vdd. The EN terminal of the dynamic gate 104 extends from the gate of an N-channel FET switch arranged between the FET switch connected to the PC terminal and Vss. The connection point between the FET switch connected to the PC terminal and the FET switch connected to the EN terminal is connected to the OUT terminal, with an H keeper 141 arranged between them.

[0092] Figure 10 shows the operating waveforms of the dynamic gate. The vertical axis of Figure 8 represents voltage, and the horizontal axis represents the passage of time. Graph 21 represents the waveform of the input signal to the PC terminal, graph 22 represents the waveform of the input signal to the EN terminal, and graph 23 represents the waveform of the output signal from the OUT terminal.

[0093] As shown in graph 22, when the trg signal input to the EN terminal of the dynamic gate 104 is in a low state, a negative pulse having a width of period T21 is input to the PC terminal from the precharge line PC as shown in graph 21. As a result, the output from the OUT terminal of the dynamic gate 104 is precharged to high during period T22, which corresponds to period T21, as shown in graph 23. Even after period T21 has elapsed and the PC terminal of the dynamic gate 104 returns to high, the H keeper 141 continues to hold the output from the OUT terminal at high for period T23, as shown in graph 23. After this, the trg signal input to the EN terminal changes to high, ending period T23, and the output from the OUT terminal of the dynamic gate 104 changes from high to low. Then, when a negative pulse is input from the precharge line PC in the next cycle, the output from the OUT terminal of the dynamic gate 104 is reset to high, and the operation shown in FIG. 10 is repeated. This dynamic gate 104 is an example of a "holding circuit." The period T23 is an example of a "predetermined period."

[0094] FIG. 11 is a diagram showing the operating waveforms of each signal in the SRAM according to the second embodiment. Next, with reference to FIG. 11, the operation of the SRAM 10 according to this embodiment will be described. In each of graphs 221 to 223 in FIG. 11, the vertical axis represents voltage and the horizontal axis represents the passage of time. Graph 221 represents the operating waveforms of each signal when Vdd is in the low voltage range. Graph 222 represents the operating waveforms of each signal when Vdd is in the medium voltage range between the low voltage range and the high voltage range. Graph 223 represents the operating waveforms of each signal when Vdd is in the high voltage range.

[0095] Prior to the transition of the write enable signal WE from L to H, a negative pulse is applied to the PC terminal of the dynamic gate 104, the output from the OUT terminal is reset to H, and the ASSIST ENX terminal changes from L to H (step S21). Next, when the write enable signal WE changes from L to H, the bit line Bit is dropped to Vss. Furthermore, if Vdd is a low voltage, when the write enable signal WE changes from L to H, the Vdd dependency generating circuit 103 generates a negative pulse (step S22). The inverter G5 converts the negative pulse output from the Vdd dependency generating circuit 103 into a positive pulse to generate a trg signal, which is input to the EN terminal of the dynamic gate 104 (step S23). When the trg signal is input to the EN terminal of the dynamic gate 104, the output from the OUT terminal changes from H to L (step S24). As a result, the ASSIST ENX terminal changes from H to L, and the bit line Bit is driven to a negative potential (step S25). The processes indicated by arrows in graph 222 correspond to the processes described in graph 221. Furthermore, the processes indicated by arrows in graph 223 correspond to the processes of steps S21 to S23 in graph 221.

[0096] As Vdd increases, the trg signal input to the EN terminal becomes thinner, as shown in graph 222. When the voltage further increases and Vdd reaches a high voltage range, the Vdd dependency generating circuit 103 does not generate a negative pulse and the trg signal also becomes smaller, so the bit line Bit does not become a negative potential lower than Vss.

[0097] As described above, in the semiconductor memory device according to this embodiment, when Vdd is a low voltage, the ASSIST ENX terminal transitions from H to L and then maintains L until it is reset by an input signal from the precharge PC in the next cycle. During the period when the ASSIST ENX terminal is maintained at L, the bit line remains at a negative potential. Since the semiconductor memory device according to the first embodiment provides assistance only during the pulse width, it is preferable to increase the amount of bit line pull-down to a certain extent for sufficient assistance. In contrast, the semiconductor memory device according to this embodiment can extend the assistance period, allowing the assistance strength to be relatively small. Therefore, the assist capacitance can be reduced, thereby reducing the area and power consumption of the assist circuit.

[0098] Furthermore, in the semiconductor memory device according to this embodiment, the assist is completely released in the high voltage range, so that a voltage up to the maximum rated value can be applied to the SRAM without being restricted by the withstand voltage of the memory cell. Furthermore, in the semiconductor memory device according to this embodiment, the operation of the step-down circuit itself is suppressed by releasing the assist. Therefore, power consumption can be kept low in the voltage range. [Example]

[0099] 12 is a configuration diagram of an SRAM according to Example 3. The SRAM 10 according to Example 3 differs from Example 2 in that the amount of step-down of the bit line Bit is changed depending on the voltage. In the following explanation, the functions of each unit that have already been explained will not be explained again.

[0100] The Vdd dependency generating circuit 103 according to this embodiment has two outputs, each with a different voltage at which no output pulse is generated. The Vdd dependency generating circuit 103 includes an inverter chain 134 in addition to the inverter chains 131 and 132. The Vdd dependency generating circuit 103 also includes a NAND circuit 135 in addition to the NAND circuit 133.

[0101] The inverter chain 134 has gates, each having a transistor whose gate delay is highly dependent on voltage, arranged in series in an even number of stages. In other words, the inverter chain 134 has a delay that is highly dependent on voltage. The input terminal of the inverter chain 134 is connected to the output terminal of the inverter chain 132. In addition, the ENX'' terminal, which is the output terminal of the inverter chain 134, is connected to one input terminal of the NAND circuit 135. This inverter chain 134 is an example of a "third inverter."

[0102] One input terminal of the NAND circuit 135 is connected to the ENX″ terminal which is the output terminal of the inverter chain 134. The other input terminal of the NAND circuit 135 is connected to the EN′ terminal which is the output terminal of the inverter chain 131.

[0103] Here, the output terminal of the NAND circuit 133 is called an EN_NPLS1 terminal, and the output terminal of the NAND circuit 135 is called an EN_NPLS2 terminal.

[0104] The input terminal of the inverter G5 is connected to the EN_NPLS1 terminal which is the output terminal of the NAND circuit 133. The input terminal of the inverter G7 is connected to the EN_NPLS2 terminal which is the output terminal of the NAND circuit 135. Here, the output signal of the inverter G5 is called the trg1 signal, and the output signal of the inverter G7 is called the trg2 signal.

[0105] The dynamic gate 104A has an EN terminal to which the trg1 signal output from the inverter G5 is input. The dynamic gate 104B has an EN terminal to which the trg2 signal output from the inverter G7 is input. The PC terminals of both the dynamic gates 104A and 104B are connected to a precharge line PC. The OUT terminal, which is the output terminal of the dynamic gate 104A, is connected to the ASSIST ENX1 terminal. The OUT terminal, which is the output terminal of the dynamic gate 104B, is connected to the ASSIST ENX2 terminal.

[0106] The step-down circuit 102A includes a buffer G4 and a coupling capacitor C1. The input terminal of the buffer G4 is connected to the ASSIST ENX1 terminal. The output terminal of the buffer G4 is connected to the coupling capacitor C1. The coupling capacitor C1 is connected between the connection node a and the NMOS transistor T5.

[0107] The step-down circuit 102B has a buffer G6 and a coupling capacitor C2. The input terminal of the buffer G6 is connected to the ASSIST ENX2 terminal. The output terminal of the buffer G6 is connected to the coupling capacitor C2. The coupling capacitor C2 is connected between the connection node a and the NMOS transistor T5. The ASSIST ENX2 terminal is connected to the gate of the NMOS transistor T5. These step-down circuits 102A and 102B are examples of a "first step-down circuit" and a "second step-down circuit."

[0108] As described above, the SRAM 10 of this embodiment is provided with two sets of control circuits, namely, the step-down circuits 102A and 102B and their control circuits, the dynamic gates 104A and 104B, each of which is connected to one of the two output terminals of the Vdd dependency generating circuit 103.

[0109] The operation of the SRAM 10 according to this embodiment will now be described. When Vdd is in the low voltage range, both step-down circuits 102A and 102B operate. As Vdd voltage increases, step-down circuit 102A stops, and eventually both step-down circuits 102A and 102B stop operating. While two sets of control circuits have been described here, it is also possible to have three or more sets of control circuits, each including a step-down circuit 102 and a dynamic gate 104. When there are multiple control circuits, all step-down circuits 102 operate when Vdd is in the low voltage range. As Vdd increases, the number of operating step-down circuits 102 decreases, and eventually all step-down circuits 102 stop operating.

[0110] 13 is a diagram showing the operation waveforms of the Vdd dependency generating circuit according to the third embodiment. In each of graphs 301 to 303 in FIG. 13, the vertical axis represents voltage and the horizontal axis represents the passage of time. Graph 301 represents the operation waveforms of each signal when Vdd is in the low voltage range. Graph 302 represents the operation waveforms of each signal when Vdd is in the medium voltage range between the low voltage range and the high voltage range. Graph 303 represents the operation waveforms of each signal when Vdd is in the high voltage range.

[0111] The NAND circuit 135 receives the output from the EN' terminal and the output from the ENX" terminal of the inverter chain 134. Then, the NAND circuit 135 outputs a signal from the EN_NPLS2 terminal. At the timing when the output from the EN' terminal changes to H, both the EN_NPSL1 terminal and the EN_NPSL2 terminal are dropped to L (step S31). At the timing when the ENX' terminal changes to L, the EN_NPSL1 terminal returns to H (step S32). At the timing when the ENX" terminal changes to L, the EN_NPSL2 terminal returns to H (step S33).

[0112] The processes indicated by the arrows in graph 302 correspond to the processes in graph 301. The processes indicated by the arrows in graph 303 correspond to the processes in steps S31 and S33 in graph 301.

[0113] The ENX'' terminal has a larger delay than the ENX' terminal due to the delay caused by the inverter chain 134, so the negative pulse generated at the EN_NPLS2 terminal is wider than the negative pulse generated at the EN_NPLS1 terminal. Therefore, when Vdd is in the low voltage range, negative pulses are generated at both the EN_NPLS1 terminal and the EN_NPLS2 terminal, as shown in graph 301. Furthermore, as the voltage of Vdd is increased, the negative pulse at the EN_NPLS1 terminal disappears, as shown in graph 302, and the negative pulse generated at the EN_NPLS2 terminal remains. When the voltage of Vdd is further increased and reaches the high voltage range, negative pulses no longer occur at either the EN_NPLS1 terminal or the EN_NPLS2 terminal, as shown in graph 303.

[0114] Here, if the potential required for writing at the assumed minimum voltage is Vss-2α and the capacitance required to generate that potential is C, then coupling capacitances C1 and C2 are set so that their sum is C. By adjusting the number of stages and voltage dependency of the delay of each inverter chain 131, 132, and 134 that make up the Vdd dependency generating circuit 103, the width of each negative pulse can be adjusted, and the voltage at which each negative pulse disappears can be adjusted. For example, it is possible to adjust the voltage so that when writing becomes possible at Vss-α, the generation of pulses at the EN_NPLS1 terminal stops.

[0115] 14 is a diagram showing the operation waveforms of the SRAM according to the third embodiment. In each of graphs 301 to 303 in FIG. 14, the vertical axis represents voltage and the horizontal axis represents the passage of time. Graph 311 represents the operation waveforms of each signal when Vdd is in the low voltage range. Graph 312 represents the operation waveforms of each signal when Vdd is in the medium voltage range between the low voltage range and the high voltage range. Graph 313 represents the operation waveforms of each signal when Vdd is in the high voltage range.

[0116] When Vdd is in the low voltage range, as shown in graph 311, a PC signal is input from the precharge line PC to the dynamic gates 104A and 104B, and both the ASSIST_ENX1 terminal and the ASSIST_ENX2 terminal change to H (step S34). Thereafter, a trg1 signal is input to the dynamic gate 104A, and the OUT terminal changes to H, causing the ASSIST_ENX1 terminal to change from L to H (step S35). Similarly, a trg2 signal is input to the dynamic gate 104B, and the OUT terminal changes to H, causing the ASSIST_ENX2 terminal to change from L to H (step S36). As a result, both the step-down circuits 102A and 102B operate to pull down the bit line Bit to Vss-2α (step S37).

[0117] The processes indicated by the arrows in graph 312 correspond to steps S34, S36, and S37 in graph 311. The processes indicated by the arrows in graph 313 correspond to step S34 in graph 311.

[0118] When the Vdd voltage is increased to Vss-α, at which writing becomes possible, the generation of negative pulses at the EN_NPLS1 terminal stops and the trg1 signal disappears, as shown in graph 312. In this case, the operation of the step-down circuit 102A stops, while the operation of the step-down circuit 102B continues, lowering the bit line Bit to Vss-α.

[0119] When Vdd reaches a high voltage range and becomes a voltage at which writing is possible at Vss, the generation of negative pulses at the EN_NPLS2 terminal also stops, and the trg2 signal disappears, as shown in graph 313. In this case, both the step-down circuits 102A and 102B stop operating, and the bit line Bit is pulled down to Vss.

[0120] As explained above, in the semiconductor memory device according to this embodiment, the amount of step-down of the bit line voltage changes stepwise depending on the voltage level. This reduces wasted power and reduces the voltage applied to the memory cell, minimizing degradation. Furthermore, although the explanation has been given here for a case in which there are two sets of Vdd dependency generating circuits and step-down circuits, the effect can be enhanced by increasing the number of sets.

[0121] Furthermore, in the above description, a case where a dynamic gate is used has been described, but a similar configuration can also be incorporated into the configuration of the first embodiment which does not use a dynamic gate. [Example]

[0122] Next, a fourth embodiment will be described. The SRAM 10 according to this embodiment differs from the second embodiment in that it can adjust the voltage at which no drive pulse is generated from the step-down circuit 102. In the following description, the functions of the components already described will not be described.

[0123] In the Vdd dependency generating circuit 103 according to this embodiment, the voltage at which the step-down circuit 102 no longer generates a drive pulse is adjusted by an external signal. In the Vdd dependency generating circuit 103, either or both of the number of stages of the inverter chain 131, which has low voltage dependency and determines the leading edge of the negative pulse, and the number of stages of the inverter chain 132, which has high voltage dependency and determines the trailing edge of the negative pulse, are switched externally. This changes the width of the negative pulse output by the Vdd dependency generating circuit 103, and as a result, the voltage at which the pulse disappears is adjusted.

[0124] FIG. 15 is a configuration diagram of an SRAM according to a fourth embodiment. FIG. 15 shows an example in which the number of stages of inverter chain 132, which has a large voltage dependency, is adjusted in three stages. Vdd dependency generating circuit 103 according to this embodiment includes inverter chains 136 and 137 in addition to inverter chains 131 and 132. These inverter chains 136 and 137 are an example of a "fourth inverter." Vdd dependency generating circuit 103 also includes selectors 401 to 403. Vdd dependency generating circuit 103 also includes a NAND circuit 133.

[0125] 16 is a circuit diagram of a selector. Selectors 401 to 403 are turned on when the signal input to their SEL terminals is H and turned off when the signal is L. For example, the input to the SEL terminals of selectors 401 to 403 may be a 3-bit signal SEL[0:2]. In this case, when a signal in which the input of the selector of the stage to be selected among SEL[0:2] is H and the inputs of the others are L is input to selectors 401 to 402, Vdd dependency generation circuit 103 switches the width of the negative pulse, i.e., the voltage at which the negative pulse disappears.

[0126] An example of setting the width of a negative pulse will be described. Here, of the 3-bit signal SEL[0:2], the signal input to selector 401 is SEL[0], the signal input to selector 402 is SEL[1], and the signal input to selector 401 is SEL[2]. The width of the negative pulse output by Vdd dependency generation circuit 103 is determined by selecting one of selectors 401-403 whose SEL terminal is set to H. Therefore, the total number of stages of inverter chains 132 and 136 selected when SEL[1] is set to H is set to a value calculated using the median value of manufacturing variations. Furthermore, the number of stages of inverter chain 132 selected when SEL[0] is set to H is smaller than the number of stages when SEL[1] is set to H. Furthermore, the number of stages of inverter chain 137 selected when SEL[2] is set to H is larger than the number of stages when SEL[1] is set to H.

[0127] In this case, if the voltage at which the assist should be cancelled deviates from the central value due to manufacturing variations, and the assist is cancelled even though the voltage is still suitable for assisting, the pulse width is widened by setting SEL[2] to H. If the assist is not cancelled even though no assist is required, the pulse width is narrowed by setting SEL[0] to H. In this way, by selecting the selectors 401 to 403, the SRAM 10 according to this embodiment can achieve appropriate assist even if manufacturing variations occur. [Example]

[0128] Next, a fifth embodiment will be described. When using the SRAM 10 shown in the fourth embodiment, which is capable of adjusting the release voltage of the assist, it is preferable to correct the release voltage if it deviates from the center value due to manufacturing variations. Therefore, in this embodiment, a test is performed using a test circuit 50 equipped with a replica of the SRAM 10, and if the release voltage deviates from the center value due to manufacturing variations, an adjustment amount for correcting this is determined and reflected in the actual SRAM 10. In the following description, the functions of each part that have already been described will not be described.

[0129] 17 is a configuration diagram including an LSI tester, a test circuit, and a pulse width setting circuit according to Example 5. In this example, an LSI tester 53, a test circuit 50, and a pulse width setting circuit 51 are provided. Here, the SRAM 10 has the configuration shown in FIG.

[0130] When using the SRAM 10 described in the fourth embodiment, if the release voltage deviates from the center value due to manufacturing variations, the LSI tester 53, test circuit 50, and pulse width setting circuit 51 adjust the assist timing to correct this. The test circuit 50 checks the pulse loss voltage of the Vdd dependency generation circuit 103 built into the SRAM 10, i.e., the deviation of the assist release voltage from the center value. The pulse width setting circuit 51 also stores the optimal pulse width setting determined from the test results by the test circuit 50 and distributes this value to the SEL terminals of the selectors 401 to 403 of the Vdd dependency generation circuit 103 of the SRAM 10 shown in FIG. 15.

[0131] The LSI tester 53 controls various tests on the LSI 1. For example, the LSI tester 53 controls tests on the SRAM 10 performed by the test circuit 50 and the pulse width setting circuit 51.

[0132] 18 is a configuration diagram of a test circuit according to a fifth embodiment. As shown in FIG. 18, the test circuit 50 includes a Vdd dependency generator circuit replica 501, which is obtained by making minimal circuit changes and minimal layout changes to the Vdd dependency generator circuit 103 built into the SRAM 10 shown in FIG. 15. By using the Vdd dependency generator circuit replica 501, it is possible to minimize the difference in characteristics between the test circuit 50 and the Vdd dependency generator circuit 103 of the SRAM 10. The test circuit 50 also includes NAND circuits 511 and 512, inverters 513-515, dynamic gates 516-518, and flip-flops 521-523.

[0133] The Vdd dependency generating circuit replica 501 has an inverter chain 502 whose delay has small voltage dependency and inverter chains 503 to 505 whose delay has large voltage dependency. The inverter chains 502, 504, and 505 have even stages, while the inverter chain 502 has odd stages. The leading edge of the negative pulse to be generated is determined by a signal from the EN' terminal of the inverter chain 502. The trailing edge of the negative pulse to be generated is determined by signals output from the ENX'0 terminal, ENX'1 terminal, and ENX' terminal of the inverter chains 503 to 505.

[0134] Furthermore, the Vdd dependency generating circuit replica 501 has selectors 506 to 508 and a NAND circuit 509. The selectors 506 to 508 have, for example, the circuit configuration shown in Fig. 14. The test circuit 50 having this Vdd dependency generating circuit replica 501 is an example of a "test execution unit."

[0135] Here, the Vdd dependency generation circuit 103 shown in FIG. 15 generates one negative pulse by switching the connections of the output terminals of the inverter chains 132, 136, and 137 using selectors 506-508 and inputting the result to one NAND circuit 133. In contrast, the Vdd dependency generation circuit replica 501 has an EN' terminal connected in common to one input terminal of NAND circuits 509, 511, and 512. Furthermore, an ENX'0 terminal is connected to the other input terminal of NAND circuit 509, an ENX'1 terminal is connected to the other input terminal of NAND circuit 511, and an ENX'2 terminal is connected to the other input terminal of NAND circuit 512. As a result, the NAND circuits 509, 511, and 512 generate three negative pulses with different widths. It is desirable that the NAND circuits 509, 511, and 512 have the same shape. The outputs of the NAND circuits 509, 511 and 512 are converted into positive pulses by the inverters 513-515, respectively, and input to the dynamic gates 516-518.

[0136] The dynamic gates 516 to 518 have, for example, the circuit configuration shown in Fig. 9. The signals S[2:0] output from the dynamic gates 516 to 518 are input to data terminals of flip-flops 521 to 523, which are positive edge triggered D-type flip-flops equipped with a scan function. The flip-flop 521 has, for example, the circuit configuration shown in Fig. 19. Fig. 19 is a diagram showing an example of the circuit configuration of a flip-flop mounted on a test circuit.

[0137] FIG. 20 is a diagram showing an example of a test pattern in the fifth embodiment. FIG. 21 is a timing diagram of the test pattern in the fifth embodiment. The operation of the test circuit 50 will be described with reference to FIGS. 20 and 21. In pattern #0, a negative pulse on the precharge line PC indicated by "N" in FIG. 20 causes the PC terminals of the dynamic gates 516 to 518 to change as shown in FIG. 19. As a result, the signals S[2:0] output from the dynamic gates 516 to 518 are precharged to H. Then, the signals S[2:0] precharged to H are taken in from the D terminals of the flip-flops 521 to 523 by a positive pulse on the CLK terminals of the flip-flops 521 to 523 indicated by "P" in FIG. 20, and all are initialized to H. Next, in test pattern #1, the EN terminal of the inverter chain 502 of the Vdd dependency generation circuit replica 501 changes from L to H. As a result, as shown in FIG. 19, negative pulses are generated at the outputs of NAND circuits 509, 511, and 512 according to the voltage. The negative pulses are inverted by inverters 513-515 and input to the EN terminals of dynamic gates 516-518. At this time, the outputs of the dynamic gates 516-518 that generated pulses change from H to L. The results of the pulse generation from the dynamic gates 516-518 are captured into each of flip-flops 521-523 by a positive pulse at each of their CLK terminals shown in FIG. 21. Next, in patterns #2 and #3, the SM terminals of each of flip-flops 521-523 are set to 1 as shown in FIG. 21, and the flip-flops 521-523 enter scan shift mode. Then, each time a positive pulse is input to the CLK terminal of each of the flip-flops 521-523, the flip-flops 521-523 sequentially output the captured pulse generation results from their SO terminals. By repeating the above test while changing the voltage, the test circuit 50 can obtain the number of stages in the inverter chains 503 to 505 at which the negative pulse output by the Vdd dependency generating circuit replica 501 disappears. In other words, the test circuit 50 can obtain the correlation between the settings of SEL[2:0] of the selectors 506 to 508 and the voltage.

[0138] FIG. 22 shows an example of test results in Example 5. FIG. 22 shows a table listing the values ​​of the signals S[2:0] output from the dynamic gates 516-518 when the test pattern #1 was run at each voltage, dividing the measurement voltage into nine stages V[0:8] from the minimum voltage Vmin to Vmax. In the table of FIG. 20, an output L indicates that a pulse was generated, and an output H indicates that a pulse was not generated. The maximum voltage at which assistance is desirable is a standard value provided by the semiconductor manufacturer based on the number of memory cells 100 and manufacturing variations. Here, the maximum voltage at which assistance is desirable is V[2], two steps higher than Vmin. In other words, range 541 is the voltage range at which assistance is desirable. The minimum voltage at which assistance is not desirable is the maximum rated voltage specified by the semiconductor manufacturer minus the potential difference by which the bit line Bit is lowered below Vss due to assistance. Here, the minimum voltage at which assistance is not desirable is V[6], two steps lower than Vmax. That is, range 542 is a voltage range where no assistance is performed.

[0139] In this case, the setting for assist is preferably one in which the test result is L in the voltage range V[2:0] and H in the voltage range V[8:6]. In this example of test results, signals S[0] and S[1] satisfy this condition. However, as the voltage rises, the earlier the assist is released, the less power consumption and stress on the elements will be, so signal S[0] is the optimal condition. Therefore, in this example of test results, the optimal setting for the signal input to selectors 401 to 403 of Vdd dependency generation circuit 103 is SEL[0] set to H.

[0140] FIG. 23 is a configuration diagram showing an example of a pulse width setting circuit. The pulse width setting circuit 51 according to this embodiment has a set of each of the FUSE elements 551-553 and the readout circuits 554-556, and the number of sets is equal to the number of selection signals of the selectors 401-403 of the Vdd dependency generation circuit 103 shown in FIG. 15. The Vdd dependency generation circuit 103 shown in FIG. 15 performs selection using three bits of SEL[2:0], which are signals input to the selectors 401-403, so an example of three bits is shown here. The setting of SEL[2:0], which is a signal input to the Vdd dependency generation circuit 103 and determined by the test circuit 50, is written into the FUSE elements 551-553. The readout circuits 554-556 output H when the connected FUSE elements 551-553 are disconnected by writing the setting, and output L when the connected FUSE elements 551-553 are not disconnected. The FUSE elements 551-553 may be, for example, laser fuses, electric fuses, or the like. The read circuits 554 to 556 may, for example, pass a current through the FUSE elements 551 to 553 for a short time immediately after power is turned on, determine whether or not they have been blown, and store the result in a latch.

[0141] 24 is a flowchart of the operation of the test circuit and pulse width setting circuit according to the fifth embodiment. Next, the flow of operation of the test circuit 50 and pulse width setting circuit 51 according to this embodiment will be described with reference to FIG. Here, an example will be described in which the Vdd dependency generation circuit 103 makes a selection using three bits of SEL[2:0], which are signals input to the selectors 401 to 403. Hereinafter, the signals of each bit will be represented as S[n] (n=0, 1, 2).

[0142] At the start of the test, the LSI tester 53 sets the power supply voltage V to Vmin (step S201).

[0143] Then, the test circuit 50 runs a predetermined test pattern, for example, as shown in FIG. 18, once (step S202).

[0144] Next, the LSI tester 53 determines whether the power supply voltage V is equal to or greater than Vmax (step S203). If the voltage V is less than Vmax (step S203: No), the LSI tester 53 increases the power supply voltage V by a predetermined step (V=V+step) (step S204). Then, the process returns to step S202.

[0145] On the other hand, if the voltage V is equal to or greater than Vmax (step S203: Yes), the LSI tester 53 collects the test results and obtains the test results shown in FIG. 20 (step S205).

[0146] Next, the LSI tester 53 acquires the number of Ls L[n] and the number of Hs H[n] of SEL[n] (step S206). Specifically, the LSI tester 53 stores the number of pulses generated at each output through all voltages V, i.e., the number of Ls output to the signal S[n], as variables L[n] on the tester program. The LSI tester 53 also stores the number of pulses that did not occur, i.e., the number of Hs output, as variables H[n] on the tester program.

[0147] Here, if the number of steps in the voltage range where assistance is desirable as shown in range 541 in Figure 20 is denoted as LP, and the number of steps in the voltage range where assistance is not desirable as shown in range 542 is denoted as HP, the appropriate pulse conditions are H[n]≧HP and L[n]≧LP.

[0148] Therefore, the LSI tester 53 sets n=0 (step S207). Next, the LSI tester 53 determines whether n is 2 or less (step S208). If n is greater than 2 (step S208: No), the LSI tester 53 determines that the SRAM 10 under test is defective (step S209) and ends the test.

[0149] On the other hand, if n is 2 or less (step S208: Yes), the LSI tester 53 determines whether H[n]≧HP and L[n]≧LP (step S210). If H[n] is less than HP or L[n] is less than LP, or both (step S210: No), the LSI tester 53 increments n by 1 (step S211) and returns to step S208.

[0150] On the other hand, if H[n]≧HP and L[n]≧LP (step S210: Yes), the LSI tester 53 determines that S[n] at that time is the optimal negative pulse width, and sets S[k] to H as S[n] at that time, with k=n (step S212).

[0151] Next, the LSI tester 53 writes to the pulse width setting circuit 51 that S[k] is set to H (step S213). As a result, one of the fuse elements 551 to 553 in the pulse width setting circuit 51 that corresponds to S[k] is disconnected. This sets an optimal pulse width for the Vdd dependency generation circuit 103 of the SRAM 10.

[0152] Thereafter, the LSI tester 53 performs a normal LSI test (step S214), and then determines whether the configured SRAM 10 is good or bad based on the test results (step S215).

[0153] As described above, the test circuit and pulse width setting circuit according to this embodiment use a replica of the Vdd dependency generating circuit mounted on the SRAM to identify an optimum pulse width for the SRAM and determine the signal input to the selector so that the identified pulse width is achieved. This makes it possible to automatically correct the assist release voltage to the optimum value without being aware of deviations from the center value of the assist release voltage due to manufacturing variations. [Example]

[0154] Next, a sixth embodiment will be described. In the fifth embodiment, the maximum voltage at which it is preferable to perform the assist was a standard value provided by the semiconductor manufacturer based on the number of memory cells 100 to be mounted and manufacturing variations. This standard value includes a margin to cover fluctuations in the center of the finished memory cells 100, and depending on the actual center value of the finished memory cells 100, the assist may be excessive. Therefore, it is more preferable to use a setting for the assist that matches the actual finished state of the memory cells 100.

[0155] The pulse width setting circuit 51 according to this embodiment differs from that of the fifth embodiment in that the pulse width of the Vdd dependency generation circuit 103 of the SRAM 10 can be changed by scan shift. Fig. 25 is a configuration diagram of a pulse width setting circuit according to the sixth embodiment. In the following description, the functions of the components already described will not be repeated.

[0156] In pulse width setting circuit 51, the outputs of flip-flops 521 to 523 corresponding to SEL[2:0], which are signals input to selectors 401 to 403 of Vdd dependency generation circuit 103 shown in Fig. 15, are connected as follows: The output of flip-flop 532 is connected to the input of flip-flop 522, and the output of flip-flop 522 is connected to the input of flip-flop 521. As a result, every time a positive pulse is input to the CK terminal, data input from the SI terminal is stored in the order of flip-flop 523, flip-flop 522, and flip-flop 521 by scan shift.

[0157] 26 is a flowchart of the operation of the test circuit and pulse width setting circuit according to the sixth embodiment. Next, the flow of operation of the test circuit 50 and pulse width setting circuit 51 according to this embodiment will be described with reference to FIG. 26. Here, an example will be described in which the Vdd dependency generation circuit 103 makes a selection using three bits of SEL[2:0], which are signals input to the selectors 401 to 403. Hereinafter, the signals of each bit will be represented as S[n] (n=0, 1, 2).

[0158] At the start of the test, the LSI tester 53 sets the power supply voltage V input to the test circuit 50 to Vmin (step S301).

[0159] Then, the test circuit 50 runs a predetermined test pattern, for example, as shown in FIG. 18, once (step S302).

[0160] Next, the pulse width setting circuit 51 initializes the Vdd dependency generating circuit 103 built in the SRAM 10 by setting SEL[2:n]=0 (step S303).

[0161] Next, the test circuit 50 sets n in SEL[n] to 0 (step S304).

[0162] Next, the test circuit 50 sets SEL[n] to H (step S305).

[0163] Next, the test circuit 50 writes SEL[2:0] to the pulse width setting circuit 51 by scanning (step S306). As a result, a signal with SEL[n] set to H is input to SEL[2:n] of the Vdd dependency generating circuit 103 built in the SRAM 10.

[0164] Thereafter, the LSI tester 53 executes an SRAM function test on the SRAM 10 (step S307).

[0165] Next, the test circuit 50 determines whether n is equal to or greater than the maximum number 2 (step S308). If n is less than 2 (step S308: No), the pulse width setting circuit 51 initializes the Vdd dependency generation circuit 103 built in the SRAM 10 by setting SEL[2:n]=0 (step S309).

[0166] Next, the test circuit 50 increments n in SEL[n] by 1 (step S310), after which the test circuit 50 returns to step S305.

[0167] On the other hand, if n is 2 or more (step S308: Yes), the test circuit 50 determines whether the power supply voltage V is equal to or greater than Vmax (step S311). If the voltage V is less than Vmax (step S311: No), the LSI tester 53 increases the power supply voltage V by a predetermined step (V=V+step) (step S312). Then, the process returns to step S302.

[0168] On the other hand, if the voltage V is equal to or greater than Vmax (step S311: Yes), the test circuit 50 collects the test results (step S313). FIG. 27 is a diagram illustrating an example of test results obtained in the sixth embodiment. For example, the test circuit 50 obtains test results 601 and SRAM function test results 602 obtained by running a test pattern, as shown in FIG. 27. As shown in FIG. 27, the test results 601 obtained by running the test pattern are similar to those in the fifth embodiment. A range 603 in the test results 601 is a voltage range in which no assistance is performed. In contrast, the SRAM function test results 602 represent information collected for each voltage step regarding whether the function of the SRAM 10 operated normally at each pulse width setting, with P (Pass) indicating normal operation and F (Fail) indicating failure. In this case, a pulse width registered as F in the SRAM function test results 602 is not suitable for use.

[0169] Here, the conditions for an appropriate pulse width obtained from the test results of Figure 27 are that the SRAM 10 functions normally at all voltages and that no pulse is generated in the voltage range where no assist is performed. In the case of Figure 27, the signals that satisfy these conditions are s[1] and s[2], but of these, s[1] with a narrower pulse width is optimal from the perspective of power consumption and stress reduction on the memory cell 100. Therefore, as shown below, the LSI tester 53 performs a calculation to determine this optimal pulse width.

[0170] Next, the LSI tester 53 counts the number of Hs in SEL[n] in the test results 601 obtained by the test circuit 50, where no pulses were generated at each output across all voltages, and stores the counted number as H[n] (step S314).

[0171] Furthermore, the LSI tester 53 counts the number of Fs in SEL[n] in the SRAM function test result 602 and stores the count as F[n] (step S315).

[0172] Here, when the number of voltage steps at which no assistance is performed is HP as in the fifth embodiment, the appropriate pulse conditions are H[n]≧HP and F[n]=0. In the case of FIG. If there are multiple values ​​of n that satisfy this condition, the one with the narrowest pulse width is optimal, but this can be done by starting from n=0 and selecting the first n that satisfies the condition.

[0173] The LSI tester 53 sets n=0 (step S316).

[0174] Next, the LSI tester 53 determines whether n is equal to or less than 2 (step S317). If n is greater than 2 (step S317: No), the LSI tester 53 determines that the SRAM 10 under test is defective (step S318) and ends the test.

[0175] On the other hand, if n is 2 or less (step S317: Yes), the LSI tester 53 determines whether H[n]≧HP and F[n]≧0 (step S319). If H[n] is less than HP or F[n] is less than 0, or both (step S319: No), the LSI tester 53 increments n by 1 (step S320) and returns to step S317.

[0176] On the other hand, if H[n]≧HP and F[n]≧0 (step S319: Yes), the LSI tester 53 determines that S[n] at that time is the optimal negative pulse width, and sets S[k] to H as S[n] at that time, with k=n (step S321).

[0177] Then, when the LSI1 is started up, the pulse width setting circuit 51 sets SEL[k]=H in the Vdd voltage dependent circuit 103 of the SRAM 10 by scanning (step S322). For example, the value of SEL[2:0] that gives the obtained optimum pulse width is stored in a ROM (Read Only Memory) or the like outside the LSI1, and is sent to the pulse width setting circuit 51 via a JTAG (Joint Test Action Group) or the like when the LSI1 is powered on, thereby setting the value.

[0178] As described above, the method according to the sixth embodiment makes it possible to adjust the voltage at which it is preferable to perform the assist to the actual performance of the memory cell, rather than to the standard value including a margin provided by the semiconductor manufacturer. As a result, it becomes possible to minimize the power and stress on the memory cell due to the assist.

[0179] Furthermore, the method according to this embodiment makes it possible to test the SRAM while changing the voltage at which the assist is released. This allows for a setting that matches the actual state of the memory cells. As a result, it becomes possible to set the voltage at which the assist is released, which minimizes power consumption and the stress applied to the memory cells. [Example]

[0180] Next, a seventh embodiment will be described. Fig. 28 is a configuration diagram of a pulse width setting circuit according to the seventh embodiment. A test circuit 50 according to this embodiment is similar to the test circuit 50 shown in Fig. 18.

[0181] The pulse width setting circuit 51 has a set of each of the FUSE elements 551-553, the read circuits 554-556, and the flip-flops 521-523, and has as many sets as the number of selection signals of the selectors 401-403 of the Vdd dependency generating circuit 103 shown in FIG.

[0182] The flip-flops 521 to 523 are positive edge trigger D-type flip-flops equipped with a scan function. The data input terminals of the flip-flops 521 to 523 are connected to the output terminals of the read circuits 554 to 556.

[0183] When the SM terminal is L, the flip-flops 521 to 523 acquire data read from the FUSE elements 551 to 553. When the SM terminal is H, the flip-flops 521 and 522 take in the output of the preceding flip-flop 522 or 523 by scan shift.

[0184] 29 is a flowchart of the operation of the test circuit and pulse width setting circuit according to Example 7. Next, the flow of the operation of the test circuit 50 and pulse width setting circuit 51 according to this example will be described with reference to FIG.

[0185] The LSI tester 53, the test circuit 50, and the pulse width setting circuit 51 execute a process of acquiring correlations between the power supply voltage and the pulse loss and SRAM function test (step S401). For example, the LSI tester 53, the test circuit 50, and the pulse width setting circuit 51 execute the processes of steps S301 to S311 in the flow shown in FIG. 26 as specific processes corresponding to this process.

[0186] Next, the LSI tester 53, the test circuit 50, and the pulse width setting circuit 51 execute a process of determining SEL[2:0], which are selection signals of the selectors 401 to 403 of the Vdd dependency generation circuit 103 (step S402). For example, the LSI tester 53, the test circuit 50, and the pulse width setting circuit 51 execute the processes of steps S313 to S321 in the flow shown in FIG. 26 as specific processes corresponding to this process.

[0187] Thereafter, the pulse width setting circuit 51 blows off the FUSE element[k] corresponding to the SEL[k] determined to be H among the FUSE elements 551 to 553 (step S403).

[0188] According to the method of this embodiment, it is possible to determine the optimum pulse width according to manufacturing variations by reflecting the results of SRAM function tests performed for all pulse width settings. Furthermore, according to the method of this embodiment, by writing the optimum pulse width determination results into FUSE elements, it is not necessary to load settings from an external ROM or the like during system operation, thereby reducing operating costs. [Example]

[0189] Next, an eighth embodiment will be described. Fig. 30 is a configuration diagram including a test circuit and a pulse width setting circuit according to the eighth embodiment. In this embodiment, when using the SRAM 10 shown in Fig. 15 that is adjustable in voltage for canceling the assist, the voltage for canceling the assist is set based on the results of an SRAM function test. In this embodiment, a test and pulse width setting circuit 801 is provided.

[0190] 31 is a diagram showing the configuration of the test and pulse width setting circuit. The test and pulse width setting circuit 801 detects a setting at which the negative pulse generated by the Vdd dependency generating circuit 103 built into the SRAM 10 disappears at each voltage, and stores that setting. Furthermore, the test and pulse width setting circuit 801 sets the stored setting as SEL[2:0], which is a signal that selects the selectors 401 to 403 of the Vdd dependency generating circuit 103 built into each SRAM 10.

[0191] The test and pulse width setting circuit 801 includes a Vdd dependency generating circuit replica 501, NAND circuits 511 to 512, inverters 513 to 515, dynamic gates 516 to 518, XOR circuits 811 to 813, and flip-flops 521 to 523. The Vdd dependency generating circuit replica 501, the NAND circuits 511 to 512, the inverters 513 to 515, and the dynamic gates 516 to 518 operate in the same manner as in the fifth embodiment.

[0192] One input terminal of each of the XOR circuits 811 to 813 is connected to the output terminal of the dynamic gates 516 to 518. The other input terminal of the XOR circuit 811 is connected to the output terminal of the dynamic gate 517. The other input terminal of the XOR circuit 812 is connected to the output terminal of the dynamic gate 518. The other input terminal of the XOR circuit 813 is connected to Vss.

[0193] The XOR circuit 811 outputs a signal S[0] which is the exclusive OR of the signals P[0] and P[1] output from the dynamic gates 516 and 517. The XOR circuit 812 outputs a signal S[1] which is the exclusive OR of the signals P[1] and P[2] output from the dynamic gates 517 and 518. The XOR circuit 813 outputs a signal S[2] which is the exclusive OR of the signal P[2] output from the dynamic gate 518 and Vss.

[0194] The flip-flops 521 to 523 receive the signals S[2:0] output from the XOR circuits 811 to 813, respectively.

[0195] Fig. 32 is a diagram showing an example of a pulse loss setting detection pattern, and Fig. 33 is a timing diagram of the pulse loss setting pattern.

[0196] The test and pulse width setting circuit 801 clears the flip-flops 521 to 523 to 1 by running pattern #00 in the pulse loss setting detection pattern 820. Next, the test and pulse width setting circuit 801 runs pattern #01 in the pulse loss setting detection pattern 820, generating pulses that are captured by the flip-flops 521 to 523. When running each of patterns #00 and #01, the test and pulse width setting circuit 801 actually changes each signal at the timing shown in FIG.

[0197] 34 is a diagram showing changes in internal signals when a pulse loss setting detection pattern is run. Here, the internal signals are signals P[2:0] output from dynamic gates 516 to 518 and signals S[2:0] output from XOR circuits 811 to 813.

[0198] When the pulse loss setting detection pattern 820 is run while changing the power supply voltage, the signals P[2:0] and S[2:0] change as shown in FIG. 32. As the pulse width is narrowed from P[2] to P[0] at each voltage, the XOR circuits 811-813 corresponding to the pulse loss output a high at the transition point where the pulse disappears, and the other circuits output a low. That is, by running the pulse loss setting detection pattern 820 at a voltage lower than the voltage at which no assist is performed, the test and pulse width setting circuit 801 can set the assist cancellation voltage in the Vdd dependency generating circuit 103 according to the voltage at which the pulse disappears. If the SRAM 10 subsequently passes the SRAM function test by the LSI tester 53, it is confirmed that there is no problem with canceling assist at the set voltage.

[0199] 35 is a flowchart of the test and operation of the pulse width setting circuit according to the embodiment 8. Next, the flow of the test and operation of the pulse width setting circuit 801 according to this embodiment will be described with reference to FIG.

[0200] At the start of the test, the LSI tester 53 sets the power supply voltage V to Vmin (step S501).

[0201] 30 once (step S502). As a result, the test and pulse width setting circuit 801 sets the Vdd dependency generating circuit 103 of the SRAM 10 so that the assist is released at the voltage V.

[0202] With the assist at voltage V set to be released, the LSI tester 53 executes an SRAM function test on the SRAM 10. Then, the LSI tester 53 determines whether the SRAM 10 passes the SRAM function test (step S503).

[0203] If the SRAM function test is passed (step S503: Yes), the LSI tester 53 decreases the voltage V by a predetermined step (step S504), after which the process returns to step S502.

[0204] On the other hand, if the SRAM function test fails (step S503: No), the LSI tester 53 sets a voltage one step higher than the voltage V at that time as Vpset, which is the voltage for canceling the optimal assist. That is, the LSI tester 53 sets Vpset=V+step (step S505). Next, the LSI tester 53 notifies the test and pulse width setting circuit 801 of Vpset.

[0205] The test and pulse width setting circuit 801 sets the voltage V to Vpset (step S506).

[0206] Then, the test and pulse width setting circuit 801 runs the pulse loss setting detection pattern 820 again (step S507), and resets the voltage for canceling the assist of the SRAM 10 to Vpset.

[0207] Thereafter, the LSI tester 53 performs a normal LSI test on the SRAM 10 (step S508), and then the LSI tester 53 determines whether the SRAM 10 is good or bad based on the results of the LSI test (step S509).

[0208] Fig. 36 is a flowchart of the operation of a system equipped with an SRAM according to the eighth embodiment. Next, the flow of operation of a system equipped with an SRAM 10 set by the test and pulse width setting circuit 801 according to this embodiment will be described with reference to Fig. 36. The test and pulse width setting circuit 801 writes Vpset determined in step S506 of the flow in Fig. 35 to, for example, a ROM external to the LSI 1.

[0209] The LSI1 is powered on and starts up (step S511).

[0210] The LSI1 reads Vpset from the external ROM using the LSI startup program and sets the voltage V to Vpset (step S512).

[0211] Next, the LSI1 runs the pulse loss setting detection pattern 820 to set a voltage for canceling the assist in the Vdd dependency generating circuit 103 of the SRAM 10 in the LSI1 (step S513).

[0212] Thereafter, the LSI1 returns the voltage V to the normal setting without turning off the power (step S514), and then the LSI1 shifts to normal operation (step S515).

[0213] As described above, the test and pulse width setting circuit according to this embodiment gradually lowers the assist release voltage while performing an SRAM function test, thereby identifying the lower limit of the assist release voltage. This allows the test and pulse width setting circuit to set a lower limit for the assist release voltage that matches the state of the memory cell at that time, without being constrained by the standard values ​​provided by semiconductor manufacturers. Therefore, the increase in power due to the assist and the stress on the memory cell can be minimized. [Explanation of symbols]

[0214] 1 LSI 2 cores 3. L1 Cache 4. L2 cache 5 Memory Cell Array 50 Test Circuit 51 Pulse width setting circuit 53 LSI tester 10 SRAM 100 memory cells 101 Bit selection circuit 102 Step-down circuit 103 Vdd Dependent Generator Circuit 104, 104A, 104B Dynamic Gate 131, 132, 134, 136, 137 Inverter chain 133, 135 NAND circuit 141 H Keeper 401~403 Selector 501 Vdd dependent generator replica 502~505 Inverter Chain 506~508 Selector 509, 511, 512 NAND circuits 513~515 Inverter 516~518 Dynamic Gate 521~523 Flip-flops 551~553 FUSE elements 554~556 Readout circuit 801 Test and pulse width setting circuit 811~813 XOR circuit

Claims

1. a storage element for storing data; a bit line connected to the memory element and dropping to a reference voltage to invert data held by the memory element; a first step-down circuit that reduces a bit line voltage, which is a voltage applied to the bit line, to a first predetermined value that is equal to or lower than a reference voltage; a control unit that detects a first voltage change based on a first output from a first inverter having a voltage dependency of a generation delay and a second output from a second inverter having a voltage dependency of a generation delay greater than that of the first inverter, and controls an amount of reduction of the bit line voltage by the first step-down circuit in accordance with the amount of the detected first voltage change; A semiconductor memory device comprising:

2. The control unit a predetermined signal having a voltage change at a specific timing is input to each of the first inverter and the second inverter; a difference between the timing of the first output relative to the voltage change of the predetermined signal and the timing of the second output relative to the voltage change of the predetermined signal is calculated as the amount of the detected first voltage change, and the first step-down circuit is caused to drop the bit line to the first predetermined value during a period of the difference; 2. The semiconductor memory device according to claim 1, wherein:

3. 3. The semiconductor memory device according to claim 1, further comprising a holding circuit for maintaining the first predetermined voltage drop of the bit line by the first step-down circuit for a predetermined period of time.

4. a second step-down circuit that further reduces the voltage of the bit line from the first predetermined value by a second predetermined value; The control unit a third inverter connected in series to the second inverter and having a voltage dependency of a generation delay greater than that of the first inverter; controlling the amount of reduction of the bit line voltage by the first step-down circuit based on the first output and the second output; A second voltage change is detected based on the first output and a third output from the third inverter, and an amount of reduction of the bit line voltage by the second step-down circuit is controlled according to the amount of the detected second voltage change.

4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to the first and second memory cells.

5. The control unit a fourth inverter connected in series to the second inverter and having a voltage dependency of a generation delay greater than that of the first inverter; selecting either the second output or a fourth output from the fourth inverter; When the second output is selected, the amount of reduction of the bit line voltage by the first step-down circuit is controlled in accordance with the amount of the first voltage change; When the fourth output is selected, a third voltage change is detected based on the first output and the fourth output, and the amount of reduction of the bit line voltage by the first step-down circuit is controlled according to the amount of the detected third voltage change.

4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to the first and second memory cells.

6. a test execution unit that detects a fourth voltage change based on a fifth output from a fifth inverter having a voltage dependency of a generation delay and a sixth output from a sixth inverter having a voltage dependency of a generation delay greater than that of the fifth inverter, and determines an amount of reduction of the bit line voltage by the first step-down circuit according to the amount of the detected fourth voltage change; The control unit controls the amount by which the bit line voltage is reduced by the first step-down circuit based on the amount by which the bit line voltage is reduced determined by the test execution unit.

6. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to the first and second memory cells.

7. 1. A method for controlling a semiconductor memory device having a memory element for storing data, a bit line connected to the memory element and for inverting the data stored in the memory element by dropping to a reference voltage, and a first step-down circuit for dropping a bit line voltage, which is a voltage applied to the bit line, to a first predetermined value that is equal to or lower than the reference voltage, Detecting a voltage change based on a first output from a first inverter having a voltage dependency of a generation delay and a second output from a second inverter having a voltage dependency of a generation delay greater than that of the first inverter; The amount by which the bit line voltage is reduced by the first step-down circuit is controlled according to the amount of the detected voltage change.

2. A method for controlling a semiconductor memory device comprising:

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