Semiconductor Components and Electronic Devices

Abstract

The embodiments of this application relate to the field of semiconductor technology to provide a semiconductor component and electronic device and to reduce the gate-drain parasitic capacitance of the semiconductor component, the semiconductor component including a substrate, a channel layer and a barrier layer sequentially stacked on the substrate, a source and a drain disposed on the barrier layer, a first gate and a second gate disposed on the barrier layer, the first gate and the second gate being located between the source and the drain and the second gate being disposed between the first gate and the drain, a first gate field plate, the first gate field plate being at least partially disposed on a side of the first gate closer to the drain, and a first source field plate, the first source field plate covering the first gate field plate.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor components and electronic devices. [Background technology]

[0002] With the development of semiconductor technology, semiconductor components with high thermal conductivity, high electron drift velocity, high temperature resistance, and stable chemical properties are widely used in high frequency, high temperature, and microwave fields.

[0003] It has been found through research that how to increase the operating voltage of semiconductor components so as to effectively improve the microwave power characteristics of semiconductor components is a key issue in the current semiconductor field. Summary of the Invention

[0004] SUMMARY OF THE INVENTION Embodiments of the present application provide semiconductor components and electronic devices for increasing the operating voltage of semiconductor components.

[0005] To achieve the above objectives, the following technical solutions are used in this application:

[0006] According to a first aspect of an embodiment of the present application, there is provided a semiconductor component. The semiconductor component may be, for example, a high electron mobility transistor component. The semiconductor component includes: a substrate; a channel layer and a barrier layer stacked in order on the substrate; a source and a drain disposed on the barrier layer; a first gate and a second gate disposed on the barrier layer, the first gate and the second gate being located between the source and the drain, and the second gate being located between the first gate and the drain; a first gate field plate at least partially located on a side of the first gate closer to the drain; and a first source field plate covering the first gate field plate.

[0007] In this embodiment of the present application, a first gate field plate and a first source field plate are arranged in a semiconductor component to change the electric field distribution between the first gate and the drain and to reduce the electric field strength on the side of the first gate closer to the drain. This reduces the possibility of breakdown of the material in the barrier layer, increasing the breakdown voltage of the semiconductor component and increasing the operating voltage of the semiconductor component. Based on this, a second gate is arranged between the first gate and the drain. This second gate reduces the feedback path between the first gate and the drain, achieving a certain degree of shielding effect and reducing the gate-drain parasitic capacitance between the first gate and the drain, thereby reducing the impact of the gate-drain parasitic capacitance on the performance of the semiconductor component, increasing the operating voltage of the semiconductor component, and reducing its impact on other performance aspects of the semiconductor component.

[0008] In one possible implementation, the semiconductor component further includes a second gate field plate, the second gate field plate being at least partially located on a side of the second gate closer to the drain. The second gate field plate is disposed within the semiconductor component to significantly reduce the electric field strength in the region closer to the second gate. This reduces the likelihood of breakdown of the material in the barrier layer, further increasing the breakdown voltage of the semiconductor component and ensuring the performance of the semiconductor component. Furthermore, the second gate field plate disposed within the semiconductor component can achieve a certain degree of shielding effect, further expanding the depletion region and reducing the gate-drain parasitic capacitance between the first gate and the drain.

[0009] In one possible implementation, the semiconductor component further includes a second source field plate that covers the second gate field plate. When the second source field plate is disposed within the semiconductor component, the conductive structure of the second source field plate adjusts the electric field distribution between the second gate field plate and the drain to reduce the electric field strength on a side of the second gate that is closer to the drain, thereby reducing the peak electric field in the semiconductor component and further increasing the breakdown voltage of the semiconductor component.

[0010] In one possible implementation, the first source field plate covers the second gate field plate. The first source field plate can overlap the second gate. Thus, even if the spacing between the first and second gates is reduced, the process difficulty of the first source field plate does not increase excessively, and the process is easy to implement.

[0011] In one possible implementation, the first source field plate is connected to the second source field plate, and therefore the first and second source field plates can be manufactured using existing processes without changing the manufacturing process of the first source field plate.

[0012] In one possible implementation, a gap exists between the first and second source field plates. A gap is provided between the first and second source field plates. Compared to connecting the first source field plate to the second source field plate, this can increase the small signal gain of the semiconductor component.

[0013] In one possible implementation, the spacing between the first gate field plate and the second gate is in the range of 0.5 μm to 2.7 μm. Reducing the spacing between the first gate field plate and the second gate significantly increases the saturation current of the semiconductor component, thereby increasing the power of the semiconductor component. However, the knee-point voltage of the semiconductor component also increases, resulting in a decrease in the efficiency of the semiconductor component. In addition, the gate-drain parasitic capacitance of the semiconductor component increases, reducing the gain characteristics of the semiconductor component. Therefore, the spacing between the first gate field plate and the second gate is set to be in the range of 0.5 μm to 2.7 μm to comprehensively meet the performance and reliability requirements of the semiconductor component.

[0014] In one possible implementation, the first gate field plate includes a first portion located closer to the drain of the first gate and a second portion located closer to the source of the first gate, and the first and second portions are separately in contact with and connected to the first gate. The first and second portions of the first gate field plate are located on both sides of the first gate, respectively. When the first gate and the first gate field plate are manufactured, the requirements for the alignment boundary accuracy of the first gate field plate may not be excessively high. Even if the alignment is inaccurate and the first and second portions obtained through manufacturing differ in size, the impact on the function of the first gate field plate is small. Furthermore, if the alignment is inaccurate, only the sizes of the first and second portions are affected, and the width of the first gate is not affected. This avoids the impact on the performance of the semiconductor component caused by changes in the size of the first gate.

[0015] In one possible implementation, the semiconductor component further includes a third gate disposed between the second gate and the drain, and by further increasing the number of gates, the gate-drain parasitic capacitance is further reduced and the small-signal gain of the semiconductor component is increased.

[0016] In one possible implementation, the semiconductor component further includes a third gate field plate disposed at least partially on a side of the third gate proximal to the drain, and further increasing the number of gate field plates further increases the breakdown voltage of the semiconductor component.

[0017] In one possible implementation, the semiconductor component further includes a third source field plate overlying the third gate field plate, and further increasing the number of source field plates further increases the breakdown voltage of the semiconductor component.

[0018] According to a second aspect of an embodiment of the present application, there is provided a semiconductor component. The semiconductor component may be, for example, a high electron mobility transistor component. The semiconductor component includes: a substrate; a channel layer and a barrier layer stacked in this order on the substrate; a source and a drain disposed on the barrier layer; a first gate and a second gate disposed on the barrier layer, the first gate and the second gate being located between the source and the drain, and the first gate being located between the second gate and the drain; a first gate field plate at least partially located on a side of the first gate closer to the drain; and a first source field plate covering the first gate field plate.

[0019] In this embodiment of the present application, a first gate field plate and a first source field plate are arranged in the semiconductor component to change the electric field distribution between the second gate and the drain and to reduce the electric field strength on the side of the second gate closer to the drain. This reduces the possibility of breakdown of the material in the barrier layer, increases the breakdown voltage of the semiconductor component, and increases the operating voltage of the semiconductor component. Based on this, a first gate is arranged between the second gate and the drain, which reduces the feedback path between the second gate and the drain, achieving a certain degree of shielding effect and reducing the gate-drain parasitic capacitance between the second gate and the drain, thereby reducing the impact of the gate-drain parasitic capacitance on the performance of the semiconductor component, increasing the operating voltage of the semiconductor component, and reducing its impact on other performance aspects of the semiconductor component.

[0020] According to a third aspect of an embodiment of the present application, there is provided an electronic device including a semiconductor component and an antenna, the semiconductor component being configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation, the semiconductor component being a semiconductor component according to any of the implementations of the first or second aspect.

[0021] The electronic device provided in the third aspect of the embodiment of this application includes a semiconductor component according to the implementation of either the first or second aspect, and the beneficial effects of the electronic device are the same as those of the semiconductor component, and the details will not be described again here.

[0022] According to a fourth aspect of the present application, there is provided an electronic device including a semiconductor component according to the implementation of either the first or second aspect, and a printed circuit board electrically connected to the semiconductor component, wherein the substrate of the semiconductor component is a conductive substrate.

[0023] An electronic device provided in a fourth aspect of the embodiment of this application includes a semiconductor component according to the implementation of either the first or second aspect, and the beneficial effects of the electronic device are the same as those of the semiconductor component, and the details will not be described again here. [Brief explanation of the drawings]

[0024] For a more comprehensive understanding of the present invention, reference is now made to the following brief description, taken in conjunction with the accompanying drawings and detailed description, which are not necessarily drawn to scale. [Figure 1A] 1 is a schematic diagram of a configuration of an electronic device according to an embodiment of the present application. [Figure 1B] 1 is a schematic diagram of an active antenna unit configuration according to one embodiment of the present application; [Figure 1C]FIG. 10 is a schematic diagram of the configuration of another electronic device according to an embodiment of the present application. [Figure 2A] 1 is a schematic diagram of a structure of a semiconductor component according to an embodiment of the present application; [Figure 2B] FIG. 2 is a schematic diagram of the structure of another semiconductor component according to an embodiment of the present application. [Figure 3] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 4] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 5] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 6A] FIG. 2C is an output curve diagram of the semiconductor component shown in FIG. 2B according to an embodiment of the present application. [Figure 6B] FIG. 6 is an output curve diagram of the semiconductor component shown in FIG. 5 according to an embodiment of the present application. [Figure 7A] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 7B] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 8] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 9] 3 is a diagram illustrating the distribution of an electric field at each position of a semiconductor component according to an embodiment of the present application. [Figure 10A] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 10B] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 11A] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 11B]FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 11C] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Figure 12] FIG. 10 is a schematic diagram of a structure of yet another semiconductor component according to an embodiment of the present application. [Explanation of symbols]

[0025] 1: base station, 2: charger, 11: baseband processing unit, 12: active antenna unit, 121: computation unit, 122: first transmitting unit, 123: antenna unit, 124: power supply, 1210: control unit, 1211: second transmitting unit, 1212: baseband unit, 1213: power supply unit, 1221: RF unit, 1222: PA, 20: substrate, 30: channel layer, 40: barrier layer, 50: nucleation layer, 60: graded buffer layer, 70: insertion layer, 80: cap layer. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, the technical solutions in the embodiments of this application will be described with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part, rather than all, of the embodiments of this application.

[0027] The terms "first" and "second" in the embodiments of this application are intended for descriptive purposes only and are not to be understood as indicating or implying the relative importance or quantity of the technical features referred to. Thus, features qualified by "first," "second," or the like may explicitly or implicitly include one or more features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] Furthermore, in the embodiments of this application, the terms "upper", "lower", "left", and "right" are not limited to definitions relative to the directions in which parts are schematically arranged in the accompanying drawings. It should be understood that these directional terms are relative concepts used for relative description and clarity, and may change correspondingly based on changes in the directions in which parts are arranged in the accompanying drawings.

[0029] In the embodiments of this application, unless the context clearly dictates otherwise, throughout the specification and claims, the term "comprising" is interpreted as "open and inclusive," i.e., "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "examples," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. General references to such terms do not necessarily refer to the same embodiment or example. Furthermore, the particular feature, structure, material, or characteristic may be included in any one or more embodiments or examples in any appropriate manner.

[0030] When describing some embodiments, the terms "coupled" and "connected" and their extensions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more parts are in direct physical or electrical contact with each other. In another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more parts are in direct physical or electrical contact with each other. However, the term "couple" may also mean that two or more parts are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this specification.

[0031] In the embodiments of this application, implementations are described with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams used as idealized examples in the accompanying drawings. In the accompanying drawings, thicknesses of layers and regions are exaggerated for clarity. Thus, variations in the shapes of the drawings due, for example, to manufacturing techniques and / or tolerances, can be expected. Therefore, implementations should not be construed as limited to the shapes of regions shown in this specification, but rather include deviations in shape due, for example, to manufacturing. For example, an etched region shown as a rectangle will typically have curved characteristics. Therefore, the regions shown in the accompanying drawings are exemplary in nature, and their shapes are not intended to represent the actual shapes of regions of a device, nor are they intended to limit the scope of implementations.

[0032] In the embodiments of this application, the term "two-dimensional electron gas (2DEG)" means that the movement of electrons perpendicular to the interface direction is constrained by a potential well and therefore quantized. The movement of electrons parallel to the surface remains free. In this case, such free electrons in two dimensions are referred to as a two-dimensional electron gas.

[0033] In the embodiments of this application, the term "semi-insulating (SI)" means a material with a resistivity of 10 5 For example, a semi-insulating SiC substrate has a resistivity of 10 5 This means that the resistance is higher than Ω·cm.

[0034] In the embodiments of this application, the term "current collapse effect" refers to the effect that when the drain voltage of a semiconductor component exceeds a certain value, the current begins to decrease as the drain voltage increases and cannot reach an ideal value.

[0035] In the embodiments of this application, the term "knee-point voltage" refers to the inflection point voltage that exists when a semiconductor component enters from the linear region to the saturation region.

[0036] In the embodiments of this application, the term "depletion region" means a region in a semiconductor pn junction, Schottky junction, or heterojunction where the energy band near the interface is bent due to the difference in the original chemical potentials of the semiconductors on either side of the interface, forming an interface region with a reduced concentration of electrons or holes in the region where the energy band is bent.

[0037] One embodiment of the present application provides an electronic device, such as a charger, a small rechargeable consumer electronic device, an unmanned aerial vehicle, an aerospace device, a lidar driver, a laser, a detector, a radar, and a 5G (the 5 th The electronic device may be a different type of user equipment or terminal equipment, such as a (5th generation mobile network) communication device. Alternatively, the electronic device may be a network device, such as a base station. Alternatively, the electronic device may be a device, such as a power amplifier, within the aforementioned electronic device. The specific form of the electronic device is not particularly limited in the embodiments of this application.

[0038] In the past 30 years, semiconductor components with high thermal conductivity, high electron drift velocity, high temperature resistance, and stable chemical properties have been widely used as radio frequency components or power components in the fields of power electronics, microwave radio frequency, and photoelectric components.

[0039] For example, third-generation semiconductor gallium nitride (GaN) materials have excellent properties, such as a large bandgap (3.4 eV), a high breakdown field (3.3 MV / cm), a large saturation velocity (2.5 e7 cm / s), and a high 2DEG density caused by the polarization effect at the aluminum gallium nitride (AlGaN) / GaN heterojunction interface. Therefore, GaN high-electron-mobility transistor (HEMT) components can operate at high voltages, high temperatures, and high frequencies, and are therefore widely used as radio frequency components or power components.

[0040] When the semiconductor components are used as radio frequency components, the configuration of an electronic device will be described using a base station as an example. As shown in FIG. 1A, the base station 1 includes a baseband processing unit (BBU) 11 and an active antenna unit (AAU) 12. The BBU 11 mainly performs baseband digital signal processing, such as fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT), modulation / demodulation, and channel coding / decoding. As shown in FIG. 1B, the AAU 12 includes a calculation unit 121, a first transmission unit 122, and an antenna unit 123. The calculation unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212, and a power supply unit 1213. The control unit 1210, the second transmission unit 1211, the baseband unit 1212, and the power supply unit 1213 are electrically connected to each other. The control unit 1210 is configured to control radio frequency signals. The second transmitting unit 1211 is configured to transmit radio frequency signals. The baseband unit 1212 is configured to convert between digital and analog signals. For example, the baseband unit 1212 is a digital-to-analog converter (DAC). The DAC may convert the digital signal output by the BBU 11 into an analog signal. The power supply unit 1213 is electrically connected to the power supply 124 and configured to supply power to the control unit 1210, the second transmitting unit 1211, and the baseband unit 1212 in the computing unit 121. The first transmitting unit 122 is configured to transmit and amplify radio frequency signals. The first transmitting unit 122 includes a radio frequency (RF) unit 1221 and a power amplifier (PA) 1222. The RF unit 1221 is configured to convert the analog signal into a low-power radio frequency signal.The PA 1222 is configured to amplify the power of the low-power radio frequency signal and output the power-amplified radio frequency signal to the antenna unit 123. The antenna unit 123 is responsible for radiating the radio frequency signal. As shown in FIG. 1B , the AAU 12 may include multiple RF units 1221, multiple PAs 1222, and multiple antenna units 123. Note that the PA 1222 may be a semiconductor component.

[0041] It should be understood that when the semiconductor component is used as a PA, the electronic device provided in this embodiment of the present application is not limited to the base station shown in Figures 1A and 1B. Any electronic device that uses a power amplifier to amplify a signal belongs to the application scenario of this embodiment of the present application.

[0042] When a semiconductor component is used as a power component, the configuration of an electronic device will be described using an example in which the electronic device is a charger. As shown in FIG. 1C , a charger 2 may include power components, a resistor R, an inductor L, and a capacitor C. The power components may be, for example, semiconductor components. The semiconductor components, the resistor R, the inductor L, and the capacitor C may be interconnected using a printed circuit board (PCB).

[0043] It should be understood that when a semiconductor component is used as a power component, the electronic device provided in this embodiment of the present application is not limited to the charger shown in Fig. 1C. Any electronic device that uses a power component belongs to the application scenario of this embodiment of the present application.

[0044] The microwave power characteristics of a semiconductor component can be effectively improved by increasing the operating voltage of the semiconductor component, and increasing the breakdown voltage of the semiconductor component is a prerequisite for increasing the operating voltage of the semiconductor component.

[0045] 2A , the semiconductor component includes a substrate 20, a channel layer 30 and a barrier layer 40 (used as a heterojunction in the semiconductor component) disposed on the substrate 20, and a source S, a drain D, and a gate G disposed on the barrier layer 40. The source S and the drain D form ohmic contacts with the barrier layer 40, and the gate G forms a Schottky contact with the barrier layer 40. Based on this, the semiconductor component further includes a gate field plate (GFP). A gap exists between the gate field plate GFP and the barrier layer 40.

[0046] When the semiconductor component is in operation, an electric field is generated between the gate G and the drain D. The electric field concentration point is at the sharp corner of the gate G close to the drain D. This easily causes breakdown (irreversible physical damage) of the material of the barrier layer 40, resulting in failure of the semiconductor component. The gate field plate GFP is disposed on the gate G. This means that the gate field plate GFP extends the gate G toward the drain D, thereby changing the electric field distribution between the gate G and the drain D, and moving the electric field concentration point to the top corner of the gate field plate close to the drain D. There is no longer an electric field concentration point at the sharp corner of the gate close to the drain D, which means that the electric field intensity on the side of the gate G close to the drain D is reduced. Although there is an electric field concentration point on the side of the gate field plate GFP close to the drain D, the gap between the gate field plate GFP and the barrier layer 40 reduces the possibility of breakdown of the material of the barrier layer 40, increases the breakdown voltage of the semiconductor component, and ensures the performance of the semiconductor component.

[0047] However, there exists a gate-drain parasitic capacitance Cgd (also called feedback capacitance) between the gate G and the drain D. After the gate field plate GFP is disposed, the gate-drain parasitic capacitance Cgd further increases, which results in a decrease in the small signal gain, current gain cutoff frequency, and power gain cutoff frequency of the semiconductor component.

[0048] Based on this, in some embodiments, as shown in FIG. 2B, the semiconductor component further includes a source field plate (SFP), which overlaps with and is disposed above the gate field plate GFP.

[0049] The source field plate SFP is disposed within the semiconductor component to interrupt the feedback path between the gate G and the drain D, reducing the gate-drain parasitic capacitance Cgd of the semiconductor component and increasing the small-signal gain, current gain cutoff frequency, and power gain cutoff frequency of the semiconductor component. In addition, the conductive structure of the source field plate SFP adjusts the electric field distribution between the gate field plate GFP and the drain D, reducing the electric field strength on the side of the gate G closer to the drain D, reducing the peak electric field of the semiconductor component and further increasing the breakdown voltage of the semiconductor component. After the electric field strength is reduced, the possibility of electrons being excited into surface states by a strong electric field is reduced, thereby suppressing the current collapse effect of the semiconductor component.

[0050] However, the introduction of the source field plate SFP increases the gate-source parasitic capacitance Cgs of the semiconductor component, which degrades the frequency characteristics of the semiconductor component.

[0051] In some embodiments, the source field plate SFP is extended to the drain D side to improve the gain characteristics of the semiconductor component.

[0052] However, this approach only increases the small signal gain to a limited extent, and in addition, it significantly increases the gate-source parasitic capacitance Cgs of the semiconductor component, which may further reduce the drain efficiency of the semiconductor component and degrade the frequency characteristics of the semiconductor component.

[0053] In some embodiments, the gate length (the size in the direction from the source S to the drain D) is shortened to reduce the gate-drain parasitic capacitance Cgd and further improve the gain characteristics of the semiconductor component. For example, a gate length process with a gate length of 0.25 μm or a gate length of 0.1 μm is used.

[0054] However, shorter gate lengths require more precise lithography equipment (e.g., electron beam lithography equipment) or more complex processes (e.g., linewidth scaling processes). In addition, shorter gate lengths can also result in short channel effects, which can reduce the output impedance of the semiconductor component and cause poor turn-off characteristics in the case of high leakage voltages.

[0055] Therefore, in designing a semiconductor component, it is necessary to comprehensively consider the breakdown voltage, gain characteristics, etc. of the semiconductor component. How to reduce the influence on characteristics including the small signal gain, current gain cutoff frequency, and power gain of the semiconductor component when lowering the breakdown voltage of the semiconductor component is a technical problem that needs to be solved by those skilled in the art.

[0056] Hereinafter, some detailed examples will be used to describe the semiconductor components provided in the embodiments of this application.

[0057] Example 1

[0058] 3, the semiconductor component mainly includes a substrate 20, a channel layer 30 and a barrier layer 40 stacked in this order on the substrate 20, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1 and a second gate G2 positioned between the source S and the drain D and arranged on the barrier layer 40, a first gate field plate GFP1 and a first source field plate SFP1.

[0059] In some embodiments, the substrate 20 is a diamond substrate or a silicon carbide (SiC) substrate.

[0060] When the substrate 20 is a SiC substrate and the raw material is not highly pure, the SiC substrate obtained by growth is a conductive substrate, whereas when the raw material is highly pure, the SiC substrate obtained by growth is a semi-insulating substrate.

[0061] When the substrate 20 is a diamond substrate, the diamond substrate formed by normal growth is a semi-insulating substrate. When the diamond substrate has a high impurity content or is doped in the process of forming the diamond substrate, the diamond substrate formed is a conductive substrate.

[0062] If the substrate 20 is a conductive substrate, the semiconductor components are used as power components in the electronic device and interconnect with a PCB in the electronic device, whereas if the substrate 20 is a semi-insulating substrate, the semiconductor components are used as radio frequency components in the electronic device and perform signal communication with an antenna in the electronic device.

[0063] The thermal conductivity of a diamond substrate is typically 1000 W m -1 ·K -1 to 2000 W·m -1 ·K -1 , and the thermal conductivity of a SiC substrate is typically about 370 W m -1 ·K -1When the substrate 20 is a diamond substrate or a SiC substrate, the substrate 20 has a high heat dissipation capability, and as a result, the heat dissipation capability of the semiconductor component can be improved.

[0064] In some embodiments, the semiconductor component further includes a nucleation layer 50, as shown in FIG.

[0065] Nucleation layer 50 is disposed on substrate 20. For example, nucleation layer 50 is disposed on the surface of substrate 20.

[0066] The method for forming the nucleation layer 50 may be, for example, metal-organic chemical vapor deposition (MOCVD) growth or molecular beam epitaxy (MBE) growth.

[0067] The material of the nucleation layer 50 may include, for example, one or more of GaN, AlGaN, and aluminum nitride (AlN).

[0068] The function of the nucleation layer 50 is to match the lattice structure of the substrate 20 with that of the channel layer 30. For example, a nucleation layer 50 with a lattice structure that is close to that of the substrate 20 can be first placed on the substrate 20, and then a channel layer 30 with a lattice structure that is close to that of the nucleation layer 50 is provided on the nucleation layer 50. The nucleation layer 50 may have a superlattice structure. The repeating unit of the superlattice structure includes two different semiconductor material layers. If the thickness and periodic length of these two semiconductor material layers are smaller than the mean free path of electrons, a quantum size effect can be generated within the superlattice structure. In this case, the well sandwiched between the two semiconductor material layers of the superlattice structure is a quantum well. The energy potential well created by the quantum well constrains electrons, allowing them to move in a direction parallel to the interface of the nucleation layer 50, improving the lateral movement of electrons and avoiding or reducing the probability of electrons directly entering the substrate 20 in a perpendicular direction parallel to the interface, thereby reducing electrical leakage in the substrate 20.

[0069] In some embodiments, the semiconductor component further includes a graded buffer layer 60, as shown in FIG.

[0070] The graded buffer layer 60 is disposed on the side of the nucleation layer 50 remote from the substrate 20. For example, the graded buffer layer 60 is disposed on the surface of the nucleation layer 50 remote from the substrate 20.

[0071] A method for forming the graded buffer layer 60 may be, for example, to use an MOCVD process to epitaxially grow an AlGaN graded layer whose Al (aluminum) content gradually decreases.

[0072] For example, Al may be deposited on the side of the nucleation layer 50 away from the substrate 20 by using an MOCVD process. 0.8 Ga 0.2 N layer, Al 0.5 Ga 0.5 N layer and Al 0.2 Ga 0.8 N layers are formed sequentially to form the graded buffer layer 60 .

[0073] It may also be understood that the composition of the graded buffer layer 60 present when the semiconductor component is used as a radio frequency component may differ from the composition of the graded buffer layer 60 present when the semiconductor component is used as a power component.

[0074] The function of the graded buffer layer 60 is to deepen the potential well of the heterojunction including the barrier layer 40 and the channel layer 30, because the band gap of the graded buffer layer 60 is different from that of the channel layer 30, thereby increasing the two-dimensional electron gas (2DEG) concentration. In addition, to suppress the decrease in mobility caused by electron scattering, the graded buffer layer 60 usually has an undoped structure.

[0075] In some embodiments, a channel layer 30 is disposed on a substrate 20, as shown in FIGS.

[0076] For example, as shown in Figure 3, the channel layer 30 is disposed on the surface of the substrate 20. Alternatively, as shown in Figure 4, the channel layer 30 is disposed on the surface of the graded buffer layer 60.

[0077] The channel layer 30 may be formed by, for example, MOCVD growth or MBE growth.

[0078] The material of the channel layer 30 may include, for example, one or more of GaN, AlGaN, indium aluminum nitride (InAlN), AlN, and scandium aluminum nitride (ScAlN).

[0079] In some embodiments, the semiconductor component further includes an intercalation layer 70, as shown in FIG.

[0080] The insertion layer 70 is disposed on the channel layer 30. For example, the insertion layer 70 is disposed on the surface of the channel layer 30.

[0081] The method for forming the insertion layer 70 may be, for example, MOCVD growth or MBE growth.

[0082] By disposing the insertion layer between the channel layer 30 and the barrier layer 40, the 2DEG concentration can be increased.

[0083] In some embodiments, a barrier layer 40 is disposed on the channel layer 30, as shown in FIGS.

[0084] 3, the barrier layer 40 is disposed on the surface of the channel layer 30. Alternatively, for example, the barrier layer 40 is disposed on the surface of the insertion layer 70.

[0085] The method for forming the barrier layer 40 may be, for example, MOCVD growth or MBE growth.

[0086] The material of the barrier layer 40 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.

[0087] It can be appreciated that the channel layer 30 and the barrier layer 40 form a heterojunction of semiconductor components, with two-dimensional electron gas being generated above the channel layer 30. Thus, the material of the channel layer 30 is different from the material of the barrier layer 40. For example, the material of the channel layer 30 includes GaN and the material of the barrier layer 40 includes AlGaN.

[0088] In some embodiments, the semiconductor component further includes a cap layer 80, as shown in FIG.

[0089] The cap layer 80 is disposed on the barrier layer 40. For example, the cap layer 80 is disposed on the surface of the barrier layer 40.

[0090] The method for forming the cap layer 80 may be, for example, by using an MOCVD growth method or an MBE growth method in combination with an etching process to form the cap layer.

[0091] The cap layer 80 has openings for placing the source S and drain D (at the locations where the source S and drain D will be placed), which expose the barrier layer 40 .

[0092] The material of the cap layer 80 can be, for example, GaN or silicon nitride (Si3N4).

[0093] The cap layer 80 formed on the barrier layer 40 can protect the barrier layer 40, prevent the surface of the barrier layer 40 from oxidation, and reduce the surface state of the semiconductor component, which in turn reduces the on-resistance of the semiconductor component, reduces the electrical leakage and power consumption of the gate of the semiconductor component, and improves the reliability of the semiconductor component.

[0094] In some embodiments, as shown in Figure 4, a small amount of etching may be performed on the barrier layer 40 when the opening in the cap layer 80 is etched. In other words, a recess ultimately exists on the barrier layer 40.

[0095] Thus, a new ohmic contact surface can be formed in the recesses on the source S, drain D, and barrier layer 40, which facilitates the diffusion of TiN (titanium nitride) formed between the source S and drain D and the surface of the barrier layer 40 to form a second conductive channel, effectively reducing the ohmic contact resistance. Also, using the recess structure formed on the barrier layer 40 can effectively increase the maximum current of the drain D and lower the on-resistance of the semiconductor component.

[0096] In some embodiments, as shown in FIGS. 3 and 4, the source S and drain D are disposed on the barrier layer 40 and are located in openings on the cap layer 80 to form ohmic contacts with the barrier layer 40.

[0097] The source S and the drain D can be formed, for example, by using a photolithography and etching process, and the source S and the drain D can be formed, for example, simultaneously.

[0098] The material of the source S and the drain D may be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer, and a gold (Au) layer stacked in this order, i.e., Ti / Al / Ni / Au. Alternatively, the material of the source S and the drain D may be a Ti layer, an Al layer, a platinum (Pt) layer, and an Au layer stacked in this order, i.e., Ti / Al / Pt / Au. Alternatively, the material of the source S and the drain D may be a Ti layer, a tantalum (Ta) layer, and a Ti layer stacked in this order, i.e., Ti / Ta / Ti. Alternatively, the material of the source S and the drain D may be Au or palladium (Pd).

[0099] In some embodiments, a first gate G1 and a second gate G2 are disposed on the barrier layer 40, located between the source S and the drain D, as shown in FIGS.

[0100] 3, the first gate G1 and the second gate G2 are disposed on the surface of the barrier layer 40 and form Schottky contacts with the barrier layer 40. Alternatively, the first gate G1 and the second gate G2 are disposed on the surface of the cap layer 80 and form Schottky contacts with the barrier layer 40, as shown in FIG.

[0101] The first gate G1 and the second gate G2 can be formed, for example, by using a photolithography and etching process, and the first gate G1 and the second gate G2 can be formed, for example, simultaneously.

[0102] The material of the first gate G1 and the second gate G2 may be, for example, Au or Pd.

[0103] 3 and 4, the first gate G1 is disposed near the source S, and the second gate G2 is disposed near the drain D. In other words, the first gate G1 is disposed between the source S and the second gate G2.

[0104] In some embodiments, the spacing L1 between the first gate field plate GFP1 and the second gate G2 ranges from 0.5 μm to 2.7 μm.

[0105] For example, the distance L1 between the first gate field plate GFP1 and the second gate G2 is 0.7 μm, 1.0 μm, 1.3 μm, 1.5 μm, 1.7 μm, 2.0 μm, 2.3 μm, or 2.5 μm.

[0106] Reducing the distance L1 between the first gate field plate GFP1 and the second gate G2 significantly increases the saturation current of the semiconductor component, thereby increasing its power. However, the knee-point voltage of the semiconductor component also increases, resulting in a decrease in the efficiency of the semiconductor component. In addition, the gate-drain parasitic capacitance Cgd of the semiconductor component increases, reducing the gain characteristics of the semiconductor component. Therefore, to comprehensively meet the performance and reliability requirements of the semiconductor component, the distance L1 between the first gate field plate GFP1 and the second gate G2 is set to a range of 0.5 μm to 2.7 μm.

[0107] In some embodiments, as shown in FIGS. 3 and 4 , the first gate field plate GFP1 is at least partially disposed on a side of the first gate G1 closer to the drain D, the first gate field plate GFP1 is electrically connected to the first gate G1, and a gap exists between the first gate field plate GFP1 and the barrier layer 40.

[0108] For example, as shown in Figures 3 and 4, the first gate field plate GFP1 includes only a portion located closer to the drain D of the first gate G1, and the first gate field plate GFP1 is in contact with and connected to the first gate G1.

[0109] For example, the first gate field plate GFP1 and the first gate G1 are of an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0110] 5, the first gate field plate GFP1 includes a first portion GFP1-1 located closer to the drain D of the first gate G1 and a second portion GFP1-2 located closer to the source S of the first gate G1. Both the first portion GFP1-1 and the second portion GFP1-2 of the first gate field plate GFP1 are in contact with and connected to the first gate G1.

[0111] For example, the first portion GFP1-1 and second portion GFP1-2 of the first gate field plate GFP1 and the first gate G1 have an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0112] The first portion GFP1-1 and the second portion GFP1-2 of the first gate field plate GFP1 are disposed on either side of the first gate G1. When the first gate G1 and the first gate field plate GFP1 are manufactured, the requirements for the alignment boundary accuracy of the first gate field plate GFP1 may not be excessively high. Even if the alignment is inaccurate and the first portion GFP1-1 and the second portion GFP1-2 obtained through manufacturing differ in size, the impact on the function of the first gate field plate GFP1 is small. Furthermore, if the alignment is inaccurate, only the sizes of the first portion GFP1-1 and the second portion GFP1-2 are affected, and the width of the first gate G1 is not affected. This avoids an impact on the performance of the semiconductor component caused by changes in the size of the first gate G1.

[0113] The shape of the first gate field plate GFP1 is not limited to this embodiment of the present application, and the shapes of the gate field plates shown in Figures 3, 4, and 5 are merely examples.

[0114] In some embodiments, as shown in Figures 3, 4, and 5, a first source field plate SFP1 is disposed on the side of the first gate field plate GFP1 that is farther from the substrate 20, and the first source field plate SFP1 is electrically connected to the source S.

[0115] Certainly, one or more interlayer dielectric layers may be disposed between the first source field plate SFP1 and the first gate field plate GFP1 as needed, and the first source field plate SFP1 is electrically connected to the source S through a via hole in the interlayer dielectric layer.

[0116] 3, the side of the first source field plate SFP1 farther from the first gate field plate GFP1 is located between the first gate G1 and the second gate G2. Alternatively, the side of the first source field plate SFP1 farther from the first gate field plate GFP1 overlaps with the second gate G2.

[0117] The first source field plate SFP1 covers the first gate field plate GFP1. In other words, in the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20), the first source field plate SFP1 overlaps with the first gate field plate GFP1.

[0118] For example, in the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20), the side surface of the first source field plate SFP1 closer to the first gate field plate GFP1 overlaps with the first gate field plate GFP1.

[0119] Alternatively, it can be understood as the orthogonal projection of the first source field plate SFP1 onto the substrate 20 overlapping with the orthogonal projection of the first gate field plate GFP1 onto the substrate 20 on the side closer to the first gate field plate GFP1.

[0120] In some embodiments, the first source field plate SFP1 overlaps the first gate G1, but the first source field plate SFP1 does not cover the first gate G1. Alternatively, in some embodiments, the first source field plate SFP1 does not overlap the first gate G1.

[0121] Alternatively, it can be understood that the side of the first source field plate SFP1 closer to the first gate G1 does not extend over the first gate G1.

[0122] By arranging the first source field plate SFP1 only on the side of the first gate field plate GFP1 that is closer to the drain D, the area directly facing the first source field plate SFP1 and the first gate G1 can be reduced, the gate-source parasitic capacitance Cgs of the semiconductor component is reduced, and the effect of the first source field plate SFP1 on the frequency characteristics of the semiconductor component is reduced.

[0123] In some embodiments, the first source field plate SFP1 is in contact with and connected to the source S so as to implement an electrical connection between the first source field plate SFP1 and the source S. The first source field plate SFP1 can be in contact with and connected to the source S, bypassing the first gate G1.

[0124] The material of the first source field plate SFP1 may be, for example, the same as the material of the source S and the drain D. If, in the manufacture of a semiconductor component, the first gate G1 and the second gate G2 are formed first, and then the source S and the drain D are formed, the first source field plate SFP1 may be formed, for example, simultaneously with the source S and the drain D.

[0125] Certainly, a structure such as a dielectric layer or a planar layer may be disposed on the side of the first source field plate SFP1 that is farther from the substrate 20, as needed, but this is not limited to this embodiment of the present application.

[0126] The semiconductor component provided in this example includes a first gate G1 and a second gate G2. When the semiconductor component is in operation, the first gate G1 is configured to receive a drive signal Vgate1 and a radio frequency signal RF, and the second gate G2 is configured to receive a fixed voltage signal Vgate2. Based on this, FIG. 6A is an output curve diagram of the single-gate semiconductor component shown in FIG. 2B, and FIG. 6B is an output characteristic curve of the dual-gate semiconductor component shown in FIG. 3. Comparing FIG. 6A and FIG. 6B, it can be seen that in FIG. 6B, the output voltage of the semiconductor component reaches saturation when the drain D voltage is low (the black dots in the diagram represent the knee-point voltage). Therefore, the knee-point voltage of the semiconductor component provided in this example is significantly lower than that of the semiconductor component shown in FIG. 2B. In FIGS. 6A and 6B, the horizontal axis represents the drain D voltage, and the vertical axis represents the drain D current. FIGS. 6A and 6B are simulations performed when the fixed voltage signal Vgate2 received by the second gate G2 has a constant value (e.g., 2 V). The different curves are curves when the first gate G1 receives different driving signals Vgate1. When Vgate1 is -4.0V and when Vgate1 is -6.0V, the output curves are basically aligned with the horizontal axis. [Table 1]

[0127] As shown in Table 1, when the Vgate2 applied to the second gate G2 is 2 V and the distance L1 between the first gate field plate GFP1 and the second gate G2 is 1.7 μm, simulations show that placing the second gate G2 in the semiconductor component changes the carrier distribution in the channel, reducing the carrier concentration and decreasing the semiconductor current, lowering the knee-point voltage of the semiconductor component, and improving the efficiency of the semiconductor component. As shown in Figure 6B, a smaller Vgate1 indicates a lower knee-point voltage of the semiconductor component. In addition, by disposing the second gate G2 between the first gate G1 and the drain D, the second gate G2 can block the feedback path between the first gate G1 and the drain D, and the second gate G2 can achieve a certain degree of shielding effect to reduce the gate-drain parasitic capacitance Cgd between the first gate G1 and the drain D when the semiconductor component is in an off state (for example, a bias is applied so that the semiconductor component is in an off state, and the voltage of the first gate G1 is −6 V and the drain voltage is 50 V), and can also increase the small signal gain of the semiconductor component (the small signal gain can be increased by about 5 dB compared to that of the semiconductor component shown in FIG. 2B), the current gain cutoff frequency, and the power gain cutoff frequency.

[0128] Example 2

[0129] The main difference between Example 2 and Example 1 is that the semiconductor component in Example 2 is based on the semiconductor component structure in Example 1 and further includes a second gate field plate GFP2.

[0130] As shown in FIG. 7A , a semiconductor component is provided, which mainly includes a substrate 20, a channel layer 30 and a barrier layer 40 stacked in this order on the substrate 20, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1 and a second gate G2 located between the source S and the drain D and arranged on the barrier layer 40, a first gate field plate GFP1 and a second gate field plate GFP2, and a first source field plate SFP1.

[0131] The second gate field plate GFP2 is at least partially disposed on a side of the second gate G2 closer to the drain D. The second gate field plate GFP2 is electrically connected to the second gate G2, and a gap exists between the second gate field plate GFP2 and the barrier layer 40.

[0132] For example, the second gate field plate GFP2 includes only a portion located closer to the drain D of the second gate G2, and the second gate field plate GFP2 is in contact with and connected to the second gate G2.

[0133] For example, the second gate field plate GFP2 and the second gate G2 are of an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0134] 7A, the second gate field plate GFP2 includes a first portion GFP2-1 located on a side closer to the drain D of the second gate G2 and a second portion GFP2-2 located on a side closer to the source S of the second gate G2. Both the first portion GFP2-1 and the second portion GFP2-2 of the second gate field plate GFP2 are in contact with and connected to the second gate G2.

[0135] For example, the first portion GFP2-1 and second portion GFP2-2 of the second gate field plate GFP2 and the second gate G2 have an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0136] The shape of the second gate field plate GFP2 is not limited to this embodiment of the present application, and the shape of the second gate field plate GFP2 shown in Figure 7A is just an example.

[0137] 7A, the value of the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 ranges from 0.5 μm to 2.5 μm. For example, the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.7 μm, 1.0 μm, 1.3 μm, 1.5 μm, 1.7 μm, 2.0 μm, or 2.3 μm.

[0138] In this example, the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is greater than the length L3 of the portion of the first source field plate SFP1 that is located between the first gate field plate GFP1 and the second gate field plate GFP2.

[0139] In this example, the structures of the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1, and the first source field plate SFP1 are the same as those in Example 1. For details, please refer to the relevant descriptions in Example 1. The details will not be described again here.

[0140] 7B, the semiconductor component further includes a nucleation layer 50, a graded buffer layer 60, an insertion layer 70, and a cap layer 80. The structures of the nucleation layer 50, the graded buffer layer 60, the insertion layer 70, and the cap layer 80 are the same as those in Example 1. For details, please refer to the related descriptions in Example 1. The details will not be described again here.

[0141] As shown in Table 2, when the Vgate2 applied to the second gate G2 is 2 V and the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 1.5 μm, simulations show that the placement of the second gate field plate GFP2 within the semiconductor component significantly reduces the electric field strength in the region near the second gate G2. This reduces the likelihood of breakdown of the material in the barrier layer 40, further increasing the breakdown voltage of the semiconductor component and ensuring its performance. Furthermore, the placement of the second gate field plate GFP2 within the semiconductor component provides a certain degree of shielding effect, further expanding the depletion region, reducing the gate-drain parasitic capacitance Cgd between the first gate G1 and the drain D, and improving the small-signal gain, current gain cutoff frequency, and power gain cutoff frequency of the semiconductor component. [Table 2]

[0142] Example 3

[0143] The main difference between Example 3 and Example 2 is that the semiconductor component in Example 3, based on the semiconductor component structure in Example 2, further includes a second source field plate SFP2.

[0144] As shown in Figure 8, a semiconductor component is provided, which mainly includes a substrate 20, a channel layer 30 and a barrier layer 40 stacked in order on the substrate 20, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1 and a second gate G2 located between the source S and the drain D and arranged on the barrier layer 40, a first gate field plate GFP1 and a second gate field plate GFP2, and a first source field plate SFP1 and a second source field plate SFP2.

[0145] The second source field plate SFP2 is disposed on the side of the second gate field plate GFP2 that is farther from the substrate 20 and is electrically connected to the source S.

[0146] Certainly, one or more interlayer dielectric layers can be disposed between the second source field plate SFP2 and the second gate field plate GFP2 as needed. Furthermore, the electrical connection of the second source field plate SFP2 to the source S may mean that the second source field plate SFP2 is electrically connected to the source S directly, or that the second source field plate SFP2 is electrically connected to the first source field plate SFP1, thereby implementing the electrical connection between the second source field plate SFP2 and the source S.

[0147] The second source field plate SFP2 covers the second gate field plate GFP2. In other words, the second source field plate SFP2 overlaps with the second gate field plate GFP2 in the direction perpendicular to the substrate 20 (or in the thickness direction of the substrate 20).

[0148] For example, in the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20), the side surface of the second source field plate SFP2 closer to the second gate field plate GFP2 overlaps with the second gate field plate GFP2.

[0149] Alternatively, it can be understood as the orthogonal projection of the second source field plate SFP2 onto the substrate 20 overlapping with the orthogonal projection of the second gate field plate GFP2 onto the substrate 20 on the side closer to the second gate field plate GFP2.

[0150] In some embodiments, the second source field plate SFP2 overlaps the second gate G2, but the second source field plate SFP2 does not cover the second gate G2, or in some embodiments, the second source field plate SFP2 does not overlap the second gate G2.

[0151] Alternatively, it can be understood that the side of the second source field plate SFP2 closer to the second gate G2 does not extend over the second gate G2.

[0152] By arranging the second source field plate SFP2 only on the side of the second gate field plate GFP2 that is closer to the drain D, the area directly facing the second source field plate SFP2 and the second gate G2 can be reduced, the gate-source parasitic capacitance Cgs of the semiconductor component is reduced, and the effect of the second source field plate SFP2 on the frequency characteristics of the semiconductor component is reduced.

[0153] In some embodiments, the second source field plate SFP2 is in contact with and connected to the first source field plate SFP1 to implement an electrical connection between the second source field plate SFP2 and the first source field plate SFP1. The second source field plate SFP2 can be in contact with and connected to the first source field plate SFP1, bypassing the second gate G2.

[0154] The material of the second source field plate SFP2 may be, for example, the same as the material of the source S and the drain D. The second source field plate SFP2 may be, for example, formed simultaneously with the first source field plate SFP1.

[0155] The length of the second source field plate SFP2 (size in the direction from the source S to the drain D) may be, for example, greater than, less than, or equal to the length of the first source field plate SFP1 (size in the direction from the source S to the drain D).

[0156] The shape of the second source field plate SFP2 is not limited to this embodiment of the present application. The second source field plate SFP2 overlaps the second gate G2 and extends to a position between the second gate G2 and the drain D. The shape of the second source field plate SFP2 shown in FIG. 8 is just an example.

[0157] In this example, the structures of the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1, the second gate field plate GFP2, and the first source field plate SFP1 are the same as those in Example 1. For details, please refer to the relevant descriptions in Example 1. The details will not be described again here.

[0158] In some embodiments, the first gate G1 and the second gate G2 have the same structure, the first gate field plate GFP1 and the second gate field plate GFP2 have the same structure, and the first source field plate SFP1 and the second source field plate SFP2 have the same structure, which makes the structure simple and easy to manufacture.

[0159] In some embodiments, the value of the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 ranges from 0.5 μm to 1.5 μm.

[0160] 8, the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is equal to or greater than the length L3 of the portion of the first source field plate SFP1 that is located between the first gate field plate GFP1 and the second gate field plate GFP2. Alternatively, the first source field plate SFP1 does not overlap the second gate field plate GFP2 in the direction perpendicular to the substrate 20. [Table 3]

[0161] As shown in Table 3, when Vgate2 applied to the second gate G2 is 2 V and the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 1.5 μm, simulations show that when the second source field plate SFP2 is disposed within the semiconductor component, the conductive structure of the second source field plate SFP2 adjusts the electric field distribution between the second gate field plate GFP2 and the drain D, reducing the electric field strength on the side of the second gate G2 closer to the drain D (the electric field strength can be reduced by approximately 55% compared to that of the semiconductor component shown in FIG. 2B), thereby lowering the peak electric field of the semiconductor component and further increasing the breakdown voltage of the semiconductor component. In addition, after the electric field strength is reduced, the possibility of electrons being excited into surface states by a strong electric field is reduced, thereby suppressing the current collapse effect of the semiconductor component. In addition, a second source field plate SFP2 is disposed in the semiconductor component, which can achieve a certain degree of shielding effect, further extend the depletion region, reduce the gate-drain parasitic capacitance Cgd between the first gate G1 and the drain D, and increase the small signal gain (the small signal gain can be increased by about 7 dB compared to that of the semiconductor component shown in FIG. 2B), the current gain cutoff frequency, and the power gain cutoff frequency of the semiconductor component.

[0162] 9, after the second gate G2 is disposed between the first gate G1 and the drain D, as the second gate field plate GFP2 and the second source field plate SFP2 corresponding to the second gate G2 are added, the electric field strength between the first gate G1 and the drain D gradually decreases and the breakdown voltage of the semiconductor component gradually increases. In FIG. 9, the ordinate represents the electric field strength V / cm, and the abscissa represents the position within the semiconductor component.

[0163] 10A, the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is smaller than the length L3 of the portion of the first source field plate SFP1 located between the first gate field plate GFP1 and the second gate field plate GFP2. In other words, the first source field plate SFP1 covers the second gate field plate GFP2. Alternatively, this can be understood as the first source field plate SFP1 overlapping the second gate field plate GFP2 in the direction perpendicular to the substrate 20.

[0164] For example, as shown in FIG. 10A, in the direction perpendicular to the substrate 20, the side surface of the first source field plate SFP1 closer to the second gate G2 overlaps with the second gate field plate GFP2.

[0165] 3 can reduce the gate-drain parasitic capacitance Cgd of the semiconductor component, but can also reduce the saturation current of the semiconductor component. Reducing the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 can mitigate the reduction in saturation current.

[0166] In one implementation, as shown in FIG. 10A, the first source field plate SFP1 is not connected to the second source field plate SFP2.

[0167] Based on reducing the spacing between the first gate field plate GFP1 and the second gate field plate GFP2, the manufacturing process of the first source field plate SFP1 is modified so that the first source field plate SFP1 and the second source field plate SFP2 are not connected. [Table 4]

[0168] As shown in Table 4, when the Vgate2 applied to the second gate G2 is 2 V and the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.5 μm, simulations show that, compared to the structure of FIG. 8, the structure of FIG. 10A shortens the spacing between the first gate field plate GFP1 and the second gate field plate GFP2, resulting in a significant increase in the saturation current of the semiconductor component, but a slight increase in the knee-point voltage and gate-drain parasitic capacitance Cgd, and a slight decrease in the small-signal gain of the semiconductor component. Therefore, to appropriately set the spacing L2 between the first gate G1 and the second gate G2, the requirements for the small-signal gain and knee-point voltage of the semiconductor component can be comprehensively considered as needed.

[0169] In another implementation, the first source field plate SFP1 is connected to the second source field plate SFP2, as shown in FIG. 10B.

[0170] Because the first source field plate SFP1 is connected to the second source field plate SFP2, the first source field plate SFP1 and the second source field plate SFP2 can be manufactured using existing processes without changing the manufacturing process of the first source field plate SFP1. However, as shown in Table 5, when Vgate2 applied to the second gate G2 is 2 V and the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.5 μm, it can be seen through simulation that, compared to the structure of FIG. 10A, in the structure of FIG. 10B, the first source field plate SFP1 is connected to the second source field plate SFP2, resulting in a slight decrease in the small signal gain of the semiconductor component. [Table 5]

[0171] Example 4

[0172] The difference between Example 4 and Examples 1 to 3 is that the semiconductor component further includes a third gate G3 based on the semiconductor component structure provided in Examples 1 to 3.

[0173] 11A , a semiconductor component is provided, which mainly includes a substrate 20, a channel layer 30 and a barrier layer 40 stacked in this order on the substrate 20, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1, a second gate G2, and a third gate G3 positioned between the source S and the drain D and arranged on the barrier layer 40, a first gate field plate GFP1 and a second gate field plate GFP2, and a first source field plate SFP1 and a second source field plate SFP2.

[0174] As shown in FIG. 11A, the first gate G1, the second gate G2, and the third gate G3 are located between the source S and the drain D and are disposed on the barrier layer 40.

[0175] For example, as shown in FIG. 11A, a first gate G1, a second gate G2, and a third gate G3 are disposed on the surface of the barrier layer 40 and form Schottky contacts with the barrier layer 40.

[0176] The first gate G1, the second gate G2, and the third gate G3 are formed, for example, by using a photolithography and etching process, and the first gate G1, the second gate G2, and the third gate G3 are formed, for example, simultaneously.

[0177] It can be understood that a fourth gate or more gates may be disposed between the third gate G3 and the drain D. This is not limited to this embodiment of the present application. The gates may be disposed appropriately as needed.

[0178] Similar to the principle of adding the second gate G2 in Example 1, the third gate G3 is added between the second gate G2 and the drain D, and the third gate G3 can achieve a certain degree of shielding effect to reduce the gate-drain parasitic capacitance Cgd between the first gate G1 and the drain D, and also increase the small signal gain, current gain cutoff frequency, and power gain cutoff frequency of the semiconductor component.

[0179] In some embodiments, as shown in FIG. 11B, the semiconductor component further includes a third gate field plate GFP3.

[0180] The third gate field plate GFP3 is at least partially disposed on a side of the third gate G3 closer to the drain D. The third gate field plate GFP3 is electrically connected to the third gate G3, and a gap exists between the third gate field plate GFP3 and the barrier layer 40.

[0181] For example, the third gate field plate GFP3 includes only a portion located closer to the drain D of the third gate G3, and the third gate field plate GFP3 is in contact with and connected to the third gate G3.

[0182] For example, the third gate field plate GFP3 and the third gate G3 are of an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0183] 11B, the third gate field plate GFP3 includes a first portion GFP3-1 located closer to the drain D of the third gate G3 and a second portion GFP3-2 located closer to the source S of the third gate G3. Both the first portion GFP3-1 and the second portion GFP3-2 of the third gate field plate GFP3 are in contact with and connected to the third gate G3.

[0184] For example, the first portion GFP3-1 and second portion GFP3-2 of the third gate field plate GFP3 and the third gate G3 have an integrally formed structure and are formed simultaneously in the same manufacturing process.

[0185] The shape of the third gate field plate GFP3 is not limited to this embodiment of the application, and the shape of the third gate field plate GFP3 shown in FIG. 11B is merely an example.

[0186] By disposing the third gate field plate GFP3 within the semiconductor component, the electric field strength in the region near the third gate G3 can be significantly reduced. This reduces the possibility of breakdown of the material of the barrier layer 40, further increasing the breakdown voltage of the semiconductor component and ensuring the performance of the semiconductor component. Furthermore, by disposing the third gate field plate GFP3 within the semiconductor component, the third gate field plate GFP3 achieves a certain degree of shielding effect, further expanding the depletion region, reducing the gate-drain parasitic capacitance Cgd between the first gate G1 and the drain D, and increasing the small-signal gain, current gain cutoff frequency, and power gain cutoff frequency of the semiconductor component.

[0187] 11C, the semiconductor component further includes a third source field plate SFP3. The third source field plate SFP3 is disposed on the side of the third gate field plate GFP3 that is farther from the substrate 20 and is electrically connected to the source S.

[0188] The third source field plate SFP3 covers the third gate field plate GFP3. In other words, the third source field plate SFP3 overlaps with the third gate field plate GFP3 in the direction perpendicular to the substrate 20 (or in the thickness direction of the substrate 20).

[0189] For example, in the direction perpendicular to the substrate 20 (or understood as the thickness direction of the substrate 20), the side of the third source field plate SFP3 closer to the third gate field plate GFP3 overlaps with the third gate field plate GFP3.

[0190] Alternatively, it can be understood as the orthogonal projection of the third source field plate SFP3 onto the substrate 20 overlapping with the orthogonal projection of the third gate field plate GFP3 onto the substrate 20 on the side closer to the third gate field plate GFP3.

[0191] According to various structures of the second source field plate SFP2 and various distances between the second gate G2 and the third gate G3, the second source field plate SFP2 and the third source field plate SFP3 may or may not be connected. Figure 11C is shown using an example in which the second source field plate SFP2 is connected to the third source field plate SFP3.

[0192] In some embodiments, the first gate G1, the second gate G2, and the third gate G3 have the same structure, the first gate field plate GFP1, the second gate field plate GFP2, and the third gate field plate GFP3 have the same structure, and the first source field plate SFP1, the second source field plate SFP2, and the third source field plate SFP3 have the same structure, which makes the structure simple and easy to manufacture.

[0193] As shown in Table 6, when Vgate2 applied to the second gate G2 is 2 V, the spacing L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.5 μm, and the spacing between the second gate field plate GFP2 and the third gate field plate GFP3 is 0.5 μm, it can be seen through simulation that by further increasing the number of gates, gate field plates, and source field plates, the gate-drain parasitic capacitance Cgd can be further reduced and the small-signal gain of the semiconductor component can be increased. [Table 6]

[0194] Example 5

[0195] The difference between Example 5 and Examples 2 to 4 is that the first gate G1 is positioned closer to the drain D than the second gate G2.

[0196] As an example, a comparison with the semiconductor component provided in Example 2 will be used. As shown in Fig. 12, a semiconductor component is provided, which mainly includes a substrate 20, a channel layer 30 and a barrier layer 40 stacked in this order on the substrate 20, a source S and a drain D arranged side by side on the barrier layer 40, a first gate G1 and a second gate G2 located between the source S and the drain D and arranged on the barrier layer 40, a first gate field plate GFP1 and a first source field plate SFP1.

[0197] It should be emphasized that in this example semiconductor component, the first gate G1 is arranged between the second gate G2 and the drain D, as shown in FIG.

[0198] In this example, the structures of the substrate 20, the channel layer 30 and the barrier layer 40, the source S and the drain D, the first gate G1 and the second gate G2, the first gate field plate GFP1, the second gate field plate GFP2, and the first source field plate SFP1 are the same as those in Example 2. For details, please refer to the relevant descriptions in Example 2. The details will not be described again here. [Table 7]

[0199] As shown in Table 7, when Vgate2 applied to the second gate G2 is 2 V and the distance L2 between the first gate field plate GFP1 and the second gate field plate GFP2 is 0.5 μm, it is found through simulation that the saturation current and small signal gain of the semiconductor component are large when the first source field plate SFP1 is disposed on the first gate G1 close to the drain D and the second source field plate SFP2 is not disposed on the second gate G2 away from the drain D. Assuming that the saturation current and small signal gain of the semiconductor component are the same, compared to the semiconductor component shown in FIG. 10B, the structure of the semiconductor component is simpler and the gate-source parasitic capacitance Cgs of the semiconductor component can be reduced.

[0200] It can be seen from the above description of the semiconductor component provided in the embodiments of this application that by appropriately designing the number of gates, the number of gate field plates, the number of source field plates, the structure of the source field plates, and the spacing between the gate field plates according to the actual requirements for the semiconductor component, it is possible to effectively balance the radio frequency characteristics of the semiconductor component, including power (related to the saturation current), small signal gain (related to the gate-drain parasitic capacitance Cgs), and efficiency (related to the knee-point voltage).

[0201] The semiconductor components provided in the embodiments of this application may not only be used in GaN HEMT components, but also in other III-V semiconductor components, such as GaAs (gallium arsenide) HEMTs.

[0202] The above description is merely a specific implementation of this application and is not intended to limit the scope of protection of this application. Any modifications or substitutions within the technical scope disclosed in this application will fall within the scope of protection of this application. Therefore, the scope of protection of this application is subject to the scope of protection of the claims.

Claims

1. A substrate; a channel layer and a barrier layer stacked in this order on the substrate; a source and a drain disposed on the barrier layer; a first gate and a second gate disposed on the barrier layer and located between the source and the drain, the second gate being disposed between the first gate and the drain; a first gate field plate having a first portion disposed on a side of the first gate proximate to the drain; a first source field plate disposed on a side of the first gate field plate that is remote from the substrate; and the first source field plate overlaps the first portion of the first gate field plate but does not cover the first gate; Semiconductor components.

2. 10. The semiconductor component of claim 1, further comprising a second gate field plate, the second gate field plate being at least partially located on a side of the second gate proximal to the drain.

3. 3. The semiconductor component of claim 2, wherein the first source field plate overlies the second gate field plate.

4. 4. The semiconductor component of claim 2, further comprising a second source field plate, the second source field plate overlying the second gate field plate.

5. The semiconductor component of claim 4 , wherein the first source field plate is connected to the second source field plate.

6. The second gate field plate has a first portion disposed on a side of the second gate closer to the drain, the semiconductor component further comprises a second source field plate; the second source field plate overlaps the first portion of the second gate field plate but does not cover the second gate; The semiconductor component of claim 2 .

7. 7. The semiconductor component of claim 1, wherein the spacing between the first gate field plate and the second gate is in the range of 0.5 [mu]m to 2.7 [mu]m.

8. 8. The semiconductor component of claim 1, wherein the first gate field plate further comprises a second portion disposed on a side of the first gate closer to the source, the first portion and the second portion separately contacting and connected to the first gate.

9. 9. A semiconductor component according to claim 1, further comprising a third gate, the third gate being arranged between the second gate and the drain.

10. the semiconductor component further comprises a third gate field plate; 10. The semiconductor component of claim 9, wherein the third gate field plate is at least partially disposed on a side of the third gate proximal to the drain.

11. 11. The semiconductor component of claim 10, further comprising a third source field plate, the third source field plate overlying the third gate field plate.

12. An electronic device having a semiconductor component and an antenna, the semiconductor component configured to amplify a radio frequency signal and output the amplified radio frequency signal to the antenna for radiation; The semiconductor component is a semiconductor component according to any one of claims 1 to 11. electronic equipment.

13. 1. An electronic device having a semiconductor component and a printed circuit board electrically connected to the semiconductor component, The semiconductor component is a semiconductor component according to any one of claims 1 to 11, wherein the substrate of the semiconductor component is a conductive substrate. electronic equipment.

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