Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing the generation of wrapping and twisting.SOLUTION: A semiconductor device includes: a lower substrate 100; a semiconductor element 300 that is arranged at a space between the lower substrate and an upper substrate, and is mounted on the lower substrate; and a plurality of bonding materials 20 that bonds conductive pads of the upper and lower substrates. The lower substrate comprises: a first side 151 and a second side 152 extended in parallel to a first direction; and a third side 153 and a fourth side 154 extended in parallel to a second direction vertical to the first direction. The semiconductor element comprises: a fifth side 355 and a sixth side 356 extended in parallel to the first direction; and a seventh side 357 and an eighth side 358 extended in parallel to the second direction. The fifth and sixth sides are longer than the seventh and eighth sides. A part of the bonding materials forms a first column between the first side and the fifth side, forms a second column between the second side and the sixth side, forms a third column between the third side and the seventh side, and forms a fourth column between the fourth side and the eighth side. The numbers of the third and fourth columns are smaller than those of the first and second columns.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device in which a semiconductor chip is provided between an upper substrate and a lower substrate has been disclosed (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2007 / 069606 Summary of the Invention [Problem to be solved by the invention]

[0004] Although the semiconductor device described in Patent Document 1 achieves the intended purpose, when the shapes of semiconductor chips become more diverse, warping or undulation may occur in the semiconductor device depending on the shape of the semiconductor chip.

[0005] An object of the present disclosure is to provide a semiconductor device that can suppress the occurrence of warping and waviness. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a first substrate having a first main surface and a plurality of first conductive pads on the first main surface, a second substrate having a second main surface opposite to the first main surface and a plurality of second conductive pads on the second main surface, a semiconductor element disposed between the first substrate and the second substrate and mounted on the first main surface of the first substrate, and a plurality of bonding materials bonding the first conductive pads and the second conductive pads; a resin filled between the first substrate and the second substrate; and the bonding material has a conductive core ball containing copper and a solder layer covering a surface of the conductive core ball, and the direction of warping due to thermal deformation of the first substrate and the direction of warping due to thermal deformation of the second substrate are opposite to each other;In a plan view from a direction perpendicular to the first main surface, the first substrate has a rectangular planar shape with first and second sides extending parallel to a first direction and third and fourth sides extending parallel to a second direction perpendicular to the first direction, the semiconductor element has a rectangular planar shape with fifth and sixth sides extending parallel to the first direction and seventh and eighth sides extending parallel to the second direction, the fifth and sixth sides being longer than the seventh and eighth sides, the fifth side being closer to the first side than the sixth side, and the seventh side being closer to the third side than the eighth side, and some of the plurality of bonding materials are spaced apart from the first side and the eighth side. a semiconductor device is provided in which some of the bonding materials are arranged in two or more first rows extending parallel to the first direction between the second side and the fifth side, some of the bonding materials are arranged in two or more second rows extending parallel to the first direction between the second side and the sixth side, some of the bonding materials are arranged in one or more third rows extending parallel to the second direction between the third side and the seventh side, and some of the bonding materials are arranged in one or more fourth rows extending parallel to the second direction between the fourth side and the eighth side, and the number of the third rows and the number of the fourth rows are smaller than the number of the first rows and the number of the second rows. [Effects of the Invention]

[0007] According to the disclosed technology, the occurrence of warping and undulation can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] 5A and 5B are schematic diagrams illustrating the arrangement of a bonding material on a lower substrate in the embodiment. [Figure 3] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. [Figure 5] 10A to 10C are cross-sectional views (part 3) illustrating the method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 10A and 10B are cross-sectional views (part 4) illustrating the method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 5 is a cross-sectional view (part 5) showing the method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 6 is a cross-sectional view (part 6) illustrating the method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 10 is a schematic diagram showing the arrangement of a bonding material on a lower substrate in a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side being the upper side and the Z2 side being the lower side. A planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side. However, the semiconductor device can be used upside down or positioned at any angle.

[0010] 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0011] The semiconductor device 10 according to the embodiment has a lower substrate 100, an upper substrate 200, and a semiconductor element 300. The lower substrate 100 has an upper surface 101 that is approximately parallel to the XY plane, and the upper substrate 200 has a lower surface 201 that is approximately parallel to the XY plane. The upper substrate 200 is disposed above the lower substrate 100 (Z1 side). The lower surface 201 of the upper substrate 200 faces the upper surface 101 of the lower substrate 100. The lower substrate 100 is an example of a first substrate, and the upper substrate 200 is an example of a second substrate. The upper surface 101 of the lower substrate 100 is an example of a first main surface, and the lower surface 201 of the upper substrate 200 is an example of a second main surface.

[0012] The lower substrate 100 has, for example, a core layer 110, a build-up layer 120 provided on the upper surface of the core layer 110, and a build-up layer 130 provided on the lower surface of the core layer 110. The lower substrate 100 may be a coreless substrate that does not include a core layer.

[0013] The core layer 110 has an insulating substrate 111 in which a through hole 114 is formed, a through electrode 112 formed on the inner wall surface of the through hole 114, and a filler material 113 filled inside the through electrode 112. For example, the material of the core layer 110 is glass epoxy or the like, and the material of the through electrode 112 is copper or the like. Alternatively, a through electrode 112 in which the filler material 113 is not present and the inside of the through hole 114 is entirely filled with metal may be used.

[0014] The buildup layer 120 has an insulating layer 121, a wiring layer 122, and a solder resist layer 123. The solder resist layer 123 has an opening 123A for connection to the upper substrate 200 and an opening 123B for mounting the semiconductor element 300. The wiring layer 122 includes, on the uppermost surface of the insulating layer 121, a plurality of conductive pads 124A for connection to the upper substrate 200 and a plurality of conductive pads 124B for mounting the semiconductor element 300. The conductive pads 124A are exposed from the opening 123A, and the conductive pads 124B are exposed from the opening 123B. The wiring layer 122 is made of a conductor such as copper. The conductive pads 124A are an example of a first conductive pad.

[0015] The build-up layer 130 has an insulating layer 131, a wiring layer 132, and a solder resist layer 133. The solder resist layer 133 has openings 133A for external connection. The wiring layer 132 includes conductive pads 134 on the bottom surface of the insulating layer 131. The conductive pads 134 are exposed through the openings 133A. The wiring layer 132 is made of a conductor such as copper. Solder balls 135 are provided on the conductive pads 134. Note that there are also cases where the solder balls 135 are not provided and the conductive pads 134 are directly connected to electrodes of an external device.

[0016] The conductive pads 124A, 124B, and 134 are electrically connected via the wiring layer 122, the through electrodes 112, and the wiring layer 132. The number of insulating layers 121 and wiring layers 122 included in the buildup layer 120, and the number of insulating layers 131 and wiring layers 132 included in the buildup layer 130 are not particularly limited.

[0017] The semiconductor element 300 is flip-chip mounted on the upper surface 101 of the lower substrate 100. That is, the bumps 301 of the semiconductor element 300 are electrically connected to the conductive pads 124B of the lower substrate 100 via the bonding material 310. The bonding material 310 is made of, for example, solder. An underfill material 320 is filled between the semiconductor element 300 and the lower substrate 100.

[0018] The upper substrate 200 has, for example, a core layer 210, a plurality of conductive pads 211, a plurality of conductive pads 212, a solder resist layer 214, and a solder resist layer 215. However, the upper substrate 200 may be a coreless substrate that does not include a core layer.

[0019] The conductive pad 211 is provided on the lower surface of the core layer 210, and the conductive pad 212 is provided on the upper surface of the core layer 210. The conductive pad 212 is connected to the conductive pad 211 through a via hole 213 formed in the core layer 210. The conductive pads 211 and 212 are made of a conductor such as copper. The conductive pad 211 is an example of a second conductive pad.

[0020] A solder resist layer 214 covers the lower surface of the core layer 210. An opening 214A for connection to the lower substrate 100 is formed in the solder resist layer 214. The conductive pad 211 is exposed from the opening 214A. A solder resist layer 215 covers the upper surface of the core layer 210. An opening 215A for external connection is formed in the solder resist layer 215. The conductive pad 212 is exposed from the opening 215A. The conductive pad 212 is used to mount electronic components such as semiconductor elements, passive elements, or other wiring boards on the upper substrate 200.

[0021] The semiconductor device 10 has a plurality of bonding materials 20 that bond a plurality of conductive pads 124A of the lower substrate 100 to a plurality of conductive pads 211 of the upper substrate 200. The bonding materials 20 have, for example, copper-core balls 21 and solder layers 22 that cover the surfaces of the copper-core balls 21. The bonding materials 20 are, for example, solder balls with copper cores. The bonding materials 20 may be composed of metal pillars and a solder layer that covers the surfaces of the pillars. Copper can be used as the metal, and the pillars may be not only cylindrical but also rectangular pillars, and a Ni layer may be formed on the surface of the pillars.

[0022] The conductive pad 124A of the lower substrate 100 and the conductive pad 211 of the upper substrate 200 face each other. The copper core ball 21 is in contact with both the conductive pad 124A and the conductive pad 211. The shape of the copper core ball 21 may be spherical or ellipsoidal. A Ni layer may be formed on the surface of the copper core ball 21.

[0023] The solder layer 22 may be in contact with both the conductive pad 124A and the conductive pad 211. The material of the solder layer 22 is, for example, Sn (tin), Sn-Ag (silver), Sn-Cu, or Sn-Ag-Cu based Pb (lead)-free solder.

[0024] Here, the arrangement of the bonding material 20 will be described in detail. Fig. 2 is a schematic diagram showing the arrangement of the bonding material on the lower substrate in this embodiment. Fig. 1 corresponds to a cross-sectional view taken along line II in Fig. 2.

[0025] The lower substrate 100 has a planar shape including a first side 151 and a second side 152 extending parallel to the X1-X2 direction and a third side 153 and a fourth side 154 extending parallel to the Y1-Y2 direction in a plan view. The first side 151 is on the Y1 side of the second side 152, and the second side 152 is on the Y2 side of the first side 151. The third side 153 is on the X1 side of the fourth side 154, and the fourth side 154 is on the X2 side of the third side 153. For example, the lengths of the third side 153 and the fourth side 154 are 0.95 to 1.05 times the lengths of the first side 151 and the second side 152. The planar shape of the lower substrate 100 may be square. That is, the lengths of the third side 153 and the fourth side 154 may be equal to the lengths of the first side 151 and the second side 152.

[0026] In a plan view, the semiconductor element 300 has a planar shape including a fifth side 355 and a sixth side 356 extending parallel to the X1-X2 direction, and a seventh side 357 and an eighth side 358 extending parallel to the Y1-Y2 direction. The fifth side 355 is on the Y1 side of the sixth side 356, and the sixth side 356 is on the Y2 side of the fifth side 355. The seventh side 357 is on the X1 side of the eighth side 358, and the eighth side 358 is on the X2 side of the seventh side 357. The fifth side 355 is closer to the first side 151 than the sixth side 356, the sixth side 356 is closer to the second side 152 than the fifth side 355, the seventh side 357 is closer to the third side 153 than the eighth side 358, and the eighth side 358 is closer to the fourth side 154 than the seventh side 357. The fifth side 355 and the sixth side 356 are longer than the seventh side 357 and the eighth side 358 .

[0027] In a plan view, the semiconductor element 300 is disposed approximately at the center of the lower substrate 100. The plurality of bonding materials 20 are regularly arranged around the semiconductor element 300. Some of the plurality of bonding materials 20 are arranged between the first side 151 and the fifth side 355 to form two first rows extending parallel to the X1-X2 direction, and some of the plurality of bonding materials 20 are arranged between the second side 152 and the sixth side 356 to form two second rows extending parallel to the X1-X2 direction. Some of the plurality of bonding materials 20 are arranged between the third side 153 and the seventh side 357 to form a third row extending parallel to the Y1-Y2 direction, and some of the plurality of bonding materials 20 are arranged between the fourth side 154 and the eighth side 358 to form a fourth row extending parallel to the Y1-Y2 direction. In this manner, in this embodiment, the number of third columns and the number of fourth columns are smaller than the number of first columns and the number of second columns.

[0028] The plurality of conductive pads 124A of the lower substrate 100 and the plurality of conductive pads 211 of the upper substrate 200 are also arranged regularly around the semiconductor element 300 in plan view so as to correspond to the plurality of bonding materials 20.

[0029] A molding resin 40 is filled between the upper substrate 200 and the lower substrate 100, and the upper substrate 200 is fixed to the lower substrate 100. The distance between the upper substrate 200 and the lower substrate 100 is maintained by a copper core ball 21.

[0030] Next, a method for manufacturing the semiconductor device 10 according to the embodiment will be described. Figures 3 to 8 are cross-sectional views showing a method for manufacturing the semiconductor device 10 according to the embodiment.

[0031] First, as shown in Fig. 3, the lower substrate 100 is prepared. As described above, the lower substrate 100 has the conductive pads 124A and 124B. Next, for example, the bonding material 310 is formed on the conductive pads 124B. The bonding material 310 can be formed by electrolytic plating or the like.

[0032] 4, the semiconductor element 300 on which the bumps 301 are formed is flip-chip mounted on the lower substrate 100. That is, the bumps 301 are electrically connected to the conductive pads 124B of the lower substrate 100 via the bonding material 310. Next, an underfill material 320 is filled between the semiconductor element 300 and the lower substrate 100.

[0033] 5, an upper substrate 200 is prepared. As described above, the upper substrate 200 has conductive pads 211 and the like. Next, copper-core solder balls are mounted on the conductive pads 211 as the bonding material 20. The bonding material 20 has spherical copper-core balls 21 and a solder layer 22 provided on the outer periphery of the copper-core balls 21. A Ni layer may be formed on the surface of the copper-core balls 21.

[0034] After filling the gap between the semiconductor element 300 and the lower substrate 100 with the underfill material 320 and mounting the bonding material 20, the upper substrate 200 is placed on the lower substrate 100 so that the bonding material 20 contacts the conductive pads 124A, while providing a molding resin 40 between the lower substrate 100 and the upper substrate 200, as shown in Fig. 6. The semiconductor element 300 is disposed between the lower substrate 100 and the upper substrate 200.

[0035] Next, the solder layer 22 is reflowed. As a result, as shown in Fig. 7, the solder layer 22 melts and solidifies, and the copper core ball 21 comes into contact with the conductive pad 124A. An alloy layer (not shown) is formed from the components of the solder layer 22 (e.g., tin), the components of the conductive pad 124A (e.g., copper), and the components of the conductive pad 211 (e.g., copper). The reflow temperature is, for example, about 260°C. The solder layer 22 may also be melted by pressing a heated tool against it.

[0036] Next, as shown in FIG. 8, solder balls 135 are formed on the conductive pads 134.

[0037] In this manner, the semiconductor device 10 according to the embodiment can be manufactured.

[0038] It is also possible to not provide the mold resin 40 when placing the upper substrate 200 on the lower substrate 100, but to provide the mold resin 40 after reflowing the solder layer 22. It is also possible to not provide the mold resin 40 when placing the upper substrate 200 on the lower substrate 100, but to provide the mold resin 40 when reflowing the solder layer 22.

[0039] Here, the effects of this embodiment will be described in comparison with a reference example. Fig. 9 is a schematic diagram showing the arrangement of the bonding material on the lower substrate in the reference example.

[0040] 9, some of the bonding materials 20 are arranged between the third side 153 and the seventh side 357 to form two third rows extending parallel to the Y1-Y2 direction, and some of the bonding materials 20 are arranged between the fourth side 154 and the eighth side 358 to form two fourth rows extending parallel to the Y1-Y2 direction. Thus, in the reference example, the number of third rows and the number of fourth rows are equal to the number of first rows and the number of second rows. The other configurations are the same as those of this embodiment.

[0041] In both the present embodiment and the reference example, during manufacturing, the lower substrate 100 is thermally deformed, for example, during reflow of the solder layer 22. After the solder layer 22 has solidified, the thermal deformation of the lower substrate 100 is restrained by the upper substrate 200 via the bonding material 20.

[0042] Furthermore, the semiconductor element 300 also undergoes thermal deformation, but the coefficient of thermal expansion (CTE) of the semiconductor element 300 is significantly smaller than that of the lower substrate 100. Therefore, the thermal deformation of the semiconductor element 300 is significantly smaller than that of the lower substrate 100. Therefore, the thermal deformation of the lower substrate 100 is also restricted by the semiconductor element 300.

[0043] In the reference example, because the number of third columns and the number of fourth columns are equal to the number of first columns and the number of second columns, thermal deformation of the lower substrate 100 in the X1-X2 direction and thermal deformation in the Y1-Y2 direction are constrained by the upper substrate 200 to the same extent. Furthermore, the fifth side 355 and the sixth side 356 of the semiconductor element 300 are longer than the seventh side 357 and the eighth side 358. Therefore, the semiconductor element 300 constrains thermal deformation of the lower substrate 100 in the X1-X2 direction more than thermal deformation in the Y1-Y2 direction. Therefore, in the reference example, the lower substrate 100 is more likely to thermally deform in the X1-X2 direction than in the Y1-Y2 direction. Therefore, significant anisotropy may occur in the thermal deformation of the lower substrate 100 within the XY plane. The greater the anisotropy of thermal deformation, the more likely the semiconductor device is to warp or undulate.

[0044] On the other hand, in this embodiment, the number of third columns and the number of fourth columns are fewer than the number of first columns and the number of second columns. Therefore, the upper substrate 200 restrains the thermal deformation of the lower substrate 100 in the Y1-Y2 direction more than the thermal deformation in the X1-X2 direction. Also, as in the reference example, the semiconductor element 300 restrains the thermal deformation of the lower substrate 100 in the X1-X2 direction more than the thermal deformation in the Y1-Y2 direction. Therefore, in this embodiment, the restraint of the thermal deformation of the lower substrate 100 by the upper substrate 200 and the restraint of the thermal deformation of the lower substrate 100 by the semiconductor element 300 reduce the anisotropy of the thermal deformation of the lower substrate 100. Therefore, warping and undulation of the semiconductor device 10 due to the anisotropy of the thermal deformation of the lower substrate 100 can be suppressed.

[0045] A first distance L1 between the fifth side 355 and the first row of the bonding material 20 and a first distance L2 between the sixth side 356 and the first row of the bonding material 20 The second column of The second distance L2 between the seventh side 357 and the third row of bonding materials 20 is preferably 1.5 times or less the third distance L3 between the seventh side 357 and the third row of bonding materials 20, and is also preferably 1.5 times or less the fourth distance L4 between the eighth side 358 and the fourth row of bonding materials 20. This is to reduce the anisotropy of thermal contraction of the lower substrate 100. The first distance L1 and the second distance L2 are more preferably 1.3 times or less the third distance L3 and 1.3 times or less the fourth distance L4, and even more preferably 1.1 times or less the third distance L3 and 1.1 times or less the fourth distance L4.

[0046] The plurality of bonding materials 20 are preferably arranged regularly in a grid pattern in a plan view, but due to restrictions on wiring routing, etc., there may be areas where the bonding materials 20 are missing.

[0047] As long as the number of third columns and the number of fourth columns are less than the number of first columns and the number of second columns, the number of first columns, the number of second columns, the number of third columns, and the number of fourth columns are not limited. For example, if the number of first columns and the number of second columns are 3 and the number in the third column and the number in the fourth column are 1 In addition, the number of first columns and the number of second columns may be 3 and the number in the third column and the number in the fourth column are 2 The number of first columns, the number of second columns, the number of third columns and the number of fourth columns may be greater.

[0048] It is preferable that the direction of warping due to thermal deformation of the lower substrate 100, on which the semiconductor element 300 and the bonding material 20 are not provided, is opposite to the direction of warping due to thermal deformation of the upper substrate 200, on which the bonding material 20 is not provided. For example, when the lower substrate 100 warps convexly, it is preferable that the upper substrate 200 warps concavely.

[0049] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0050] 10 Semiconductor devices 20 Bonding material 21 Copper Core Balls 22 solder layer 100 Lower board 101 Top surface 124A, 124B Conductive Pads 200 Upper board 201 Bottom surface 211 Conductive Pad 300 Semiconductor elements

Claims

1. a first substrate having a first major surface and a plurality of first conductive pads on the first major surface; a second substrate having a second main surface opposite to the first main surface and including a plurality of second conductive pads on the second main surface; a semiconductor element disposed between the first substrate and the second substrate and mounted on the first main surface of the first substrate; a plurality of bonding materials for bonding the first conductive pad and the second conductive pad; a resin filled between the first substrate and the second substrate; and The bonding material is A conductive core ball containing copper; a solder layer covering the surface of the conductive core ball; and a direction of warpage due to thermal deformation of the first substrate and a direction of warpage due to thermal deformation of the second substrate are opposite to each other; In a plan view from a direction perpendicular to the first main surface, the first substrate has a rectangular planar shape including first and second sides extending parallel to a first direction, and third and fourth sides extending parallel to a second direction perpendicular to the first direction; the semiconductor element has a rectangular planar shape with fifth and sixth sides extending parallel to the first direction and seventh and eighth sides extending parallel to the second direction, the fifth side and the sixth side are longer than the seventh side and the eighth side, the fifth side is closer to the first side than the sixth side, the seventh side is closer to the third side than the eighth side, some of the plurality of bonding materials are arranged between the first side and the fifth side to form two or more first rows extending parallel to the first direction; some of the plurality of bonding materials are arranged in two or more second rows extending parallel to the first direction between the second side and the sixth side; some of the plurality of bonding materials are arranged between the third side and the seventh side to form one or more third rows extending parallel to the second direction, some of the plurality of bonding materials are arranged between the fourth side and the eighth side to form one or more fourth rows extending parallel to the second direction; The number of the third columns and the number of the fourth columns are smaller than the number of the first columns and the number of the second columns.

2. A first distance between the fifth side and the first row and a second distance between the sixth side and the second row are: is equal to or less than 1.5 times the third distance between the seventh side and the third row; and 2. The semiconductor device according to claim 1, wherein the distance is 1.5 times or less of a fourth distance between the eighth side and the fourth row.

3. 3. The semiconductor device according to claim 1, wherein the lengths of the third side and the fourth side are 0.95 to 1.05 times the lengths of the first side and the second side.

4. A semiconductor device described in any one of claims 1 to 3, characterized in that the number of the third columns and the number of the fourth columns are each 2 or more.

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