Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of a semiconductor device with a field plate section.SOLUTION: On the main surface of a semiconductor substrate SB that constitutes the semiconductor device, an insulating film ZF is formed to cover a field plate portion FP, a metal pattern thicker than the field plate portion FP is formed on the insulating film ZF, and a protective film PF is formed on the insulating film ZF to cover the metal pattern. The field plate portion FP is made of polycrystalline silicon, and the insulating film ZF is made of a laminated film of one or more layers of silicon nitride film and one or more layers of silicon oxide film.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, in a semiconductor device having a field plate portion and a method for manufacturing the same. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2019-62031 (Patent Document 1) and International Publication No. WO2013 / 069408 (Patent Document 2) describe technology related to a semiconductor device having a resistive field plate portion, and Japanese Patent Laid-Open Publication No. 2015-230965 (Patent Document 2) describes technology related to metal wiring for suppressing electric field concentration. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-62031 [Patent Document 2] International Publication No. WO2013 / 069408 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-230965 Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable to improve the reliability of a semiconductor device having a field plate portion.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate, a field plate formed on a major surface of the semiconductor substrate with a first insulating film interposed therebetween, and a second insulating film formed on the major surface of the semiconductor substrate to cover the first insulating film and the field plate. The semiconductor device further includes a first metal pattern and a second metal pattern formed on the second insulating film, and an insulating protective film formed on the second insulating film to cover the first metal pattern and the second metal pattern. The first metal pattern and the second metal pattern are each electrically connected to the field plate and are thicker than the field plate. The field plate is made of polycrystalline silicon, and the second insulating film is a stacked film of one or more silicon nitride films and one or more silicon oxide films. [Effects of the Invention]

[0007] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a bottom view of the semiconductor device according to the embodiment; [Figure 3] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 4] 1 is a plan view of a main part of a semiconductor device according to an embodiment; [Figure 5] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 6] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 7] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 8] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 9] 1 is a cross-sectional view of a main part of a semiconductor device during a manufacturing process according to an embodiment of the present invention; [Figure 10]10 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 16. [Figure 18] FIG. 18 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. [Figure 19] FIG. 19 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 18. [Figure 20] FIG. 2 is a cross-sectional view of a main part of a semiconductor device according to a first studied example. [Figure 21] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second studied example. [Figure 22] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third studied example. [Figure 23] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a first modified example. [Figure 24] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second modified example. [Figure 25] FIG. 11 is a plan view of a main part of a semiconductor device according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0010] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0011] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0012] (Embodiment 1) <About the structure of semiconductor devices> The structure of the semiconductor device CP of this embodiment will be described with reference to FIGS. 1 to 9. FIG. 1 is a top view of the semiconductor device CP of this embodiment, and FIG. 2 is a bottom view (rear view) of the semiconductor device CP of this embodiment. FIG. 3 is a plan perspective view of the semiconductor device CP of this embodiment, and FIG. 4 is a plan view of a main part of the semiconductor device CP of this embodiment. FIG. 5 is a plan perspective view of the semiconductor device CP of this embodiment, and the formation positions of the p-type semiconductor region FPR and the insulating film IL1 are indicated by hatching. FIGS. 6 to 8 are cross-sectional views of a main part of the semiconductor device CP of this embodiment. FIG. 4 corresponds to a partially enlarged plan view of the region RG1 surrounded by a dotted line in FIG. 1. Also, FIG. 6 corresponds to a cross-sectional view taken along the line A1-A1 in FIG. 4. 7 and 8 are cross-sectional views of key parts of the element region DR shown in FIG. 3, with FIG. 7 corresponding to a cross-sectional view of a region where the emitter electrode EE is exposed from an opening in the protective film PF (opening for the emitter pad), and FIG. 8 corresponding to a cross-sectional view of a region where the emitter electrode EE is covered by the protective film PF.

[0013] The semiconductor device (semiconductor chip) CP of this embodiment is, for example, a power device including a power transistor (electrical power transistor), and the power transistor is formed on a semiconductor substrate SB constituting the semiconductor device CP. The semiconductor substrate SB constituting the semiconductor device CP is made of, for example, single crystal silicon and has a main surface and a back surface opposite thereto. The semiconductor device CP and the semiconductor substrate SB constituting it have a rectangular planar shape.

[0014] The semiconductor device CP has, as the uppermost layer wiring, an emitter electrode EE, a gate electrode wiring GEW, an inner peripheral wiring (metal pattern) FCW, an outer peripheral wiring (metal pattern) SCW, and a connection wiring portion JW. The emitter electrode EE, the gate electrode wiring GEW, the inner peripheral wiring FCW, and the outer peripheral wiring SCW are each made of a metal material, and therefore can be considered as a metal electrode, metal wiring, or metal pattern. The emitter electrode EE, the gate electrode wiring GEW, the inner peripheral wiring FCW, and the outer peripheral wiring SCW are wirings (metal patterns) in the same layer, and are made of a laminated conductor film of a barrier conductor film BR and a main conductor film MC formed thereon.

[0015] In plan view, an emitter electrode EE is arranged in the center of the semiconductor device CP, a gate electrode wiring GEW is arranged on the outer periphery (outside) of the emitter electrode EE, an inner circumferential wiring FCW is arranged on the outer periphery (outside) of the gate electrode wiring GEW, and an outer circumferential wiring SCW is arranged on the outer periphery (outside) of the inner circumferential wiring FCW.

[0016] In the present application, a plan view corresponds to a view seen in a plane parallel to the main surface or rear surface of the semiconductor device CP or the semiconductor substrate SB.

[0017] The emitter electrode EE is electrically connected to the emitter region of the power transistor formed in the semiconductor device CP (semiconductor substrate SB). The emitter electrode EE is formed, for example, in a substantially square shape in plan view.

[0018] The gate electrode wiring GEW is electrically connected to the gate electrode of the power transistor formed in the semiconductor device CP (semiconductor substrate SB). The gate electrode wiring GEW is arranged on the outer periphery of the emitter electrode EE so as to surround the emitter electrode EE in a plan view, and has a gate electrode portion GE and a gate wiring portion GW that are integrally formed. The gate electrode portion GE is formed, for example, in a substantially square shape in a plan view, and is arranged near one corner of the emitter electrode EE. Furthermore, the gate wiring portion GW is formed in a strip-like pattern that is narrower than the gate electrode portion GE, and is arranged so as to surround the emitter electrode EE in a plan view.

[0019] The inner peripheral wiring FCW is disposed on the outer periphery of the gate electrode wiring GEW so as to surround the gate electrode wiring GEW in a plan view. The inner peripheral wiring FCW is electrically connected to the emitter electrode EE through the connection wiring portion JW. The inner peripheral wiring FCW, the connection wiring portion JW, and the emitter electrode EE are made of the same conductor film and are integrally formed.

[0020] The outer peripheral wiring SCW is disposed on the outer periphery of the inner peripheral wiring FCW so as to surround the inner peripheral wiring FCW in a plan view, and is electrically connected to a collector region of a power transistor formed in the semiconductor device CP (semiconductor substrate SB).

[0021] The semiconductor device CP also has a field plate portion (resistive field plate portion, conductor plate portion) FP that electrically connects the inner surrounding wiring FCW and the outer surrounding wiring SCW. The field plate portion FP is a resistive field plate portion made of polycrystalline silicon. In plan view, the field plate portion FP is disposed between the inner surrounding wiring FCW and the outer surrounding wiring SCW. Although FIGS. 1 and 4 are plan views, the field plate portion FP is hatched to make the drawings easier to understand. The field plate portion FP is formed of conductor patterns FCP, TCP, and SCP that electrically connect the collector and emitter of the power transistor.

[0022] 3, an element region (active region, inner periphery region) DR is arranged in the center of the main surface of the semiconductor substrate SB constituting the semiconductor device CP. Furthermore, on the main surface of the semiconductor substrate SB, a peripheral region (outer periphery region) PR is arranged on the periphery of the element region DR so as to surround the element region DR.

[0023] The element region DR is a region in which semiconductor elements are formed. A plurality (a large number) of unit transistor cells are arranged in the element region DR, and these unit transistors are connected in parallel to form a power transistor. Each unit transistor cell has the same structure.

[0024] The unit transistor cell in the element region DR will be described below with reference to Figures 7 and 8. Figures 7 and 8 are cross-sectional views of a main part showing an example of a unit transistor cell arranged in the element region DR of Figure 3. However, as described above, Figure 7 corresponds to a cross-sectional view of a region where the emitter electrode EE is exposed from an opening in the protective film PF, and Figure 8 corresponds to a cross-sectional view of a region where the emitter electrode EE is covered with the protective film PF.

[0025] As shown in Figures 7 and 8, for example, a mesa-type insulated gate bipolar transistor (IGBT) is formed as a unit transistor cell. Hereinafter, the insulated gate bipolar transistor will be simply referred to as a transistor. The transistor (element) is made up of a p-type collector region CR, an n-type emitter region ER, and an n-type - The n-type drift region DF and the p-type channel formation region CH are provided, and the trench gate electrode TG is provided.

[0026] That is, a p-type collector region CR is formed on the back surface side of the semiconductor substrate SB, extending from the back surface of the semiconductor substrate SB to a predetermined depth. The collector region CR is made of a p-type semiconductor region formed in the semiconductor substrate SB. A collector electrode CE is formed on the back surface of the semiconductor substrate SB, and the collector region CR is adjacent to and electrically connected to the collector electrode CE. The collector electrode CE is made of, for example, a laminated film of an aluminum (Al) layer on the back surface of the semiconductor substrate SB, a titanium (Ti) layer thereon, a nickel (Ni) layer thereon, and a gold (Au) layer thereon. The collector electrode CE is formed on the entire back surface of the semiconductor substrate SB.

[0027] p-type collector region CR and n - An n-type field stop region SR is formed between the emitter region ER and the drift region DF. The field stop region SR is made of an n-type semiconductor region formed in the semiconductor substrate SB, and the drift region DF is made of an n-type semiconductor region formed in the semiconductor substrate SB. The n-type impurity concentration of the field stop region SR is higher than that of the drift region DF, and the n-type impurity concentration of the emitter region ER is higher than that of the field stop region SR. The field stop region SR has the function of preventing the punch-through phenomenon (a phenomenon in which a depletion layer growing from the channel formation region CH in the drift region DF comes into contact with the collector region CR) from occurring when the transistor is turned off. The field stop region SR also has the function of limiting the amount of holes injected from the collector region CR into the drift region DF.

[0028] An n-type emitter region ER is formed on the main surface side of the semiconductor substrate SB to a predetermined depth from the main surface of the semiconductor substrate SB. The emitter region ER is made of an n-type semiconductor region formed in the semiconductor substrate SB. Of the drift region DF and the channel formation region CH, the channel formation region CH is adjacent to the emitter region ER, the emitter region ER is located above the channel formation region CH, and the channel formation region CH is interposed between the emitter region ER and the drift region DF. The p-type channel formation region CH is made of a p-type semiconductor region formed in the semiconductor substrate SB.

[0029] In the element region DR, the semiconductor substrate SB has a trench (gate trench) TR formed therein, extending from its main surface in the thickness direction of the semiconductor substrate SB. The trench TR is formed to penetrate the emitter region ER and the channel formation region CH thereunder, and reach the drift region DF. From another perspective, the channel formation region CH is formed between adjacent trenches TR, and the emitter region ER is formed above the channel formation region CH and adjacent to the trench TR.

[0030] A trench gate electrode TG is buried in the trench TR via a gate insulating film GF. The gate insulating film GF is made of, for example, a silicon oxide film and is formed on the bottom and side surfaces of the trench TR. The trench gate electrode TG is made of, for example, a polycrystalline silicon film doped with n-type impurities (for example, phosphorus). The trench gate electrode TG functions as the gate (gate electrode) of the unit transistor cell. The trench gate electrode TG is electrically connected to the gate electrode wiring GEW.

[0031] Furthermore, an insulating film ZF is formed on the main surface of the semiconductor substrate SB so as to cover the upper surfaces of the emitter region ER and the trench gate electrode TG. The insulating film ZF is a laminated film of one or more silicon nitride films and one or more silicon oxide films. In the case of FIGS. 7 and 8, the insulating film ZF is a laminated film of a silicon oxide film OX1, a silicon nitride film NT on the silicon oxide film OX1, and a silicon oxide film OX2 on the silicon nitride film NT. The emitter electrode EE is formed on the insulating film ZF.

[0032] The emitter electrode EE is formed of a laminated film of a barrier conductor film BF and a main conductor film MF formed thereon. The thickness of the main conductor film MF is thicker than the thickness of the barrier conductor film BF. The barrier conductor film BF is made of, for example, titanium tungsten (TiW). The main conductor film MF is made of, for example, a simple aluminum (Al) film, a conductor film in which Si or copper (Cu) is added to Al, or a conductor film in which Si and Cu are added to Al. Among these, AlSi is preferred from the viewpoint of suppressing Al spikes. The Si content in Al is, for example, in the range of 0.5% to 1.5%.

[0033] In the element region DR, a contact hole (connection trench) CT1 is formed, which penetrates the insulating film ZF and the emitter region ER and reaches the channel formation region CH. The contact hole CT1 is filled with an emitter electrode EE. The emitter electrode EE is in contact with the emitter region ER exposed from the side surface of the contact hole CT1 and is electrically connected to the emitter region ER. The emitter electrode EE is also formed in a p-type trench formed in the semiconductor substrate SB at a position adjacent to the bottom of the contact hole CT1. + The emitter electrode EE is electrically connected to the p-type channel formation region CH through the p-type semiconductor region PS1. In plan view, the emitter electrode EE is formed over the entire element region DR in which a plurality of unit transistor cells constituting the power transistor are formed.

[0034] The semiconductor device CP has an insulating protective film (surface protective film, passivation film) PF as its uppermost film (insulating film). The protective film PF is made of an insulating film, preferably a resin film such as a polyimide resin. In this embodiment, the protective film PF does not include a silicon nitride film. The emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, the outer surrounding wiring SCW, and the connection wiring portion JW are covered with the protective film PF. That is, the protective film PF is formed on the insulating film ZF so as to cover the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, the outer surrounding wiring SCW, and the connection wiring portion JW. The protective film PF is in contact with the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW.

[0035] However, an opening for a pad (bonding pad) is formed in the protective film PF. The opening for the emitter pad in the protective film PF is formed so as to be included in the emitter electrode EE in a plan view, and a part of the emitter electrode EE is exposed from the opening for the emitter pad in the protective film PF. The emitter electrode EE exposed from the opening for the emitter pad in the protective film PF forms an emitter pad (emitter bonding pad). Furthermore, the opening for the gate pad in the protective film PF is formed so as to be included in the gate electrode portion GE in a plan view, and a part of the gate electrode portion GE is exposed from the opening for the gate pad in the protective film PF. The gate electrode portion GE exposed from the opening for the gate pad in the protective film PF forms a gate pad (gate bonding pad). The gate wiring portion GW, the inner surrounding wiring FCW, the outer surrounding wiring SCW, and the connection wiring portion JW are entirely covered by the protective film PF and are not exposed from the protective film PF.

[0036] The trench gate electrodes TG of the plurality of unit transistor cells formed in the element region DR are electrically connected to one another through gate electrode wiring GEW, and therefore a gate voltage is supplied from the gate pad to the gate of the power transistor (the trench gate electrodes TG of the plurality of unit transistor cells constituting the power transistor) through the gate electrode wiring GEW.

[0037] Moreover, the emitter regions ER of the plurality of unit transistor cells that constitute the power transistor are electrically connected to an emitter electrode EE, and are also electrically connected to each other through the emitter electrode EE.

[0038] Moreover, the collector regions of the plurality of unit transistor cells that constitute the power transistor are electrically connected to one another through the collector regions CR and collector electrodes CE.

[0039] In addition, the case where an IGBT is applied as the semiconductor element formed in the element region DR has been described. As an alternative, a power MOSFET may be formed as the semiconductor element formed in the element region DR instead of the above-described IGBT. In that case, the emitter region ER becomes the source region, the emitter electrode EE becomes the source electrode, the collector region CR is not formed, and the collector electrode CE becomes the drain electrode. Also, as the semiconductor element formed in the element region DR, instead of an IGBT or a power MOSFET, other transistors such as an RC (Reverse-Conducting)-IGBT or a bipolar transistor may be applied as a unit transistor cell. Also, a diode may be applied as the semiconductor element formed in the element region DR. In that case, one of the emitter electrode EE and the collector electrode CE becomes the anode electrode and the other becomes the cathode electrode, and no gate electrode wiring GEW is formed.

[0040] Next, the peripheral region (PR) of the semiconductor device CP (semiconductor substrate SB) will be described with reference to FIG. 1 and FIGS.

[0041] As shown in FIG. 6, in the peripheral region of the semiconductor device CP, a p-type semiconductor region FPR and a p-type semiconductor region FPR are provided on the main surface side of the semiconductor substrate SB. - The p-type semiconductor region FPR is formed in the semiconductor substrate SB, and the resurf region RS is formed in the semiconductor substrate SB. - p - The impurity concentration (p-type impurity concentration) of the resurf region RS is lower than the impurity concentration (p-type impurity concentration) of the p-type semiconductor region FPR. As shown in FIG. 5, the planar shape of the p-type semiconductor region FPR is formed in a frame shape in plan view so as to surround the element region DR. The p-type semiconductor region FPR is fixed to a potential of 0 V (ground potential) when the power transistor is off.

[0042] Also, p -A p-type resurf region RS is also formed to surround the element region DR. This resurf region RS extends toward the outer periphery of the semiconductor device CP while being electrically connected to the p-type semiconductor region FPR, and is formed below (directly below) the field plate portion FP. The combination of the field plate portion FP and the resurf region RS is very compatible in terms of breakdown voltage characteristics, and by providing the resurf region RS, the electric field (surface electric field) in the main surface of the semiconductor substrate SB can be alleviated, thereby improving the breakdown voltage.

[0043] Further, on the main surface of the semiconductor substrate SB, on the outer side (outer periphery side) of the field plate portion FP, n + A p-type channel stopper region CS is formed in the power transistor. The channel stopper region CS has the function of suppressing the extension of a depletion layer extending from the p-type semiconductor region FPR. This channel stopper region CS is fixed to a potential of, for example, about 600 V when the power transistor is off.

[0044] 6, in the peripheral region of the semiconductor device CP, an insulating film IL1 and an insulating film IL2 are formed on the main surface of the semiconductor substrate SB so as to cover the insulating film IL1. The insulating film IL1 is thicker than the insulating film IL2. The insulating film IL1 is made of, for example, a silicon oxide film and has a thickness of, for example, about 1 μm. As shown in FIG. 5, the planar shape of the insulating film IL1 is formed in a frame shape in plan view so as to surround the p-type semiconductor region FPR. The p-type semiconductor region FPR is formed in a self-aligned manner with the insulating film IL1, and in plan view, the outer peripheral edge of the p-type semiconductor region FPR approximately coincides with the inner peripheral edge of the thick insulating film IL1. The insulating film IL2 is made of, for example, a silicon oxide film like the insulating film IL1, but is thinner than the insulating film IL1 and has a thickness of, for example, about 0.2 μm.

[0045] 6, the above-mentioned field plate portion FP is formed on the insulating film IL1 and the insulating film IL2. The field plate portion FP is a structure for ensuring the breakdown voltage of the peripheral region PR of the semiconductor device CP when the power transistor is off. The field plate portion FP is arranged in the peripheral region PR (see FIG. 3) of the semiconductor device CP, in a state electrically connected between the collector and the emitter of the power transistor (a power transistor composed of a plurality of unit transistor cells formed in the element region DR). By passing a current through the conductor patterns FCP, TCP, and SCP that make up the field plate portion FP, a field plate having a constant potential is formed, and this potential distribution can ensure the breakdown voltage of the peripheral region.

[0046] As shown in FIGS. 1, 4, and 6, the field plate portion FP integrally comprises an inner conductor pattern FCP, an outer conductor pattern SCP, and an intermediate conductor pattern TCP that electrically connects them (the conductor patterns FCP and SCP). These conductor patterns FCP, SCP, and TCP are made of polycrystalline silicon (polysilicon) and have a thickness of, for example, about 500 to 600 nm. The conductor patterns FCP, SCP, and TCP contain a predetermined concentration of impurities (n-type or p-type impurities) so that they have a resistivity suitable for a field plate. The impurity concentration of the conductor patterns FCP, SCP, and TCP is, for example, 1×10 17 / cm 3 ~1×10 20 / cm 3 It can be about.

[0047] 1 and 4, the inner conductor pattern FCP is formed in a frame shape so as to surround the element region DR in plan view. As shown in Fig. 6, the inner conductor pattern FCP integrally has a portion that overlaps with the insulating film IL1 and a portion that does not overlap with the insulating film IL1 in plan view. That is, an inner peripheral portion of the inner conductor pattern FCP is formed on the insulating film IL2 on the semiconductor substrate SB (p-type semiconductor region FPR), and the insulating film IL1 does not exist below that portion, but an outer peripheral portion of the inner conductor pattern FCP is formed on the insulating film IL2 on the insulating film IL1, and the insulating film IL1 exists below that portion.

[0048] 1 and 4, the outer conductor pattern SCP is formed in a frame shape so as to surround the inner conductor pattern FCP in plan view. As shown in Fig. 6, the outer conductor pattern SCP integrally has a portion that overlaps with the insulating film IL1 and a portion that does not overlap with the insulating film IL1 in plan view. That is, the inner peripheral portion of the outer conductor pattern SCP is formed on the insulating film IL2 that is on the insulating film IL1, with the insulating film IL1 present below it, while the outer peripheral portion of the outer conductor pattern SCP is formed on the insulating film IL2 on the semiconductor substrate SB, with the insulating film IL1 not present below it.

[0049] 1 and 4, the intermediate conductor pattern TCP is formed between the inner conductor pattern FCP and the outer conductor pattern SCP in plan view, and is formed on the insulating film IL2 on the insulating film IL1 in cross-sectional view. Therefore, the insulating film IL1 exists below the intermediate conductor pattern TCP.

[0050] 1 and 4, the intermediate conductor pattern TCP is formed, for example, in a spiral shape (vortex shape) in plan view. Of the two opposite ends of the intermediate conductor pattern TCP, one end is integrally connected to the inner conductor pattern FCP, and the other end is integrally connected to the outer conductor pattern SCP.

[0051] When a current (e.g., a current of about several μA) is passed through the conductor patterns FCP, TCP, and SCP of such a field plate portion FP from the collector toward the emitter (i.e., from the outer conductor pattern SCP toward the inner conductor pattern FCP), the potential is divided by the conductor patterns FCP, TCP, and SCP, and a field plate with a constant potential is formed in the peripheral region PR. The potential distribution of the field plate then homogenizes the electric field distribution within the semiconductor substrate SB in the peripheral region PR, and also fixes the potential of the upper surface of the semiconductor substrate SB, thereby improving the breakdown voltage of the peripheral region PR of the semiconductor device CP and improving the reliability of the semiconductor device CP. Furthermore, in a peripheral structure using the field plate portion FP, the potential distribution between the collector and emitter is fixed by the current flowing through the conductor patterns FCP, SCP, and TCP, making the semiconductor device CP less susceptible to the effects of external charges.

[0052] 6, the insulating film ZF described above is formed on the main surface of the semiconductor substrate SB so as to cover the field plate portion FP (conductor patterns FCP, SCP, TCP) and the insulating film IL2, etc. Then, the inner surrounding wiring FCW and the outer surrounding wiring SCW described above are formed on this insulating film ZF. Like the emitter electrode EE, the inner surrounding wiring FCW and the outer surrounding wiring SCW are formed of a laminated film of a barrier conductor film BF and a main conductor film MF formed thereon.

[0053] As shown in FIG. 6, the inner surrounding wiring FCW is electrically connected to the p-type semiconductor region FPR through a contact hole CT2 formed in the insulating film ZF and the insulating film IL2. That is, the contact hole CT2 is formed at a position overlapping with the p-type semiconductor region FPR in a plan view, penetrates the insulating film ZF and the insulating film IL2 thereunder, and the contact hole CT2 is filled with the inner surrounding wiring FCW. The inner surrounding wiring FCW is electrically connected to a portion of the semiconductor substrate SB exposed from the insulating film ZF (contact hole CT). Specifically, the p-type semiconductor region FPR is exposed at the bottom of the contact hole CT2, and the inner surrounding wiring FCW in the contact hole CT2 and the p-type semiconductor region FPR are electrically connected. In addition, a p-type semiconductor region FPR having a higher impurity concentration than the p-type semiconductor region FPR is formed at a position adjacent to the bottom of the contact hole CT2 in the p-type semiconductor region FPR. + The inner peripheral wiring FCW is formed in the p + The side wiring FCW can be electrically connected to the p-type semiconductor region FPR through the p-type semiconductor region PS2, thereby reducing the connection resistance between the side wiring FCW and the p-type semiconductor region FPR.

[0054] 6, the inner surrounding wiring FCW is electrically connected to the conductor pattern FCP of the field plate portion FP through a contact hole CT3 formed in the insulating film ZF. That is, the contact hole CT3 is formed at a position overlapping the conductor pattern FCP of the field plate portion FP in a plan view, penetrates the insulating film ZF, and the contact hole CT3 is filled with the inner surrounding wiring FCW. The conductor pattern FCP of the field plate portion FP is exposed at the bottom of the contact hole CT3, and the inner surrounding wiring FCW in the contact hole CT3 and the conductor pattern FCP of the field plate portion FP are electrically connected. Also, a p-type impurity having a higher impurity concentration than the conductor pattern FCP is formed at a position adjacent to the bottom of the contact hole CT3 in the conductor pattern FCP of the field plate portion FP. + A p-type semiconductor region (not shown) is formed. +The inner surrounding wiring FCW can also be electrically connected to the conductor pattern FCP of the field plate portion FP through the insulating film IL1. This reduces the connection resistance between the inner surrounding wiring FCW and the conductor pattern FCP of the field plate portion FP. In the case of Figure 6, the contact hole CT3 is formed not on the portion of the conductor pattern FCP located on the insulating film IL1 but on the portion of the conductor pattern FCP not located on the insulating film IL1.

[0055] In another embodiment, the contact hole CT3 may be provided on the conductor pattern FCP in a portion located on the insulating film IL1 (i.e., on the conductor pattern FCP in a position overlapping the insulating film IL1 in plan view). In this case, the entire conductor pattern FCP may overlap the insulating film IL1 in plan view.

[0056] The contact hole CT3 can be formed so as to go around the outer periphery of the inner surrounding wiring FCW in plan view, and the same can be said for the contact hole CT2.

[0057] As shown in FIG. 6, the outer peripheral wiring SCW is connected to the p + type semiconductor region PS3 and n + It is electrically connected to the channel stopper region CS of the p type. + The contact hole CT4 is a p-type semiconductor region PS3 formed in the semiconductor substrate SB, and the channel stopper region CS is an n-type semiconductor region formed in the semiconductor substrate SB. + The contact hole CT4 is formed at a position overlapping the type semiconductor region PS3 in plan view, penetrates the insulating film ZF and the insulating film IL2 thereunder, and an outer peripheral wiring SCW is embedded in the contact hole CT4. The outer peripheral wiring SCW is electrically connected to a portion of the semiconductor substrate SB exposed from the insulating film ZF (contact hole CT4). Specifically, the outer peripheral wiring SCW in the contact hole CT4 is electrically connected to the p-type semiconductor region PS3 exposed at the bottom of the contact hole CT2. +The outer peripheral wiring SCW is electrically connected to the p-type semiconductor region PS3 through the contact hole CT4 and the p + The outer peripheral wiring SCW is electrically connected to the collector region CR on the back surface side of the semiconductor substrate SB through the type semiconductor region PS3. Therefore, the outer peripheral wiring SCW is electrically connected to the collector electrode CE through the semiconductor substrate SB.

[0058] 6, the outer surrounding wiring SCW is electrically connected to the conductor pattern SCP of the field plate portion FP through a contact hole CT5 formed in the insulating film ZF. That is, the contact hole CT5 is formed at a position overlapping the conductor pattern SCP of the field plate portion FP in a plan view, penetrates the insulating film ZF, and the contact hole CT5 is filled with the outer surrounding wiring SCW. The conductor pattern SCP of the field plate portion FP is exposed at the bottom of the contact hole CT5, and the outer surrounding wiring SCW in the contact hole CT5 and the conductor pattern SCP of the field plate portion FP are electrically connected. Also, a p-type impurity having a higher impurity concentration than the conductor pattern SCP is formed at a position adjacent to the bottom of the contact hole CT5 in the conductor pattern SCP of the field plate portion FP. + A p-type semiconductor region (not shown) is formed. + The outer peripheral wiring SCW can also be electrically connected to the conductor pattern SCP of the field plate portion FP through the insulating film IL1. This reduces the connection resistance between the outer peripheral wiring SCW and the conductor pattern SCP of the field plate portion FP. In the case of Figure 6, the contact hole CT5 is formed not on the portion of the conductor pattern SCP located on the insulating film IL1 but on the portion of the conductor pattern SCP not located on the insulating film IL1.

[0059] Alternatively, the contact hole CT5 may be provided on the conductor pattern SCP in a portion located on the insulating film IL1 (i.e., on the conductor pattern SCP in a position overlapping the insulating film IL1 in plan view). In this case, the entire conductor pattern SCP may overlap the insulating film IL1 in plan view.

[0060] The contact hole CT5 can be formed so as to go around the outer periphery of the outer surrounding wiring SCW in plan view, and the same can be said for the contact hole CT4.

[0061] Therefore, in the element region DR of the semiconductor device CP (semiconductor substrate SB), an insulating film ZF is formed on the main surface of the semiconductor substrate SB so as to cover the emitter region ER and the trench gate electrode TG. Furthermore, in the peripheral region PR of the semiconductor device CP (semiconductor substrate SB), a field plate portion FP is formed on the main surface of the semiconductor substrate SB via an insulating film (here, an insulating film consisting of insulating films IL1 and IL2). The insulating film ZF is then formed on the main surface of the semiconductor substrate SB so as to cover the insulating films IL1 and IL2 and the field plate portion FP (conductor patterns FCP, SCP, TCP). The insulating film ZF can function as an interlayer insulating film, but since it covers the field plate portion FP, it can also function as a protective film for the field plate portion FP. Furthermore, an emitter electrode EE, a gate electrode wiring GEW, an inner surrounding wiring FCW, and an outer surrounding wiring SCW are formed on the insulating film ZF, and a protective film PF is formed on the insulating film ZF so as to cover them.

[0062] The thickness of each of the emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, and outer surrounding wiring SCW is thicker than the thickness of the field plate portion FP (conductor patterns FCP, SCP, TCP). Note that the thickness of each of the emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, and outer surrounding wiring SCW can be defined as the thickness of the portion located on the insulating film ZF (thickness T1 shown in FIG. 6). FIG. 6 also shows the thickness T2 of the field plate portion FP, and T1 > T2 holds.

[0063] The protective film PF is the topmost film of the semiconductor device CP, which is a semiconductor chip. A part (central part) of the emitter electrode EE is exposed from the opening of the protective film PF to form an emitter pad, and a part of the gate electrode portion GE of the gate electrode wiring GEW is exposed from the opening of the protective film PF to form a gate pad.

[0064] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 9 to 19. Figures 9 to 19 are cross-sectional views of a main part during the manufacturing process of the semiconductor device according to this embodiment. In each of Figures 9 to 19, the cross section shown on the left side of the figure corresponds to Figure 7 above, and the cross section shown on the right side of the figure corresponds to Figure 6 above.

[0065] First, as shown in FIG. 9, a semiconductor substrate SB is prepared. At this stage, the semiconductor substrate SB is a semiconductor wafer having a substantially circular shape in a plan view. The semiconductor substrate SB has a main surface and a back surface opposite thereto. The semiconductor substrate SB is made of, for example, single crystal silicon, and has an n-type impurity doped therein. - As the semiconductor substrate SB, an epitaxial wafer having an epitaxial semiconductor layer formed on a semiconductor substrate can also be used.

[0066] Next, an insulating film such as a silicon oxide film is formed on the main surface of the semiconductor substrate SB, and then the insulating film is patterned using photolithography and etching techniques to form a pattern of an insulating film IL1 on the main surface of the semiconductor substrate SB in the peripheral region PR, as shown in FIG. 10.

[0067] Next, ion implantation is performed on the main surface side of the semiconductor substrate SB in the peripheral region PR using a photoresist pattern as a mask, thereby forming p - A resurf region RS of the type is formed.

[0068] A p-type semiconductor region FPR is formed on the main surface side of the semiconductor substrate SB in the peripheral region PR by performing ion implantation using a photoresist pattern and the insulating film IL1 as a mask. The p-type semiconductor region FPR is formed in self-alignment with the inner peripheral end of the insulating film IL1.

[0069] 11, a trench TR is formed in the semiconductor substrate SB in the element region DR by etching, and then a gate insulating film GF is formed on the inner surface (side and bottom surfaces) of the trench TR by thermal oxidation or the like. Then, a conductor film (e.g., a polycrystalline silicon film) for forming the trench gate electrode TG is formed on the main surface of the semiconductor substrate SB by CVD (Chemical Vapor Deposition) or the like so as to fill the trench TR, and then the conductor film is etched back. As a result, the trench gate electrode TG is formed by the conductor film remaining in the trench TR via the gate insulating film GF.

[0070] Next, as shown in Figure 12, an insulating film IL2 and a polycrystalline silicon film (a polycrystalline silicon film for forming the field plate portion FP) are formed in this order on the main surface of the semiconductor substrate SB using a method such as CVD, and then p-type or n-type impurities are introduced into the polycrystalline silicon film PC by ion implantation. The polycrystalline silicon film is then patterned using photolithography and etching techniques to form the conductor patterns FCP, SCP, and TCP that constitute the field plate portion FP. Figure 12 shows this stage. The conductor patterns FCP, SCP, and TCP that constitute the field plate portion FP are formed on the main surface of the semiconductor substrate SB via an insulating film (here, an insulating film made up of insulating films IL1 and IL2).

[0071] Next, as shown in FIG. 13, a p-type channel formation region CH is formed by ion implantation of p-type impurities into the semiconductor substrate SB in the element region DR using a photoresist pattern as a mask, and then an n-type emitter region ER is formed by ion implantation of n-type impurities using the same photoresist pattern as a mask.

[0072] Next, ion implantation is performed on the main surface side of the semiconductor substrate SB in the peripheral region PR using a photoresist pattern as a mask, thereby forming n + A channel stopper region CS is formed.

[0073] 14, an insulating film ZF is formed on the main surface of the semiconductor substrate SB so as to cover the trench gate electrode TG, the field plate portion FP (conductor patterns FCP, SCP, TCP), the insulating film IL2, and the insulating film IL1. As described above, the insulating film ZF is made of a stacked film of one or more silicon nitride films and one or more silicon oxide films. The silicon nitride films and silicon oxide films constituting the insulating film ZF can each be formed using a CVD method or the like.

[0074] 14, the insulating film ZF is made of a stacked film of a silicon oxide film OX1, a silicon nitride film NT on the silicon oxide film OX1, and a silicon oxide film OX2 on the silicon nitride film NT. In this case, the step of forming the insulating film ZF includes the steps of forming the silicon oxide film OX1, forming the silicon nitride film NT on the silicon oxide film OX1, and forming the silicon oxide film OX2 on the silicon nitride film NT.

[0075] 15, a contact hole CT1 is formed in the insulating film ZF using photolithography and etching techniques. The semiconductor substrate SB is etched at the bottom of the contact hole CT1, so that the contact hole CT1 penetrates the insulating film ZF and the emitter region ER and reaches the channel formation region CH. Furthermore, contact holes CT2, CT3, CT4, and CT5 are formed in the insulating film ZF using photolithography and etching techniques.

[0076] Next, as shown in FIG. 16, p + The p-type semiconductor regions PS1, PS2, and PS3 are formed. +The p-type semiconductor region PS1 is formed in the channel formation region CH exposed at the bottom of the contact hole CT1. + The p-type semiconductor region PS2 is formed in the semiconductor substrate SB exposed at the bottom of the contact hole CT3. + The type semiconductor region PS3 is formed in the semiconductor substrate SB exposed at the bottom of the contact hole CT5. At this time, the upper part of the conductor pattern FCP exposed at the bottom of the contact hole CT3 and the upper part of the conductor pattern SCP exposed at the bottom of the contact hole CT5 are covered with p + A mold semiconductor region (not shown) may also be formed.

[0077] Next, as shown in Fig. 17, a barrier conductor film BF is formed on the insulating film ZF, including on the inner surfaces (side and bottom surfaces) of the contact holes CT1, CT2, CT3, CT4, and CT5, using a method such as sputtering, and then a main conductor film MF is formed on the barrier conductor film BF using a method such as sputtering so as to fill the contact holes CT1, CT2, CT3, CT4, and CT5. Then, the barrier conductor film BF and the main conductor film MF are patterned using photolithography and etching techniques to form the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW. Fig. 17 shows this stage.

[0078] 18, a protective film PF made of polyimide resin or the like is formed on the insulating film ZF so as to cover the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW. Then, an emitter pad opening and a gate pad opening are formed in the protective film PF. A part of the emitter electrode EE is exposed from the emitter pad opening in the protective film PF to form an emitter pad, and the gate electrode portion GE of the gate electrode wiring GEW is exposed from the gate pad opening in the protective film PF to form a gate pad.

[0079] Next, if necessary, the rear surface side of the semiconductor substrate SB is ground to thin the semiconductor substrate SB.

[0080] Next, as shown in FIG. 19, an n-type field stop region SR is formed on the back surface side of the semiconductor substrate SB by ion implantation, and then a p-type collector region CR is formed by ion implantation.

[0081] Next, a collector electrode CE is formed on the back surface of the semiconductor substrate SB by sputtering or the like. After that, the semiconductor substrate SB is cut into individual pieces by dicing. In this way, semiconductor devices CP as semiconductor chips are manufactured.

[0082] Furthermore, a semiconductor package can be manufactured using the manufactured semiconductor device CP. For example, the semiconductor device CP is mounted on a die pad of a lead frame (not shown), and the die pad is electrically connected to the collector electrode CE of the semiconductor device CP. Then, the multiple leads of the lead frame are electrically connected to the emitter pad (emitter electrode EE) and gate pad (gate electrode GE) of the semiconductor device CP via conductive connecting members (e.g., bonding wires). Then, the semiconductor device CP, the conductive connecting members, the die pad, and the leads are sealed with resin, and the leads and die pad are cut and separated from the lead frame. In this manner, a semiconductor package can be manufactured.

[0083] <Background of the review> The present inventors have been studying a semiconductor device having a resistive field plate portion. The resistive field plate portion (corresponding to the above-mentioned field plate portion FP) is made of polycrystalline silicon and is formed on the main surface of a semiconductor substrate SB via an insulating film.

[0084] Fig. 20 is a cross-sectional view of a main part of a semiconductor device of a first study example studied by the present inventors, and corresponds to Fig. 6. In the semiconductor device of the first study example shown in Fig. 20, the insulating film ZF100, which corresponds to the insulating film ZF, is composed of a single film of silicon oxide.

[0085] For semiconductor devices having a resistive field plate, it is important to improve moisture resistance. This is because if moisture penetrates into the semiconductor device CP and reaches the field plate FP, the polycrystalline silicon field plate FP may react with the moisture and deteriorate, potentially causing defects. For example, the field plate FP has a narrow pattern (conductor pattern TCP), and this narrow pattern may react with the infiltrating moisture, potentially causing a break.

[0086] In the semiconductor device of the first study example shown in FIG. 20, the insulating film ZF100 covering the field plate portion FP is composed of a single film of silicon oxide. A silicon oxide film has low barrier properties against moisture and is a film that easily allows moisture to pass through (a film with high moisture permeability). For this reason, moisture that passes through the protective film PF easily passes further through the insulating film ZF100 and reaches the field plate portion FP, raising concerns that the field plate portion FP will react with moisture. Reaction of the field plate portion FP with moisture leads to a decrease in the reliability of the semiconductor device. In order to improve the reliability of a semiconductor device having a resistive field plate portion, it is important to prevent the resistive field plate portion made of polycrystalline silicon from reacting with moisture.

[0087] <Main features and effects> The field plate portion FP is made of polycrystalline silicon and is formed on the main surface of the semiconductor substrate SB via an insulating film (here, an insulating film consisting of insulating films IL1 and IL2), and an insulating film ZF is formed on the insulating film so as to cover the field plate portion FP.

[0088] In this embodiment, the insulating film ZF is a laminated film of one or more silicon nitride films and one or more silicon oxide films. In the cases of FIGS. 6 to 8, the insulating film ZF is a laminated film of a silicon oxide film OX1, a silicon nitride film NT on the silicon oxide film OX1, and a silicon oxide film OX2 on the silicon nitride film NT. Compared to a silicon oxide film, a silicon nitride film has a higher barrier property against moisture and is a film that is less permeable to moisture (a film with low moisture permeability). In this embodiment, the insulating film ZF covering the field plate portion FP includes a silicon nitride film NT that has a high barrier property against moisture, and the silicon nitride film NT included in the insulating film ZF can function as a barrier film against moisture. Therefore, since the insulating film ZF includes the silicon nitride film NT, moisture can be suppressed or prevented from passing through the insulating film ZF and reaching the field plate portion FP. This suppresses or prevents the field plate portion FP made of polycrystalline silicon from reacting with moisture, thereby improving the reliability of a semiconductor device having a resistive field plate portion.

[0089] Fig. 21 is a cross-sectional view of a main part of a semiconductor device of a second study example studied by the present inventors, and corresponds to Fig. 6. In the semiconductor device of the second study example shown in Fig. 21, the insulating film ZF200, which corresponds to the insulating film ZF, is composed of a single film of silicon nitride.

[0090] 21, the insulating film ZF200 covering the field plate portion FP is made of a single film of silicon nitride, which suppresses or prevents moisture from passing through the insulating film ZF200 and reaching the field plate portion FP. This suppresses or prevents the field plate portion FP made of polycrystalline silicon from reacting with moisture.

[0091] However, in the case of the second studied example shown in FIG. 21, the insulating film ZF200 covering the field plate portion FP is made of a single film of silicon nitride, which causes the following problems.

[0092] That is, compared with a silicon oxide film formed on the main surface of a semiconductor substrate, a silicon nitride film formed on the main surface of the semiconductor substrate is more likely to generate stress in the semiconductor substrate. Furthermore, the thicker the silicon nitride film formed on the main surface of the semiconductor substrate, the greater the stress it generates in the semiconductor substrate. Therefore, in the second study example shown in FIG. 21 , the insulating film ZF200 covering the field plate portion FP is composed of a single silicon nitride film, and the insulating film ZF200 made of silicon nitride is likely to generate stress in the semiconductor substrate SB. If large stress is generated in the semiconductor substrate during the manufacturing of the semiconductor device, it can cause warping of the semiconductor substrate, making it difficult to manage the manufacturing process of the semiconductor device. Furthermore, if large stress is generated in the semiconductor substrate after manufacturing, it may affect the electrical characteristics of the semiconductor device. This is undesirable because it leads to variations in the electrical characteristics of the semiconductor device. Therefore, in the second study example shown in FIG. 21 , it is possible to reduce the thickness of the insulating film ZF200 in order to suppress the stress generated in the semiconductor substrate SB by the insulating film ZF200 covering the field plate portion FP. However, if the insulating film ZF200 is made thinner, the function of the insulating film ZF200 covering the field plate portion FP to protect the field plate portion FP will be reduced. Furthermore, the insulating film ZF200 also serves as an interlayer insulating film, and if the insulating film ZF200 is made thinner, its function as an interlayer insulating film will also be reduced. Therefore, the insulating film ZF200 needs to be made thick to a certain extent. However, if the insulating film ZF200 is made thicker, there is a concern that stress will be generated in the semiconductor substrate SB due to the insulating film ZF200, as described above.

[0093] In contrast, in this embodiment, the insulating film ZF is not a single film of a silicon nitride film, but is made of a laminated film of one or more silicon nitride films and one or more silicon oxide films. Therefore, even without increasing the thickness of the silicon nitride film NT included in the insulating film ZF, the thickness of the insulating film ZF can be ensured by including one or more silicon oxide films (here, silicon oxide films OX1 and OX2) in the insulating film ZF. Therefore, while suppressing the thickness of the silicon nitride film NT included in the insulating film ZF, the thickness of the insulating film ZF can be ensured, and the insulating film ZF covering the field plate portion FP can be ensured to protect the field plate portion FP. Furthermore, the function of the insulating film ZF as an interlayer insulating film can also be ensured.

[0094] Furthermore, compared with a silicon nitride film formed on the main surface of the semiconductor substrate, a silicon oxide film formed on the main surface of the semiconductor substrate is less likely to cause stress in the semiconductor substrate. Therefore, in this embodiment, even if the insulating film ZF includes one or more silicon oxide films (here, silicon oxide films OX1 and OX2), stress generated in the semiconductor substrate SB can be suppressed. In this embodiment, since the insulating film ZF includes one or more silicon oxide films (here, silicon oxide films OX1 and OX2), the thickness of the silicon nitride film NT included in the insulating film ZF can be suppressed, thereby suppressing or preventing stress generated in the semiconductor substrate SB due to the silicon nitride film NT. This makes it possible to suppress or prevent warping of the semiconductor substrate due to stress generated in the semiconductor substrate during manufacturing of the semiconductor device, thereby facilitating management of the semiconductor device manufacturing process. Furthermore, it is possible to suppress or prevent the stress generated in the semiconductor substrate from affecting the electrical characteristics of the semiconductor device after manufacturing. This improves the reliability of the semiconductor device.

[0095] Fig. 22 is a cross-sectional view of a main part of a semiconductor device of a third study example studied by the present inventors, and corresponds to Fig. 6 above. In the semiconductor device of the third study example shown in Fig. 22, an insulating film ZF100 corresponding to the insulating film ZF is composed of a single film of silicon oxide film, as in the first study example. In the semiconductor device of the third study example shown in Fig. 22, a protective film PF100 corresponding to the protective film PF is formed of a stacked film of a silicon nitride film PF101 and a resin film PF102 on the silicon nitride film PF101.

[0096] 22, the protective film PF100 includes a silicon nitride film PF101, and this silicon nitride film PF101 can function as a barrier film against moisture. Therefore, in the third studied example shown in FIG. 22, moisture can be suppressed or prevented from passing through the silicon nitride film PF101, and therefore moisture can be suppressed or prevented from passing through the silicon nitride film PF101 and the insulating film ZF100 to reach the field plate portion FP. This makes it possible to suppress or prevent the field plate portion FP made of polycrystalline silicon from reacting with moisture.

[0097] However, in the case of the third studied example shown in Fig. 22, there is a risk of cracks occurring in the silicon nitride film PF101. The reason for this will be explained below.

[0098] 22 , the protective film PF100 including the silicon nitride film PF101 is formed to cover the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW, but the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW are thick. Therefore, a large step is generated in the silicon nitride film PF101 covering the thick electrodes (emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, and outer surrounding wiring SCW), and stress is concentrated at the step, making it easy for cracks to occur. When a crack occurs in the silicon nitride film PF101, the function of the silicon nitride film PF101 to prevent moisture penetration is reduced. Therefore, moisture passes through the silicon nitride film PF101 and the insulating film ZF100 to reach the field plate portion FP, and the field plate portion FP made of polycrystalline silicon is likely to react with moisture. To prevent cracks from occurring in the silicon nitride film PF101, the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW must be thinned. However, thinning them is undesirable because it may degrade the performance of the semiconductor device. This is because it is desirable to reduce the resistance of the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW, and to achieve this, their thicknesses must be increased to a certain extent. Furthermore, to reduce resistance, the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW are formed of a metal material rather than polycrystalline silicon. Furthermore, if the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW are thinned, there is a concern that damage (e.g., damage to the structure below the pads) may occur due to pressure or ultrasonic vibration applied to the emitter pads and gate pads during the wire bonding process when manufacturing a semiconductor package using the semiconductor device (semiconductor chip).

[0099] In contrast, in this embodiment, the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW are formed on the insulating film ZF. Therefore, the insulating film ZF is lower than the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW, and therefore the silicon nitride film NT included in the insulating film ZF is lower than the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW. In other words, the silicon nitride film NT included in the insulating film ZF is present below the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW, but is not present above the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW. In other words, the silicon nitride film NT included in the insulating film ZF does not run over the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW.

[0100] Therefore, steps due to the emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, or outer surrounding wiring SCW do not occur in the insulating film ZF or the silicon nitride film NT included in the insulating film ZF. Therefore, even if the emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, or outer surrounding wiring SCW are thick, this does not affect the insulating film ZF or the silicon nitride film NT included in the insulating film ZF. Furthermore, the thickness of the field plate portion FP (conductor patterns FCP, TCP, SCP) is smaller than the thickness of the gate electrode wiring GEW, inner surrounding wiring FCW, or outer surrounding wiring SCW. This is because, while the emitter electrode EE, gate electrode wiring GEW, inner surrounding wiring FCW, and outer surrounding wiring SCW need to be formed of a metal material and have a certain thickness to reduce resistance, the field plate portion FP needs to have a certain degree of resistance, so it is formed of polycrystalline silicon rather than a metal material, and there is no need for a large thickness of the field plate portion FP. For this reason, even if a step due to the field plate portion FP occurs in the silicon nitride film NT included in the insulating film ZF covering the field plate portion FP, the size of the step will be smaller than the step that may occur in the silicon nitride film PF101 in the third studied example of Figure 22. For this reason, the risk of cracks occurring in the silicon nitride film NT included in the insulating film ZF covering the field plate portion FP is lower than the risk of cracks occurring in the silicon nitride film PF101 in the third studied example of Figure 22.

[0101] 22, cracks are less likely to occur in the silicon nitride film NT included in the insulating film ZF covering the field plate portion FP, and the silicon nitride film NT included in the insulating film ZF can therefore accurately maintain its function of preventing moisture penetration. As a result, moisture can be accurately suppressed or prevented from passing through the silicon nitride film NT included in the insulating film ZF and reaching the field plate portion FP, and the phenomenon in which the field plate portion FP made of polycrystalline silicon reacts with moisture can be accurately suppressed or prevented. This makes it possible to accurately improve the reliability of semiconductor devices having resistive field plate portions.

[0102] In addition, in this embodiment, the protective film PF does not include a silicon nitride film. In the third example shown in Fig. 22, since the protective film PF100 includes the silicon nitride film PF101, there is a concern that a large step will occur in the silicon nitride film PF101 included in the protective film PF100, and that the step will cause a crack. However, in this embodiment, since the protective film PF does not include a silicon nitride film, such a concern does not arise.

[0103] Moreover, the protective film PF is preferably made of a resin film. A resin film is softer than an inorganic insulating film. Using a resin film as the protective film PF makes the semiconductor device CP easier to handle. However, a resin film is more permeable to moisture than an inorganic insulating film. Therefore, when a resin film is used as the protective film PF, moisture easily passes through the protective film PF. In contrast, in this embodiment, the silicon nitride film NT included in the insulating film ZF covering the field plate portion FP can function as a barrier film against moisture, thereby suppressing or preventing moisture that has passed through the protective film PF from passing through the insulating film ZF and reaching the field plate portion FP. Therefore, even when a resin film is used as the protective film PF, it is possible to accurately suppress or prevent the field plate portion FP made of polycrystalline silicon from reacting with moisture, thereby accurately improving the reliability of a semiconductor device having a resistive field plate portion.

[0104] <Modification> Figure 23 is a cross-sectional view of a main part showing a first modified example of the semiconductor device CP of this embodiment, and Figure 24 is a cross-sectional view of a main part showing a second modified example of the semiconductor device CP of this embodiment, each of which is a cross-sectional view corresponding to Figure 6 above.

[0105] 6, 23 (first modified example), and 24 (second modified example), the insulating film ZF is a laminated film of one or more silicon nitride films and one or more silicon oxide films. However, the specific configuration of the laminated film constituting the insulating film ZF differs between the cases of Fig. 6, 23 (first modified example), and 24 (second modified example).

[0106] 6, the insulating film ZF is made of a stacked film of a silicon oxide film OX1, a silicon nitride film NT on the silicon oxide film OX1, and a silicon oxide film OX2 on the silicon nitride film NT. The silicon oxide film OX1, which is the bottom layer of the stacked film constituting the insulating film ZF, contacts the field plate portion FP (conductor patterns FCP, TCP, SCP), and the silicon oxide film OX2, which is the top layer of the stacked film constituting the insulating film ZF, contacts the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW.

[0107] 23 (first modified example), the insulating film ZF is made of a laminated film of a silicon nitride film NT and a silicon oxide film OX2 on the silicon nitride film NT. The silicon nitride film NT, which is the bottom layer of the laminated film constituting the insulating film ZF, contacts the field plate portion FP (conductor patterns FCP, TCP, SCP), and the silicon oxide film OX2, which is the top layer of the laminated film constituting the insulating film ZF, contacts the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW.

[0108] 24 (second modified example), the insulating film ZF is made of a stacked film of a silicon oxide film OX1 and a silicon nitride film NT on the silicon oxide film OX1. The silicon oxide film OX1, which is the bottom layer of the stacked film constituting the insulating film ZF, contacts the field plate portion FP (conductor patterns FCP, TCP, SCP), and the silicon nitride film NT, which is the top layer of the stacked film constituting the insulating film ZF, contacts the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, and the outer surrounding wiring SCW.

[0109] 6, 23 (first modified example), and 24 (second modified example), the insulating film ZF includes the silicon nitride film NT, which makes it possible to suppress or prevent moisture from passing through the insulating film ZF and reaching the field plate portion FP, as described above. This makes it possible to suppress or prevent the field plate portion FP made of polycrystalline silicon from reacting with moisture, thereby improving the reliability of the semiconductor device having a resistive field plate portion.

[0110] In any of the cases of FIG. 6, FIG. 23 (first modified example), and FIG. 24 (second modified example), the insulating film ZF also includes a silicon oxide film, so that the thickness of the insulating film ZF can be ensured without increasing the thickness of the silicon nitride film NT included in the insulating film ZF. Therefore, the thickness of the insulating film ZF can be ensured while suppressing the thickness of the silicon nitride film NT included in the insulating film ZF, and the insulating film ZF covering the field plate portion FP can be ensured to protect the field plate portion FP. Furthermore, the function of the insulating film ZF as an interlayer insulating film can be ensured. Furthermore, stress occurring in the semiconductor substrate SB due to the silicon nitride film NT can be suppressed or prevented.

[0111] In each of the cases of Figure 6, Figure 23 (first variant), and Figure 24 (second variant), the thickness of the insulating film ZF can be, for example, about 400 nm to 2000 nm, and the thickness of the silicon nitride film NT can be, for example, about 10 nm to 300 nm.

[0112] 6, 23 (first modified example), and 24 (second modified example), the thickness of the silicon nitride film NT is preferably set to a thickness that provides a certain degree of barrier effect against moisture. From this perspective, the thickness of the silicon nitride film NT is preferably set to 10 nm or more. Since it is desirable to suppress the thickness of the silicon nitride film NT in order to suppress the generation of stress in the semiconductor substrate SB due to the silicon nitride film NT, the thickness of the silicon nitride film NT is preferably set to less than half the thickness of the insulating film ZF. That is, it is preferable to allocate the majority (more than half) of the thickness of the insulating film ZF to the silicon oxide film. For this reason, in the case of FIG. 6, the thickness of the silicon nitride film NT is preferably set to be smaller than the sum of the thicknesses of the silicon oxide film OX1 and the silicon oxide film OX2. In the case of FIG. 23 (first modified example), the thickness of the silicon nitride film NT is preferably set to be smaller than the thickness of the silicon oxide film OX2. In the case of FIG. 24 (second modified example), the thickness of the silicon nitride film NT is preferably set to be smaller than the thickness of the silicon oxide film OX1.

[0113] Incidentally, a silicon nitride film is an insulating film that has a charge storage function. For this reason, in the case of FIG. 23 (first modified example), the silicon nitride film NT is in contact with the field plate portion FP, which raises the following concerns. That is, compared to a silicon oxide film, a silicon nitride film has more charge traps in the film, and charge is more likely to accumulate in the film. For this reason, charge accumulates in the silicon nitride film during film formation, and this charge storage state is likely to be maintained even after the semiconductor device is manufactured. For this reason, when the silicon nitride film NT is in contact with the field plate portion FP, the accumulated charge in the silicon nitride film NT will affect the electrical characteristics of the field plate portion FP, and there is a risk that the electrical characteristics of the field plate portion FP will fluctuate.

[0114] In contrast, in the case of FIG. 6 and the case of FIG. 24 (second modified example), the silicon nitride film NT included in the insulating film ZF is not in contact with the field plate portion FP. That is, a silicon oxide film OX1 is interposed between the silicon nitride film NT and the field plate portion FP. Therefore, even if charges are accumulated in the silicon nitride film NT, the silicon oxide film OX1 is interposed between the silicon nitride film NT and the field plate portion FP, so that it is possible to suppress or prevent the accumulated charges in the silicon nitride film NT from affecting the electrical characteristics of the field plate portion FP. Therefore, it is possible to suppress or prevent fluctuations in the electrical characteristics of the field plate portion FP due to the accumulated charges in the silicon nitride film NT.

[0115] 6, the silicon nitride film NT is not in contact with the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, or the outer surrounding wiring SCW, so that it is possible to prevent charges from moving from the emitter electrode EE, the gate electrode wiring GEW, the inner surrounding wiring FCW, or the outer surrounding wiring SCW to the silicon nitride film NT and accumulating in the silicon nitride film NT. For this reason, the case of FIG. 6 is the best for preventing fluctuations in the electrical characteristics of the field plate portion FP due to accumulated charges in the silicon nitride film NT.

[0116] On the other hand, in the case of Fig. 6, forming the insulating film ZF requires the steps of depositing three insulating films, whereas in the cases of Fig. 23 (first modified example) and Fig. 24 (second modified example), forming the insulating film ZF requires the steps of depositing two insulating films. Therefore, the number of manufacturing steps for the semiconductor device can be reduced in the cases of Fig. 23 (first modified example) and Fig. 24 (second modified example) compared to the case of Fig. 6.

[0117] FIG. 25 is a plan view of a main part showing a third modified example of the semiconductor device CP of this embodiment, and shows the conductor pattern TCP of the field plate portion FP.

[0118] In the cases of FIGS. 1 to 8, the field plate portion FP (conductor patterns FCP, TCP, SCP) is either entirely a p-type semiconductor region or entirely an n-type semiconductor region.

[0119] 25, the conductor pattern TCP of the field plate portion FP has a structure in which a plurality of p-type semiconductor regions PRG and n-type semiconductor regions NRG are alternately arranged along the extending direction (direction of current flow) of the conductor pattern TCP. A PN junction is formed between the p-type semiconductor regions PRG and the n-type semiconductor regions NRG. The conductor pattern FCP of the field plate portion FP is entirely made up of a p-type semiconductor region or an n-type semiconductor region, and the conductor pattern SCP of the field plate portion FP is entirely made up of a p-type semiconductor region or an n-type semiconductor region.

[0120] In the case of the third modified example shown in Fig. 25, when a current flows through the conductor pattern TCP of the field plate portion FP, the current alternately passes through the p-type semiconductor region PRG and the n-type semiconductor region NRG, resulting in the current passing through multiple PN junctions. Therefore, compared to when the entire field plate portion FP (conductor patterns FCP, TCP, SCP) is a p-type semiconductor region or when the entire field plate portion FP (conductor patterns FCP, TCP, SCP) is an n-type semiconductor region, the third modified example shown in Fig. 25 can reduce the current flowing between the collector and emitter through the field plate portion FP. When the third modified example shown in Fig. 25 is applied, the leakage current of a semiconductor element (e.g., an IGBT) formed in the semiconductor device CP can be suppressed, making it suitable for semiconductor devices that require a low leakage current.

[0121] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0122] BF barrier conductor film CE collector electrode CH channel formation region CP Semiconductor Devices CR Collector Region CS channel stopper area CT1, CT2, CT3, CT4, CT5 contact holes DR element area EE emitter electrode ER emitter region FCP Conductor Pattern FCW inner circumferential wiring FP field plate section FPR p-type semiconductor region IL1,IL2 insulating film JW connection wiring part GE gate electrode part GEW Gate electrode wiring GF gate insulating film GW Gate wiring section MF main conductor membrane NRG n-type semiconductor region NT Silicon nitride film OX1, OX2 silicon oxide film PF,PF100 Protective film PF101 Silicon nitride film PF102 resin film PR Peripheral Areas PRG p-type semiconductor region PS1, PS2, PS3 p + Type semiconductor region RS Resurf region SB semiconductor substrate SCP Conductor Pattern SCW outer circuit wiring SR field stop region TCP conductor pattern TG trench gate electrode TR groove ZF, ZF100, ZF200 insulating film

Claims

1. a semiconductor substrate having a main surface and a back surface located opposite to each other; a field plate portion formed on the main surface of the semiconductor substrate via a first insulating film; a second insulating film formed on the main surface of the semiconductor substrate so as to cover the first insulating film and the field plate portion; a first metal pattern and a second metal pattern formed on the second insulating film; an insulating protective film formed on the second insulating film so as to cover the first metal pattern and the second metal pattern; and each of the first metal pattern and the second metal pattern is electrically connected to the field plate portion; each of the first metal pattern and the second metal pattern is thicker than the field plate portion; the field plate portion is made of polycrystalline silicon, The semiconductor device, wherein the second insulating film is a laminated film of one or more silicon nitride films and one or more silicon oxide films.

2. 2. The semiconductor device according to claim 1, the second insulating film is a stacked film of a first silicon oxide film, a first silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the first silicon nitride film.

3. 3. The semiconductor device according to claim 2, The first silicon oxide film is in contact with the field plate portion.

4. 2. The semiconductor device according to claim 1, the second insulating film is a stacked film of a first silicon oxide film and a first silicon nitride film on the first silicon oxide film.

5. 5. The semiconductor device according to claim 4, The first silicon oxide film is in contact with the field plate portion.

6. 2. The semiconductor device according to claim 1, the second insulating film is a stacked film of a first silicon nitride film and a first silicon oxide film on the first silicon nitride film.

7. 7. The semiconductor device according to claim 6, The first silicon nitride film is in contact with the field plate portion.

8. 2. The semiconductor device according to claim 1, the protective film is in contact with the first metal pattern and the second metal pattern; The semiconductor device, wherein the protective film does not include a silicon nitride film.

9. 9. The semiconductor device according to claim 8, The semiconductor device, wherein the protective film is a top layer film.

10. 2. The semiconductor device according to claim 1, The protective film is made of a resin film.

11. 2. The semiconductor device according to claim 1, an element region in which a semiconductor element is formed is disposed in a central portion of the main surface of the semiconductor substrate; the first metal pattern is arranged to surround the element region in a plan view and is electrically connected to a first portion of the semiconductor substrate exposed from the second insulating film; the second metal pattern is disposed so as to surround the first metal pattern in a plan view, and is electrically connected to a second portion of the semiconductor substrate exposed from the second insulating film; the field plate portion integrally includes a first conductor pattern arranged to surround the element region in a plan view, a second conductor pattern arranged to surround the first conductor pattern in a plan view, and a third conductor pattern arranged between the first conductor pattern and the second conductor pattern in a plan view and connecting the first conductor pattern and the second conductor pattern, the first metal pattern is electrically connected to the first conductor pattern of the field plate portion, The second metal pattern is electrically connected to the second conductor pattern of the field plate portion.

12. 12. The semiconductor device according to claim 11, a first electrode for the semiconductor element is formed on the second insulating film on the element region; a second electrode for the semiconductor element is formed on the back surface of the semiconductor substrate; The protective film covers a portion of the first electrode.

13. 13. The semiconductor device according to claim 12, the first metal pattern is electrically connected to the first electrode; The second metal pattern is electrically connected to the second electrode through the semiconductor substrate.

14. 12. The semiconductor device according to claim 11, In the third conductor pattern, a plurality of p-type semiconductor regions and a plurality of n-type semiconductor regions are alternately arranged along an extending direction of the third conductor pattern.

15. (a) providing a semiconductor substrate having opposed main and back surfaces; (b) forming a semiconductor element in an element region of the semiconductor substrate; (c) forming a field plate portion on the main surface of the semiconductor substrate via a first insulating film; (d) forming a second insulating film on the main surface of the semiconductor substrate so as to cover the first insulating film and the field plate portion; (e) forming a first metal pattern and a second metal pattern on the second insulating film; (f) forming an insulating protective film on the second insulating film so as to cover the first metal pattern and the second metal pattern; and each of the first metal pattern and the second metal pattern is electrically connected to the field plate portion; the field plate portion is made of polycrystalline silicon, The method for manufacturing a semiconductor device, wherein the second insulating film is a laminated film of one or more silicon nitride films and one or more silicon oxide films.

16. 16. The method for manufacturing a semiconductor device according to claim 15, In the step (e), a first electrode for the semiconductor element is formed on the second insulating film on the element region; After the step (f), (g) forming a second electrode for the semiconductor element on the back surface of the semiconductor substrate; and the first metal pattern is electrically connected to the first electrode; The second metal pattern is electrically connected to the second electrode through the semiconductor substrate.

17. 16. The method for manufacturing a semiconductor device according to claim 15, the second insulating film is a stacked film including a first silicon oxide film in contact with the field plate portion, a first silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the first silicon nitride film.

18. 16. The method for manufacturing a semiconductor device according to claim 15, the second insulating film is a stacked film of a first silicon oxide film in contact with the field plate portion and a first silicon nitride film on the first silicon oxide film.

19. 16. The method for manufacturing a semiconductor device according to claim 15, the second insulating film is a stacked film of a first silicon nitride film in contact with the field plate portion and a first silicon oxide film on the first silicon nitride film.

20. 16. The method for manufacturing a semiconductor device according to claim 15, The method for manufacturing a semiconductor device, wherein the protective film is in contact with the first metal pattern and the second metal pattern and does not include a silicon nitride film.

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