Improved SiC substrates and methods for the production of SiC epilayers

Abstract

To provide a method, a SiC substrate, and a semiconductor device that improve the quality and performance of SiC epilayers by reducing the concentration of TM incorporated into the SiC epilayer during processing.SOLUTION: A method for manufacturing a silicon carbide (SiC) substrate includes at least the steps of a) providing a SiC substrate 1 suitable for growing a SiC epilayer, and b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions, wherein the irradiation is performed at an energy between 100 keV and 200 keV and at an irradiation dose between 105 cm-2 and 1010 cm-2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Technical Field The present invention relates to methods for fabricating silicon carbide (SiC) substrates and SiC epilayers on such substrates, where the substrates are modified to capture transition metals (TM). Additionally, the present invention relates to the modified SiC substrates themselves and semiconductor devices comprising these SiC substrates. [Background technology]

[0002] Background technology With respect to the functionality and lifetime of state-of-the-art electronics, the quality of semiconductor devices is of paramount importance. Impurities must be avoided, especially in the field of epitaxially grown SiC layers, as they can impair the structural and electronic properties of the semiconductor layer. Such defects are particularly detrimental in semiconductor layers processed for high-voltage (HV) applications. One source of unwanted impurities introduced into the process and layers is TM. TM are typically present in the crucible material and can be incorporated into the SiC boule or SiC substrate during bulk growth. After substrate preparation, such impurities can diffuse into the final epilayer during homoepitaxy of the epilayer. Transition metal impurities are known to form deep levels in the bandgap of SiC that can impair device functionality. As a function of the crucible material and overall processing conditions, the TM concentration in the epilayer can vary from 10 13 cm -3 From 10 14 cm -3 For HV applications, the epilayer doping is low (<10 14 cm -3 ), the presence of such TM in the epilayer poses serious problems for the fabrication of HV devices. Therefore, it is important to reduce the TM concentration in the epilayer or to pre-passivate the TM.

[0003] Patent documents also disclose suitable means for treating impurities in SiC semiconductor devices. For example, U.S. Pat. No. 9,508,802 discloses a process for manufacturing a semiconductor device. The process includes forming a SiC epitaxial layer on a SiC substrate, implanting ions into the epitaxial layer, forming a gettering layer with a defect density higher than that of the SiC substrate, and subjecting the epitaxial layer to a heat treatment. The semiconductor device includes a SiC substrate, a SiC epitaxial layer formed on the SiC substrate, and a gettering layer with a defect density higher than that of the SiC substrate. The method is based on implanting He into the epilayer. After high-temperature treatment, the He-implanted region functions as a gettering layer for diffusing TM. A drawback of this method is that implanting the epilayer creates more electrically active defects, which affect the electronic properties of the completed HV device in terms of leakage current, minority carrier lifetime, and on-resistance. Summary of the Invention [Problem to be solved by the invention]

[0004] Summary of the Invention It is therefore an object of the present invention to provide a solution for improving the quality and performance of SiC epilayers, in particular by reducing the concentration of TMs incorporated into the SiC epilayers during processing, and in particular to avoid or mitigate the drawbacks of known solutions. [Means for solving the problem]

[0005] The object of the present invention is solved by the features of the independent claims. Preferred embodiments are detailed in the dependent claims.

[0006] The object is therefore to provide a method for producing a silicon carbide (SiC) substrate, comprising: a) providing a SiC substrate suitable for growing a SiC epilayer; b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions; and The irradiation energy is between 100 keV and 200 keV, and 5 cm -2 Over 10 10 cm -2 This is solved by the method, which is carried out at the following irradiation doses:

[0007] Specifically, the present invention proposes a method for producing silicon carbide (SiC) substrates. SiC substrates are generally used as a basis for growing structurally defined SiC epilayers. The materials and structures are used as semiconductors for high-voltage and / or high-temperature applications. The substrates can be in the form of a boule or a wafer. If a boule is used, wafers can be cut from the boule in a later step to produce wafers. If the substrate is in the form of a wafer, the wafer dimensions can be adjusted according to specific needs. Standard wafer thicknesses and diameters can be used in the process of the present invention. Substrate thicknesses can range, for example, from 10 to 400 μm. Suitable substrate diameters can range from 1 cm to 10 cm. Typical boule dimensions are in the range of 10 to 20 cm.

[0008] The method includes step a). In this step, a SiC substrate suitable for the growth of a SiC epilayer is provided. This means that the substrate is suitable for providing the characteristics necessary for depositing a structurally coherent and defined SiC epilayer in a subsequent step. The defined SiC epilayer may be, for example, a 2H-, 4H-, or 6H-SiC epilayer. 4H- and 6H-SiC epilayers are preferred. The substrate may be, for example, a seed substrate that includes a special seed layer on top of the substrate. The seed layer can also be deposited after the formation of the substrate of the invention. The substrate is particularly suitable for growth if a suitable epilayer can be formed using high-temperature chemical vapor deposition techniques or any other technique that achieves a structurally well-defined epilayer.

[0009] The method further includes a step b) of implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions. The SiC substrate is modified by incorporating a group Va element into the substrate. Group Va elements are elements of the fifth main group of the periodic system of elements, namely N, P, As, Sb, and Bi. The elements N, P, and As are preferred. The implantation or incorporation can be carried out, for example, by accelerating the element in the form of particles and bombarding the accelerated particles with the substrate. The element can be kinetically incorporated into the substrate, for example, by irradiation. Suitable implantation of group Va elements can be based on the incorporation of the respective ions, where Va ions are accelerated by an electric accelerator and directed toward the substrate surface.

[0010] The irradiation in step b) is carried out with an energy of 100 keV to 200 keV and 10 5 cm -2 Over 10 10 cm -2The irradiation is performed at the following doses: The overall irradiation conditions, in the form of energy and dose, are selected to achieve a certain Va implantation level in the substrate. The selection of the irradiation parameters allows, in particular, to generate carbon vacancies (VC) in the substrate without changing the electrical properties of the substrate. Therefore, it is not the intention of the irradiation or implantation process to specifically affect the resistivity or conductivity of the substrate; such changes are not achieved at the specified dose and energy levels. Higher doses and / or higher energy levels may result in undesirable changes in the electrical substrate properties, in particular the substrate resistivity may be affected.

[0011] The present invention and the embodiments described herein provide an improved SiC substrate, which can capture TM metals at VC sites by forming transition metal-VC (TM-VC) complexes. Transition metals are known to function as acceptors, particularly in n-type 4H-SiC. Therefore, we propose using carbon vacancies, which can effectively bond with transition metals. VC-TM complexes are easily formed and energetically stable. This method allows a TM gettering / passivation layer to be formed in or by the substrate prior to epitaxial growth. In this way, the final device is immune to further ion beam processing. While the implantation results in the formation of VC, the resistivity of the substrate is not affected due to the presence of the implanted Va group element. The proposed implantation characteristics are suitable for achieving an appropriate VC concentration in the substrate. The VC concentration achievable by these ranges does not affect the resistivity of the substrate. Furthermore, because the dose is below the amorphization level of the crystal, high-temperature post-implantation processing is not required.

[0012] TM gettering occurs within the substrate without damaging the crystalline structure of the deposited epilayer. This leaves the epilayer structurally intact, resulting in better physical properties. The TM-VC complex is energetically very stable, effectively preventing the diffusion of TM from the substrate into the epilayer during homoepitaxial growth.

[0013] This solution is preferable to the use of an additional buffer layer, since the buffer layer must be grown in a separate step, whereas the trapping proposed in this invention is achieved by implantation. In contrast to a heavily doped buffer layer, the doping of this implanted layer is much lower, leaving the electrical properties of the substrate unchanged. Because the Fermi level of the buffer layer is close to the conduction band, a heavy doping of the buffer layer also leads to faster TM diffusion. This means that the formation energy of TMs in such a buffer layer is lower, which also affects their migration and diffusion energies.

[0014] As a result, the proposed solution includes several advantages compared to buffer layers known in the art.

[0015] The object is to provide a method for producing a silicon carbide (SiC) epilayer on a SiC substrate, comprising: a) providing a SiC substrate suitable for growing a SiC epilayer; b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions, the irradiation having an energy of 100 keV to 200 keV and a concentration of 10 5 cm -2 Over 10 10 cm -2 performed at a dose of: c) epitaxially growing a SiC epilayer on the SiC substrate obtained in method step b), the growth being carried out at a temperature between 1200°C and 1500°C. The problem is further solved by a method comprising at least

[0016] This method can be considered as a method for producing a final product, whereas the previous method can be considered as a method for producing an intermediate product. The difference can be seen in the last method step c), where the epitaxial layer is produced.

[0017] Surprisingly, it has been found that when the epitaxial layer is grown under the above-defined conditions, the diffusion of TM from the substrate is significantly reduced, resulting in an improved epitaxial layer. In particular, the structural and electrical properties of the epitaxial layer are superior to the standard, resulting in a SiC epitaxial layer with a long lifetime. For further advantages of the method for producing a SiC epitaxial layer, please refer in particular to the method for producing a SiC substrate. A high temperature in method step b) can be disadvantageous, since in this case TM can diffuse into the epilayer. A low temperature can be disadvantageous, since it hinders the growth of the epilayer.

[0018] The objective is to provide a carbon vacancy (VC) and a transition metal VC complex, the sum of the concentrations of VC and the transition metal VC complex being 10 12 cm -3 Over 10 16 cm -3The following is further resolved by the SiC substrate: The total amount of VC and TM-VC complexes in the substrate can be assessed by electron spin resonance (ESR) experiments. Both species have distinct and unique ESR signatures, allowing for quantitative measurements. The concentrations of VC and transition metal-VC complexes can be assessed separately, and adding both concentrations results in the total amount. The substrate can exist in the form of a boule of regular or irregular shape, or it can exist in the form of a flat disk, plate, or wafer. Plate-like means that the shape is flat and / or at least substantially extends in two of the three dimensions. A plate may be flat in one direction but substantially elongate in two directions, with all three directions being perpendicular to each other. In particular, the width and length of a plate are each at least 2, 5, 10, 50, or 100 times greater than the thickness to be considered plate-like. The advantages of the SiC substrate according to the present invention have been described above in connection with the method for producing the SiC substrate of the present invention.

[0019] The above-mentioned object is further achieved by a semiconductor device comprising a SiC substrate and an epitaxial layer on the SiC substrate, the SiC substrate being a SiC substrate according to the present invention. In particular, semiconductor devices can benefit from improved SiC substrates. The devices can have better electronic properties and exhibit better lifetimes. These advantages are achieved by controlling and reducing the TM content in the epilayer of the device. The semiconductor device can be, for example, a thyristor, a diode, a gate turn-off thyristor, a power metal-insulator-semiconductor field-effect transistor, a power metal-oxide-semiconductor field-effect transistor, a junction field-effect transistor, a bipolar junction transistor, an insulated gate bipolar transistor, or an integral gate commutated thyristor. The advantages of the semiconductor device according to the present invention have been described above in relation to the method for manufacturing the SiC substrate according to the present invention and the SiC substrate.

[0020] In a first preferred embodiment of the method for producing a SiC substrate, in an additional method step b'), the SiC substrate obtained in method step b) is heat-treated at a temperature between 1000°C and 1700°C for a time period between 5 and 24 hours. The heat treatment of the substrate under the above conditions allows the substrate to equilibrate and promotes the formation of TM-VC complexes if TMs are already present in the substrate. This step reduces the number of diffusible TMs in the substrate. Preferably, this heat treatment step can be carried out at a temperature between 1100°C and 1600°C for a time period between 8 and 20 hours, or even at a temperature between 1200°C and 1400°C for a time period between 10 and 18 hours. This heat treatment preferably produces a uniform distribution of Va ions and VC throughout the substrate. A concentration difference of 10 mol% / cm is preferred. 3 If < , the distribution is uniform across the substrate. The concentration can be quantitatively determined as a function of position on the substrate by EPR.

[0021] In a second preferred embodiment of the method for producing a SiC substrate, in step b) carbon vacancies (VC) are generated in the substrate, and the concentration of VC in the substrate is 10 13 cm -3 Over 10 17 cm -3 This VC concentration has been shown to be useful for capturing sufficient TM in the substrate and largely avoiding the possibility of TM diffusion into the epilayer during epitaxial growth. Lower concentrations can be disadvantageous because they do not achieve sufficient complex formation with TM. Higher concentrations can be disadvantageous because they have a significant effect on the electrical properties of the substrate. Furthermore, the VC concentration in the substrate is 10 14 cm -3 Over 10 16 cm -3 It may be the following:

[0022] In a third preferred embodiment of the method for producing a SiC substrate, the Va group ions are selected from the group consisting of nitrogen ions, phosphorus ions, or a mixture thereof. Implantation of N and P ions into the substrate has been found to be useful for reliably producing the required VC concentration in various substrates without changing the electronic properties of the substrate.

[0023] In a fourth preferred embodiment of the method for producing a SiC substrate, the resistivity of the SiC substrate after step b) changes by less than 10% compared to the resistivity of the SiC substrate in step a). One of the main advantages of the method is that the implantation of Va ions and the generation of VC essentially do not change the resistivity of the substrate. In a preferred embodiment, the resistivity of the SiC substrate after step b) changes by less than 8% compared to the resistivity of the SiC substrate in step a), and more preferably, the resistivity of the SiC substrate after step b) changes by less than 5% compared to the resistivity of the SiC substrate in step a). The resistivity of the substrate is evaluated at 20°C according to methods known to those skilled in the art, such as the four-point probe method with removable graphite contacts.

[0024] In a fifth preferred embodiment of the method for producing a SiC substrate, the implantation density of group Va ions in the SiC substrate is 10 10 cm -3 Over 10 16 cm -3 Such implantation of group Va ions into SiC substrates has been shown to be useful for producing optimal VC concentrations within the substrate. The overall electrical and structural properties of the substrate remain largely unchanged. Furthermore, the density of group Va ions in the SiC substrate is 10 11 cm -3 Over 10 15 cm -3 More preferably, the density of Va group ions in the SiC substrate is 10 12 cm -3 Over 10 14 cm -3It may be: It is further preferred that the implantation is uniform throughout the substrate.

[0025] In a sixth preferred embodiment of the method for producing a SiC substrate, the SiC substrate in method steps a) and b) has n-type conductivity. In particular, for substrates with n-type conductivity, the method according to the present invention can provide highly effective VC generation and TM complex formation. Furthermore, the formed TM-VC complex is highly stable, allowing epitaxial layers to be grown on TM-free substrates.

[0026] In a seventh preferred embodiment of the method for producing a SiC substrate, step b) is carried out at a temperature of 20° C. to 800° C. This temperature range for the Va implantation and VC generation steps can result in a reasonably uniform VC distribution in the substrate.

[0027] In a first preferred embodiment of the method for producing a SiC epilayer, after method step b) and before method step c), the SiC substrate is heat-treated at a temperature between 1000°C and 1900°C for a time period between 0.5 and 24 hours. Heat-treating the substrate under the above given conditions has proven useful for the safe and reproducible formation of TM complexes in the substrate prior to epitaxial growth. The structure of the substrate remains unchanged, but TMs are trapped, likely due to a diffusion process. Non-diffusive complexes are produced. These complexes are fairly stable and do not interact with the epilayer grown in step c). As a result, a TM-free or TM-reduced epilayer is achieved, which exhibits better electronic properties and a longer lifetime.

[0028] In a second preferred embodiment of the method for producing a SiC epilayer, the thickness of the SiC epilayer is 50 μm or more and 250 μm or less. The method for producing a SiC epilayer is particularly suitable for producing epilayers of the above thickness. The epilayer is particularly suitable for high-voltage applications, and due to the fact that the TM is reliably captured within the substrate, the epilayer exhibits outstanding lifespan and uniform electrical properties. Furthermore, the thickness of the SiC epilayer may be 60 μm or more and 200 μm or less, and more preferably, the thickness of the SiC epilayer may be 80 μm or more and 50 μm or less.

[0029] In a first preferred embodiment of the semiconductor device, the epitaxial layer is an n-type 4H—SiC epitaxial layer, and in particular, n-type 4H SiC epitaxial layers can benefit from a reduced TM concentration in the epitaxial layer.

[0030] In a second preferred embodiment of the semiconductor device, the thickness of the epitaxial layer is 50 μm to 200 μm. The advantages of a semiconductor device comprising an epitaxial layer in such a thickness range have already been described in the context of the epilayer.

[0031] BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. [Brief explanation of the drawings]

[0032] [Figure 1] 1 shows a preferred embodiment of a method according to the invention for producing a silicon carbide (SiC) substrate. [Figure 2] 1 shows a preferred embodiment of a method according to the invention for producing a silicon carbide epilayer on a SiC substrate. DETAILED DESCRIPTION OF THE INVENTION

[0033] Description of the Preferred Embodiments The description includes procedural or methodological aspects when describing structural features of the claimed invention; in this way, the structural features can be fully understood. The reader is reminded that such structural features can be extracted from the described context without hesitation or intermediate generalization issues to form aspects of the present invention. The reader is also reminded that any structural feature described below, regardless of its possibility of being extracted from the context, can be understood as an individual aspect of the present invention for the purpose of distinguishing it from known solutions.

[0034] FIG. 1 illustrates a process for the production of a SiC substrate 1. The substrate 1 may be provided in the form of a boule, wafer, or plate. In this figure, a plate-like shape is shown. The SiC substrate 1 contains a transition metal 2. TM2 is distributed within the SiC substrate 1. In the next process step, method step b), the SiC substrate 1 is irradiated with a group Va element. The group Va element may be in the form of particles or ions. Preferably, the group Va element is provided in the form of ions, which are accelerated and kinetically implanted into the SiC substrate 1. The implantation of the Va ions into the SiC substrate 1 forms carbon vacancies VC3. In a separate method step, the SiC substrate 1 can be heat-treated at a higher temperature. The heat treatment leads to the diffusion of VC3 and TM2, resulting in the formation of positionally stable TM-VC complexes 4. The TM-VC complexes 4 remain trapped at their formation sites and can no longer diffuse throughout the SiC substrate 1. Using this method step, a SiC substrate 1 is produced that does not contain much mobile TM2. The SiC substrate 1 can be stored for further processing. Additionally, the SiC substrate 1 can be immediately used to epitaxially grow an epitaxial layer 5 on the substrate 1. The epitaxial growth of the epitaxial layer 5 can be performed according to methods known to those skilled in the art. By including this separate method step, a SiC epilayer 5 is produced on the SiC substrate 1, and the SiC epilayer 5 does not contain TM2. In general, the overall concentration of diffusible TM2 is significantly reduced. This method can be used to produce an epilayer 5 for high-voltage applications. The epilayer 5 can be, for example, a 4-H SiC epilayer.

[0035] FIG. 2 illustrates a process for producing a SiC epilayer 5 on a SiC substrate 1. The provided substrate 1 may be in the form of a boule, wafer, or plate. In this illustration, a plate-like shape is used. The SiC substrate 1 contains a transition metal 2. TM2 is distributed within the SiC substrate 1. In the next process step, method step b), the SiC substrate 1 is irradiated with a Va element. The Va element may be in the form of particles or ions. Preferably, the Va element is provided in the form of ions, which are accelerated and kinetically implanted into the SiC substrate 1. The implantation of the Va ions into the SiC substrate 1 results in the formation of carbon vacancies 3. This SiC substrate 1 can be used in the next method step, in which an epilayer 5 is grown on the surface of the SiC substrate 1. During the growth of the epilayer 5, TM2 diffuses through the SiC substrate 1 and is trapped in VC3. It can be seen in this illustration that one diffusible TM2 not bound to VC3 is still present. The remaining TM2 is converted into the thermodynamically and spatially stable TM-VC complex 4. The TM-VC complex 4 remains in the SiC substrate 1 and does not diffuse into the epilayer 5 during epitaxial growth. This reduces the amount of TM2 incorporated into the epilayer 5, improving the electronic and structural properties of the epilayer 5. The epitaxial growth of the epilayer 5 can be performed according to methods known to those skilled in the art. This method can be used to produce epilayers 5 for high-voltage applications. The epilayer 5 can be, for example, a 4-H SiC epilayer.

[0036] A possible method sequence can include providing a SiC substrate 1, the SiC substrate 1 having a thickness of 350 μm. 18 cm -3 N-doped to a concentration of about 10 14 cm -3 The implantation of Va group elements is carried out in process step b). The implantation is carried out by applying N ions at RT. 7 cm -2A dose of 100 keV is used, and the implant energy is 100 keV. Using these parameters, a dose of approximately 3 × 10 14 cm -3 of VC was generated, and the concentration of injected N was approximately 10 12 cm -3 An additional heat treatment step is performed at 1200°C for 10 hours. In this step, the Vc-TM complex 4 is formed. In the next step, a 100 μm 4H—SiC epilayer 5 is grown (N is about 10 14 cm -3 ) No TM2 is found in the epitaxially grown layer 5, and the resistivity of the epitaxial layer 5 is intact. Devices can now be fabricated. The anode is formed by implanting Al and then annealing at 1700°C for 30 minutes. A mesa is formed by RIE, and ohmic metal is deposited to produce a 10 kV pin diode. [Explanation of symbols]

[0037] List of reference numbers 1. SiC substrate 2 Transition metals (TM) 3 Carbon vacancy (VC) 4 Transition metal-carbon vacancy (TM-VC) composite 5 epilayer

Claims

1. A method for manufacturing a silicon carbide (SiC) substrate (1), comprising: a) providing a SiC substrate (1) suitable for growing a SiC epilayer (5); b) implanting group Va elements into the SiC substrate (1) by irradiating at least a portion of the SiC substrate (1) with group Va ions; and The irradiation has an energy of 100 keV or more and 200 keV or less, and ５ cm －２ 10 above １０ cm －２ The method is carried out at the following doses:

2. 2. The method according to claim 1, wherein in an additional method step b') the SiC substrate (1) obtained in method step b) is heat treated at a temperature between 1000 ° C and 1700 ° C for a time between 5 and 24 hours.

3. In step b), carbon vacancies (VC) (3) are generated in the substrate (1), and the concentration of VC (3) in the substrate (1) is 10 １３ cm －３ 10 above １７ cm －３ 3. The method of claim 1 or 2, wherein:

4. 3. The method of claim 1, wherein the group Va ions are selected from the group consisting of nitrogen ions, phosphorus ions, or mixtures thereof.

5. 3. The method according to claim 1 or 2, wherein the resistivity of the SiC substrate (1) after step b) changes by less than 10% compared to the resistivity of the SiC substrate (1) in step a).

6. The implantation density of the Va group ions in the SiC substrate (1) is 10 １０ cm －３ 10 above １６ cm －３ 3. The method of claim 1 or 2, wherein:

7. 3. The method according to claim 1, wherein the SiC substrate (1) in method steps a) and b) has n-type conductivity.

8. 3. The method according to claim 1, wherein step b) is carried out at a temperature of 20°C to 800°C.

9. A method for producing a silicon carbide (SiC) epilayer (5) on a SiC substrate (1) produced by the method of claim 1, comprising: c) epitaxial growth of a SiC epilayer (5) on the SiC substrate (1) obtained in method step b), said growth being carried out at a temperature between 1200°C and 1500°C. The method includes at least the following.

10. 10. The method according to claim 9, wherein after method step b) and before method step c), the SiC substrate (1) is heat treated at a temperature between 1000 ° C and 1900 ° C for a time between 0.5 h and 24 h.

11. 11. The method according to claim 9 or 10, wherein the thickness of the SiC epilayer (5) is between 50 μm and 250 μm.

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