Transistors and related manufacturing methods involving semiconductor surface modification

Abstract

The transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein exposing a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 325,488, filed May 20, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to transistor devices and related manufacturing methods. [Background technology]

[0003] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for low power and, in the case of Si, low frequency applications. However, these materials may be less suitable for high power and / or high frequency applications due, for example, to their relatively small bandgaps (1.12 eV for Si and 1.42 for GaAs at room temperature) and relatively small breakdown voltages.

[0004] In high-power, high-temperature, and / or high-frequency applications and devices, wide bandgap semiconductor materials such as silicon carbide (SiC) (e.g., having a bandgap of about 3.2 eV for 4H—SiC at room temperature) and Group III nitrides (e.g., having a bandgap of about 3.36 eV for gallium nitride (GaN) at room temperature) may be used. These materials may have higher electric field breakdown strengths and higher electron saturation velocities compared to GaAs and Si.

[0005] A device of particular interest for high power and / or high frequency applications is the high electron mobility transistor (HEMT), also known as the modulation doped field effect transistor (MODFET). In a HEMT device, a two-dimensional electron gas (2DEG) may form at the heterojunction of two semiconductor materials with different band gap energies. The smaller band gap material may have a higher electron affinity than the wider band gap material. The 2DEG is an accumulation layer in the undoped smaller band gap material, e.g., 10 13 Carrier / cm 2 HEMTs can contain a relatively high sheet electron concentration exceeding 1000 MHz. Additionally, electrons from the wider bandgap semiconductor can migrate to the 2DEG, allowing for relatively high electron mobility due to reduced ionized impurity scattering. The combination of relatively high carrier concentration and carrier mobility allows HEMTs to achieve a relatively large transconductance, giving them a performance advantage over metal-oxide-semiconductor field effect transistors (MOSFETS) for high-frequency applications.

[0006] HEMTs fabricated with III-nitride materials (such as the gallium nitride / aluminum gallium nitride (GaN / AlGaN) material system) can generate large amounts of radio frequency (RF) power due to a combination of material properties such as a relatively high breakdown field, a relatively wide bandgap, a relatively large conduction band offset, and / or a relatively high saturated electron drift velocity. Therefore, HEMT devices may be used in RF power amplifiers. III-nitride-based HEMTs also offer high charge density, high electron mobility, and improved thermal conductivity, especially on SiC substrates.

[0007] Electron trapping and the resulting discrepancy between DC and RF characteristics can be a limiting factor in the performance of these devices. Silicon nitride (SiN) passivation has been employed to mitigate this trapping problem, enabling high-performance devices with power densities exceeding 10 W / mm at 10 GHz. For example, U.S. Patent No. 6,586,781 to Wu et al. describes methods and structures for reducing trapping effects in GaN-based transistors. However, due to the high electric fields present in these structures, charge trapping can still be a concern. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Patent No. 6,586,781 [Patent Document 2] U.S. Patent No. 5,210,051 [Patent Document 3] U.S. Patent No. 5,393,993 [Patent Document 4] U.S. Patent No. 5,523,589 [Patent Document 5] U.S. Patent No. 7,030,428 [Patent Document 6] U.S. Patent No. 8,563,372 [Patent Document 7] U.S. Patent No. 9,214,352 [Patent Document 8] U.S. Patent No. 8,120,064 [Patent Document 9] U.S. Patent No. 6,548,333 Summary of the Invention [Means for solving the problem]

[0009] According to some embodiments of the present invention, a transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact, the surface passivation layer including an opening therein exposing a first region of the semiconductor structure for processing the first region.

[0010] In some embodiments, the semiconductor structure may include a channel layer and a barrier layer defining a heterojunction therebetween. The first region may have a higher conductivity than a second region of the semiconductor structure adjacent the gate. In some embodiments, the first region may have a lower sheet resistance than the second region.

[0011] In some embodiments, the first region may have different surface properties than the second region.

[0012] In some embodiments, the first region may have modified interface states, and the second region may have no modified interface states or may have interface states that are modified in a different way.

[0013] In some embodiments, the opening may be laterally separated from the gate by a second region. In some embodiments, the gate may include a side lobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, and the side lobe portion may extend over the second region. In some embodiments, the opening may be spaced laterally from the gate along the surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

[0014] In some examples, the surface passivation layer may be a first passivation layer. A second passivation layer may be disposed on the first passivation layer and extend into the opening to contact the first region. The interface between the first region and the second passivation layer may have a modified interface state that may differ from the interface between the second region and the first passivation layer.

[0015] In some embodiments, the modified interface state may be defined by the formation of a second passivation layer.

[0016] In some embodiments, a field plate may be provided on the second passivation layer and between the gate and drain contacts, and the opening may be laterally spaced from at least a portion of the field plate.

[0017] In some embodiments, the field plate may at least partially overlap the opening with the second passivation layer therebetween.

[0018] In some embodiments, the surface treated region may be defined by ion bombardment, plasma nitridation, plasma oxidation, hydrogen plasma treatment, and / or annealing in a gas environment.

[0019] According to some embodiments, a transistor device includes a semiconductor structure including a channel layer and a barrier layer defining a heterojunction therebetween, a source contact and a drain contact on the semiconductor structure, and a gate on the semiconductor structure between the source and drain contacts, the semiconductor structure including a first region between the gate and the source or drain contact and a second region adjacent to the gate, the first region having a higher conductivity than the second region.

[0020] In some embodiments, the first region may have a lower sheet resistance than the second region.

[0021] In some embodiments, the semiconductor structure including the first region and the second region may have a conductivity that varies non-uniformly between the gate and the source or drain contact.

[0022] In some embodiments, the first region may have different surface properties than the second region.

[0023] In some embodiments, the first region may have modified interface states, and the second region may have no modified interface states or may have interface states that are modified in a different way.

[0024] In some embodiments, a surface passivation layer may be provided on the surface of the semiconductor structure between the gate and the source or drain contact, and the surface passivation layer may include an opening therein exposing the first region.

[0025] In some embodiments, the opening may be laterally separated from the gate by a second region. In some embodiments, the gate may include a side lobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, and the side lobe portion may extend over the second region. In some embodiments, the opening may be spaced laterally from the gate along the surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

[0026] In some embodiments, the surface passivation layer may be a first passivation layer. A second passivation layer may be disposed on the first passivation layer and extend into the opening to contact the first region. The interface between the first region and the second passivation layer may have a modified interface state that may differ from the interface between the second region and the first passivation layer.

[0027] According to some embodiments, a transistor device includes a semiconductor structure including a channel layer and a barrier layer defining a heterojunction therebetween, source and drain contacts on the semiconductor structure, a gate on a surface of the semiconductor structure between the source and drain contacts, and one or more passivation layers on a surface of the semiconductor structure between the gate and the source or drain contacts, wherein the conductivity of the semiconductor structure varies non-uniformly in a direction along an interface with the one or more passivation layers thereon.

[0028] In some embodiments, the semiconductor structure includes a first region between the gate and the source or drain contact and a second region adjacent to the gate, the first region having a higher conductivity than the second region, and in some embodiments, the first region may have a lower sheet resistance than the second region.

[0029] In some embodiments, the first region may have different surface properties than the second region, and in some embodiments, the first region may have modified interface states and the second region may have no modified interface states or may have interface states modified in a different way.

[0030] In some embodiments, the one or more passivation layers may include a first passivation layer on a second region of the semiconductor structure adjacent to the gate, the first passivation layer may include an opening therein exposing the first region, and the opening may be laterally separated from the gate by the second region.

[0031] In some embodiments, the one or more passivation layers may further include a second passivation layer on the first passivation layer and extending into the opening to contact the first region. The interface may include a first interface between the first region and the second passivation layer and a second interface between the second region and the first passivation layer. The first interface may have a modified interface state that is different from the second interface.

[0032] In some embodiments, a field plate may be provided on the second passivation layer between the gate and drain contacts, and the opening may be laterally spaced from at least a portion of the field plate.

[0033] According to some embodiments, a method of fabricating a transistor device includes forming a surface passivation layer on a semiconductor structure; forming source and drain contacts and a gate on the semiconductor structure, the gate being between the source and drain contacts; forming an opening in the surface passivation layer exposing a first region of the semiconductor structure between the gate and the source or drain contact; and treating the first region of the semiconductor structure exposed by the opening differently from a second region of the semiconductor structure adjacent the gate.

[0034] In some embodiments, the semiconductor structure may include a channel layer and a barrier layer defining a heterojunction therebetween, and the first region may have a higher conductivity than a second region of the semiconductor structure upon processing.

[0035] In some embodiments, the first region may have a lower sheet resistance than the second region depending on processing.

[0036] In some embodiments, the first region may have different surface properties than the second region depending on the treatment.

[0037] In some embodiments, the treatment may include performing a surface treatment on the first region exposed by the opening to modify its interface state, and the second region may be substantially unaffected by the surface treatment.

[0038] In some embodiments, the surface treatment may include ion bombardment, plasma nitridation, plasma oxidation, hydrogen plasma treatment, and / or annealing in a gas environment.

[0039] In some embodiments, the surface treatment may include wet etching with an acidic chemical solution, wet etching with a basic chemical solution, and / or treatment with a neutral chemical solution.

[0040] In some examples, the surface passivation layer may be a first passivation layer, and a second passivation layer may be formed on the first passivation layer and extending into the opening to contact the first region. The interface between the first region and the second passivation layer may have modified interface conditions that may differ from the interface between the second region and the first passivation layer.

[0041] In some embodiments, the modified interface state of the first region may be preserved by forming a second passivation layer.

[0042] In some embodiments, the surface passivation layer may be a first passivation layer, and a second passivation layer may be formed on the first passivation layer and extending into the opening to contact the first region. Forming the second passivation layer may modify the interface state of the first region.

[0043] In some embodiments, the interface conditions of the first region may be modified by forming an opening in the surface passivation layer.

[0044] In some embodiments, the opening may be laterally separated from the gate by a second region.

[0045] In some embodiments, the gate may include a side lobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, and the side lobe portion may extend over the second region.

[0046] In some embodiments, the openings may be spaced laterally from the gate along the surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

[0047] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon review of the following figures and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0048] [Figure 1A] 1 is a schematic cross-sectional view of a transistor device including higher conductivity source and / or drain access regions according to some embodiments of the present invention. [Figure 1B] 1 is a schematic cross-sectional view of a transistor device including higher conductivity source and / or drain access regions according to some embodiments of the present invention. [Figure 1C] 1 is a schematic cross-sectional view of a transistor device including higher conductivity source and / or drain access regions according to some embodiments of the present invention. [Figure 2] 1 is a schematic cross-sectional view of a transistor device including higher conductivity source and / or drain access regions according to some embodiments of the present invention. [Figure 3A] 1A-1C are schematic cross-sectional views of transistor devices including higher conductivity source and / or drain access regions with various configurations of field plates according to some embodiments of the present invention. [Figure 3B] 1A-1C are schematic cross-sectional views of transistor devices including higher conductivity source and / or drain access regions with various configurations of field plates according to some embodiments of the present invention. [Figure 3C] 1A-1C are schematic cross-sectional views of transistor devices including higher conductivity source and / or drain access regions with various configurations of field plates according to some embodiments of the present invention. [Figure 4A]1 is a graph illustrating non-uniform variation in sheet resistance between a gate and a source or drain region in a transistor device according to some embodiments of the present invention. [Figure 4B] 1 is a graph illustrating non-uniform variation in sheet resistance between a gate and a source or drain region in a transistor device according to some embodiments of the present invention. [Figure 5A] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 5B] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 5C] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 5D] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 5E] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 5F] 1A-1D are schematic cross-sectional views illustrating exemplary intermediate fabrication steps in methods of fabricating transistor structures according to some embodiments of the present invention. [Figure 6] 1 is a flowchart illustrating a method for fabricating a transistor structure according to some embodiments of the present invention. [Figure 7] 1 is a schematic plan view of a III-nitride based transistor die according to an embodiment of the present invention showing metallization on the surface of the semiconductor layer structure. [Figure 8A] 1 is a schematic cross-sectional view illustrating one of several exemplary packages including a transistor device according to an embodiment of the present invention to provide a packaged transistor amplifier. [Figure 8B]FIG. 10 is a schematic cross-sectional view illustrating another of several exemplary packages including a transistor device according to an embodiment of the present invention providing a packaged transistor amplifier. [Figure 8C] 1 is a schematic cross-sectional view illustrating yet another of several exemplary packages including a transistor device according to an embodiment of the present invention providing a packaged transistor amplifier. DETAILED DESCRIPTION OF THE INVENTION

[0049] Some embodiments of the present invention arise from the recognition that improvements in device performance (including, but not limited to, RF and DC performance) in transistor devices can be achieved by altering or modifying the interface states between a semiconductor structure and a passivation layer, which may increase the surface potential in the channel region or otherwise increase conductivity. For example, the density of interface states along the interface between a semiconductor structure and a passivation layer can reduce surface electron mobility and introduce carrier traps (also referred to herein as charge trapping), which in turn reduce the desired performance characteristics of the device. High electron mobility transistor (HEMT) devices with improved device performance (e.g., higher saturation power, lower charge trapping) can be achieved by modifying or altering the interface states between the passivation layer and the underlying semiconductor layer (e.g., AlGaN / SiN interface states) to increase the conductivity of the semiconductor layer in the channel region. However, the presence of such altered interface states near the gate can result in unacceptably high gate leakage current.

[0050] Embodiments of the present invention relate to transistor devices, such as HEMT devices, with improved performance. HEMT devices include high-conductivity, low-sheet-resistance regions in the active area or region to provide localized charge control in portions of the channel region between the gate and the source and / or drain regions, also referred to herein as source and / or drain access regions. More specifically, some embodiments of the present invention provide devices and fabrication methods that include localized surface modifications in the active area to provide non-uniform variations in conductivity in the conduction channel along the lateral direction between the gate and drain (or source). For example, one or more surface treatments may be applied to the surface of a barrier layer in the source and / or drain access regions of a HEMT device to modify the interface conditions between the barrier layer and the passivation layer in those regions. Thus, device performance can be improved while maintaining low leakage levels, in some cases without additional process steps to facilitate integration with conventional fabrication processes.

[0051] 1A, 1B, and 1C are schematic cross-sectional views of transistor devices according to some embodiments of the present invention, illustrated by way of example with reference to unit cell transistor structures 100a, 100b, and 100c (also referred to herein as transistor structures or transistor cells) of a transistor device, such as a HEMT. In particular, FIGS. 1A-1C illustrate examples of HEMT devices that include high conductivity regions or surfaces as described herein.

[0052] As shown in FIGS. 1A-1C, transistor structures 100a, 100b, and 100c are formed on a substrate 122, such as a silicon carbide substrate. Hundreds or thousands of unit cell transistor structures 100a, 100b, and 100c may be formed on the semiconductor substrate 122 and electrically connected (e.g., in parallel) to provide a HEMT device. The substrate 122 may be a semi-insulating silicon carbide substrate, which may be, for example, the 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include the 3C, 6H, and 15R polytypes. While silicon carbide may be used as the substrate material, embodiments of the present disclosure may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The substrate 122 may be a silicon carbide wafer, and the HEMT devices may be formed, at least in part, through wafer-level processing, and the wafer may then be diced or otherwise singulated to provide dies including a plurality of unit cell transistor structures 100 a, 100 b, 100 c.

[0053] The transistor structures 100a, 100b, 100c include a channel layer 124 on a substrate 122 and a barrier layer 126 on the channel layer 124 opposite the substrate 122. Source and drain electrodes (also referred to herein as source and drain contacts) 115 and 105 are formed on top of the barrier layer 126 and are laterally spaced apart from each other (e.g., along the X direction). The source and drain contacts 115 and 105 may form ohmic contacts to the barrier layer 126.

[0054] One or more insulating layers (e.g., one or more passivation layers) 150, 155 are formed on the barrier layer, and a gate contact (or simply "gate") 110 is formed on the surface of the barrier layer 126 between the source electrode 115 and the drain electrode 105. Depending on the configuration, one or more of the insulating layers 150, 155 may be formed before and / or after the formation of the gate 110.

[0055] The channel layer 124 may have a bandgap that is less than the bandgap of the barrier layer 126, and the channel layer 124 may have a greater electron affinity than the barrier layer 126. The channel layer 124 and the barrier layer 126 may together define a semiconductor structure 190. In the illustrated example, the semiconductor structure 190 may be a semiconductor layer structure including one or more layers formed by epitaxial growth, and thus includes one or more epitaxial layers 124, 126. Techniques for epitaxial growth of III-nitrides are described, for example, in U.S. Pat. No. 5,210,051, U.S. Pat. No. 5,393,993, and U.S. Pat. No. 5,523,589, the disclosures of which are incorporated herein by reference in their entireties.

[0056] In the exemplary HEMT device, the semiconductor layer structure 190 may be based on III-nitrides, although other material systems may be used. III-nitrides may refer to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, such as aluminum (Al), gallium (Ga), and / or indium (In), to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. Thus, AlGaN, AlInN, and AlInN, where 0≦x≦1, may be used. x Ga 1-xFormulas such as ZnO, ZnS, ZnN, ZnS ...

[0057] Although semiconductor structure 190 is shown with reference to one or more epitaxial layers 124, 126 for illustrative purposes, semiconductor structure 190 may include additional layers / structures / elements, such as isolation layer(s) 71, buffer layer(s) and / or nucleation layer(s) on or between substrate 122 and one or more epitaxial layers 124, and / or a cap layer on top surface 126A of epitaxial layer 126. For example, an AlN buffer layer may be formed on top surface 122A of substrate 122 to provide a suitable crystal structure transition between silicon carbide substrate 122 and the remainder of the layers of semiconductor structure 190. Additionally, strain-balancing transition layer(s) may also and / or alternatively be provided, as described, for example, in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer / nucleation / transition layer, as well as the channel layer 124 and / or barrier layer 126, may be deposited by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and / or hydride vapor phase epitaxy (HVPE).

[0058] The material of gate 110 may be selected based on the composition of semiconductor structure 190 and may, in some embodiments, be a Schottky contact. Some materials that can make a Schottky contact to a III-nitride based semiconductor material that may be used as gate 110 include, for example, nickel (Ni), platinum (Pt), nickel silicide (NiSi), and the like. x ), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W) and / or tungsten silicon nitride (WSiN).

[0059] The source contact 115 and / or the drain contact 105 may comprise a metal capable of forming an ohmic contact to a III-nitride based semiconductor material. Suitable metals include refractory metals such as Ti, W, titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), and NiSi. x , titanium silicide (TiSi), titanium nitride (TiN), WSiN, Pt, etc. Thus, source contact 115 and / or drain contact 105 may include an ohmic contact portion in direct contact with layer 126. In some embodiments, source contact 115 and / or drain contact 105 may be formed from multiple layers to form ohmic contacts that may be provided, for example, as described in U.S. Pat. Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference in their entireties and assigned to the assignee of the present invention.

[0060] In operation, a two-dimensional electron gas (2DEG) layer 40 may form at the junction between the channel layer 124 and the barrier layer 126 when the HEMT device is biased to its conductive or "on" state. The 2DEG layer 40 acts as a highly conductive channel that allows current to flow between the source and drain regions underlying the source and drain contacts 115 and 105, respectively. In particular, the channel layer 124 and the barrier layer 126 of the semiconductor structure 190 may be formed of materials having different bandgaps, thereby defining a heterojunction at the interface between the channel layer 124 and the barrier layer 126. In some embodiments, the substrate 122 comprises silicon carbide, the channel layer 124 comprises GaN, and the barrier layer 126 comprises AlGaN. The 2DEG conduction channel 40 may be induced at the heterointerface between the channel layer 124 and the barrier layer 126. The channel layer 124, the 2DEG conduction channel 40, and the barrier layer 126 may collectively form the active region of the HEMT device. Although this specification will be described primarily with reference to the fabrication and construction of HEMT devices, it should be noted that the elements and concepts of the embodiments described herein are applicable to many different types of transistor structures.

[0061] As described above, improved performance can be achieved in some embodiments of the present invention by selectively modifying regions of the semiconductor structure 190 adjacent to the source and / or drain regions to provide localized charge control of the channel in those regions without affecting the regions adjacent to the gate 110. For example, a combination of surface treatment(s) and deposition process(es) may be used to optimize or modify the interface state near the gate in a manner different from modifying the interface state adjacent to the source and / or drain regions. As shown in FIGS. 1A-1C , an initial or first surface passivation layer 150 is formed on the surface 126A of the semiconductor structure 190. The surface passivation layer 150 may be formed by a passivation process that results in a low surface potential of the barrier layer 126 so as to reduce leakage current in the region 126G adjacent to the gate 110. The surface passivation layer 150 may be a silicon nitride or other electrically insulating material layer formed using a relatively low surface energy process that may not substantially increase the surface potential of the surface 126A. Such deposition processes may include PVD, PECVD, LPCVD, SACVD, pyrolytic deposition, PEALD, ALD, and / or any combination thereof, which may form the surface passivation layer 150 as a single layer or a multi-layer stack. Deposition of the surface passivation layer 150 may modify the surface condition of the surface 126A. The thickness of the surface passivation layer 150 can affect the gate-to-source capacitance and the gate-to-drain capacitance, which can have a strong impact on the switching speed of the device.

[0062] In some embodiments, surface 126A may be treated by one or more surface treatment steps prior to deposition of surface passivation layer 150. Such pre-passivation surface treatment steps may include in-situ and ex-situ steps. Example in-situ surface treatment steps may include, but are not limited to, plasma nitridation, ion bombardment, plasma oxidation, hydrogen (H) plasma treatment (which may create nitrogen vacancies / depletions near surface 126A), annealing in a chemically active gas environment (including, but not limited to, forming gases (e.g., mixtures of H and N with varying concentrations), nitric oxide, nitrogen dioxide, and ammonia), and annealing in a chemically inert gas environment. Example ex-situ surface treatment steps include, but are not limited to, wet etching in an acidic chemical bath, wet etching in a basic chemical bath, and treatment in a neutral chemical solution (e.g., buffered oxide etchant (BOE)).

[0063] The surface passivation layer 150 includes one or more openings 151, 151′ (e.g., trenches) extending therethrough and exposing the passivated surface 126A of the semiconductor structure 190 in one or more regions. When a region is “exposed” by a layer or opening, it is understood that the region remains exposed by the layer or opening regardless of whether additional layers or elements are subsequently formed on or covering the region. That is, “exposing” may define the relationship between a layer or opening and a region, regardless of subsequent processes on the region. For example, the surface passivation layer 150 may be selectively etched to define the openings 151, 151′. The gate 110 may be formed in the surface 126A of the semiconductor structure 190 exposed by the opening 151, also referred to herein as a gate opening. The length L of the gate 110 at the opening 151 G defines the interface between the gate 110 and the barrier layer 126. G affects the transconductance and gate parasitics and can have a strong impact on the switching and efficiency of the device.

[0064] In some embodiments, the gate 110 may include one or more extensions that extend laterally onto portions of the surface passivation layer 150, such as opposing side lobe portions 110-1, 110-2 that define a gamma (Γ) shape (also referred to as a "Γ-gate") or a T-shape (also referred to as a "T-gate"). The gate 110 and the side lobe portion(s) 110-1, 110-2 may be of a number of different lengths (Γ G1 and Γ G2 ), which may affect the gate-source capacitance or gate-drain capacitance of the device, and therefore the switching speed and / or gain of the device. The side lobe portion(s) 110-1, 110-2 may, in some embodiments, extend asymmetrically or substantially symmetrically over the surface passivation layer 150 on either side of the gate 110. For example, on the drain side, the side lobe portion 110-2 of the gate 110 may extend asymmetrically or substantially symmetrically over the surface passivation layer 150 on either side of the gate 110. G2 In some embodiments, Γ may extend toward the drain contact 105 by only about 0.05 μm to 0.5 μm, for example. G2 On the source side, the side lobe portion 110-1 of the gate 110 is spaced apart by a distance Γ G1 In some embodiments, Γ may extend only about 0.05 μm to 0.5 μm toward the source contact 115. G1 may be approximately 0.1 μm.

[0065] The opening(s) 151′ in the surface passivation layer 150 may be formed during the same etching step used to form the gate opening 151, or in a different etching step before or after forming the gate opening 151. The opening(s) 151′ may have the same or a different profile as the gate opening 151. The opening(s) 151′ are laterally spaced from the gate opening 151 adjacent to the source contact 115 and / or drain contact 105. In some embodiments, the opening(s) 151′ are laterally spaced from an area where a field plate will be formed between the gate 110 and the source contact 115 or the drain contact 105. The opening(s) 151′ may be laterally spaced or separated from the gate opening 151 (e.g., as measured from the top of the opening opposite surface 126A) by a distance on the order of tens of nanometers (nm), e.g., by about 10 nm (0.01 μm) or more, about 100 nm (0.1 μm) or more, or about 150 nm (0.15 μm) or more, as limited by the gate-drain or gate-source spacing. In some embodiments, the minimum lateral separation or separation between the opening(s) 151′ and the gate opening 151 is less than the length Γ of the gate sidelobe portion(s) 110-1, 110-2. G1 , Γ G2 , which may define an overhanging portion that protects underlying portions of the surface passivation layer 150 from the etching operation used to form the opening(s) 151′.

[0066] Region(s) 126S of semiconductor structure 190 are exposed by opening(s) 151′ for processing, e.g., using surface treatment steps and / or deposition operations as described herein. In particular, region(s) 126S exposed by opening(s) 151′ may be modified as described herein to obtain a non-uniform variation in conductivity, sheet resistance, charge trap concentration, and / or surface potential along a lateral direction (e.g., the X direction) between gate contact 110 and drain contact 105 (or source contact 115). For example, one or more surface treatment steps may be performed to change the surface properties of region(s) 126S of semiconductor structure 190 exposed by opening(s) 151′ to be different from the surface properties of region 126G adjacent to gate 110. Such surface treatment processes may include in-situ processes (e.g., before deposition of a subsequent layer such as passivation layer 155) and ex-situ processes (e.g., before loading semiconductor structure 190 into a passivation tool). Example in-situ surface treatment processes include, but are not limited to, plasma nitridation, ion bombardment, plasma oxidation, hydrogen (H) plasma treatment (which may create nitrogen vacancies along the exposed region 126S / interface), annealing in a chemically active gas environment (including, but not limited to, forming gas, nitric oxide, nitrogen dioxide, and ammonia), and annealing in a chemically inert gas environment. Example ex-situ surface treatment processes include, but are not limited to, wet etching in an acidic chemical bath, wet etching in a basic chemical bath, and treatment with a neutral chemical solution.

[0067] The surface treatment step(s) are configured to modify the interface conditions in the region(s) 126S exposed by the opening(s) 151′. For example, the surface treatment step(s) may locally alter the interface conditions in the region(s) 126S exposed by the opening(s) 151′ to reduce sheet resistance or otherwise form higher conductivity regions 126S of the conduction channel 40 below the modified surface between the gate 110 and the source contact 115 or the drain contact 105 (compared to the region 126G adjacent to the gate 110). In some embodiments, the etching process used to form the opening(s) 151′ may remove certain interface conditions that were modified prior to deposition of the surface passivation layer 150 (e.g., by the pre-passivation surface treatment process described above), or may otherwise modify the interface conditions of the regions 126S exposed by the opening(s) 151′, and the interface conditions of the regions 126S may be further modified by one or more surface treatment processes performed after forming the opening(s) 151′.

[0068] 1A illustrates the formation of a high conductivity region 126S at the surface 126A between the gate 110 and the drain electrode 105, FIG. 1B illustrates the formation of a high conductivity region 126S at the surface 126A between the gate 110 and the source electrode 115, and FIG. 1C illustrates the formation of a high conductivity region 126S at the surface 126A between the gate 110 and the drain electrode 105 and between the gate 110 and the source electrode 115. In some embodiments, the region(s) 126S may be referred to herein as a surface treatment region or a modified interface region.

[0069] When opening(s) 151′ are laterally spaced from gate opening 151, surface-treated region(s) 126S are laterally separated or offset from gate 110. That is, surface-treated region 126S is separated from gate 110 by region 126G, which may be free of interface modifications due to surface treatment step(s) or may otherwise have different surface properties than surface-treated region 126S. For example, as described above, region 126G may have a differently modified interface state (compared to region 126S) due to prior passivation surface treatment step(s) and / or etching step(s) that define different surface properties. The modified surface / interface region 126S may improve the conductivity and / or sheet resistance of the active region of the transistor device, thereby improving device performance. However, the same properties that may improve device performance when present in the source and / or drain access regions may also increase leakage current and therefore reduce the breakdown and reliability performance of the device if placed too close to the gate contact 110. By spacing the modified surface / interface region 126S an offset distance from the gate 110, embodiments of the present invention provide improved conductivity and performance in the source and / or drain access regions 126S without substantially affecting the region 126G adjacent to the gate 110, thus avoiding increased leakage current.

[0070] A second insulating or interlayer passivation layer (e.g., inter field plate passivation (IFPP)) 155 is formed on the surface passivation layer 150 and on the region 126S of the semiconductor structure 190 exposed by the opening(s) 151′ to define an interface between the region 126S and the interlayer passivation layer 155. The properties of the interface between the first insulating layer 150 and the barrier layer 126 adjacent the gate 110 may be different from the modified surface / interface region 126S in the drain access region and / or the source access region. For example, in some embodiments, the interface state, conductivity, sheet resistance, charge trap concentration, and / or surface potential at the interface between the surface passivation layer 150 and the barrier layer 126 (corresponding to region 126G) may be different from those at the interface between the interlayer passivation layer 155 and the barrier layer 126 (corresponding to region 126S).

[0071] Non-uniform variations in interface states, conductivity, sheet resistance, charge trap concentration, and / or surface potential may therefore occur along the interface(s) between the surface 126A, 126S and the passivation layer 150, 155 in the lateral direction between the gate contact 110 and the drain contact 105 (or the source contact 115). In some embodiments, the interlayer passivation layer 155 may be formed adjacent to or immediately after the surface treatment step(s) to preserve the surface modification of the region 126S achieved by the surface treatment. The interlayer passivation layer 155 may be formed using a relatively high surface energy process, such as PVD, PECVD, LPCVD, SACVD, pyrolysis deposition, PEALD, ALD, and / or any combination thereof, and the interlayer passivation layer 155 may be formed as a single layer or a multi-layer stack.

[0072] In some embodiments, the modified interface state at the interface between the interlayer passivation layer 155 and the barrier layer 126 (corresponding to region 126S) may be defined by the deposition of the interlayer passivation layer 155 itself, independent of or in addition to any surface treatment step(s). That is, the non-uniform variation in interface state, conductivity, sheet resistance, charge trap concentration, and / or surface potential as described herein may be achieved by any combination of surface treatment(s) and deposition step(s), including, for example, prior passivating surface treatment step(s), deposition and / or etching of the surface passivation layer 150, subsequent surface treatment step(s), and / or deposition of the interlayer passivation layer 155. Thus, the region(s) of higher conductivity 126S extend along and / or below the respective interface between the portion of the surface 126A of the semiconductor structure 190 exposed by the opening(s) 151′ and the interlayer passivation layer 155.

[0073] The surface passivation layer 150 and the interlayer passivation layer 155 may each include a single layer or multiple layers. For example, the surface passivation layer 150 and the interlayer passivation layer 155 may include one or more layers of a multilayer insulator structure, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or an oxide-nitride-oxide layer. In particular embodiments, the surface passivation layer 150 and the interlayer passivation layer 155 may each include silicon nitride. Additional passivation layers (e.g., the final passivation layer 560 shown in FIG. 5F ) and / or metal contacts (e.g., the metal contact 565 shown in FIG. 5F ) may be formed for electrical connections, such as for “off-chip” input and / or output connections to one or more external devices and / or for ground connections. The metal contacts may be directly or indirectly connected to corresponding terminals (e.g., gate 110, drain 105, and source 115 terminals) of one or more transistor structures 100a, 100b, 100c, and thus may define input (e.g., gate), output (e.g., drain), and / or ground (e.g., source) contact pads or terminals of the HEMT device, as discussed below with reference to FIG. 7.

[0074] Although illustrated primarily herein with reference to a planar HEMT configuration having the gate 110 and source and drain electrodes 115, 105 on the surface 126A of the barrier layer 126, it will be understood that embodiments of the present invention may be used in other HEMT configurations, such as recessed gate HEMTs (where the source and drain electrodes 115, 105 are elevated relative to the gate 110 on the surface 126A) and recessed source / drain HEMTs (where the source and drain electrodes 115, 105 extend beyond the surface 126A towards the channel layer 124).

[0075] FIG. 2 is a schematic cross-sectional view of a transistor structure 200 according to some embodiments of the present invention. The transistor structure 200 includes a substrate 122, a semiconductor structure 190, a gate 110, a source contact 115, and a drain contact 105 similar to the embodiments of FIGS. 1A-1C. The transistor structure 200 further includes a surface passivation layer 250 having a wider opening 251 and a larger surface treatment area 126S compared to those of the transistor structure 100a. While the example is illustrated with reference to the opening 251 between the gate 110 and the drain contact 105, it is understood that an opening of similar or different dimensions in the surface passivation layer 250 may also be provided between the gate 110 and the source contact 115, additionally (as in FIG. 1C) or alternatively (as in FIG. 1B).

[0076] 2, the opening(s) 251 in the surface passivation layer 250 may have a width dimension W along the lateral (e.g., X) direction between the gate 110 and the drain contact 105 (or source contact 115). The opening(s) 251 may correspond to the gate-drain spacing L in FIG. 1A. GD or gate-source spacing L GSThe lateral distance L between the gate 110 and the drain or source contact 115 or 105 at the bottom of the gate opening 151 may be exposed up to most (but less than the entire) of the surface 126A between the gate 110 and the drain or source contact 115 or 105, as shown by GD The lateral distance L between the gate contact 110 and the source contact 115 at the bottom of the gate opening 151 may be between 1.75 μm and 4 μm, for example, about 1.98 μm. GS may be between 0.5 μm and 1 μm, for example about 0.6 μm.

[0077] The opening(s) 251 may, in some embodiments, have a length Γ of the gate extension(s) 110-1, 110-2 (e.g., as measured along the surface 126A at the bottom of the opening(s)). G1 , Γ G2 In some embodiments, the opening(s) 251 may be adjacent to or extend laterally to the drain contact 105 (and / or source contact 105). For example, a gate-drain spacing L of about 1.98 μm on the drain side may be used. GD and a gate sidelobe length Γ of approximately 0.05 μm G2 In a device having a width W of the opening 251, the width W is at most about 1.975 μm (L GD Negative Γ G2 Similarly, the gate-source spacing L of about 0.6 μm on the source side may be GS and a gate sidelobe length Γ of approximately 0.05 μm G1 In a device having a width W of the opening 251, the width W is at most about 0.55 μm (L GS Negative Γ G1 ) or less. More generally, the width W of the opening 251 may be less than the gate-drain spacing L GD (or gate-source distance L GS ) and the desired lateral spacing from the surface exposed by gate opening 151 to region 126S exposed by opening 251.

[0078] 1A-1C, whereby the surface-treated region(s) 126S have different surface properties than the region 126G of the semiconductor structure 190 adjacent to the gate 110. In particular, the region(s) 126S may include modified interface states compared to the region 126G of the semiconductor structure 190 adjacent to the gate 110. The region(s) 126S may be closer to the gate-drain spacing L than the region 126G of the semiconductor structure 190 adjacent to the gate 110. GD (and / or gate-source spacing L GS ) as described above. As described above, the region(s) 126S may be isolated from the gate 110 (e.g., Γ) by the region 126G to avoid increasing leakage current. G2 or Γ G1 may be separated or offset laterally (by as little as

[0079] 2 illustrates, by way of example, such a high conductivity region 126S between the gate 110 and the drain contact 105 at the surface 126A therebetween, although it will be understood that a similar high conductivity region may (additionally or alternatively) be provided between the gate 110 and the source electrode 115. That is, although shown on the drain side of the transistor structure 200 in FIG. 2, embodiments of the present invention may additionally or alternatively include a wider opening 251 and surface treatment region 126S on the source side of the transistor structure 200.

[0080] As in Figures 1A to 1C, a second or interlayer passivation layer (e.g., IFPP) 155 is formed on the surface passivation layer 250 and within the opening(s) 251, such that the surface treatment region(s) 126S extend along one or more interfaces between the portion(s) of the surface 126A exposed by the opening(s) 251 and the interlayer passivation layer 155.

[0081] 3A, 3B, and 3C are schematic cross-sectional views of transistor structures 300a, 300b, and 300c including various configurations of field plates 328a, 328b, and 328c (collectively 328) according to some embodiments of the present invention. Field plates 328a, 328b, and 328c may be used to enhance HEMT performance, for example, at microwave frequencies. For example, field plates 328a, 328b, and 328c may be configured to reduce the peak electric field in transistor structures 300a, 300b, and 300c, which can result in increased breakdown voltage and reduced charge trapping. Reducing the electric field can also provide other benefits, such as reduced leakage current and improved reliability. Field plates and techniques for forming field plates are discussed, for example, in U.S. Patent No. 8,120,064, the disclosure of which is incorporated herein by reference in its entirety.

[0082] As shown in Figures 3A-3C, the field plate 328 is separated from the gate 110 by the interlayer passivation layer 155 and from the barrier layer 126 by the interlayer passivation layer 155 and the surface passivation layer 150. The field plate 328 may extend laterally toward the drain contact 105 on the drain side of the structures 300a, 300b, and 300c and be electrically connected to the gate 110 (by a connection outside the active area of ​​the transistor structures 300a, 300b, and 300c). This configuration reduces the electric field on the gate-drain side of the transistor structure, thereby resulting in an increased breakdown voltage and reduced high-field trapping effects. The extension distance of the field plate 328 beyond the gate 110 can affect the gate-to-source capacitance and breakdown voltage of the device, which can have a significant impact on the voltage rating and switching speed of the device.

[0083] In some embodiments, the field plate 328 may be electrically connected to the source contact 115. Connecting the field plate 328 to the source contact 115 reduces the gate-to-drain capacitance (C gd ), which can increase the gain of the device.gd In addition to reducing the drain bias voltage, the presence of the field plate 328 can improve the linearity of the device and / or reduce the drain bias dependence of the capacitance.

[0084] Field plates 328 may be implemented on interlayer passivation layer 155 in various configurations according to embodiments of the invention. In Figure 3A, field plate 328a extends conformally along interlayer passivation layer 155 over a portion of gate 110, thereby partially overlapping gate 110 in the vertical (e.g., Z) direction. In Figures 3B and 3C, field plates 328b, 328c do not extend over gate 110 and are laterally spaced from gate 110 by interlayer passivation layer 155, so do not overlap gate 110 in the vertical direction.

[0085] 3A and 3B, field plates 328a, 328b have a stepped profile including two or more portions: a first step portion adjacent gate 110 and a second step portion adjacent drain contact 105. The stepped field plates 328a, 328b may be defined by a continuous layer or by a stack of discontinuous layers. Each step portion of field plates 328a, 328b is positioned at a different distance or spacing from surface 126A (and thus the underlying conduction channel 40). Field plates 328a, 328b including first and second step portions that are closer and farther from conduction channel 40 have a C gd This can allow for reduced trapping effects and reduced peak electric fields adjacent to the drain contact 105.

[0086] In FIG. 3A , field plate 328a is completely outside of, or otherwise does not overlap, opening 151′ in surface passivation layer 150 that exposes surface treatment region 126S. That is, surface passivation layer 150 and opening 151′ in region 126S may be between field plate 328a and drain contact 105 and may be laterally spaced apart from (and therefore not overlap with) field plate 328a. In FIG. 3B , field plate 328b extends along interlayer passivation layer 155 so as to partially extend into or overlap opening 151′ in surface passivation layer 150. Thus, field plate 328b at least partially overlaps opening 151′ in surface passivation layer 150 and surface treatment region 126S.

[0087] In FIG. 3C , field plate 328c extends along interlayer passivation layer 155 so as to conformally extend along the portion of layer 155 at opening 151′ in surface passivation layer 150. Thus, field plate 328c fully overlaps surface passivation layer 150 and opening 151′ in surface treatment region 126S. As shown in the example of FIG. 3C , field plate 328c has a T-shaped configuration including a central concave portion above opening 151′ and one or more wing portions extending laterally from the concave portion toward source contact 115 and toward drain contact 105. Adjusting the distance between the central portion and / or wings of field plate 328c and barrier layer 126, as well as the width of field plate 328c and / or the width of its lateral extensions, provides several degrees of freedom for modulating the gate-to-source and gate-to-drain capacitance of the device.

[0088] 4A and 4B show the lateral sheet resistance R between the gate and the drain (or source) resulting from modified interface states according to some embodiments of the present invention. sh 4A and 4B are graphs showing the non-uniform variation of the sheet resistance R. shis relatively uniform in region 126G of semiconductor structure 190 adjacent gate 110, but is locally reduced in surface-treated region 126S (shown as being reduced by about 10% in FIG. 4A and about 20% in FIG. 4B , although examples of the invention are not limited thereto). As discussed above, a surface treatment process may be used to locally modify surface properties, such as interface states, in region 126S corresponding to openings 151′, 251 in surface passivation layer 150. Without being bound by theory, the modified interface states in region 126S can result in an increased surface potential relative to region 126G adjacent gate 110. More generally, the sheet resistance R may be reduced as a result of the localized interface state modification in surface-treated region 126S. sh and / or charge trap concentration is reduced (and thus conductivity is increased), while the region 126G more directly or immediately adjacent to the gate 110 is substantially unaffected by the surface treatment or otherwise has different properties, reducing leakage adjacent to the gate 110.

[0089] 4A and 4B, the modified interface states of region 126S result in non-uniform variations in sheet resistance, charge trap concentration, conductivity, and / or surface potential along the interface(s) between surface 126A of semiconductor structure 190 and passivation layer(s) 150, 155, which may be abrupt or gradual in some embodiments. GD The gate-source spacing L is discussed with reference to non-uniform variations over GS It will be appreciated that similar or proportional variations across the entire surface may additionally or alternatively occur. Figure 4A illustrates a more localized variation, for example, in an embodiment having openings 151' in the surface passivation layer 150 shown in Figures 1A-1C. Figure 4B illustrates a reduced sheet resistance R in an embodiment having wider opening(s) 251 in the surface passivation layer 150 between the gate 110 and the drain contact 105 (and / or source contact 105), for example, as shown in Figure 2. sh / The high conductivity region 126S is the gate-drain spacing LGD (and / or gate-source spacing L GS ), but more generally, non-uniform variations in sheet resistance, charge trap concentration, conductivity, and / or surface potential may extend to a large extent beyond the lateral separation or offset (e.g., Γ G2 or Γ G1 The non-uniform variation in sheet resistance, charge trap concentration, conductivity, and / or surface potential may occur anywhere between the gate and the source or drain contact, as long as the non-uniform variation in sheet resistance, charge trap concentration, conductivity, and / or surface potential is maintained. In some embodiments, the non-uniform variation in sheet resistance, charge trap concentration, conductivity, and / or surface potential may be achieved by performing one or more surface treatment steps prior to forming the surface passivation layer 150 and using a self-aligned gate fabrication process to alter the surface properties, for example, as described in commonly assigned U.S. patent application Ser. No. 5308,3153, the disclosure of which is incorporated herein by reference.

[0090] Figures 5A, 5B, 5C, 5D, 5E, and 5F are schematic cross-sectional views illustrating example intermediate fabrication steps in a method of fabricating a transistor structure according to some embodiments of the present invention. Figure 6 is a flowchart illustrating a method of fabricating a transistor structure according to some embodiments of the present invention.

[0091] 5A and 6, a surface passivation layer 150 is formed on a semiconductor structure 190 on a substrate 122 (block 602). As described above, the semiconductor structure 190 may define one of a plurality of unit cell structures (e.g., 100, 200, 300) on the substrate 122. The substrate 122 may include silicon carbide, sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), or other materials capable of supporting the growth of Group III nitride materials. As an example, silicon carbide may have a better crystal lattice match to Group III elements than sapphire, allowing high-quality Group III nitride films to be formed thereon. Silicon carbide also has very high thermal conductivity, so that the total output power of III-nitride devices on silicon carbide may not be limited by the heat dissipation of the substrate (as is the case for some devices formed on sapphire). However, embodiments of the present invention are not limited to silicon carbide, and any suitable material may be utilized for the substrate 122.

[0092] In the illustrated embodiment, semiconductor structure 190 includes a channel layer 124 and a barrier layer 126. The channel layer 124 and / or the barrier layer(s) may be deposited on substrate 122 using buffer layers, transition layers, and / or nucleation layers, as described above. The channel layer 124 and the barrier layer 126 may be formed of materials having different bandgaps (e.g., GaN and AlGaN, respectively) to define a heterojunction of a HEMT device, although embodiments of the invention are not limited thereto. In some embodiments, the channel layer 124 and the barrier layer 126 may have different lattice constants, e.g., a smaller lattice constant for the relatively thin barrier layer 126, such that the barrier layer 126 "stretches" at the interface between the two. Thus, a pseudomorphic HEMT (pHEMT) device may be provided.

[0093] The surface passivation layer 150 may be formed by a passivation process that results in a low surface potential on the surface 126A of the semiconductor structure 190. The surface passivation layer 150 may be formed of silicon nitride (Si x N y The surface passivation layer 150 may be a dielectric material such as silicon dioxide (SiO), aluminum nitride (AlN), silicon dioxide (SiO), and / or other suitable protective materials. Other materials may also be utilized for the surface passivation layer 150. For example, the surface passivation layer 150 may include magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. Furthermore, the surface passivation layer 150 may be a single layer or may include multiple layers of uniform and / or non-uniform composition. For example, the surface passivation layer 150 may be a silicon nitride or other electrically insulating material layer that is blanket formed on the surface 126A of the semiconductor structure 190 using a relatively low surface energy process, such as PVD, PECVD, LPCVD, SACVD, pyrolytic deposition, PEALD, ALD, and / or any combination thereof, to modify the surface state of the surface 126A without increasing the surface potential of the surface 126A. Surface passivation layer 150 may be sufficiently thick to protect underlying surface 126A during subsequent processing, for example, during annealing of ohmic contacts. As noted above, forming surface passivation layer 150 may, in some embodiments, be preceded by one or more pre-passivation surface treatment steps, which can modify the interface conditions of surface 126A prior to deposition of surface passivation layer 150.

[0094] As shown in FIG. 5B , the surface passivation layer 150 is patterned to form source contacts 115 and drain contacts 105. For example, the surface passivation layer 150 may be patterned to form openings exposing the surface 126A of the barrier layer 126 for placement of the source contacts 115 and drain contacts 105. The openings may be etched using a patterned mask and a low-damage etchant relative to the barrier layer 126. Ohmic metal may be formed on the exposed portions of the barrier layer 126. However, it will be appreciated that in other embodiments, the barrier layer 126 may also be recessed through the openings, and the source contacts 115 and drain contacts 105 may extend through the barrier layer 126. Suitable metals include Ti, W, TiW, Si, TiWN, WSi, Re, Nb, Ni, Au, Al, Ta, Mo, and NiSi. x , TiSi, TiN, WSiN, Pt, etc. The ohmic metal may be annealed to provide source contact 115 and drain contact 105.

[0095] The surface passivation layer 150 may also be patterned to provide the gate contact 110, for example, before, after, or simultaneously with forming the source contact 115 and the drain contact 105. The surface passivation layer 150 may be etched to form an opening or trench 151 exposing the surface 126A of the barrier layer 126 for placement of the gate contact 110. The gate contact 110 may be formed in the etched opening 151 or may extend through the opening 151 to contact the exposed portion of the barrier layer 126. Suitable gate materials include Ni, Pt, NiSi x, Au, Ti, Cu, Pd, Cr, TaN, W, and / or WSiN. The trench 151 (and thus the gate 110 therein) may extend in the Y direction along the surface 126A. Also, portions or side lobes of the gate 110 may extend laterally (e.g., in the X direction) on the surface passivation layer 150. While shown in FIG. 5C as being on the surface 126A of the barrier layer 126, it will be understood that in some embodiments, the source contact 115, the gate contact 110, and / or the drain contact 105 may be formed within a recess in the surface 126A of the barrier layer 126.

[0096] 5C and 6, the surface passivation layer 150 is etched to define one or more openings 151′ that expose the region 126S of the semiconductor structure 190 (block 604). For example, the opening(s) 151′ may define trenches extending in the Y direction along the surface 126A. The opening(s) 151′ are formed between the gate 110 and the drain contact 105 (and / or between the gate 110 and the source contact 115, shown in phantom in FIG. 5C). The opening(s) 151′ are laterally spaced from the gate opening 151 adjacent the drain contact 105 (and / or the source contact 115).

[0097] In some embodiments, the opening(s) 151′ in the surface passivation layer 150 may be formed during the same etching step used to form the gate opening 151, or in a different etching step before or after forming the gate opening 151 and / or the openings for the source contact 115 and drain contact 105. For example, in a GaN-based semiconductor structure 190 including a GaN channel layer 124 and an AlGaN barrier layer 126, during the etching used to form the gate opening 151, one or more additional openings 151′ are etched into the surface passivation layer 150 to expose one or more regions 126S of the AlGaN barrier layer 126 between where the gate 110 will be formed and where the drain contact 105 (and / or source contact 115) will be formed. In embodiments in which a pre-passivation surface treatment step is performed, the etching step used to define the opening(s) 151′ can remove or modify the interface condition of the regions 126S exposed by the opening(s) 151′.

[0098] 5D and 6, one or more surface treatment steps ST are performed to modify the surface properties of the region(s) 126S of the semiconductor structure 190 exposed by the opening(s) 151′ (block 608). The surface treatment step(s) ST are configured to modify the interface state of the region(s) 126S exposed by the opening(s) 151′. The surface treatment step(s) may include, but are not limited to, in-situ processes (e.g., plasma nitridation, ion bombardment, plasma oxidation, H plasma treatment, annealing in a chemically active gas environment (including, but not limited to, forming gas, nitric oxide, nitrogen dioxide, and ammonia), annealing in a chemically inert gas environment), and ex-situ processes (e.g., wet etching with an acidic chemical solution, wet etching with a basic chemical solution, treatment with a neutral chemical solution).

[0099] For example, in a GaN-based semiconductor structure 190 including exposed regions 126S of an AlGaN barrier layer 126, ion bombardment may be used to modify the interface states (thus increasing the AlGaN surface potential) in the regions 126S exposed by the openings 151′, thereby forming high-conductivity, low-sheet-resistivity regions 126S in portions of the conduction channel 40, enabling higher saturation power and lower charge trapping. Regions more directly or immediately adjacent to the gate 110 are not affected by the surface treatment(s) ST, and therefore retain the lower surface potential resulting from the formation of the first / surface passivation layer 150 (at block 602), reducing leakage adjacent to the gate 110. That is, the surface treatment step(s) ST can locally modify the interface state of the region(s) 126S exposed by the opening(s) 151′, thereby forming a surface treatment region 126S between the gate 110 and the source contact 115 or drain contact 105, and achieving higher conductivity in the underlying portion of the conduction channel 40.

[0100] 5E-5F and 6 illustrate that one or more additional passivation layers 155, 560 (e.g., interlayer passivation layer 155 and final passivation layer 560) are formed on semiconductor structure 190 (block 610). The additional passivation layer(s) 155, 560 may be insulating layer(s) or dielectric layer(s) and, in some embodiments, have a different dielectric constant than surface passivation layer 150. As shown in FIG. 5E, interlayer passivation layer 155 may be an IFPP formed on first / surface passivation layer 150 and on regions 126S of semiconductor structure 190 exposed by opening(s) 151′, with surface treatment region(s) 126S extending along interface(s) between surface 126A and interlayer passivation layer 155. The interlayer passivation layer 155 is formed (block 610) near or immediately after the surface treatment step(s) ST (block 608) to maintain or preserve the surface properties in the region 126S achieved by the surface treatment P. As described above, the interlayer passivation layer 155 may be formed using a relatively high surface energy process, such as PVD, PECVD, LPCVD, SACVD, pyrolytic deposition, PEALD, ALD, and / or any combination thereof, thereby allowing the interlayer passivation layer 155 to be formed as a single layer or a multilayer stack. As described above, the modified interface state of the region 126S may be defined by the deposition of the interlayer passivation layer 155, independently of or in addition to any surface treatment step(s). For example, the operation shown in FIG. 5D may be omitted in some instances, and the modified interface state of the region 126S may be defined by the deposition of the interlayer passivation layer 155 itself.

[0101] As shown in FIG. 5F , respective metal contacts 565 may be formed and extend through openings in the interlayer passivation layer 155 to contact one or more of the contacts 105, 110, and 115. For example, the interlayer passivation layer 155 may be patterned to form openings that expose the source contacts 115 and / or the drain contacts 105, and a conductive metal may be formed on the exposed portions of the source contacts 115 and / or the drain contacts 105 to form the metal contacts 565. The metal contacts 365 may comprise a metal or other highly conductive material, such as copper, cobalt, gold, and / or composite metals. In the example of FIG. 5F , the metal contacts 565 are provided on the drain contact 505 and the source contact 515, although it is understood that in some embodiments, the metal contacts 565 may be provided on all three terminals (i.e., the source, gate, and drain). In some embodiments, a field plate 328 may be formed on the IFPP 155, for example, according to the configuration shown in Figures 3A-3C.

[0102] 5F , an electrically insulating and / or passivating layer 560 (of similar or different composition than insulating layers 150 and / or 155) may be formed over metal contacts 565 as a final passivation layer and patterned to define openings exposing metal contacts 565 for electrical connection, e.g., input and / or output connection and / or ground connection to one or more external devices. Metal contacts 565 may therefore define input (e.g., gate), output (e.g., drain), and / or ground (e.g., source) contact pads or terminals that may be directly or indirectly connected to corresponding terminals of any of transistor structures 100 a, 100 b, 100 c, 200, 300 a, 300 b, 300 c described herein (e.g., gate 110, drain 105, and source 115 terminals of a HEMT device).

[0103] In contrast to some conventional devices (e.g., GaN / AlGaN HEMTs) in which only the gate opening is etched into the surface passivation layer and the interface state of the channel region may be set by the passivation process used to form the first or second surface passivation layer, embodiments of the present invention may provide a higher conductivity region in a portion (or most) of the semiconductor structure between the gate and the source and / or drain contacts, for example, by forming one or more additional openings in the surface passivation layer. This allows for localized modification of the interface state of the region of the semiconductor structure exposed by the opening to create a higher conductivity region without affecting the area or region directly adjacent to the gate. More generally, embodiments of the present invention may use any combination of surface treatment process(es) and / or passivation layer deposition steps, including but not limited to those described above by way of example, to differentially modify the interface state of a first region of the semiconductor structure adjacent the source or drain compared to a second region adjacent the gate.

[0104] Embodiments of the present invention may be formed as discrete devices or as part of a monolithic microwave integrated circuit (MMIC). MMIC refers to an integrated circuit operating on radio and / or microwave frequency signals in which all of the circuitry for a specific function is integrated into a single semiconductor chip. An example MMIC device is a transistor amplifier, including associated matching circuits, feed networks, etc., all mounted on a common substrate. MMIC transistor amplifiers typically include multiple unit cell HEMT transistors connected in parallel. Embodiments of the present invention provide a transistor design capable of producing higher power density, enabling smaller and more powerful MMIC chips.

[0105] Embodiments of the present invention may provide improved performance in RF devices. However, embodiments of the present invention are not limited to RF applications and may be used in any DC device, including, but not limited to, Ka-band, MMIC, and power switching devices. For example, embodiments of the present invention may be used in applications having operating frequencies ranging from approximately below 4 GHz up to Ka-band designs (e.g., 26 to 40 GHz).

[0106] In some embodiments, as shown in FIG. 7 , a transistor device or die 1000 may include multiple transistor structures 100 a, 100 b, 100 c (collectively 100) connected in parallel to device terminals or electrodes (e.g., input, output, and ground terminals). For example, gate 110, drain 105, and source 115 contacts may extend in a first direction (e.g., the Y direction) to define gate, drain, and / or source “fingers,” which may be connected by one or more respective buses (e.g., by gate bus and drain bus on top surface 126A of semiconductor structure 190). In FIG. 7 , gate fingers 110, drain fingers 105, and source fingers 115 may extend in parallel with one another, with gate fingers 110 extending in a first direction from gate bus 112 and drain fingers 105 extending in a direction opposite the first direction from drain bus 114. Each gate finger 110 may be positioned between drain fingers 105 and source fingers 115 to define a unit cell 100. Gate fingers 110, drain fingers 105, and source fingers 315 (and connecting busses) may define portions of the gate, drain, and source connecting electrodes of the device, respectively, as defined by the top or front side metallization structure. Dielectric layers isolating the various conductive elements of the front side metallization structure from one another are not shown in FIG. 7 to simplify the drawing. It can be seen that the unit cell transistors 100 are electrically connected in parallel, with gate fingers 110 electrically connected to a common gate bus, drain fingers 105 electrically connected to a common drain bus, and source fingers 115 electrically connected to each other (e.g., via respective via openings 146 on the back side 122B of substrate 122 and backside metal layers).

[0107] One of the terminals of the device (e.g., a source terminal connected to the source contact(s) 115) may be configured to be coupled to a reference signal, such as electrical ground. In some embodiments, a via connection or structure through the conductive substrate (e.g., a backside via opening formed through the backside 122B) may extend through the substrate 122 and the epitaxial layer(s) 124, 126 to expose a portion of one of the contacts 105, 115 and provide a contact pad or terminal on the backside 122B of the substrate (e.g., coupling the source contact 115 to ground). In other embodiments, a ground connection to one of the terminal devices (e.g., the source terminal) may be made outside the active area, e.g., in a peripheral area. In some embodiments, a backside metal layer on the backside 122B of the substrate 122 may form a backside ground plane, e.g., in applications where proximity to ground is desired.

[0108] Although embodiments of the present invention have been described herein with reference to particular HEMT structures, the present invention should not be construed as limited to such structures, but may be applied to the formation of many different transistor structures, such as pHEMTs (including GaAs / AlGaAs pHEMTs) and / or GaN MESFETs.

[0109] Additionally, additional layers may be included in the transistor structure while still benefiting from the teachings of the present invention. Such additional layers may include, for example, a GaN cap layer as described in U.S. Patent No. 6,548,333 to Smith. In some embodiments, a SiN x An insulating layer such as GaN, AlGaN, or relatively high-quality AlN may be deposited to create a MISHEMT and / or to passivate the surface. Additional layers may include one or more compositionally graded transition layers. In addition, the barrier layer 126 and / or channel layer 124 described above may include multiple layers. Thus, embodiments of the present invention should not be construed as limiting these layers to a single layer, but may include, for example, barrier layers having a combination of GaN, AlGaN, and / or AlN layers.

[0110] 8A, 8B, and 8C are schematic cross-sectional views illustrating some example ways in which RF transistor amplifier dies according to embodiments of the present invention can be packaged to provide packaged RF transistor amplifiers 800A, 800B, and 800C. Figures 8A-8C illustrate packaging a transistor device 1000, which may include any of the transistor structures described herein.

[0111] 8A is a schematic side view of a packaged III-nitride-based RF transistor amplifier 800A. As shown in FIG. 8A, the packaged RF transistor amplifier 800A includes an RF transistor amplifier die 1000 packaged in an open cavity packaging structure 810A. The packaging structure 810A includes a metal gate lead 822A, a metal drain lead 824A, a metal submount 830, sidewalls 840, and a lid 842.

[0112] Submount 830 may include a material configured to aid in thermal management of package 800A. For example, submount 830 may include copper and / or molybdenum. In some embodiments, submount 830 may be constructed of multiple layers and / or include vias / interconnects. In an example embodiment, submount 830 may be a multi-layer copper / molybdenum / copper metal flange with a core molybdenum layer and copper cladding layers on either major surface thereof. In some embodiments, submount 830 may include a metal heat sink that is part of a lead frame or metal slug. Sidewalls 840 and / or lid 842 may be formed of or include an insulating material in some embodiments. For example, sidewalls 840 and / or lid 842 may be formed of or include a ceramic material. In some embodiments, sidewalls 840 and / or lid 842 may be formed of, for example, Al2O3. Lid 842 may be adhered to sidewalls 840 using an epoxy adhesive. Sidewall 840 may be attached to submount 830 via brazing, for example. Gate lead 822A and drain lead 824A may be configured to extend through sidewall 842, although embodiments of the invention are not limited in this respect.

[0113] The RF transistor amplifier die 1000 is mounted on top of the metal submount 830 in an air-filled cavity 812 defined by the metal submount 830, ceramic sidewalls 840, and ceramic lid 842. The gate terminal 132 and drain terminal 134 of the RF transistor amplifier die 1000 are on the top surface of the semiconductor structure 190, while the source terminal 136 is on the bottom surface of the semiconductor structure 190. The source terminal 136 may be mounted to the metal submount 830 using, for example, a conductive die attach material (not shown). The metal submount 830 may be electrically connected to the source terminal 136 and may function as a heat dissipation structure to dissipate heat generated by the RF transistor amplifier die 1000.

[0114] An input matching circuit 850 and / or an output matching circuit 852 may be mounted within the package 800A. The matching circuits 850, 852 may include impedance matching and / or harmonic termination circuits. The impedance matching circuit may be used to match the impedance of the fundamental component of the RF signal input to or output from the RF transistor amplifier to the impedance at the input or output of the RF transistor amplifier die 1000, respectively. The harmonic termination circuit may be used to ground harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 1000. Two or more input matching circuits 850 and / or output matching circuits 852 may be provided. As shown schematically in FIG. 8A , the input matching circuit 850 and the output matching circuit 852 may be mounted on a metal submount 830. Gate lead 822A may be connected to input matching circuit 850 by one or more bond wires 854, which may be connected to gate terminal 132 of RF transistor amplifier die 1000 by one or more additional bond wires 854. Similarly, drain lead 824A may be connected to output matching circuit 852 by one or more bond wires 854, which may be connected to drain terminal 134 of RF transistor amplifier die 1000 by one or more additional bond wires 854. Bond wire 854, which is an inductive element, may form part of the input matching circuit and / or the output matching circuit.

[0115] 8B is a schematic side view of a packaged III-nitride-based RF transistor amplifier 800B including a transistor device 1000 packaged in a printed circuit board-based packaging structure 810B. The packaged RF transistor amplifier 800B is very similar to the packaged RF transistor amplifier 800A of FIG. 8A, except that the gate lead 822A and drain lead 824A of the packaging structure 810A are replaced by printed circuit board-based leads 822B, 824B of the packaging structure 810B.

[0116] The package structure 810B includes a submount 830, a ceramic sidewall 840, and a ceramic lid 842, each of which may be substantially identical to the like-numbered elements of the package structure 810A discussed above. The package structure 810B further includes a printed circuit board 820. Conductive traces on the printed circuit board 820 form a metal gate lead 822B and a metal drain lead 824B. The printed circuit board 820 may be attached to the submount 830 via, for example, a conductive adhesive. The printed circuit board 820 includes a central opening, and the RF transistor amplifier die 1000 is mounted within this opening in the submount 830. The other components of the RF transistor amplifier 800B may be the same as the like-numbered components of the RF transistor amplifier 800A and will not be described further.

[0117] 8C is a schematic side view of another packaged III-nitride-based RF transistor amplifier 800C. RF transistor amplifier 800C differs from RF transistor amplifier 800A by including a different packaging structure 810C. Package structure 810C includes a metal submount 830 (which may be similar or identical to submount 830 of package structure 810A), as well as a metal gate lead 822C and a metal drain lead 824C. RF transistor amplifier 800C also includes a plastic overmold 860 that at least partially surrounds RF transistor amplifier die 1000, leads 822C, 824C, and metal submount 830. Other components of RF transistor amplifier 800C may be the same as the like-numbered components of RF transistor amplifier 800A and will not be described further.

[0118] The present invention will now be described with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

[0119] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "upon" another element, it is understood that it can be directly on or extending directly onto the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0120] It should also be understood that, although terms such as "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention.

[0121] Additionally, relative terms such as "below" or "bottom" and "up" or "top" may be used herein to describe the relationship of one element to another element, as illustrated in the figures. It is understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures were inverted, an element described as being on the "down" side of the other element would be oriented on the "up" side of the other element. The exemplary term "below" can thus encompass both an orientation of "below" and "up" depending on the particular orientation of the figure. Similarly, if the device in one of the figures were inverted, an element described as being "down" or "below" the other element would be oriented "up" the other element. The exemplary terms "below" or "down" can thus encompass both an orientation of up and down.

[0122] The terminology used in the description of the present invention herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the description of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The term "and / or," as used herein, is also understood to refer to and encompass any and all possible combinations of one or more of the associated listed items. Furthermore, it is understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups.

[0123] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are expected. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include, for example, deviations in shape that result from manufacturing. For example, an implanted region illustrated as a rectangle typically has rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from implanted to non-implanted. Similarly, a buried region formed by implantation may result in some implantation in the region between the implanted region and the surface where the implantation occurs. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device, nor are they intended to limit the scope of the present invention.

[0124] Unless otherwise specified, all terms used in disclosing embodiments of the present invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs and are not necessarily limited to the specified definitions known at the time the present invention is described. Accordingly, these terms may include equivalent terms created after such time. Furthermore, terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and the related art, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

[0125] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A transistor device comprising: a semiconductor structure; source and drain contacts on the semiconductor structure; a gate on the semiconductor structure between the source contact and the drain contact; a surface passivation layer on the semiconductor structure between the gate and the source contact or the drain contact, the surface passivation layer including an opening therein exposing the first region of the semiconductor structure for processing the first region; the first region is laterally spaced from the source contact and the drain contact; A transistor device, wherein the first region has a higher conductivity than a second region of the semiconductor structure adjacent the gate.

2. The transistor device of claim 1 , wherein the semiconductor structure includes a channel layer and a barrier layer defining a heterojunction therebetween.

3. The transistor device of claim 2 , wherein the first region has a lower sheet resistance than the second region.

4. The transistor device of claim 2 , wherein the first region has different surface properties than the second region.

5. 5. The transistor device of claim 2, wherein the first region has modified interface states and the second region is free of the modified interface states or has interface states modified in a different way.

6. The transistor device of claim 2 , wherein the opening is laterally separated from the gate by the second region.

7. 7. The transistor device of claim 6, wherein the gate includes a sidelobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, the sidelobe portion extending over the second region.

8. 7. The transistor device of claim 6, wherein the openings are spaced laterally from the gate along a surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

9. the surface passivation layer is a first passivation layer; the transistor device further comprises a second passivation layer on the first passivation layer and extending into the opening to contact the first region; 6. The transistor device of claim 5, wherein the interface between the first region and the second passivation layer has the modified interface state different from the interface between the second region and the first passivation layer.

10. The transistor device of claim 9 , wherein the modified interface states are defined by the formation of the second passivation layer.

11. 10. The transistor device of claim 9, further comprising a field plate on the second passivation layer and between the gate and the drain contact, the opening being laterally spaced from at least a portion of the field plate.

12. The transistor device of claim 11 , wherein the field plate at least partially overlaps the opening with the second passivation layer therebetween.

13. The transistor device of claim 4 , wherein the surface characteristics are defined by ion bombardment, plasma nitridation, plasma oxidation, hydrogen plasma treatment, and / or annealing in a gas environment.

14. 1. A transistor device comprising: a semiconductor structure including a channel layer and a barrier layer defining a heterojunction therebetween; source and drain contacts on the semiconductor structure; a gate on the semiconductor structure between the source contact and the drain contact; 1. A transistor device, wherein the semiconductor structure includes a first region between the gate and the source contact or the drain contact, and a second region adjacent to the gate, the first region being laterally spaced from the source contact and the drain contact and having a higher conductivity than the second region.

15. The transistor device of claim 14 , wherein the first region has a lower sheet resistance than the second region.

16. 15. The transistor device of claim 14, wherein the semiconductor structure including the first region and the second region has a conductivity that varies non-uniformly between the gate and the source contact or the drain contact.

17. 17. A transistor device according to any one of claims 14 to 16, wherein the first region has different surface properties than the second region.

18. 18. The transistor device of claim 14, wherein the first region has modified interface states and the second region is free of the modified interface states or has interface states modified in a different way.

19. 20. The transistor device of claim 17, further comprising a surface passivation layer on a surface of the semiconductor structure between the gate and the source contact or the drain contact, the surface passivation layer including an opening therein exposing the first region.

20. 20. The transistor device of claim 19, wherein the opening is laterally separated from the gate by the second region.

21. 21. The transistor device of claim 20, wherein the gate includes a sidelobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, the sidelobe portion extending over the second region.

22. 21. The transistor device of claim 20, wherein the openings are spaced laterally from the gate along the surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

23. the surface passivation layer is a first passivation layer; the transistor device further comprises a second passivation layer on the first passivation layer and extending into the opening to contact the first region; 20. The transistor device of claim 19, wherein an interface between the first region and the second passivation layer has a modified interface state that is different from an interface between the second region and the first passivation layer.

24. 1. A transistor device comprising: a semiconductor structure including a channel layer and a barrier layer defining a heterojunction therebetween; source and drain contacts on the semiconductor structure; a gate on the surface of the semiconductor structure between the source contact and the drain contact; one or more passivation layers on the surface of the semiconductor structure between the gate and the source contact or the drain contact; the conductivity of the semiconductor structure varies non-uniformly in a direction along an interface with one or more passivation layers thereon; A transistor device, wherein the conductivity maximum is between the gate and the source contact or the drain contact, and is spaced apart from the source contact and the drain contact.

25. 25. The transistor device of claim 24, wherein the semiconductor structure includes a first region between the gate and the source contact or the drain contact, and a second region adjacent the gate, the first region having a higher conductivity than the second region.

26. 26. The transistor device of claim 25, wherein the first region has a lower sheet resistance than the second region.

27. 26. The transistor device of claim 25, wherein the first region has different surface properties than the second region.

28. 28. The transistor device of claim 25, wherein the first region has modified interface states and the second region is free of the modified interface states or has interface states modified in a different way.

29. The one or more passivation layers are a first passivation layer over the second region of the semiconductor structure adjacent the gate and including an opening therein exposing the first region; 30. The transistor device of claim 28, wherein the opening is laterally separated from the gate by the second region.

30. The one or more passivation layers are a second passivation layer on the first passivation layer and extending into the opening to contact the first region; 30. The transistor device of claim 29, wherein the interfaces include a first interface between the first region and the second passivation layer and a second interface between the second region and the first passivation layer, the first interface having a different modified interface state than the second interface.

31. 31. The transistor device of claim 30, further comprising a field plate overlying the second passivation layer between the gate and the drain contact, the opening being laterally spaced from at least a portion of the field plate.

32. 1. A method of fabricating a transistor device, comprising: forming a surface passivation layer on the semiconductor structure; forming source and drain contacts and the gate on the semiconductor structure, the gate being between the source and drain contacts; forming an opening in the surface passivation layer exposing a first region of the semiconductor structure between the gate and the source contact or the drain contact; treating the first region of the semiconductor structure exposed by the opening differently from a second region of the semiconductor structure adjacent the gate; the first region is laterally spaced from the source contact and the drain contact; 10. A method of fabricating a transistor device, wherein the first region has a higher conductivity than the second region of the semiconductor structure in response to the processing.

33. the semiconductor structure includes a channel layer and a barrier layer defining a heterojunction therebetween; 33. The method of claim 32.

34. 34. The method of claim 33, wherein the first region has a lower sheet resistance than the second region in response to the treatment.

35. 34. The method of claim 33, wherein the first region has different surface properties in response to the treatment than the second region.

36. 36. The method of any one of claims 32 to 35, wherein the processing comprises performing a surface treatment of the first region exposed by the opening to modify its interface state, the second region being substantially unaffected by the surface treatment.

37. 37. The method of claim 36, wherein the surface treatment comprises ion bombardment, plasma nitridation, plasma oxidation, hydrogen plasma treatment, and / or annealing in a gas environment.

38. 37. The method of claim 36, wherein the surface treatment comprises wet etching with an acidic chemical solution, wet etching with a basic chemical solution, and / or treatment with a neutral chemical solution.

39. the surface passivation layer is a first passivation layer; The method further includes forming a second passivation layer on the first passivation layer and extending into the opening to contact the first region; 37. The method of claim 36, wherein the interface between the first region and the second passivation layer has the modified interface state different from the interface between the second region and the first passivation layer.

40. 40. The method of claim 39, wherein forming the second passivation layer preserves the modified interface state of the first region.

41. the surface passivation layer is a first passivation layer; The method further comprises forming a second passivation layer on the first passivation layer and extending into the opening to contact the first region; 36. The method of any one of claims 32 to 35, wherein forming the second passivation layer modifies the interface state of the first region.

42. 36. The method of any one of claims 32 to 35, wherein forming the opening in the surface passivation layer modifies the interface state of the first region.

43. 36. The method of any one of claims 32 to 35, wherein the opening is laterally separated from the gate by the second region.

44. 44. The method of claim 43, wherein the gate includes a sidelobe portion that extends laterally along the surface passivation layer toward the source contact or the drain contact, the sidelobe portion extending over the second region.

45. 44. The method of claim 43, wherein the openings are spaced laterally from the gate along a surface of the semiconductor structure by about 10 nanometers (nm) to about 500 nm.

Images