Semiconductor light emitting element, light emitting device, and distance measuring device

Abstract

To provide a semiconductor light emitting element with high output and easy beam control in the far field while suppressing the voltage rise of the entire element.SOLUTION: A semiconductor element has a structure in which a substrate, a first reflector, a resonator section including an active layer, a second reflector, and a tunnel junction section are stacked in this order, and further comprises: a first current narrowing section composed of an oxidation narrowing layer, and a second current narrowing section in which the tunnel junction section is provided on a portion of the upper surface of the second reflector and composed of the tunnel junction section, and the width d2 of the second current narrowing section is smaller than the width d1 of the first current narrowing section.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting element, a light-emitting device, and a distance measuring device. [Background technology]

[0002] VCSELs (Vertical Cavity Surface Emitting Lasers) are attracting attention as light sources for ToF (Time of Flight) LiDAR (Light Detection and Ranging).

[0003] In order to improve distance measurement accuracy and the measurable distance, a high output light source is required.

[0004] One way to achieve high output in VCSELs is to increase the light-emitting diameter. However, simply increasing the light-emitting diameter reduces the current density near the center of the diameter and increases it at the periphery. Therefore, simply increasing the light-emitting diameter creates problems with far-field beam control and durability.

[0005] Patent Document 1 discloses a back-surface-emitting VCSEL in which a current confinement structure different from oxide confinement is provided on the front surface of the substrate. This configuration increases the light emission diameter while increasing the current density not only at the periphery but also near the center of the light emission diameter. However, back-surface-emitting VCSELs have issues such as the inability to achieve certain wavelengths or high output due to light absorption by the substrate.

[0006] Patent Document 2 discloses a substrate surface-emitting VCSEL in which a current confinement structure different from oxidation confinement is provided on the device surface (light emission side) by diffusion or ion implantation. With this configuration, even if the emission diameter is increased, the current density can be increased not only at the periphery but also near the center of the emission diameter.

[0007] Patent Document 2 discloses a method for forming a current confinement structure in which current flows only in the central portion by implanting ions into the peripheral portion of the substrate surface to increase the resistance of the periphery. The problems that arise when forming a current confinement structure in this way will be explained with reference to FIG.

[0008] 12, a high-resistance region 712 is formed in the peripheral portion of a p-GaAs layer 710 by ion implantation, and furthermore, a current path from a second electrode 714 to a current injection region 720 is left in the upper portion of the p-GaAs layer 710. In addition, a current path from the current injection region 720 to an opening 716 is formed in the p-DBR 708. For these reasons, the thickness of the p-GaAs layer 710 must be on the order of μm. Because the distance of the current injection region 720 in the direction perpendicular to the substrate becomes thick on the order of μm, the resistance increases, and as a result, the voltage of the entire semiconductor light-emitting device increases. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2019 / 107273 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-114915 Summary of the Invention [Problem to be solved by the invention]

[0010] In consideration of the above problems, the present invention aims to provide a high-output, far-field laser diode that suppresses the voltage rise of the entire device. An object of the present invention is to provide a semiconductor light emitting device that allows easy beam control. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device having a structure in which a substrate, a first reflecting mirror, a resonator portion including an active layer, a second reflecting mirror, and a tunnel junction portion are stacked in this order, and further comprising a first current confinement portion formed by an oxide confinement layer, and the tunnel junction portion is provided on a part of the upper surface of the second reflecting mirror and a second current confinement portion formed by the tunnel junction portion, wherein a width d2 of the second current confinement portion is smaller than a width d1 of the first current confinement portion. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a semiconductor light-emitting element that has high output and easy far-field beam control while suppressing an increase in voltage across the entire element. Furthermore, by using this semiconductor light-emitting element, it is possible to provide a distance measuring device with improved distance measurement accuracy and measurable distance. [Brief explanation of the drawings]

[0013] [Figure 1] 1A and 1B are diagrams illustrating a semiconductor light emitting device according to an embodiment of the present invention. [Figure 2] 10A and 10B are diagrams showing the distribution and change of current density in the present embodiment. [Figure 3] FIG. 1 is a diagram illustrating a first embodiment. [Figure 4A] FIG. 10 is a diagram illustrating a second embodiment. [Figure 4B] FIG. 10 is a diagram illustrating a modified example of the second embodiment. [Figure 4C] FIG. 10 is a diagram illustrating a further modified example of the second embodiment. [Figure 5A] FIG. 10 is a diagram illustrating a third embodiment. [Figure 5B] FIG. 10 is a diagram illustrating a third embodiment. [Figure 6] FIG. 10 is a diagram illustrating a fourth embodiment. [Figure 7] FIG. 10 is a diagram showing the distribution and change of current density in Example 4. [Figure 8] FIG. 10 is a diagram illustrating Example 5. [Figure 9] FIG. 10 is a diagram illustrating Example 6. [Figure 10] FIG. 10 is a diagram illustrating Example 7. [Figure 11] FIG. 10 is a diagram illustrating Example 8. [Figure 12] FIG. 10 is a diagram illustrating Example 9. [Figure 13] FIG. 10 is a diagram illustrating a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0014] The following describes embodiments of the present invention. Note that the present invention is not limited to the following embodiments, and any modifications or improvements to the following embodiments based on the ordinary knowledge of a person skilled in the art without departing from the spirit of the present invention are also included in the scope of the present invention.

[0015] A semiconductor light-emitting device 100 according to one embodiment of the present invention will be described with reference to Figure 1. The semiconductor light-emitting device 100 includes a substrate 101, a first DBR (Distributed Bragg Reflector) 102, a semiconductor resonator portion 103, a second DBR 104, and a tunnel junction layer 142. The first DBR 102 and the second DBR 104 correspond to the first reflector and the second reflector of the present invention, respectively.

[0016] The substrate 101 and the first DBR 102 are made of an n-type semiconductor, and the second DBR 104 is made of a p-type semiconductor. A lower electrode 151 is in ohmic contact with the rear surface of the substrate 101.

[0017] A plurality of quantum well layers 140 are arranged in the cavity portion 103. A portion of the BR 104 includes an AlGaAs layer with a higher Al composition than the other layers. This layer is oxidized by steam oxidation to form an insulating oxidized constriction layer 106 on the periphery. The oxidized constriction layer 106 corresponds to the first constriction portion. Note that in FIG. 1, only the insulating portion is indicated by a lead and labeled with the reference numeral 106, but the unoxidized central semiconductor layer portion also corresponds to the oxidized constriction layer 106.

[0018] In this embodiment, the second DBR 104 is made of a semiconductor. As another embodiment of the present invention, a configuration in which a third, fourth, or fifth DBR different from the second DBR is further provided on the second DBR, or other modifications are also possible. Details of these configurations will be described in Examples 2 and 7 below.

[0019] The resonator portion 103 and the second DBR 104 are processed into a cylindrical mesa shape. Here, in Fig. 1, the mesa shape is formed from the second DBR 104 to the resonator portion 103, but it is sufficient that the mesa shape is formed below the oxidized constriction layer 106. Therefore, the mesa shape may be formed, for example, up to the middle of the resonator portion 103, or up to the middle of the first DBR 102.

[0020] Although the present embodiment describes a structure in which the light-emitting element is processed into a cylindrical mesa shape, the present invention is not limited to this. For example, instead of processing the periphery uniformly like a cylindrical shape, a portion may be removed by etching to the same depth, and then steam oxidation may be performed from there to form an insulating oxide constriction layer 106 around the periphery.

[0021] The first DBR 102 is configured by stacking multiple pairs of high-refractive-index layers and low-refractive-index layers, each pair having an optical film thickness of λc / 4, where λc is the center wavelength of the high-reflection band of the first DBR 102.

[0022] Quantum well layer 140 has a structure in which a well layer is sandwiched between barrier layers, and is the active layer of resonator section 103 .

[0023] The second DBR 104 is basically constructed by stacking multiple pairs of high-refractive-index layers and low-refractive-index layers, each with an optical film thickness of λc / 4. A portion of the high-refractive-index layer closest to the quantum well layer (active layer) 140 of the second DBR 104 is replaced with an AlGaAs layer with a higher Al composition than the remaining layers. After the mesa of the VCSEL 100 is formed, this AlGaAs layer is oxidized by steam oxidation from the mesa sidewalls for a predetermined length, forming an insulating oxide constriction layer 106 around the periphery.

[0024] The tunnel junction layer 142 is composed of at least two layers, that is, from the substrate 101 side, a highly doped p-type semiconductor layer 143 and a highly doped n-type semiconductor layer 141 thereon. The optical thickness of these two layers combined is set to be an integer multiple of λc / 2.

[0025] If absorption in a highly doped p-type GaAs layer becomes a problem, the p-type semiconductor layer 143 may be configured with multiple layers. For example, a two-layer configuration may be used in which the doping concentration of the layer on the substrate side is reduced and the layer above it (the layer in contact with the n-type semiconductor layer 141) is a thin, highly doped layer.

[0026] The tunnel junction layer 142 is patterned so as to be formed on a portion of the upper surface of the second DBR 104. Specifically, the tunnel junction layer 142 is formed so as to overlap the central portion of the second DBR 104, more precisely, the center of the oxidized constriction formed by the oxidized constriction layer 106 (the center of the non-oxidized portion). In this embodiment, the tunnel junction layer 142 is described as having a circular shape, but may have other shapes such as a polygon. Width of the tunnel junction layer The distance (or diameter in the case of a circle) is referred to as d2. The tunnel junction layer 142 is formed so as to be included within the confinement portion (non-oxidized portion) formed by the oxidized confinement layer 106 in plan view. Carriers supplied from the upper ring electrode 150 are supplied to the second DBR 104 from the portion where the tunnel junction layer 142 exists. Therefore, the tunnel junction portion having this tunnel junction layer 142 corresponds to the second current confinement portion. Note that in this specification, the tunnel junction portion does not refer to the interface between a p-type semiconductor layer and an n-type semiconductor layer with a high impurity concentration, but refers to a member including these semiconductor layers.

[0027] Here, an example in which a tunnel junction layer is patterned as the second current confinement structure is shown in FIG. 1, but the present invention is not limited to this, and other methods can be selected. For example, the second current confinement structure may be formed by forming an insulating film on the tunnel junction layer without patterning it, and then partially removing the insulating film. Another example will be described in the examples below.

[0028] When an etching stop layer is necessary in patterning the tunnel junction layer 142, the etching stop layer may be sandwiched between the second DBR 104 and the tunnel junction layer 142. The optical film thickness of the etching stop layer is set to be an integer multiple of λc / 2.

[0029] An n-type transparent conductive layer 162 is disposed on the tunnel junction layer 142, the second DBR 104, and the insulating film 161. Carriers supplied from the upper ring electrode 150 are supplied to the patterned tunnel junction layer 142 through the transparent conductive layer 162, as shown by the dotted line in FIG.

[0030] Since the transparent conductive layer 162 is n-type and current does not normally flow from n-type to p-type, the flow of carriers supplied from the upper ring electrode 150 is as described above even if there is no insulating film or the like between the transparent conductive layer 162 and the upper DBR 104. In other words, the width d2 of the tunnel junction layer 142 is the width of the second current confinement structure.

[0031] 1, a transparent conductive film is used as a path from the upper ring electrode 150 to the tunnel junction layer 142, but the present invention is not limited to this, and other configurations may be used as long as they provide a similar path for supplying carriers. Other examples will be described in the examples below.

[0032] 1 shows the transparent conductive layer 162 as a single layer, one or more transparent insulating films (SiOx, SiNx, TiOx, etc.) may be laminated thereon as necessary. In that case, a portion of the insulating film below the upper electrode 150 is removed, and the upper electrode 150 and the transparent conductive layer 162 are configured to be electrically connected.

[0033] The tunnel junction layer is a so-called tunnel diode, where a p-type semiconductor layer with a high carrier concentration is joined to an n-type semiconductor layer, and current also flows in the reverse direction through a thin depletion layer generated at the pn interface by the tunnel effect. Therefore, when a voltage is applied between the ring electrode 150 and the bottom electrode 151 so that the ring electrode 150 is positive, current flows from the ring electrode 150 through the transparent conductive film layer 162 and the tunnel junction layer 142 to the second DBR 104. The current that flows into the second DBR 104 diffuses within the second DBR 104, and the current density distribution injected into the active layer has a convex shape with a high current density in the center.

[0034] Therefore, according to this embodiment, it is possible to control the far-field pattern. In addition, by spreading the current density, which has been concentrated at the periphery of the oxide confinement diameter, to the center, the occurrence of non-radiative recombination regions spreading from the periphery is suppressed, thereby improving the durability of the element.

[0035] Below, we will explain in more detail, including calculation examples.

[0036] The width d2 of the tunnel junction layer 142, i.e., the width d2 of the second current confinement, is smaller than the width d1 of the semiconductor portion (i.e., the portion through which current can flow, hereinafter referred to as the non-oxidized portion) inside the oxidized confinement layer 106, which is the first current confinement. In other words, d1 and d2 are sized to satisfy formula (1). d2 < d1 (1)

[0037] The following description will be given assuming that the non-oxidized portion (the semiconductor portion inside the oxidized confinement layer 106) and the second current confinement (tunnel junction layer 142) have circular shapes, but these shapes are not limited to circular and may be elliptical, polygonal, or similar shapes. In such cases, the widths d1 and d2 when cut at a certain cross section are sized to satisfy formula (1). Sharp-angled portions tend to concentrate current at those portions, which is undesirable from the perspective of current profile and durability, and shapes that are similar to circular are preferable.

[0038] The effects of the above configuration will be explained based on the calculation results shown in Fig. 2(a). The element configuration used as the calculation model was the configuration of Example 1 described below.

[0039] Figure 2(a) shows the distribution of current density flowing into the quantum well layer 140 when the diameter d2 of the second current confinement is changed from 5 μm to 29 μm, with the oxidized confinement diameter d1 being 30 μm. The horizontal axis of Figure 2(a) represents the radial position when the center of the mesa (which is also the center of the non-oxidized portion) is set as position 0.

[0040] In addition, the change in the current density when the current density in the central part is Jc and the minimum value of the current density in the peripheral part (the part from the periphery of d1 to the central part by 10 μm) is Je is shown by the solid line in Figure 2(b).

[0041] The far-field pattern can be controlled by making the current density distribution flowing into the quantum well layer higher in the center than in the periphery. Jc > Je (2) It is preferable that:

[0042] Furthermore, Jc > 2×Je (3) It is more preferable that:

[0043] 2(a) and (b) show that a current density distribution with a central convexity can be created when the diameter d2 of the second constriction portion is smaller than 25 μm, that is, in the range that satisfies Equation 2. Furthermore, when d2 is smaller than about 15 μm, that is, in the range that satisfies Equation 3, the current density profile becomes more centrally convex.

[0044] Furthermore, by spreading the current density, which had been concentrated at the periphery of the oxide confinement diameter, to the center, the occurrence of non-radiative recombination spreading from the periphery is suppressed, thereby improving the durability of the device. The dotted line in Figure 2(b) shows the change in Jmax / Jmin when the maximum and minimum current densities in the non-oxidized portion are Jmax and Jmin, respectively. Note that when d2 is less than 20 μm, Jmax / Jmin (dotted line) is roughly consistent with Jc / Je (solid line).

[0045] In terms of durability, Jmax < 3.3 × Jmin (4) It is generally said that durability (lifespan) is inversely proportional to the square of the current density, so by satisfying the condition of Equation 4, the in-plane variation in local durability in the non-oxidized portion can be kept within one digit.

[0046] Now, if you care more about the far field profile than durability, Jmax < 10 × Jmin (5) By satisfying the condition of formula (5), the in-plane variation in local durability in the non-oxidized portion can be kept within two digits.

[0047] The three elements of the preferred device configuration, the non-oxidized confinement diameter d1, and the diameter d2 of the second current confinement portion influence each other and are determined according to the application or requirements. For example, in the device configuration shown in FIG. 1, when the non-oxidized confinement diameter d1 is 30 μm as in Example 1 described later, the preferred diameter d2 of the second current confinement portion is 12 to 18 μm if durability is emphasized. For applications where the far-field profile is more important than durability, the value of d2 may be 12 μm or less. The thickness t of the tunnel junction layer 142 is not particularly limited, but may be, for example, in the range of 10 nm to 440 nm.

[0048] When the device configuration changes, the suitable ranges of d1 and d2 change accordingly, so a suitable range should be selected depending on the application.

[0049] In the present invention, the second current confinement width is determined using the tunneling effect, and control of the interface state within a few nanometers is extremely important for the tunneling effect. Compared to a configuration in which at least one layer is fabricated by a method other than epitaxial growth, for example, a film with a doping concentration of 19 or more is fabricated by a process, fabricating the device with good controllability and reproducibility by epitaxial growth as in this embodiment can improve the reproducibility and yield of the device.

[0050] The second confinement structure is formed by providing a relatively thin tunnel junction 142 and a transparent conductive layer 162 on the second DBR 104. Furthermore, compared to the p-GaAs layer used in FIG. 12 , a transparent conductive film with high conductivity or an n-type GaAs layer, as described in the examples below, can be used. Therefore, the voltage rise in the second confinement structure for the entire VCSEL 100 can be reduced by about one order of magnitude compared to a formation method using ion implantation. Therefore, by using the element of this embodiment as a light source, it is possible to provide a distance measuring device that not only improves distance measurement accuracy and measurable distance, but also achieves miniaturization and weight reduction.

[0051] Hereinafter, examples of the present invention will be described in more detail, showing specific layer structures of light-emitting elements.

[0052] Example 1 A VCSEL 300 according to Example 1 will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view of the VCSEL 300 of Example 1. The VCSEL 300 is configured by stacking a GaAs substrate 301, a first DBR 302, a semiconductor resonator portion 303, and a second DBR 304 in this order. Although these components are shown in direct contact with each other in FIG. 3, other components may be provided between them. Furthermore, the above description is merely an explanation of the structure and does not limit the order in which the components are manufactured.

[0053] Three quantum well layers 340 are arranged in the cavity section 303. The second DBR 304 is partially made of Al. 0.98 The GaAs is oxidized by steam oxidation to form an insulating oxide confinement layer 306 around the periphery. The oxide confinement layer 306 is in the first current confinement section. Equivalent.

[0054] The resonator section 303 and the second DBR 304 are processed into a cylindrical mesa shape. A tunnel junction layer 442 is disposed on the second DBR 304. As shown in FIG. 3, the tunnel junction layer 442 exists only in a portion of the outermost surface of the second DBR 304, the portion having a diameter d2 including the center of the mesa. The diameter d2 is smaller than the diameter d1 of the non-oxidized portion of the oxidized confinement (first confinement structure). ITO (Indium Tin Oxide) is disposed on the upper surface of the tunnel junction layer 442 and on the portion of the upper surface of the second DBR 304 where the tunnel junction layer 442 is not disposed. An oxide layer 462 is formed on the surface of the semiconductor substrate 400.

[0055] The ITO layer 462 is formed on the tunnel junction layer 442 and on a portion of the second DBR 304 where the tunnel junction layer 442 is not provided, and electrically connects the upper ring electrode 450 and the tunnel junction layer 442. The optical thickness of the ITO layer 462 may be an integer multiple of λc / 2. However, since the ITO layer also absorbs some light, it is preferable that the optical thickness be λc / 2 as long as there is no problem with the conductivity in the lateral direction of the substrate.

[0056] The tunnel junction layer 442 is circular, and an upper ring electrode 450 is in electrical contact with a part of the ITO layer 462. The lower common electrode 351 is in ohmic contact with the rear surface of the GaAs substrate 301.

[0057] The first DBR302 is an Al with an optical thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The GaAs layer is counted as one pair, and 35 pairs are stacked to form the structure. λc is the center wavelength of the high reflection band of the first DBR 302, which is 940 nm in this embodiment.

[0058] The quantum well layer 340 is an 8 nm thick In 0.1 The GaAs layer is covered with 10 nm of Al 0.1 GaAs In this embodiment, three quantum well layers are arranged in the resonator section 303.

[0059] The second DBR304 is an Al 0.1 GaAs layer and Al 0.9 The Al layer closest to the quantum well layer 340 of the second DBR is 0.1 A part of the GaAs layer is covered with a 30 nm thick Al 0.98 GaAs This Al layer has been replaced by 0.98 After the mesa of the VCSEL 300 is formed, the GaAs layer is oxidized by steam oxidation from the mesa sidewalls to a predetermined length from the mesa edge, forming an insulating oxide constriction layer 306 around the periphery.

[0060] The tunnel junction layer 442 has a carrier concentration of 5×10 19 cm -3 So dope A p-type GaAs layer 440 with a carrier concentration of 1x10 19 cm -3 Doped by The optical film thickness of the two layers combined is set to be an integer multiple of λc / 2. For example, the actual thickness of the n-type GaAs layer 441 is set to 190 nm.

[0061] If absorption in a highly doped p-type GaAs layer becomes a problem, the p-type GaAs layer 440 may be composed of multiple layers. For example, the layer on the substrate side may have a carrier density of 1x10 18 cm -3 The layer above it (the layer in contact with the n-type GaAs layer 441) is doped to a carrier density of 1×10 19 cm -3 It may be a thin layer (for example, 20 nm thick), or may have a two-layer structure.

[0062] Furthermore, if an etching stop layer is necessary in patterning the tunnel junction layer 442, the etching stop layer may be sandwiched between the second DBR 304 and the tunnel junction layer 442. The optical thickness of the etching stop layer is set to be an integer multiple of λc / 2.

[0063] Thus, the tunnel junction layer has a carrier concentration of 1x10 18 cm -3 Because a p-type semiconductor layer and an n-type semiconductor layer exceeding 1000 nm are junctioned, the device forms a so-called tunnel diode, allowing current to flow in the reverse direction through a thin depletion layer generated at the pn interface by the tunnel effect. Therefore, when a voltage is applied between the ring electrode 450 and the back electrode 351 so that the ring electrode 450 is positive, current flows from the ring electrode 450 through the ITO layer 462 and the tunnel junction layer 442 to the second DBR 304. The current that flows into the second DBR 304 diffuses within the second DBR 304, and the current density distribution injected into the active layer has a convex shape with a high center.

[0064] The convex current density distribution with a high center as described above can be realized, which allows for control of the far-field pattern. In addition, by spreading the current density, which was concentrated at the periphery of the oxide confinement diameter, to the center, the occurrence of non-radiative recombination areas spreading from the periphery is suppressed, thereby improving the durability of the device.

[0065] In this embodiment, the diameter d2 of the tunnel junction layer 442 is 10 μm, and the oxide constriction layer 3 The diameter d1 of the semiconductor portion inside 06 (i.e., the portion through which current can flow, the non-oxidized portion) is 30 μm. Because the non-oxidized portion is the portion through which current can flow in the resonator portion 303, the diameter of the non-oxidized portion becomes the light-emitting diameter of the VCSEL. This is the same in this embodiment and in the following embodiments.

[0066] In this embodiment, as shown in Figures 2(a) and 2(b), the shape of the current density distribution flowing into the quantum well layer 340 is formed into a centrally convex shape, making it possible to control the far-field pattern. In the configuration of this embodiment, the values ​​of Jc / Je and Jmax / Jmin are 4.2. Since this embodiment is intended for short-term use, a value greater than 3.3 was selected as the value of Jmax / Jmin. On the other hand, if life characteristics are important, d2 can be set to, for example, 15 µm. In this case, the values ​​of Jc / Je and Jmax / Jmin are 2.4.

[0067] Furthermore, the second confinement structure is formed by providing a thin transparent conductive film 462 and a tunnel junction layer 442 on the second DBR 304. In addition, the tunnel junction layer has a carrier concentration of 10 19 This is a highly doped layer on the order of 1000 nm, and has low resistance. Therefore, compared to formation methods using ion implantation, the conductivity of the material that makes up the current path is low and it is thinner, so the voltage rise in the second confinement structure can be reduced by about one order of magnitude. Therefore, by using the element of this embodiment as a light source, it is possible to provide a distance measuring device that not only improves distance measurement accuracy and measurable distance, but also achieves miniaturization and weight reduction.

[0068] Example 2 A VCSEL 400 according to Example 2 will be described with reference to Fig. 4(a). Fig. 4(a) shows a cross-sectional view of the VCSEL 400. The VCSEL 400 has the same configuration as Example 1 from the back electrode 351 to the resonator unit 303, so the same numbers are used and the description will be omitted.

[0069] The main difference between Example 1 and this Example is that a p-type semiconductor layer 473 including an oxide constriction portion 406 is present on the resonator portion 303, and a tunnel junction layer 442 is disposed on a portion of the upper surface of the p-type semiconductor layer 473. An n-type GaAs layer 470 is disposed on the upper surfaces of the tunnel junction layer 442 and the p-type semiconductor layer 473, where the tunnel junction layer 442 is not present. The n-type GaAs layer 470 is realized by first growing a crystal up to the layer that will become the tunnel junction layer 442, then processing the tunnel junction layer 442 into a predetermined shape, and then growing a crystal of the n-type GaAs layer 470 again. An upper electrode 450 and a dielectric DBR 471 are disposed on the n-type GaAs layer 470.

[0070] In the first embodiment, the dimension of d2 was set to 10 μm or 15 μm. However, it is assumed that the dimension of d2 cannot be set to 15 μm or less due to process constraints or the like. In such a case, in order to increase Jc / Je and Jmax / Jmin, in this embodiment, the distance between the quantum well layer 340 and the tunnel junction layer 442, which is the second confinement structure, is set shorter than the distance set in the first embodiment, i.e., thinner than the thickness of the second DBR. The resulting reduced reflectivity can be compensated for by providing a third DBR 471.

[0071] Specifically, when the thickness of the p-type semiconductor layer 473 is set to 3 / 5 of that of the second DBR in Example 1, even if d2 is 15 μm, the values ​​of Jc / Je and Jmax / Jmin are 4.4.

[0072] The size of the third DBR 471 in the horizontal direction of the drawing must be optically large enough to function as a resonator above the active layer. In FIG. 4(a), the size of the third DBR 471 is smaller than the inner diameter of the upper ring electrode 450 and larger than d1, but this is not limited to this. The size of the third DBR 471 may be approximately the same as or larger than the inner diameter of the upper ring electrode 450, as long as it is configured to supply current to the upper ring electrode 450.

[0073] The p-type semiconductor layer 473 is Al 0.1 It is made of GaAs and has a 30 nm thick AlO .98 A GaAs layer is disposed. 0.98 During wafer processing after crystal growth, the GaAs layer is oxidized by steam oxidation, resulting in an oxidized constriction layer 406 .

[0074] The tunnel junction layer 442 has a carrier concentration of 5x10 19 cm -3 Highly doped p-type GaAs s layer and carrier concentration 1x10 19 cm -3 It consists of a heavily doped n-type GaAs layer. do.

[0075] The dielectric DBR 471 has a structure in which SiO2 and TiO2 are alternately laminated, and the optical film thickness of each is λc / 4. The number of pairs is adjusted appropriately so as to obtain a reflectance equivalent to that of the second DBR in Example 1.

[0076] FIG. 4(b) shows a modified example of this embodiment. While the example in which the tunnel junction layer 442 is disposed on the p-type semiconductor layer 473 has been described above, the present invention is not limited to this. As shown in FIG. 4(b), instead of the p-type semiconductor layer 473, a second DBR 483 made of a p-type semiconductor layer may be disposed on the resonator portion 303, and the tunnel junction layer 442 may be disposed thereon. The total thickness of the second DBR 483 is set to be approximately two-thirds the thickness of the second DBR 304 of Example 1.

[0077] In this modification, an oxide layer is disposed in the second DBR 483, and the periphery is partially oxidized to form an oxide constriction layer 406. A tunnel junction layer 442 is disposed on the upper DBR 483, and patterning is performed in the same manner as described above to form an n-type GaAs layer 470. A third DBR 481 made of a dielectric or semiconductor with a reflectance approximately one-third that of the upper DBR 304 of Example 1 is disposed above it. The DBR 481 has a layered structure in which multiple high-refractive-index layers and low-refractive-index layers with an optical film thickness of λc / 4 are stacked.

[0078] With this configuration, the distance between the highly doped tunnel junction layer and the active layer in the resonating portion can be made greater than that shown in FIG. 4(a), thereby making it possible to further reduce loss during resonance.

[0079] FIG. 4(c) shows a further variation of this embodiment. In FIG. 4(c), the second DBR 48 3, or on tunnel junction layer 442, a fourth DBR 490 made of an n-type semiconductor is disposed. Furthermore, only an upper ring electrode 450 is disposed on top of that. The upper DBR 483 made of a p-type semiconductor and the DBR 490 made of an n-type semiconductor are designed to act as the upper reflector of the resonator. This modification also achieves the same effects as those described above.

[0080] Example 3 A VCSEL 500 according to Example 3 will be described with reference to Fig. 5(a). Fig. 5(a) shows a cross-sectional view of the VCSEL 500. The VCSEL 500 has the same configuration as Example 1 from the lower common electrode 351 to the tunnel junction 442, so the same numbers are used and the description will be omitted.

[0081] The main difference between the first embodiment and the present embodiment is that a wiring electrode 650 is disposed on the second DBR 304. The wiring electrode 650 is not a transparent electrode but a so-called metal electrode, and is opaque to the emission wavelength of the VCSEL 500.

[0082] Fig. 5(b) is a top view of the VCSEL 500, illustrating the shape of the wiring electrode 650. Fig. 5(a) is a cross-sectional view taken along the line AA' in Fig. 5(b).

[0083] The wiring electrode 650 has a ring-shaped portion outside the mesa of the second DBR 304, from which the electrode extends to the tunnel junction layer 442 disposed on top of the upper DBR 304. The wiring electrode 650 is in ohmic contact with the tunnel junction layer 442. In other words, it is made of a material that is in ohmic contact with the highly doped n-type GaAs layer. Specifically, it has a two-layer structure with AuGe as the bottom layer and Au on top of that. An insulating film 651, separate from the insulating film 461, is provided below the wiring electrode 650. The function of the insulating film 651 will be explained later.

[0084] In this embodiment, the width of the wiring electrode 650 (top of the mesa) is 3 μm. In the VCSEL processing process, the wiring electrode 650 is formed by forming a mask using a lift-off method or photolithography, and then removing the area where the mask is not formed by etching. The minimum width of this formation process is typically about 3 μm or 5 μm. This differs significantly from the processing dimensions in silicon device processes because, in the VCSEL, the step between the mesa portion and its surrounding area is large, making it difficult to focus above and below the step during photolithography exposure, for example. Therefore, in this embodiment, the width is set to 3 μm from the perspective of making it as narrow as possible within the realistic range for mass production.

[0085] The portion of the wiring electrode 650 that is in contact with the tunnel junction layer 442 is 3 μm wide and 3 μm long. The diameter d1 of the opening in the oxidized constriction layer 306 is 30 μm (radius 15 μm), and the diameter d2 of the tunnel junction layer 442 is 15 μm (radius 7.5 μm). Therefore, the portion where the wiring electrode 650 and the light-emitting region (opening in the oxidized constriction layer 306) overlap in plan view is 10.5 μm long and 3 μm wide.

[0086] In this embodiment, the opaque wiring electrode 650 is disposed on the second DBR 304, which blocks a portion of the light emitted from directly below the wiring electrode 650. This has the disadvantage of reducing the light extraction efficiency. In this embodiment, 8.9% of the total area of ​​the light-emitting section is covered by the electrode 650.

[0087] On the other hand, materials called transparent electrodes such as ITO actually depend on the thickness and film formation method, but for example, a typical thickness of 100 nm often results in 10% or more light absorption at a wavelength of 940 nm. Since the area ratio covered is 8.9%, it is possible to achieve the same light extraction efficiency as a configuration in which the upper surface of the VCSEL is covered with an ITO film.

[0088] Furthermore, in this embodiment, in order to reduce the influence of a decrease in light extraction efficiency due to light blocking by the wiring electrode 650, an insulating film 651 is provided below the wiring electrode 650. The insulating film 651 is made of SiO2 and has a thickness of 162 nm. The thickness of the insulating film 651, in terms of optical film thickness, is ¼ of the oscillation wavelength of the VCSEL 500. The wiring electrode 650 made of metal is disposed on the insulating film 651, and the reflectance as seen from the resonator unit 303 is reduced to a degree that prevents the VCSEL 500 from oscillating. In this embodiment, the phase of the light reflected by the insulating film 651 and the wiring electrode 650 is designed to be shifted by π from the phase of the light reflected by the DBR 304, and the reflectance is designed to be lower than the reflectance of the DBR 304 alone.

[0089] As described above, by reducing the reflectance of the light-shielded portion and using a configuration that prevents laser oscillation of the VCSEL 500, this embodiment reduces the influence of the reduction in light extraction efficiency caused by light shielding by the wiring electrode 650. This will be described below.

[0090] When laser oscillation does not occur in the portion shielded by the wiring electrode 650 by disposing the wiring electrode 650 and insulating film 651 as described above, laser oscillation, in other words, carrier recombination due to stimulated emission, does not occur in this portion. Therefore, in the active layer directly below the wiring electrode 650, stimulated emission continues, resulting in a higher carrier density compared to the surrounding area, where the carrier recombination rate is higher. As a result, carriers diffuse to the surrounding area due to the difference in carrier density, and are converted into photons by stimulated emission recombination in the surrounding area. Photons generated in the surrounding area can be extracted outside the VCSEL 500 without the disadvantage of light shielding by the wiring electrode 650, and as a result, the disadvantage of reduced light extraction efficiency due to light shielding by the wiring electrode 650 can be reduced.

[0091] 5(a) shows a configuration in which the insulating film 651 is separated from the insulating film 461, but the insulating film 651 may cover the insulating film 461. Furthermore, since the insulating film 461 serves as a passivation for the mesa sidewalls from the edge of the upper mesa, it may be formed integrally with the insulating film 651 if it can be formed to the same thickness as the insulating film 651.

[0092] 5(b), the wiring electrodes 650 extend from two directions around the mesa toward the tunnel junction layer 442, but the present invention is not limited to this. The wiring electrodes 650 only need to extend from at least one direction. When multiple wiring electrodes 650 are extended, it is desirable to make the spacing between them as large as possible. For example, two electrodes are arranged at an angle of 180 degrees, and three electrodes are arranged at an angle of 120 degrees.

[0093] Furthermore, in this embodiment, a configuration having an insulator below the light-shielding portion is described as a configuration for reducing the reflectance of the light-shielded portion, but the present invention is not limited to this, and other configurations may be used as long as they are a method for reducing the reflectance of the light-shielded portion, such as removing a portion of the upper part of the upper DBR 304.

[0094] FIG. 5(c) shows a modified example of this embodiment. In this modified example, the wiring electrode 660 covers the entire periphery of the mesa and extends to the periphery of the upper mesa. In this case, the area of ​​the metal covering the mesa step is increased, and the entire periphery of the mesa is covered with metal, reducing the risk of metal breakage. Furthermore, by focusing the photolithography exposure on the upper mesa, it is possible to connect the tunnel junction 442 with a wiring electrode thinner than in the previous example, with respect to the wiring thickness arranged on the light emitting portion. This makes it possible to reduce the proportion of light blocked by the wiring electrode 660.

[0095] In this embodiment, if it is desired to increase the degree of lateral carrier diffusion in the tunnel junction 442 after current is supplied from the wiring electrodes 650 and 660 to the tunnel junction 442, the thickness of the highly doped n-type layer can be increased to a degree that does not cause light absorption problems. In this case, the increase in the thickness of the highly doped n-type layer is set so that its optical film thickness is an integer multiple of λc / 2. In other words, the thickness of the entire tunnel junction is set so that it is an integer multiple of λc / 2. Specifically, when λc is 940 nm, the thickness of the highly doped n-type layer is increased by 132 nm, making the total thickness of the highly doped n-type layer 222 nm, and the total thickness of the tunnel junction layer 442, including the p-type semiconductor layer, approximately 400 nm.

[0096] Even with this configuration, in forming the second current confinement structure, the layer configuration on the second DBR 304 becomes a tunnel junction layer 442 of about 440 nm at maximum, even considering the general film formation accuracy of ±10%. 19 It is a highly doped layer of the order of 10 ...

[0097] Example 4 A VCSEL 500 according to Example 6 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of the VCSEL 500. The VCSEL 500 is configured by laminating a GaAs substrate 301, a first DBR 302, a semiconductor resonator portion 303, a second DBR 504, and a tunnel junction layer 542 in this order.

[0098] The resonator portion 303, the second DBR 504, and the tunnel junction layer 542 are processed into a cylindrical mesa shape, and are covered with an insulating layer 561. An ITO layer 562 is formed on the insulating layer 561. The optical film thickness of the ITO layer 562 is λc / 2.

[0099] As shown in FIG. 6 , an insulating layer 561 with a partially removed central portion is provided on the upper surface of the tunnel junction layer 542, which has been processed into a mesa shape. Hereinafter, the portion where the insulating layer 561 is removed will be referred to as the insulating opening. The ITO layer 562 contacts the upper surface of the tunnel junction layer 542 through the insulating opening. In this embodiment, the insulating opening is circular. In this embodiment, carriers are supplied from the insulating opening through the tunnel junction layer 542. Therefore, the insulating layer 561 with the insulating opening in the ITO layer 562 and the tunnel junction layer 542 constitute a second current confinement section. The upper ring electrode 550 is in electrical contact with a portion of the ITO layer 562. The lower common electrode 351 is in ohmic contact with the rear surface of the GaAs substrate 501.

[0100] The tunnel junction layer 542 has a carrier concentration of 5x10 19 cm -3 Highly doped p-type Ga As layer 540 and carrier concentration 1x10 19 cm -3 Highly doped n-type GaAs layer 541 In this way, the tunnel junction layer has a carrier concentration of 1x10 18 cm -3Since two p-type semiconductor layers exceeding 1000 Ω are junctioned, it forms a so-called tunnel diode. Therefore, similar to the tunnel junction layer 442 in Examples 1 and 2, a current also flows in the reverse direction through a thin depletion layer generated at the pn interface by the tunnel effect.

[0101] 6, when the cross-sectional shape of insulating layer 561 is tapered so that it becomes thinner toward the center, the size of the second constriction structure can be defined as the distance d6 between its tip ends. In other words, d6 is the actual size of the current constriction caused by the second constriction structure.

[0102] In this embodiment, the tunnel junction layer 542 is not patterned but exists over the entire surface of the mesa, and therefore the preferred diameter d6 of the insulating opening and the diameter d5 of the non-oxidized portion are different from those in embodiments 1 and 2. The effect of this will be explained below.

[0103] In this embodiment, the diameter d6 of the insulating opening portion where the insulating layer 561 has been removed is 20 μm, and the diameter d5 of the non-oxidized portion inside the oxidized constriction layer 506 is 70 μm.

[0104] The effect of this will be explained based on the calculation results in Figure 7(a). In Figure 7(a), the horizontal axis represents the radial position in the non-oxidized area, the vertical axis represents the current density, and the numerical values ​​in the figure represent the diameter d6 of the insulating opening. Figure 7(a) shows the current density distribution when d5 is fixed at 70 μm and d6 is varied between 10 μm and 69 μm. Figure 7(a) shows that as long as d6 is up to 30 μm, the current density distribution maintains a convex shape in the center. It can also be seen that current can be injected up to the boundary between the oxidized and non-oxidized areas, that is, up to the position of 35 μm on the horizontal axis in Figure 7(a).

[0105] In Figure 7(b), the solid line shows the ratio of Jc / Je when d6 is changed while d5 is fixed at 70 μm. Figure 7(b) shows that when d6 is smaller than about 35 μm, Equation 3 is satisfied.

[0106] For comparison, the case of Example 1 is shown by a dotted line. The case of Example 1 shown here is when d1 is 70 μm in the structure of Example 1. Jmax / Jmin is omitted because it nearly matches Jc / Je when d6 or d2 is 30 μm or more.

[0107] By performing similar calculations, when d1 or d5 takes any value, it is possible to find the value of d2 or d6 that simultaneously satisfies Equation 3 and Equation 5. Table 1 lists the values ​​of d2 or d6 that simultaneously satisfy Equation 3 and Equation 5 when d1 or d5 is 30, 50, 70, or 100 μm. [Table 1]

[0108] From Table 1, in Example 1, when d1 is between 30 and 70 μm, the minimum of the preferable range of d2 is 4 μm, and when d1 is 50 μm, the maximum allowable range of d2 is 6 μm. On the other hand, in this example, when d5 is at least between 50 and 100 μm, the preferable range of d6 is at least 9 μm or more.

[0109] As described above, in this embodiment, the tunnel junction layer 542 is provided over the entire top of the mesa, and in particular, the n-type GaAs layer 541 in the tunnel junction layer 542 allows carriers to spread in a direction parallel to the substrate. Therefore, a desirable current density distribution can be achieved even if the light-emitting area is increased.

[0110] In this embodiment, the tunnel junction layer 542 is described as being located above the second DBR 504. However, instead of the high refractive index layer that is the top layer of the second DBR 504, the tunnel junction layer 542 may be located above the second DBR 504. A multi-layer may be disposed. In that case, the thickness is set so that the optical thickness of the tunnel junction layer is an odd multiple of λc / 4. In this embodiment, since carriers diffuse laterally in the n-type GaAs layer 541, this thickness must be set to a certain thickness. For example, the thickness can be set to 190 nm, and the optical thickness of the tunnel junction layer can be set to 3λc / 4.

[0111] In this embodiment, the tunnel junction layer 542 is provided over the entire top surface of the second DBR 304, but it is not necessary to provide the tunnel junction layer 542 at least in the peripheral portion of the mesa structure. For example, the tunnel junction layer 542 may be formed so that it includes the center of the mesa and has a diameter larger than d5, and so as to include the entire non-oxidized portion of the oxidized constriction layer 306 in plan view.

[0112] In this embodiment, it is possible to set the diameter of the non-oxidized portion larger than in the first embodiment, and therefore a light emitting device with higher output can be realized.

[0113] Here, for example, it is also possible to place the tunnel junction layer 542 between the resonator portion 303 and the upper DBR. However, such a configuration has the disadvantage that the distance between the highly doped tunnel junction layer and the active layer becomes shorter than in this embodiment, resulting in increased loss during resonance.

[0114] Specifically, for example, if there is 1% absorption at the tunnel junction, placing a tunnel junction layer between the resonator and the upper DBR means that 1% of the light emitted from the active layer will be absorbed, assuming that the light is 100%.

[0115] On the other hand, in a typical VCSEL design, the reflectivity of the upper DBR is generally set to about 99%. Therefore, if a tunnel junction layer is placed on the upper DBR, and the light emitted from the upper DBR (i.e., the light emitted from the active layer) is taken as 100%, then 1% of that 1%, i.e., 0.01% of the light emitted from the active layer, will be absorbed by the tunnel junction layer.

[0116] Generally, a VCSEL will cease to oscillate if the absorption increases by about 1%. Furthermore, because the upper DBR is n-type, the current confined by the insulating opening, which is the upper second confinement structure, spreads too much laterally, preventing a desirable current profile from being obtained in the active layer. For these reasons, it is preferable to locate the tunnel junction layer away from the resonator, as explained in this example.

[0117] Example 5 A VCSEL 700 according to Example 6 will be described with reference to Fig. 8. In this example, the thickness of the ITO layer is reduced to reduce light absorption in the ITO layer.

[0118] The description of this embodiment will be based on the above-described embodiment 1. The same components as those in embodiment 1 are given the same reference numerals and will not be described again.

[0119] In Example 1, if the absorption of the ITO layer is high and affects the oscillation and output of the VCSEL, it is possible to make the film thickness of the ITO layer thinner than λc / 2 and to place a single layer or multiple layers of a transparent insulator on top of it, as in this example.

[0120] In the VCSEL 700 described in this example, a tunnel junction layer 442 is provided at the center of the upper surface of the second DBR 304, which is processed into a mesa shape, and an ITO layer 762 is provided on top of that. Here, the film thickness of the ITO layer 762 is set to 100 nm. A transparent insulating film layer 763 (e.g., SiOx) is formed on top of that so that the optical film thickness of the ITO layer 762 and the transparent insulating film layer 763 combined is an integer multiple of λc / 2. A transparent insulating film layer 763 is formed on a part of the ITO layer 762. The upper ring electrode 750 is electrically connected to the part where 763 has been partially removed.

[0121] Here, if a decrease in reflectance at the insulating opening occurs due to deviation of the optical film thickness of the ITO layer 762 from λc / 2, multiple transparent insulating film layers may be further formed on the transparent insulating film layer 763. After the thickness of the transparent insulating film in contact with the ITO layer 762, combined with the ITO layer 762, is set to λc / 2, two types of layers with different refractive indexes are alternately stacked so that the optical film thickness is λc / 4, thereby making it possible to improve the reflectance at the insulating opening.

[0122] If a further transparent insulating film is formed on the transparent insulating film layer 763, openings similar to those in the transparent insulating film layer 763 are formed in these transparent insulating layers so that the upper ring electrode 750 and the ITO layer 762 are electrically connected.

[0123] According to this embodiment, in addition to the effects of Example 1, the absorption by ITO can be reduced, so that the luminous efficiency can be further improved. Also, it becomes possible to reduce the risk of oscillation not occurring due to a reduction in reflectance.

[0124] Although this embodiment has been described based on the first embodiment, the present invention is not limited to this and can be applied to other embodiments.

[0125] In this example, the thickness of the ITO layer 762 was set to 100 nm, but the thickness of the ITO layer can be made thin enough that the increase in resistance from the upper ring electrode to the tunnel junction is not a problem due to its electrical conductivity. On the other hand, considering the possibility of disconnection due to a step at the tunnel junction, it is preferable that the thickness be 10 nm or more.

[0126] Example 6 A VCSEL 800 according to Example 7 will be described with reference to Figure 9. Compared to Example 1, the VCSEL 800 further includes a third DBR 801 on the ITO layer 462. The third DBR can be made of a dielectric material such as SiOx, SiNx, or TiOx.

[0127] In the first embodiment, the size of d2 was set to 10 μm or 15 μm. However, it is conceivable that the size of d2 cannot be set to 15 μm or less due to process constraints, etc. In such a case, in order to increase the values ​​of Jc / Je and Jmax / Jmin, in this embodiment, the thickness of the second DBR 804 is set thinner than the thickness set in the first embodiment, and the resulting reduced reflectivity is compensated for by providing a third DBR.

[0128] Specifically, when the thickness of the second DBR 804 is reduced to 3 / 5 of that in Example 1, even if d2 is 15 μm, the values ​​of Jc / Je and Jmax / Jmin are 4.4.

[0129] The size of the third DBR 801 in the horizontal direction of the drawing must be optically large enough to function as a resonator above the active layer. In Fig. 9, the size of the third DBR 801 is smaller than the inner diameter of the upper ring electrode 450 and larger than d1, but this is not limiting. The size of the third DBR 801 may be approximately the same as or larger than the inner diameter of the upper ring electrode 450, as long as it is configured to supply current to the upper ring electrode 450.

[0130] In this embodiment, the thickness of the second DBR 804 is set to be thinner than in Example 1, but in order to obtain a desirable current density distribution, the thickness of the second DBR 804 may be set to be thicker than in Example 1. In that case, for example, one or more layers of the second DBR may be set to 3λc / 4.

[0131] In this embodiment, an example applied to the first embodiment has been described, but the present invention is not limited to this, and can be similarly applied to the third to sixth embodiments.

[0132] Example 7 A VCSEL 900 according to a seventh embodiment of the present invention will be described with reference to Figure 10. The VCSEL 900 differs from the first embodiment in that λc is set to 850 nm. Therefore, the optical film thickness of each layer in the first DBR 902 and the second DBR 904 is changed to λc / 4 (=212.5 nm). The composition and optical film thickness of the quantum well layer 940 and the resonator unit 903 are also adjusted as appropriate.

[0133] Specifically, the quantum well layer 940 is formed by stacking an 8-nm thick GaAs layer and an 8-nm thick Al layer. 0.3 In this embodiment, three quantum well layers are arranged in the cavity portion 903.

[0134] This makes it possible to provide a high-output semiconductor light-emitting device by suppressing the influence of absorption by the substrate, even for wavelengths in the 850 nm band, for which the substrate has high absorption and it is difficult to achieve high output with back-side emission.

[0135] This embodiment has a configuration in which the oscillation wavelength is changed from that of the first embodiment, but the example provided by the present invention can be similarly applied to any of the examples described in the second to seventh embodiments.

[0136] Example 8 A VCSEL array 1000 according to an eighth embodiment of the present invention will be described with reference to Figure 11. While the embodiments up to this point have been described with a single VCSEL light-emitting unit, the present invention is not limited to this and may be configured with multiple VCSEL light-emitting units.

[0137] As shown in Figure 11, the VCSEL array 1000 of this embodiment has a plurality of VCSELs 300 according to the first embodiment arranged in an array. A circle 910 represents the inner diameter of the upper ring electrode. A dashed-dotted line 911 indicates the light-emitting area, whose inner diameter is d1. The portion indicated by the dotted line is a pad portion 920 of the upper electrode.

[0138] As shown in Figure 11, multiple light-emitting points are connected to the same electrode, and the multiple light-emitting points emit light simultaneously. With this configuration, the output from the light-emitting element can be further increased.

[0139] Although this embodiment shows an example in which 16 light-emitting points are arranged in a 4 x 4 triangular lattice, the present invention is not limited to this, and the number of light-emitting points and the arrangement of the light-emitting points can be changed as appropriate depending on the application. Also, although an example in which a plurality of light-emitting points are driven simultaneously has been shown, the light-emitting points and their corresponding upper electrodes may be divided into a plurality of groups or individually depending on the application, and the timing of light emission may be changed.

[0140] Furthermore, although this example shows a configuration in which the VCSELs of Example 1 are arrayed, any of the VCSELs described in Examples 2 to 8 may be arrayed. By using VCSELs based on Example 4 to form an array, it is possible to set the diameter of the non-oxidized portion larger than when VCSELs based on Examples 1 to 3 are used, and therefore high output can be achieved in a smaller area when arrayed.

[0141] Example 9 12 shows a distance measuring device 2000 according to a ninth embodiment. Laser light detection and ranging (LiDAR) using EL as the light source 12, the distance measuring device 2000 is made up of an overall control unit 1010, a VCSEL driver 1020, a VCSEL 1030, a light-emitting side optical system 1040, a light-receiving side optical system 1060, a light-receiving image sensor 1070, and a distance data processing unit 1080.

[0142] In this embodiment, the VCSEL 1030 uses the VCSEL described in the first embodiment, but the present invention is not limited to this, and the VCSEL or VCSEL array described in the first to ninth embodiments can be applied as appropriate.

[0143] The VCSEL 1030 is configured by mounting the VCSEL described in the above embodiment in a package. The light-emitting side optical system 1040 and the light-receiving side optical system 1060 are configured as a single convex lens. The light receiving image sensor 1070 may be a single member or may be a lens group made up of a combination of multiple lenses. The light receiving image sensor 1070 is an image sensor in which SPAD (Single Photon Avalanche Diode) light sensors are arranged in a two-dimensional array.

[0144] The operation of the distance measuring device 2000 is outlined below. First, a drive signal is output from the overall control unit 1010 to the VCSEL driver 1020. Upon receiving the drive signal, the VCSEL driver 1020 injects a current of a predetermined value into the VCSEL 1030, causing the VCSEL 1030 to oscillate.

[0145] The laser light generated by the VCSEL 1030 passes through the light-emitting optical system 1040 and hits the measurement object 1200, and the light reflected by the measurement object 1200 passes through the light-receiving optical system 1060 and enters the light-receiving image sensor 1070. In this way, the reflected light of the light emitted from the VCSEL 1030 is detected by each pixel of the light-receiving image sensor 1070. The distance data processing unit 1080 only needs to be electrically connected to the light-receiving image sensor 1070. Therefore, the distance data processing unit 1080 may be disposed in the same package as the light-receiving image sensor 1070, or may be mounted in a separate package and electrically connected via a circuit board or the like.

[0146] The electrical signal pulses output from each pixel of the light-receiving image sensor 1070 are input to a distance data processing unit 1080. The distance data processing unit 1080 calculates distance information in the light propagation direction from the time (detection timing) of the electrical signal pulses output from each pixel of the light-receiving image sensor 1060, and generates and outputs three-dimensional information.

[0147] In this way, the distance measuring device 2000 can acquire and output three-dimensional information.

[0148] The distance measuring device 2000 can be applied to the automotive field, such as control to prevent collisions with other vehicles and automatic driving control to follow other vehicles. Furthermore, it can be used in moving bodies (moving devices) such as ships, aircraft, and industrial robots, and moving body detection systems. Furthermore, it can be widely applied to devices that use three-dimensional recognition of objects, including distance information.

[0149] The uses of 3D information are not limited to those mentioned above. For example, distance information may be used in image processing. When acquiring an image of real space and superimposing a virtual object on it, using 3D information of the real space allows the virtual object to be displayed seamlessly on the real world. In addition, by acquiring 3D information when acquiring an image, it is possible to correct the blurring effect based on the 3D information after shooting. [Explanation of symbols]

[0150] 101: Substrate, 102: First DBR (first reflector), 103: Resonator base 104: Second DBR (second reflector), 142: Tunnel junction layer

Claims

1. A semiconductor light emitting device having a structure in which a substrate, a first reflecting mirror, a resonator portion including an active layer, a second reflecting mirror, and a tunnel junction portion are stacked in this order, a first current confinement portion formed by an oxide confinement layer; a second current confinement portion including the tunnel junction portion; Including, a width d2 of the second current confinement portion is smaller than a width d1 of the first current confinement portion; A semiconductor light emitting device characterized by:

2. the tunnel junction is provided on a part of an upper surface of the second reflecting mirror, The width of the tunnel junction portion is the width d2 of the second current confinement portion. The semiconductor light emitting device according to claim 1 .

3. the tunnel junction portion is included in a non-oxidized portion inside the oxidized confinement layer of the first current confinement portion in a plan view; The semiconductor light emitting device according to claim 2 .

4. a transparent conductive layer is formed on the tunnel junction and on a portion of the top of the second reflecting mirror where the tunnel junction is not provided; The semiconductor light-emitting device according to claim 2 or 3.

5. A transparent insulating film is provided on the transparent conductive layer. The semiconductor light emitting device according to claim 4 .

6. the second reflecting mirror is made of a p-type semiconductor, an n-type semiconductor layer is formed on the tunnel junction and on a portion of the top of the second reflecting mirror where the tunnel junction is not provided; a third reflector is provided on the n-type semiconductor layer; The semiconductor light-emitting device according to claim 2 or 3.

7. the third reflecting mirror is formed of a semiconductor having a plurality of layers stacked thereon; The semiconductor light emitting device according to claim 6 .

8. the third reflecting mirror is formed of a dielectric material having a plurality of laminated layers; The semiconductor light emitting device according to claim 6 .

9. a fourth reflecting mirror is provided on the tunnel junction and on a top portion of the second reflecting mirror where the tunnel junction is not provided; The semiconductor light-emitting device according to claim 2 or 3.

10. a metal wiring electrically connected to the tunnel junction is provided on the second reflector and on a part of the tunnel junction; The semiconductor light-emitting device according to claim 2 or 3.

11. a portion of the second reflector below the metal wiring has a lower reflectance than the other portion; The semiconductor light emitting device according to claim 10 .

12. an insulating film is provided between the second reflector and the metal wiring, so that the reflectance of the second reflector below the metal wiring is lower than that of the other portion; The semiconductor light emitting device according to claim 11 .

13. The width d1 of the first current confinement portion is 30 μm ≦ d1 ≦ 70 μm The semiconductor light-emitting device according to claim 2 , which satisfies the following:

14. an insulating film having an opening formed on an upper surface of the tunnel junction; a transparent conductive film formed on the tunnel junction in the opening; Furthermore, The width of the opening is the width d2 of the second current confinement portion. The semiconductor light emitting device according to claim 1 .

15. A transparent insulating film is provided on the transparent conductive film. The semiconductor light emitting device according to claim 14 .

16. The width d1 of the first current confinement portion is 30 μm ≦ d1 ≦ 70 μm The semiconductor light-emitting element according to claim 14 or 15, which satisfies the following:

17. a fifth reflector formed of a dielectric multilayer film on the second reflector; The semiconductor light-emitting element according to any one of claims 2 to 5 and 10 to 15.

18. the second reflector is a p-type semiconductor; The semiconductor light-emitting device according to claim 1 .

19. The thickness t of the tunnel junction is 10nm≦t≦440nm The semiconductor light-emitting device according to claim 1 , which satisfies the following:

20. A plurality of semiconductor light-emitting elements according to any one of claims 1 to 19 are arranged side by side. A light emitting device comprising:

21. a light source including the semiconductor light-emitting element according to any one of claims 1 to 19; a sensor for detecting reflected light of light emitted from the light source; a processing unit that acquires distance information based on the detection timing of the reflected light; A distance measuring device comprising:

Images