Oscillator circuits, high-side switches, electronic devices, vehicles

Abstract

To provide an oscillator circuit less prone to cause erroneous operation, efficiency deterioration or the like.SOLUTION: An oscillator circuit 2 has: a plurality of transistors 2A to 2C configured to form a loop structure; a plurality of constant current sources 2F to 2H configured to respectively supply a plurality of drive currents IA to IC to each of first main electrodes of the plurality of transistors 2A to 2C; a capacitor 2J configured to be connected between either one control terminal and first main electrode of the plurality of transistors 2A to 2C; and output stages 2D and 2I configured to output a clock signal CLK by receiving input from a node voltage (for example, a node voltage VB) caused at either one of the first main electrodes of the plurality of transistors 2A to 2C.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to an oscillator circuit, and a high-side switch, an electronic device, and a vehicle that use the oscillator circuit. [Background technology]

[0002] Oscillator circuits are incorporated into various semiconductor devices (such as high-side switches).

[0003] As examples of the above-mentioned related art, Patent Documents 1 and 2 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-143416 [Patent Document 2] Japanese Patent Publication No. 2020-202438 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional oscillator circuits are generally composed of inverters, which raises concerns that a through current flowing through the inverter may cause fluctuations in the power supply potential or reference potential of the inverter, resulting in malfunctions and reduced efficiency.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide an oscillator circuit that is less likely to malfunction or deteriorate in efficiency, and a high-side switch, electronic device, and vehicle that use the oscillator circuit. [Means for solving the problem]

[0007] For example, the oscillator circuit disclosed in this specification includes a plurality of transistors configured to form a loop structure, a plurality of constant current sources configured to supply a plurality of drive currents to the first main electrodes of the plurality of transistors, respectively, a capacitor configured to be connected between the control terminal and the first main electrode of any one of the plurality of transistors, and an output stage configured to receive an input of a node voltage appearing at the first main electrode of any one of the plurality of transistors and output a clock signal.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0009] According to the invention disclosed in this specification, it is possible to provide an oscillator circuit that is less susceptible to malfunctions and deterioration in efficiency, as well as a high-side switch, electronic device, and vehicle that use the oscillator circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a high-side switch. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of an active clamp circuit. [Figure 3] FIG. 3 is a diagram illustrating a case where a DC power supply is normally connected to the high-side switch. [Figure 4] FIG. 4 is a diagram illustrating a case where a DC power supply is erroneously connected in reverse to the high-side switch. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a power supply reverse connection protection circuit. [Figure 6] FIG. 6 is a diagram illustrating an example of an active clamp operation. [Figure 7] FIG. 7 is a diagram illustrating a first configuration example of an oscillator circuit. [Figure 8]FIG. 8 is a diagram illustrating a second configuration example of the oscillation circuit. [Figure 9] FIG. 9 is a diagram showing the oscillation operation of the second configuration example. [Figure 10] FIG. 10 is an external view of the vehicle. DETAILED DESCRIPTION OF THE INVENTION

[0011] <High-side switch configuration example> The high-side switch 100 shown in FIG. 1 is a semiconductor integrated circuit device and includes multiple external pins (an input terminal IN, a power supply terminal VBB, an output terminal OUT, and a ground terminal GND) as means for establishing electrical connection with the outside of the device. The input terminal IN is an external pin for receiving an external input of a control signal from a CMOS logic IC or the like. The power supply terminal VBB is an external pin for receiving a supply voltage Vbb (e.g., 4.5 V to 18 V) from a DC power supply such as a battery. Note that multiple power supply terminals VBB may be provided in parallel (e.g., four pins in parallel) to allow a large current to flow. The output terminal OUT is an external pin to which a load (e.g., an engine control ECU [electronic control unit], an air conditioner, body equipment, etc.) is externally connected. The ground terminal GND is an external pin to which a ground voltage is applied.

[0012] The high-side switch 100 may also include external pins other than the input terminal IN, the power supply terminal VBB, the output terminal OUT, and the ground terminal GND (for example, an external pin for externally outputting a self-diagnosis signal indicating whether or not an abnormality has been detected in the high-side switch 100).

[0013] The high-side switch 100 includes an output transistor Q1, a constant voltage generating circuit 1, an oscillator circuit 2, a charge pump circuit 3, a gate control circuit 4, an active clamp circuit 5, an input circuit 6, a charging unit 7, a cutoff unit 8, a resistor R1, a blocking unit 9, and a limiting unit 10.

[0014] The high-side switch 100 also includes an internal power supply circuit (not shown). The internal power supply circuit generates a predetermined internal power supply voltage from the power supply voltage Vbb and supplies it to each component of the high-side switch 100. The internal power supply circuit is controlled to operate according to the logic level of an enable signal EN. More specifically, the internal power supply circuit is in an operating state when the enable signal EN is at a logic level for an enable state (e.g., a high level), and is in a stopped state when the enable signal EN is at a logic level for a disable state (e.g., a low level).

[0015] The high-side switch 100 also includes a protection circuit (not shown) that detects an abnormality in the high-side switch 100 (for example, an overcurrent state of the output current Io flowing through the output transistor Q1) and generates an abnormality protection signal according to the detection result.

[0016] The output transistor Q1 is a power transistor provided between the power supply terminal VBB and the output terminal OUT. The output transistor Q1 has a body diode. The output transistor Q1 is, for example, an enhancement-type N-channel MOS transistor, and its drain is connected to the power supply terminal VBB, and its source and back gate are connected to the output terminal OUT.

[0017] The constant voltage generating circuit 1 is provided between the power supply terminal VBB and the ground terminal GND, and generates a high voltage VH (≈ power supply voltage Vbb) corresponding to the power supply voltage Vbb, and a low voltage VL (≈ Vbb - REF) that is lower than the high voltage VH by a constant voltage REF (e.g., 5 V), and supplies these to the oscillation circuit 2 and the charge pump circuit 3. The constant voltage generating circuit 1 is controlled to operate according to the logic levels of an enable signal EN and an abnormality protection signal. More specifically, the constant voltage generating circuit 1 is in an operating state when the enable signal EN is at a logic level for enabling (e.g., high level) or when the abnormality protection signal is at a logic level for when an abnormality is not detected (e.g., high level), and is in a stopped state when the enable signal EN is at a logic level for disabling (e.g., low level) or when the abnormality protection signal is at a logic level for when an abnormality is detected (e.g., low level).

[0018] The constant voltage generating circuit 1 is composed of, for example, a current source 1A, an enhancement type P-channel MOS transistor 1B (hereinafter abbreviated as "transistor 1B"), a Zener diode 1C, a diode 1D, a negative voltage protection circuit 1E, a current mirror circuit 1F, and an enhancement type N-channel MOS transistor 1G (hereinafter abbreviated as "transistor 1G").

[0019] An internal power supply voltage is applied to one end of current source 1A, and a current is output from the other end of current source 1A to current mirror circuit 1F. The source and back gate of transistor 1B are connected to power supply terminal VBB. The drain of transistor 1B is connected to the cathode of Zener diode 1C, negative voltage protection circuit 1E, oscillator circuit 2, and charge pump circuit 3. Transistor 1B is on when no abnormality is detected by the protection circuit, and is off when an abnormality is detected by the protection circuit.

[0020] The anode of the Zener diode 1C is connected to the anode of the diode 1D. The cathode of the diode 1D is connected to the oscillation circuit 2 and the charge pump circuit 3. The cathode of the diode 1D is also connected to the current mirror circuit 1F via the negative voltage protection circuit 1E.

[0021] The negative voltage protection circuit 1E cuts off the current path from the ground terminal GND to the output terminal OUT when the output terminal OUT is at a negative voltage. The negative voltage protection circuit 1E may have a configuration similar to that of the cutoff unit 8. An example configuration of the cutoff unit 8 will be described later.

[0022] The current mirror circuit 1F absorbs a mirror current corresponding to the current output from the current source 1A from the transistor 1B, the Zener diode 1C, the diode 1D, and the negative voltage protection circuit 1E.

[0023] The drain of transistor 1G is connected to the connection node between current source 1A and current mirror circuit 1F, and the source and back gate of transistor 1G are connected to the connection node between current mirror circuit 1F and cutoff unit 8. An enable signal EN is supplied to the gate of transistor 1G. When the enable signal EN is disabled, the current mirror circuit 1F does not output a mirror current (sink current).

[0024] The oscillator circuit 2 operates by receiving a high voltage VH and a low voltage VL, and generates a clock signal CLK of a predetermined frequency and outputs it to the charge pump circuit 3. The clock signal CLK is a square wave signal that is pulse-driven between the high voltage VH and the low voltage VL.

[0025] The charge pump circuit 3 operates by receiving a high voltage VH and a low voltage VL, and by driving a flying capacitor using a clock signal CLK, generates a boosted voltage VCP higher than the power supply voltage Vbb and supplies it to the gate control circuit 4 and the blocking unit 9.

[0026] The gate control circuit 4 is provided between the application terminal of the boost voltage VCP and the output terminal OUT (= application terminal of the output voltage Vout), and generates a gate voltage VG and outputs it to the gate of the output transistor Q1. The gate voltage VG is at a high level (=VCP) when no abnormality is detected by the protection circuit, and at a low level (=Vout) when an abnormality is detected by the protection circuit.

[0027] The active clamp circuit 5 is connected between the power supply terminal VBB and the gate of the output transistor Q1. In applications where an inductive load is connected to the output terminal OUT, when the output transistor Q1 is switched from on to off, the output terminal OUT becomes a negative voltage due to the back electromotive force of the inductive load. For this reason, the active clamp circuit 5 is provided for energy absorption. The active clamp voltage, represented as Vbb - (Vclp + Vgs), should be set to, for example, 48 V (where Vbb is the power supply voltage, Vclp is the negative clamp voltage of the output terminal OUT, and Vgs is the gate-source voltage of the output transistor Q1).

[0028] As shown in FIG. 2, the active clamp circuit 5 is composed of an enhancement-type N-channel MOS transistor 5A (hereinafter referred to as "transistor 5A"), a Zener diode 5B, a diode 5C, and a resistor 5D. The drain of the transistor 5A is connected to the power supply terminal VBB. The source of the transistor 5A is connected to the gate of the output transistor Q1. The back gate of the transistor 5A is connected to the output terminal OUT. The cathode of the Zener diode 5B is connected to the power supply terminal VBB. The anode of the Zener diode 5B is connected to the anode of the diode 5C. The cathode of the diode 5C is connected to the gate of the transistor 5A and one end of the resistor 5D. The other end of the resistor 5D is connected to the gate of the output transistor Q1.

[0029] The input circuit 6 is a Schmitt trigger that receives a control signal input from an input terminal IN and generates an enable signal EN.

[0030] When the DC power supply 200 is connected to the high-side switch 100 in the correct orientation, the positive electrode of the DC power supply 200 is connected to the power supply terminal VBB, as shown in Fig. 3. A load 300 is connected to the output terminal OUT, and the ground voltage is applied to the ground terminal GND without connecting an external element such as a resistor. In the connection state shown in Fig. 3, the power supply voltage Vbb becomes higher than the ground voltage, and a positive bias voltage is applied between the power supply terminal VBB and the ground terminal GND.

[0031] On the other hand, if the DC power supply 200 is connected to the high-side switch 100 in the wrong direction (reverse direction), the positive electrode of the DC power supply 200 is connected to the ground terminal GND, as shown in Fig. 4. Note that the load 300 is connected to the output terminal OUT, and the ground voltage is applied to the power supply terminal VBB without connecting an external element such as a resistor. In the connection state shown in Fig. 4, the power supply voltage Vbb becomes lower than the ground voltage, and a reverse bias voltage is applied between the power supply terminal VBB and the ground terminal GND.

[0032] The charging section 7 and the cutoff section 8 are provided to prevent breakdown when a reverse bias voltage is applied between the power supply terminal VBB and the ground terminal GND.

[0033] The charging unit 7 charges the gate of the output transistor Q1 when the power supply voltage Vbb is lower than the ground voltage. This turns on the output transistor Q1 when the power supply voltage Vbb is lower than the ground voltage, reducing the power consumption and heat generation of the output transistor Q1. In other words, it is possible to prevent the output transistor Q1 from being destroyed by heat generation when the power supply voltage Vbb is lower than the ground voltage.

[0034] For example, a resistor 7A provided between the ground terminal GND and the gate of the output transistor Q1 can be used as the charging unit 7. The resistor 7A functions as a pull-down resistor when the power supply voltage Vbb is higher than the ground voltage, but has a resistance value (e.g., 500 kΩ) that does not affect the control of the output transistor Q1 by the gate control circuit 4.

[0035] The cutoff unit 8 is a power supply reverse connection protection circuit that cuts off the current path from the ground terminal GND to the power supply terminal VBB when the power supply voltage Vbb is lower than the ground voltage. This prevents the high-side switch 100 from being damaged by a current flowing from the ground terminal GND to the power supply terminal VBB through a parasitic diode in the high-side switch 100, even without connecting an external element such as a resistor or diode to the ground terminal GND.

[0036] The cutoff unit 8 is provided between the constant voltage generating circuit 1 and the ground terminal GND. The cutoff unit 8 is also connected to the power supply terminal VBB. More specifically, the cutoff unit 8 is connected to the power supply terminal VBB via a resistor R1.

[0037] As shown in FIG. 5, the cutoff unit 8 is composed of an enhancement type N-channel MOS transistor 8A (hereinafter abbreviated as "transistor 8A"), an enhancement type N-channel MOS transistor 8B (hereinafter abbreviated as "transistor 8B"), and a depletion type N-channel MOS transistor 8C (hereinafter abbreviated as "transistor 8C"), for example.

[0038] The gate of transistor 8A is connected to the power supply terminal VBB. More specifically, the gate of transistor 8A is connected to the power supply terminal VBB via resistor R1. The drain of transistor 8A is connected to the ground terminal GND. In addition, the gate of transistor 8A is connected to one end of the constant voltage generating circuit 1. More specifically, the gate of transistor 8A is connected to one end of the constant voltage generating circuit 1 via resistor R1. The source of transistor 8A is connected to the drain of transistor 8C.

[0039] The source of transistor 8A and the drain of transistor 8C are connected to the other end of the constant voltage generating circuit 1. The back gate of transistor 8A is connected to the drain and back gate of transistor 8B and to the gate, source, and back gate of transistor 8C. The gate of transistor 8B is connected to the power supply terminal VBB. More specifically, the gate of transistor 8B is connected to the power supply terminal VBB via a resistor R1. The gate of transistor 8B is also connected to one end of the constant voltage generating circuit 1. More specifically, the gate of transistor 8B is connected to one end of the constant voltage generating circuit 1 via a resistor R1. The source of transistor 8B is connected to the ground terminal GND.

[0040] 5, when the power supply voltage Vbb is higher than the ground voltage, the gate voltage of transistor 8A becomes equal to or higher than a predetermined voltage (=drain voltage+threshold voltage Vth), turning on transistor 8B. As a result, the back gate of transistor 8A has the same potential as the drain, turning on transistor 8A (the source and drain are shorted).

[0041] 5, when the power supply voltage Vbb is lower than the ground voltage, the gate voltage of transistor 8A falls below a predetermined voltage, turning off transistor 8B. Then, transistor 8C brings the back gate of transistor 8A to the same potential as the source, turning off transistor 8A.

[0042] 5, either transistor 8B or 8C connected to the back gate of transistor 8A is selectively turned on depending on the bias direction of the voltage applied between the power supply terminal VBB and the ground terminal GND. When a reverse bias voltage is applied between the power supply terminal VBB and the ground terminal GND, transistor 8C is selectively turned on and transistor 8A is turned off. This cuts off the current path from the ground terminal GND side (the drain side of transistor 8A) to the power supply terminal VBB side (the source side of transistor 8A).

[0043] When the power supply voltage Vbb is lower than the ground voltage, the blocking unit 9 blocks current from flowing from the charging unit 7 into the gate control circuit 4. This improves the reliability of charging the gate of the output transistor Q1 by the charging unit 7 when the power supply voltage Vbb is lower than the ground voltage.

[0044] The blocking unit 9 can be, for example, a depletion-type N-channel transistor 9A (hereinafter abbreviated as "transistor 9A") provided between the gate control circuit 4 and the charging unit 7 and limiting unit 10. When the power supply voltage Vbb is lower than the ground voltage, the transistor 9A is turned off. On the other hand, when the power supply voltage Vbb is higher than the ground voltage, the transistor 9A is turned on.

[0045] The limiting unit 10 defines an upper limit for the voltage applied to the gate of the output transistor Q1 when the power supply voltage Vbb is lower than the ground voltage, thereby preventing the gate voltage of the output transistor Q1 from rising excessively due to charging by the charging unit 7.

[0046] The limiting unit 10 is composed of, for example, an enhancement type P-channel transistor 10A (hereinafter abbreviated as "transistor 10A") and a Zener diode 10B. The gate, source, and back gate of the transistor 10A are connected to the power supply terminal VBB. The drain of the transistor 10A is connected to the anode of the Zener diode 10B. The cathode of the Zener diode 10B is connected to the gate of the output transistor Q1.

[0047] When the power supply voltage Vbb is lower than the ground voltage, the voltage between the power supply terminal VBB and the gate of the output transistor Q1 is clamped to the sum of the forward voltage of the PN junction between the drain and backgate of the transistor 10A and the Zener voltage of the Zener diode 10B. On the other hand, when the power supply voltage Vbb is higher than the ground voltage, the transistor 10A is turned off. Therefore, when the power supply voltage Vbb is higher than the ground voltage, the limiting unit 10 does not specify an upper limit for the voltage applied to the gate of the output transistor Q1.

[0048] <Active clamp operation> 6 is a timing chart showing an example of the active clamp operation by the active clamp circuit 5, which depicts, from top to bottom, the enable signal EN, the output voltage Vo (solid line), the gate voltage VG (dashed line), and the output current Io. Note that in this diagram, it is assumed that an inductive load is connected as the load 300.

[0049] At time t11, when the enable signal EN rises to high level (= the logical level when turning on the output transistor Q1), the gate voltage VG rises to high level, the output transistor Q1 turns on, the output current Io starts to flow, and the output voltage Vo rises to near the power supply voltage Vbb.

[0050] Then, at time t12, when the enable signal EN falls to low level (= the logic level when the output transistor Q1 is turned off), the gate voltage VG falls to low level, and the output transistor Q1 is turned off. At this time, the inductive load (such as a coil or solenoid) connected as the load 300 continues to pass the output current Iout until it releases the energy stored during the on-period of the output transistor Q1. As a result, the output voltage Vo drops to a negative voltage lower than the ground voltage GND.

[0051] However, when the output voltage Vo becomes negative, the output transistor Q1 turns on (is no longer fully on) due to the action of the active clamp circuit 5, and the output current Io is discharged via the output transistor Q1. Therefore, the output voltage Vo is limited to a lower limit voltage Vbb-α (for example, Vbb-50V) that is lower than the power supply voltage Vbb by a predetermined value α (=VZ+VF+Vgs1+Vgs2).

[0052] In the formula expressing the above predetermined value α, Vgs1 and Vgs2 are the gate-source voltages of the output transistor Q1 and the transistor 5A, respectively, VZ is the breakdown voltage of the Zener diode 5B, and VF is the forward drop voltage of the diode 5C.

[0053] In this way, when the control signal (and therefore the enable signal EN) input to the input terminal IN is set to high level (= the logic level for turning off the output transistor Q1), current flows through the active clamp circuit 5, and the output voltage Vo applied to the output terminal OUT becomes a negative voltage. At this time, the active clamp circuit 5 limits the output voltage Vo based on the power supply voltage Vbb, thereby limiting the drain-source voltage Vds (= Vbb - Vo) of the output transistor Q1 to a predetermined clamp voltage Vclp (= α) or less.

[0054] The clamp voltage Vclp must be set to a voltage value higher than the maximum rated value of the power supply voltage Vbb and lower than the drain-source breakdown voltage of the output transistor Q1. Furthermore, the higher the clamp voltage Vclp, the better the performance of the high-side switch 100. However, in consideration of the active clamp withstand capability E (mJ), a lower clamp voltage Vclp is better.

[0055] The active clamp withstand capability E (mJ) of the high-side switch 100 is determined from the clamp voltage Vclp (V), the output current Io (A), and the discharge time t (ms) by the following equation:

[0056] E(J)=Vclp(V)×Io(A)×t(ms)

[0057] <Considerations regarding application of negative voltage> As described above, the high-side switch 100 has an N-channel MOS transistor as the output transistor Q1. Therefore, to reliably turn on the output transistor Q1, it is necessary to generate a boosted voltage VCP (>Vbb) using the charge pump circuit 3. Furthermore, to drive the charge pump circuit 3, it is necessary to generate a clock signal CLK of a predetermined frequency using the oscillation circuit 2.

[0058] The high-side switch 100 is also provided with an active clamp circuit 5 as a means for absorbing the back electromotive force of the load 300 (particularly an inductive load) when the output transistor Q1 transitions to the off state. While the drain-source voltage of the output transistor Q1 is clamped by the action of the active clamp circuit 5, the output terminal OUT becomes a negative voltage lower than the ground voltage. At this time, the internal circuit (such as the charge pump described above) that is electrically connected to the output terminal OUT is also configured to become a negative voltage.

[0059] <Oscillation circuit (first configuration example)> 7 is a diagram showing a first configuration example of an oscillator circuit (corresponding to a comparative example to be compared with the second configuration example described later). The oscillator circuit 2 of the first configuration example includes inverters 2a and 2b, resistors 2c and 2d, and a capacitor 2e.

[0060] The input terminal of the inverter 2a is connected to a first terminal of the resistor 2c. The output terminal of the inverter 2a and a first terminal of the resistor 2d are both connected to the input terminal of the inverter 2b. The output terminal of the inverter 2b and a first terminal of the capacitor 2e are both connected to the output terminal of the clock signal CLK. The second terminals of the resistors 2c, 2d, and capacitor 2e are all connected in common.

[0061] As described above, the oscillator circuit 2 of the first configuration example is configured using inverters 2a and 2b. Therefore, there is a concern that the power supply potential or reference potential (e.g., the aforementioned high voltage VH or low voltage VL) of the inverters 2a and 2b may fluctuate due to the through current flowing through the inverters 2a and 2b, causing malfunctions and a decrease in efficiency. Below, we propose a novel second configuration example that can eliminate such concerns.

[0062] <Oscillation circuit (second configuration example)> 8 is a diagram showing a second configuration example of the oscillator circuit. The oscillator circuit 2 of the second configuration example includes NMOSFETs 2A to 2D, PMOSFETs 2E to 2I, and a capacitor 2J.

[0063] The source and back gate of each of the PMOSFETs 2E to 2I are connected to a terminal to which a high voltage VH is applied. The gate of each of the PMOSFETs 2E to 2I is connected to the drain of the PMOSFET 2E (= the input terminal to which the reference current I0 is applied). The drain of each of the PMOSFETs 2F to 2I is connected to the drain of each of the NMOSFETs 2A to 2D (= the application terminal to which the node voltages VA to VD are applied). The drain of the NMOSFET 2A is connected to the gate of the NMOSFET 2B. The drain of the NMOSFET 2B is connected to the gates of the NMOSFETs 2C and 2D. The drain of the NMOSFET 2C is connected to the gate of the NMOSFET 2A. The drain of the NMOSFET 2D is connected to the output terminal of the clock signal CLK. The source and back gate of each of the NMOSFETs 2A to 2D are connected to a terminal to which a low voltage VL is applied. A capacitor 2J is connected between the gate and drain of the NMOSFET 2A.

[0064] In the oscillator circuit 2 of the second configuration example, the NMOSFETs 2A to 2C correspond to a plurality of transistors configured to form a loop structure. Focusing on the adjacent NMOSFETs 2A and 2B, the drain (corresponding to the first main electrode) of the NMOSFET 2A in the preceding stage is connected to the gate (corresponding to the control terminal) of the NMOSFET 2B in the succeeding stage. Focusing on the adjacent NMOSFETs 2B and 2C, the drain of the NMOSFET 2B in the preceding stage is connected to the gate of the NMOSFET 2B in the succeeding stage. The drain of the NMOSFET 2C in the final stage is connected to the gate of the NMOSFET 2A in the preceding stage.

[0065] On the other hand, PMOSFETs 2F to 2H are connected between the application terminal of the high voltage VH and the drains of NMOSFETs 2A to 2C, respectively, and correspond to a plurality of constant current sources configured to supply drive currents I A to I C to the drains of NMOSFETs 2A to 2C, respectively. The sources (corresponding to second main electrodes) of NMOSFETs 2A to 2C are all connected to the application terminal of the low voltage VL.

[0066] Furthermore, NMOSFET 2D and PMOSFET 2I correspond to an output stage configured to receive an input of the node voltage VB appearing at the drain of NMOSFET 2B and output a clock signal CLK.

[0067] The PMOSFETs 2E-2I function as a current mirror configured to generate multiple drive currents IA-ID from a single reference current I0. That is, the drive currents IA-ID are each proportional to the reference current I0. The drive currents IA-ID may have the same current value or different current values.

[0068] FIG. 9 is a diagram showing the oscillation operation of the second configuration example, depicting node voltages VA to VD in order from the top.

[0069] First, let us focus on the charging phase of capacitor 2J (times t21 to t22). When node voltage VB becomes higher than the on-threshold of NMOSFET 2C, NMOSFET 2C turns on. Therefore, node voltage VC falls to approximately low voltage VL, and NMOSFET 2A turns off.

[0070] As a result, a current path is established from the application terminal of the high voltage VH through PMOSFET 2F, capacitor 2J, and NMOSFET 2C to the application terminal of the low voltage VL, and charging of capacitor 2J by the drive current IA begins. As capacitor 2J charges, the node voltage VA gradually rises at a slope that corresponds to the current value of the drive current IA and the capacitance value of capacitor 2J.

[0071] At this time, NMOSFET 2B switches between on and off states depending on the node voltage VA. Specifically, when the node voltage VA is lower than the on-threshold of NMOSFET 2B, NMOSFET 2B remains off. As a result, the node voltage VB continues its upward trend and rises to almost the high voltage VH.

[0072] Subsequently, as capacitor 2J continues to charge, the node voltage VA rises above the on-threshold of NMOSFET 2B, switching NMOSFET 2B to the on state. As a result, the node voltage VB falls to approximately the low voltage VL, switching NMOSFET 2C to the off state. Note that as NMOSFET 2C transitions to the off state, the path through which drive current IA flows is cut off, causing the node voltage VA to jump up.

[0073] Furthermore, the NMOSFET 2D that forms the output stage of the oscillator circuit 2 switches between on and off states in the same manner as the NMOSFET 2C. Therefore, when the NMOSFET 2C is in the off state, the NMOSFET 2D is also in the off state, and the node voltage VD falls to approximately the low voltage VL. In other words, during the charging period of the capacitor 2J (=time t21 to t22), the clock signal CLK is at low level (=VL).

[0074] Unlike the NMOSFET 2A, the gates of the NMOSFETs 2B to 2D are each provided with only a small gate capacitance, and therefore the rise and fall of each of the node voltages VB to VD are steeper than the rise and fall of the node voltage VA.

[0075] Next, we will focus on the discharge phase of capacitor 2J (times t22 to t23). When node voltage VB falls below the on-threshold of NMOSFET 2C, NMOSFET 2C enters the off state. At this time, node voltage VC rises to near the on-threshold of NMOSFET 2A (a voltage value slightly higher than the on-threshold). Therefore, NMOSFET 2A enters a half-on state (a state in the saturation region where it is on).

[0076] As a result, a current path is established from the node to which the high voltage VH is applied via PMOSFET2H, capacitor 2J, and NMOSFET2A to the node to which the low voltage VL is applied, and the drive current IC begins discharging capacitor 2J (which can be understood as charging in the opposite direction to the charging phase). As capacitor 2J discharges, the node voltage VA gradually decreases at a rate proportional to the value of drive current IC and the capacitance of capacitor 2J. In particular, because NMOSFET 2A operates in the saturation region, capacitor 2J is discharged at a constant current.

[0077] At this time, NMOSFET 2B switches between on and off states depending on the node voltage VA. Specifically, when the node voltage VA is higher than the on-threshold of NMOSFET 2B, NMOSFET 2B remains on. As a result, the node voltage VB maintains its downward trend and falls to approximately the low voltage VL.

[0078] Subsequently, as capacitor 2J discharges, the node voltage VA falls below the on-threshold of NMOSFET 2B, switching NMOSFET 2B to the off state. As a result, the node voltage VB begins to rise again. When the node voltage VB rises above the on-threshold of NMOSFET 2C, NMOSFET 2C switches to the on state. As NMOSFET 2C turns on, the node voltage VC falls to nearly the low voltage VL, and in accordance with the law of conservation of charge for capacitor 2J, the node voltage VA also falls sharply.

[0079] As mentioned above, the NMOSFET 2D that forms the output stage of the oscillator circuit 2 switches between on and off states in the same manner as the NMOSFET 2C. Therefore, when the NMOSFET 2C is on, the NMOSFET 2D is also on, causing the node voltage VD to rise to approximately the high voltage VH. That is, during the discharge period of the capacitor 2J (times t22 to t23), the clock signal CLK is at a high level (=VH).

[0080] The above series of operations is repeated after time t23, thereby generating a clock signal CLK of a predetermined frequency.

[0081] In particular, in the oscillator circuit 2 of this configuration example, constant drive currents I A to I C are supplied to the NMOSFETs 2A to 2C that form a loop structure, respectively. Therefore, compared to the first configuration example (FIG. 7) using the inverters 2a and 2b, the oscillator circuit 2 is less susceptible to the effects of fluctuations in the power supply potential or reference potential (e.g., the aforementioned high voltage VH or low voltage VL) that accompany the through current of the inverters 2a and 2b. This makes it possible to eliminate malfunctions and efficiency degradation of the oscillator circuit 2, and furthermore, to reduce the duty deviation of the clock signal CLK.

[0082] Additionally, in the active clamp operation described above, not only the output terminal OUT but also the series of circuits that control the gate of the output transistor Q1 become negative voltages. Therefore, the constant voltage generating circuit 1 described above is provided with a P-channel transistor 1B and a negative voltage protection circuit 1E to prevent any problems even if the series of circuits described above become negative voltages.

[0083] The circuit provided between this transistor 1B and negative voltage protection circuit 1E must be driven at a current equal to or lower than the current limited by current mirror circuit 1F. In the first configuration example (Fig. 7) mentioned above, if a through current flows through inverters 2a and 2b due to logic switching or the like, the necessary current cannot be supplied, causing fluctuations in the high voltage VH or low voltage VL (and ultimately a drop in the voltage between VH and VL), which can lead to malfunction.

[0084] In view of this, it is desirable to adopt the current-driven second configuration example (FIG. 8) as the circuit configuration of the oscillator circuit 2, rather than the voltage-driven first configuration example (FIG. 7).

[0085] The application of the oscillator circuit 2 is not limited to the high-side switch 100, but can be widely applied to various applications that require a clock signal CLK.

[0086] <Examples of high-side switch applications> 10 is an external view showing an example of a vehicle configuration. The vehicle X of this example configuration is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving a power supply voltage Vbb from the battery.

[0087] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0088] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0089] The electronic device X11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0090] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0091] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0092] The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0093] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0094] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0095] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0096] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0097] The high-side switch 100 described above can be incorporated into any of the electronic devices X11 to X18.

[0098] <Summary> The various embodiments described above will be generally described below.

[0099] For example, the oscillator circuit disclosed in this specification has a configuration (first configuration) including a plurality of transistors configured to form a loop structure, a plurality of constant current sources configured to supply a plurality of drive currents to the first main electrodes of the plurality of transistors, respectively, a capacitor configured to be connected between the control terminal and the first main electrode of any one of the plurality of transistors, and an output stage configured to receive an input of a node voltage appearing at the first main electrode of any one of the plurality of transistors and output a clock signal.

[0100] In the oscillator circuit according to the first configuration, the plurality of constant current sources may be configured as current mirrors configured to generate the plurality of drive currents from a single reference current (second configuration).

[0101] Furthermore, the oscillation circuit according to the first or second configuration may be configured (third configuration) such that, in the loop structure, the first main electrode of the transistor in the first stage among the plurality of transistors is connected to the control terminal of the transistor in the second stage, and the first main electrode of the transistor in the last stage is connected to the control terminal of the transistor in the first stage.

[0102] a constant voltage generation circuit configured to generate a high voltage corresponding to the power supply voltage and a low voltage that is lower than the high voltage by a constant voltage; an oscillator circuit according to any one of the first to third configurations configured to operate upon receiving the high voltage and the low voltage and to generate the clock signal; a charge pump circuit configured to operate upon receiving the high voltage and the low voltage and to drive a flying capacitor using the clock signal to generate a boosted voltage that is higher than the power supply voltage; a control circuit connected between an application terminal of the boosted voltage and the output terminal and configured to generate a drive voltage and output it to a control terminal of the output transistor; and an active clamp circuit connected between the power supply terminal and the control terminal of the output transistor (fourth configuration).

[0103] Furthermore, in the high-side switch according to the fourth configuration, the plurality of constant current sources may be connected between the high voltage application terminal and the first main electrodes of the plurality of transistors, and the second main electrodes of the plurality of transistors may all be connected to the low voltage application terminal (fifth configuration).

[0104] Furthermore, the high-side switch according to the fourth or fifth configuration may be configured (sixth configuration) to further include a charging unit configured to charge the control terminal of the output transistor when the power supply terminal is at a lower potential than the ground terminal.

[0105] Furthermore, the high-side switch according to the sixth configuration may be configured (seventh configuration) to further include a blocking unit configured to prevent current from flowing from the charging unit to the control circuit when the power supply terminal is at a lower potential than the ground terminal.

[0106] Furthermore, the high-side switch according to any one of the fourth to seventh configurations may be configured (eighth configuration) to further include a cutoff unit configured to cut off the current path from the ground terminal to the power supply terminal when the power supply terminal is at a lower potential than the ground terminal.

[0107] Furthermore, the high-side switch according to any one of the fourth to eighth configurations may be configured (ninth configuration) to further include a limiting unit configured to define an upper limit of the drive voltage applied to the control terminal of the output transistor when the power supply terminal is at a lower potential than the ground terminal.

[0108] Furthermore, the high-side switch according to any one of the fourth to ninth configurations may be configured (tenth configuration) such that when the control signal is set to a logic level that turns off the output transistor, the voltage applied to the output terminal becomes a negative voltage and a current flows through the active clamp circuit.

[0109] Furthermore, the electronic device disclosed in this specification has a configuration (eleventh configuration) including a high-side switch having any one of the fourth to tenth configurations.

[0110] In addition, the vehicle disclosed in this specification is configured (12th configuration) to include a battery and an electronic device according to the 11th configuration configured to operate by receiving power from the battery.

[0111] <Other variations> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0112] GND Ground terminal IN input terminal OUT output terminal Q1 Output transistor R1 Resistor VBB power supply terminal 1 Constant voltage generation circuit 1A current source 1B Enhancement type P-channel MOS transistor 1C Zener diode 1D diode 1E Negative voltage protection circuit 1F Current mirror circuit 1G Enhancement-type N-channel MOS transistor 2 Oscillator Circuit 2a, 2b inverter 2c, 2d resistance 2e capacitor 2A~2D NMOSFET 2E~2I PMOSFET 2J capacitor 3 Charge pump circuit 4 Gate control circuit 5 Active clamp circuit 5A enhancement type N-channel MOS transistor 5B Zener diode 5C diode 5D Resistor 6 Input circuit 7 Live parts 7A resistance 8 Breaker 8A enhancement type N-channel MOS transistor 8B Enhancement type N-channel MOS transistor 8C Depletion-type N-channel MOS transistor 9 Blocking part 9A Depletion-type N-channel transistor 10 Restrictions 10A Enhancement P-channel transistor 10B Zener diode 100 High-side switch

Claims

1. A power supply terminal configured to apply a power supply voltage; an output terminal configured to have an external load connected thereto; a ground terminal configured to receive a ground voltage; an output transistor configured to be connected between the power supply terminal and the output terminal; a constant voltage generating circuit configured to generate a high voltage corresponding to the power supply voltage and a low voltage that is lower than the high voltage by a constant voltage; an oscillator circuit configured to receive the high voltage and the low voltage to operate and generate a clock signal; a charge pump circuit configured to operate by receiving the high voltage and the low voltage and to generate a boosted voltage higher than the power supply voltage by driving a flying capacitor using the clock signal; a control circuit connected between the boosted voltage application terminal and the output terminal, configured to generate a drive voltage and output the drive voltage to the control terminal of the output transistor; an active clamp circuit configured to be connected between the power supply terminal and a control end of the output transistor; A high-side switch comprising: The constant voltage generating circuit comprises: a transistor connected between the power supply terminal and the high voltage application terminal, configured to be turned on when no abnormality is detected and turned off when an abnormality is detected; a constant voltage generating element connected between the high voltage application terminal and the low voltage application terminal to generate the constant voltage; a negative voltage protection circuit connected between the low voltage application terminal and the ground terminal and configured to cut off a current path from the ground terminal to the low voltage application terminal when the output terminal is at a negative voltage; a current mirror circuit configured to limit a current flowing through the transistor, the constant voltage generating element, and the negative voltage protection circuit; and The oscillator circuit comprises: a negative voltage protection circuit; It is necessary to drive the current mirror circuit at a current limited by the current mirror circuit or less. a plurality of transistors configured to form a loop structure; a plurality of constant current sources configured to respectively supply a plurality of drive currents to the first main electrodes of the plurality of transistors; a capacitor connected between a control terminal of any one of the plurality of transistors and a first main electrode; an output stage configured to receive an input of a node voltage appearing at a first main electrode of any one of the plurality of transistors and output the clock signal; A high-side switch having a

2. The high-side switch of claim 1 , wherein the plurality of constant current sources are current mirrors configured to generate the plurality of drive currents from a single reference current.

3. 3. The high-side switch according to claim 1, wherein in the loop structure, among the plurality of transistors, a first main electrode of a transistor in a front stage is connected to a control terminal of a transistor in a rear stage, and a first main electrode of a transistor in a last stage is connected to the control terminal of a transistor in a frontmost stage.

4. 4. The high-side switch according to claim 1, wherein the plurality of constant current sources are connected between the application terminal of the high voltage and a first main electrode of each of the plurality of transistors, and second main electrodes of each of the plurality of transistors are all connected to the application terminal of the low voltage.

5. 5. The high-side switch according to claim 1, further comprising a charging unit configured to charge a control terminal of the output transistor when the power supply terminal is at a lower potential than the ground terminal.

6. The high-side switch according to claim 5 , further comprising a blocking unit configured to block current from flowing from the charging unit to the control circuit when the power supply terminal is at a lower potential than the ground terminal.

7. 7. The high-side switch according to claim 1, further comprising a cutoff unit configured to cut off a current path from the ground terminal to the power supply terminal when the power supply terminal is at a lower potential than the ground terminal.

8. The high-side switch according to any one of claims 1 to 7, further comprising a limiting unit configured to define an upper limit of the drive voltage applied to the control end of the output transistor when the power supply terminal is at a lower potential than the ground terminal.

9. 9. The high-side switch according to claim 1, wherein when the control signal is set to a logic level for turning off the output transistor, the voltage applied to the output terminal becomes a negative voltage and a current flows in the active clamp circuit.

10. An electronic device comprising the high-side switch according to any one of claims 1 to 9.

11. A vehicle comprising: a battery; and the electronic device according to claim 10 configured to operate by receiving power from the battery.

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