Dry backside and bevel edge cleaning of photoresist

Abstract

Dry backside and bevel edge cleaning is performed without exposure to plasma to remove unwanted photoresist material from the substrate. The substrate is supported on a substrate support and elevated by a minimum contact area (MCA) support to allow etch gas access to the backside of the substrate. A gas distributor delivers a curtain gas to the front side of the substrate to protect the photoresist material on the front side. An etch gas delivery source delivers a first etch gas flow to the backside, and one or more peripheral gas inlets deliver a second etch gas flow to the periphery of the front side and around the bevel edge. A radiant heat source is positioned below the substrate to heat the substrate.

Description

[Background technology]

[0001] [Incorporated by reference] A PCT Request Form is being filed contemporaneously herewith as part of the present application. Each application to which this application claims benefit or priority as identified in the contemporaneously filed PCT Request Form is hereby incorporated by reference in its entirety for all purposes.

[0002] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process that involves photolithography. Generally, this process involves depositing materials onto a wafer and patterning the materials via lithographic techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. The steps of a typical photolithography process known in the art include preparing a substrate; applying photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern; rendering the exposed areas of the photoresist somewhat soluble in a developer; developing by applying a developer to remove either the exposed or unexposed areas of the photoresist; and subsequently processing, such as by etching or material deposition, to create features in the areas of the substrate where the photoresist was removed.

[0003] The evolution of semiconductor design has been driven by the need for and ability to create smaller and smaller features on semiconductor substrate materials. This technological advance has been characterized in "Moore's Law" as the doubling of transistor density in high-density integrated circuits every two years. In fact, chip design and manufacturing have advanced so much that modern microprocessors can contain billions of transistors and other circuit features on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or smaller, and in some cases less than 10 nm.

[0004] One challenge in the fabrication of devices with such small features is the ability to reliably and reproducibly generate photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. A unique problem arises because this light has a wavelength significantly larger than the desired size of the features to be created on the semiconductor substrate. Achieving feature sizes smaller than the wavelength of this light requires the use of complex resolution enhancement techniques, such as multiple patterning. Therefore, there has been considerable interest and research effort in developing photolithography techniques that use shorter wavelength light, such as extreme ultraviolet radiation (EUV), having a wavelength of 10 nm to 15 nm, e.g., 13.5 nm.

[0005] However, EUV photolithography processes can present challenges, including low power output and light loss during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential drawbacks when used in EUV lithography, particularly in that they have low absorption coefficients in the EUV region, which can lead to blurring or line edge roughness due to diffusion of photoactivated species. Furthermore, to provide the etch resistance required for patterning the underlying device layers, small features patterned in conventional CAR materials can result in high aspect ratios that risk pattern collapse. Therefore, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0006] The background art description provided herein is intended to generally present the context of the present technology. The inventor's work to the extent described in this background art section, and aspects of the present specification that may not otherwise qualify as prior art at the time of filing, are not admitted, expressly or impliedly, to be prior art to the present technology. Summary of the Invention

[0007] Provided herein is an apparatus for performing bevel edge and backside cleaning of a substrate. The apparatus includes a processing chamber, a substrate support for supporting the substrate in the processing chamber, a plurality of minimum contact area (MCA) supports configured to extend from the substrate support to contact a backside of the substrate, a gas distributor above the substrate support, the gas distributor having one or more central gas inlets for directing a curtain gas flow toward a center of a frontside of the substrate, an etch gas delivery source below the substrate support for directing a first etch gas flow toward the backside of the substrate, and a radiant heat source below the substrate support.

[0008] In some implementations, the gas distributor further includes one or more peripheral gas inlets for directing a second etch gas flow toward a periphery of the front surface of the substrate. In some implementations, a first gap separating the one or more peripheral gas inlets from the front surface of the substrate is larger than a second gap separating the one or more central gas inlets from the front surface of the substrate. In some implementations, the gas distributor includes a modular ring for the one or more peripheral gas inlets, the modular ring configured to adjust the spacing of the one or more peripheral gas inlets from the front surface of the substrate. In some implementations, the substrate support includes a carrier ring including an annular body for supporting the substrate. In some implementations, the carrier ring is configured to shift or rotate the positions of multiple MCA supports for supporting the substrate at different contact points on the backside of the substrate. In some implementations, the multiple MCA supports are configured to contact areas of the backside of the substrate that have little or no photoresist deposits. In some implementations, a plurality of MCA supports are configured to position the substrate above the substrate supports to permit a first etch gas flow across the backside of the substrate. In some implementations, the plurality of MCA supports include a first set of MCA supports and a second set of MCA supports, each of the first set of MCA supports and the second set of MCA supports being extendable / retractable to support the substrate. In some implementations, the etch gas delivery source has holes through the radiant heat source or holes disposed outside the radiant heat source. In some implementations, the apparatus further includes one or more heaters above the substrate coupled to the gas distributor. In some implementations, the apparatus further includes one or more sensors in the processing chamber, the one or more sensors configured to detect the presence of film deposits on a bevel edge and a backside of the substrate.In some implementations, the apparatus further comprises a controller configured with instructions for performing bevel edge and backside cleaning of the substrate, the instructions including code for providing the substrate in the processing chamber, wherein the substrate includes photoresist material deposited on the front surface, bevel edge, and backside of the substrate; extending the MCA support to lift the substrate above the substrate support; heating the substrate to an elevated temperature using the radiant heat source, wherein the elevated temperature is between about 20°C and about 170°C; introducing the first etch gas flow to the backside of the substrate; introducing the curtain gas flow to the center of the front surface of the substrate; and introducing a second etch gas flow to a periphery of the front surface of the substrate, wherein the first etch gas flow and the second etch gas flow remove at least the photoresist material from the bevel edge and backside of the substrate. In some implementations, the etch gas of the first etch gas flow and the second etch gas flow includes a hydrogen halide, hydrogen gas, and a halide gas, or boron trichloride, and the photoresist material includes an EUV resist material. In some implementations, the etch gas of the first etch gas flow and the second etch gas flow includes an oxidizing gas, and the photoresist material includes a carbon-based material. In some implementations, the etch gas of the first etch gas flow and the second etch gas flow includes a fluorine-containing gas or a chlorine-containing gas, and the photoresist material includes a silicon-based material. In some implementations, the curtain gas of the curtain gas flow includes nitrogen (N), oxygen (O), water (H), argon (Ar), helium (He), xenon (Xe), or neon (Ne). In some implementations, the controller is further configured with instructions including code for performing a post-application bake on the photoresist material by heating the substrate to a desired temperature in the same processing chamber to remove the EUV photoresist material from the bevel edge and backside of the substrate.In some implementations, the controller is further configured with instructions including code for purging the processing chamber with a purge gas after removing the photoresist material from the bevel edge and backside of the substrate. In some implementations, the controller is further configured with instructions including code for dry-depositing the photoresist material on the front surface, bevel edge, and backside of the substrate, where the deposition occurs in the same processing chamber as removing the photoresist material from the bevel edge and backside of the substrate.

[0009] Also provided herein is a method for performing bevel edge and backside cleaning of a substrate, the method comprising: providing a substrate on a substrate support in a process chamber, the substrate having photoresist material on a front surface, a bevel edge, and a backside of the substrate, the substrate being elevated above the substrate support to allow gas flow across the backside of the substrate; heating the substrate to an elevated temperature, the elevated temperature being between about 20° C. and about 170° C.; flowing a curtain gas onto a center of the front side of the substrate; and flowing an etch gas onto the backside of the substrate, the etch gas removing at least the photoresist material on the bevel edge and the backside of the substrate.

[0010] In some implementations, flowing an etch gas to the backside of the substrate includes: introducing a first etch gas flow to the backside of the substrate; and introducing a second etch gas flow to a periphery of the front side of the substrate. In some implementations, the first etch gas flow is flowed across the backside of the substrate, and the second etch gas flow is flowed along the front side of the substrate and the periphery of the bevel edge of the substrate, and the curtain gas restricts the etch gas flow to a center of the front side of the substrate. In some implementations, the first etch gas flow is introduced from one or more bottom gas inlets below a substrate support, and the second etch gas flow is introduced from one or more peripheral gas inlets of a gas distributor above a substrate support. In some implementations, a curtain gas is flowed from one or more central gas inlets of a gas distributor, and a first gap separating one or more peripheral gas inlets from a front surface of the substrate is larger than a second gap separating the one or more central gas inlets from the front surface of the substrate. In some implementations, the substrate is heated to the elevated temperature using a radiative heat source below the substrate support. In some implementations, the method further includes lifting the substrate above the substrate support using multiple MCA supports to create a gap between the substrate support and a backside of the substrate. In some implementations, the etch gas includes a hydrogen halide, hydrogen gas, and a halide gas, or boron trichloride, and the photoresist material includes an EUV resist material. In some implementations, the etch gas includes an oxidizing gas, and the photoresist material includes a carbon-based material. In some implementations, the etch gas includes a fluorine-based gas or a chlorine-based gas, and the photoresist material includes a silicon-based material. In some implementations, the curtain gas includes nitrogen (N), oxygen (O), water (H2O), argon (Ar), helium (He), xenon (Xe), or neon (Ne). In some implementations, the photoresist material includes an organometallic oxide material.In some implementations, the method further comprises dry-depositing the photoresist material on the front surface, bevel edge, and back surface of the substrate, where the deposition occurs in the same processing chamber as removing the photoresist material from the bevel edge and back surface of the substrate. In some implementations, the method further comprises performing a post-application bake on the photoresist material by heating the substrate to a desired temperature in the same processing chamber to remove the photoresist material from the bevel edge and back surface of the substrate. In some implementations, the method further comprises purging the processing chamber with a purge gas after removing the photoresist material from the bevel edge and back surface of the substrate. [Brief explanation of the drawings]

[0011] [Figure 1] 1 presents a flow diagram of an exemplary method for depositing and developing photoresist according to some embodiments.

[0012] [Figure 2A] 1A-1D show cross-sectional schematic views of various processing stages of conventional backside and bevel edge cleaning. [Figure 2B] 1A-1D show cross-sectional schematic views of various processing stages of conventional backside and bevel edge cleaning. [Figure 2C] 1A-1D show cross-sectional schematic views of various processing stages of conventional backside and bevel edge cleaning. [Figure 2D] 1A-1D show cross-sectional schematic views of various processing stages of conventional backside and bevel edge cleaning.

[0013] [Figure 3A] 1A-1D illustrate cross-sectional schematic views of various processing stages for dry backside and bevel edge cleaning of photoresist, according to some embodiments. [Figure 3B] 1A-1D illustrate cross-sectional schematic views of various processing stages for dry backside and bevel edge cleaning of photoresist, according to some embodiments. [Figure 3C]1A-1D illustrate cross-sectional schematic views of various processing stages for dry backside and bevel edge cleaning of photoresist, according to some embodiments.

[0014] [Figure 4] 1 shows a schematic diagram of a processing chamber for performing dry backside and bevel edge cleaning according to some embodiments.

[0015] [Figure 5A] 1 illustrates a perspective view of a carrier ring for supporting a substrate in a processing chamber according to some embodiments.

[0016] [Figure 5B] 1 shows a cross-sectional schematic view of a carrier ring supporting and contacting the backside of a substrate according to some embodiments.

[0017] [Figure 6] 1 illustrates a schematic diagram of an exemplary process station for maintaining a low pressure environment suitable for performing backside and bevel edge cleaning operations, according to some embodiments.

[0018] [Figure 7] 1 shows a schematic diagram of an exemplary multi-station processing tool suitable for performing the various development, cleaning, rework, descum, and smoothing operations described herein.

[0019] [Figure 8] 1 shows a cross-sectional schematic view of an exemplary inductively coupled plasma apparatus for carrying out certain embodiments and operations described herein.

[0020] [Figure 9] 1 illustrates a semiconductor process cluster tool architecture with a vacuum integrated deposition and patterning module interfaced with a vacuum transfer module suitable for carrying out the processes described herein. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present disclosure relates generally to the field of semiconductor processing. In particular aspects, the present disclosure is directed to processes and apparatus for cleaning photoresist (e.g., EUV-sensitive metal and / or metal oxide-containing photoresist) to remove unintentional photoresist deposited on the backside and bevel edge of a substrate, for example, in the context of photoresist patterning.

[0022] Reference will be made in detail herein to certain embodiments of the present disclosure. Examples of certain embodiments are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with these certain embodiments, it will be understood that it is not intended to limit the disclosure to such specific embodiments. Rather, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure. [introduction]

[0023] Patterning of thin films in semiconductor processing is often a critical step in the fabrication of semiconductors. Patterning involves lithography. In traditional photolithography, such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a light-sensitive photoresist, which causes a chemical reaction in the photoresist that removes certain portions of the photoresist to form the pattern after development.

[0024] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and beyond. At the 16 nm node, for example, the width of a typical via or line in a damascene structure is typically no greater than about 30 nm. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0025] Extreme ultraviolet (EUV) lithography can extend lithography techniques by moving to smaller imaging source wavelengths than are achievable using conventional photolithography methods. EUV sources at approximately 10-20 nm, or 11-14 nm wavelengths, e.g., 13.5 nm, can be used for advanced lithography tools, also called scanners. EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, and therefore works in a vacuum.

[0026] EUV lithography uses a patterned EUV resist to form a mask used in etching the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) produced by a liquid-based spin-on technique. An alternative to CAR is a directly photopatternable metal oxide-containing film, such as those described in U.S. Patent Application Publications US2017 / 0102612, US2016 / 021660, and US2016 / 0116839, available from Inpria of Corvallis, Oregon, the disclosures of at least those photopatternable metal oxide-containing films of which are incorporated herein by reference. Such films may be produced by spin-on techniques or dry deposition. Metal oxide-containing films can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere, providing sub-30 nm patterning resolution, as described, for example, in U.S. Pat. No. 9,996,004, entitled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARD MASKS," issued June 12, 2018, and / or International Patent Application No. PCT / US2019 / 31618, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," filed May 9, 2019, which disclosures relating to at least the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks are incorporated herein by reference. Generally, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist according to the photopattern to form a mask.

[0027] While this disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it should also be understood that it is applicable to other next-generation lithography techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and under development, the most important radiation source for such lithography is DUV (deep-UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-rays, which formally include EUV in the lower energy range of the X-ray range, and electron beams, which can cover a wide energy range. The specific methods may depend on the specific materials and applications used in the semiconductor substrate and ultimate semiconductor device. Therefore, the methods described herein are merely exemplary of methods and materials that may be used in the present technology.

[0028] Directly photopatternable EUV resists may be composed of or include metals and / or metal oxides mixed within an organic component. Metals / metal oxides hold great promise in that they can enhance EUV photon absorption, generate secondary electrons, and / or exhibit increased etch selectivity relative to the underlying film stack and device layers.

[0029] During application of a photoresist film (e.g., an EUV photoresist film) to a substrate, either by conventional wet, e.g., spin-on, processing, or dry deposition, some unintentional deposition of resist material on the wafer backside and / or bevel edge can occur. This backside and bevel edge deposition can cause downstream processing issues, including contamination of patterning (scanner) and development tools. High concentrations of metal from the unintentional metal-containing EUV resist material on the backside and / or bevel edge region of the wafer can cause an increased risk of metal release during downstream processing (e.g., EUV scanning, development). Such contamination can be detrimental to the performance of patterning and development tools as well as to films deposited on the front side of the wafer. Traditionally, removal of this backside and bevel edge deposition is accomplished by wet cleaning techniques.

[0030] The current state-of-the-art method for cleaning spin-coated metal-organic photoresists is by wet cleaning. Edge bead removal (EBR) is performed on a wet track on both the front and back sides of the wafer. Nozzles are positioned over the edge of the wafer on both the front and back sides, and a solvent is dispensed while the wafer is spinning. The organic solvent (e.g., PGME, PGMEA, 2-heptanone) dissolves the photoresist on the edge and cleans the bevel edge area. If the backside is contaminated, the wafer must go to a separate wet cleaning station for backside cleaning. For spin coating, the wafer area in contact with the chuck is typically kept clean, and a separate backside clean is not always used. Additional cleans, such as diluted hydrofluoric acid (dHF), diluted hydrochloric acid (dHCl), diluted sulfuric acid, or Standard Clean 1 (SC-1), may be necessary to reduce metal contamination. A backside scrub is typically performed before entering the EUV scanner.

[0031] The solvents used in wet cleaning processes inherently have high costs for both acquisition and disposal. Such solvents can be harmful to the environment and current health concerns. Wet cleaning processes can be limited by the uniformity of EUV resist material removal on the bevel edge region. Due to surface tension and vapor concerns, this removal is often wavy and does not result in clean removal of the EUV resist material on the bevel edge region. Furthermore, backsplash using organic solvents can create defects on the front surface of the wafer. This wet cleaning process is typically performed in a stand-alone tool / chamber, and therefore, the wafer must be transferred between tools / chambers after deposition. This can result in contamination of the tool / chamber used in the backside and / or bevel edge cleaning. [Backside and bevel edge cleaning]

[0032] The present disclosure provides dry backside and bevel edge cleaning of unwanted materials from a substrate. The dry backside and bevel edge cleaning is limited to specific areas to ensure material removal from the backside and bevel edge regions without film degradation on the front side of the substrate. In some embodiments, the unwanted material includes EUV resist material deposited on the backside and bevel edge regions of the substrate. In some embodiments, the unwanted material includes a silicon-based film or a carbon-based film. The dry backside and bevel edge cleaning is performed using an etch gas. The etch gas may be hydrogen gas, a hydrogen halide, hydrogen gas and a halide gas, or boron trichloride. The processing chamber may include a substrate support having a plurality of minimum contact area (MCA) supports that elevate the substrate to allow the etch gas to access the backside of the substrate. The substrate support may be a carrier ring. The etch gas may be delivered from below the substrate support in a first etch gas flow. A gas distributor may deliver a curtain gas to the center of the front side of the substrate to limit the etch gas from reaching the center of the front side. The gas distributor may also deliver etch gas to the periphery of the front surface of the substrate in the second etch gas flow. A heat source, such as a radiant heat source, may be applied to the substrate during the dry backside and bevel edge cleaning. The radiant heat source may be positioned below the substrate support. The backside cleaning and bevel edge cleaning are both performed in the same processing chamber. In some embodiments, the deposition operation and the dry backside and bevel edge cleaning are performed in the same processing chamber. In some embodiments, the post-application bake (PAB) and the dry backside and bevel edge cleaning are performed in the same processing chamber. Tool / chamber integration in a single chamber increases throughput, reduces costs, and reduces the possibility of contamination that would otherwise occur during transfer.

[0033] 1 presents a flow diagram of an exemplary method for depositing and developing photoresist according to some embodiments. The operations of process 100 may be performed in a different order and / or with different, fewer, or additional operations. One or more operations of process 100 may be performed using an apparatus described in any one of FIGS. 6-9. In some embodiments, the operations of process 100 may be implemented, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0034] At block 102 of process 100, a layer of photoresist is deposited, which can be either a dry deposition process, such as an evaporation process, or a wet process, such as a spin-on deposition process.

[0035] The photoresist may be a metal-containing EUV resist. The EUV-sensitive metal or metal oxide-containing film may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process has been demonstrated to be applicable to both commercially spin-coatable formulations (e.g., those available from Inpria Corp., Corvallis, Oregon) and formulations applied using dry vacuum deposition techniques, as further described below, for organotin oxide-based EUV photoresist compositions. While the photoresists described in this disclosure are often described as metal-containing EUV resist materials, it is understood that the process operations of this disclosure may be applied to any other films, such as silicon-based or carbon-based films.

[0036] The semiconductor substrate may have any material composition suitable for photolithography processing, particularly for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer on which features having an irregular surface topography ("underlying features") are created. As referred to herein, a "surface" is a surface onto which a film of the present disclosure will be deposited or exposed to EUV during processing. The underlying features may include areas from which material has been removed (e.g., by etching) or areas from which material has been added (e.g., by deposition) during processing prior to performing the methods of the present disclosure. Such pre-processing may include the methods of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0037] EUV-sensitive thin films can be deposited on semiconductor substrates, and such films can act as resists for subsequent EUV lithography and processing. Such EUV-sensitive thin films include materials that, upon exposure to EUV, undergo changes such as the loss of bulky pendant substituents bonded to metal atoms in low-density M-OH-rich materials, allowing their crosslinking into denser M-OH-bonded metal oxide materials. Through EUV patterning, areas of the film are created that have altered physical or chemical properties relative to unexposed areas. These properties can be exploited in subsequent processing, such as to dissolve either the unexposed or exposed areas or to selectively deposit materials onto either the exposed or unexposed areas. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under conditions under which such subsequent processing is performed. For example, material removal can be achieved by exploiting differences in the film's chemical composition, density, and crosslinking. Removal can be by wet or dry processes, as further described below.

[0038] In various embodiments, the thin film is an organometallic material, such as an organotin material including tin oxide, or other metal oxide material / moiety. The organometallic compound can be created by the vapor-phase reaction of an organometallic precursor with a counter-reactant. In various embodiments, the organometallic compound is formed through mixing specific combinations of organometallic precursors with bulky alkyl or fluoroalkyl groups and a counter-reactant, and polymerizing this mixture in the vapor phase to produce a low-density EUV-sensitive material that deposits on the semiconductor substrate.

[0039] In various embodiments, the organometallic precursors contain at least one alkyl group on each metal atom that can survive vapor phase reactions, but other ligands or ions coordinated to the metal atom can be replaced by counter reactants. M a R b L c (Formula 1) M is an element with a high patterning radiation absorption cross section, and R is C n H 2n+1 and the like, preferably n=1-6, L is a ligand, ion, or other moiety reactive with a counter reactant, and a≧1; b≧1; and c≧1.

[0040] In various embodiments, M is 1x10 7 cm 2 / mol. M may be, for example, selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, iodine, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R may be, for example, a compound of the formula C n F x H (2n+1)and may be fluorinated. In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R may be selected from the group consisting of methyl, ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is readily displaced by a counter reactant to generate an M-OH moiety, such as a moiety selected from the group consisting of an amine (dialkylamino, monoalkylamino, etc.), an alkoxy, a carboxylate, a halogen, and mixtures thereof.

[0041] The organometallic precursor can be any of a wide variety of candidate metal organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and analogous alkyl(tris)t-butoxy, such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0042] Counter reactants have the ability to replace reactive moieties, ligands, or ions (e.g., L in Formula 1 above) to link at least two metal atoms via a chemical bond. Counter reactants can include water, peroxides (e.g., hydrogen peroxide), di- or polyhydroxy alcohols, fluorinated di- or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the counter reactant reacts with the organometallic precursor by forming oxygen bridges between adjacent metal atoms. Other potential counter reactants include hydrogen sulfide and hydrogen disulfide, which can bridge metal atoms via sulfur bridges.

[0043] The thin film may include optional materials in addition to the organometallic precursor and counter-reactant to modify the chemical or physical properties of the film, such as to modify the film's sensitivity to EUV or to increase its etch resistance. Such optional materials may be introduced, such as by doping during vapor phase formation, before deposition on the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, a mild remote H plasma may be introduced to replace some Sn-L bonds with Sn-H, which can increase the reactivity of the resist under EUV.

[0044] In various embodiments, EUV-patternable films are created and deposited on semiconductor substrates using deposition equipment and processes known in the art. In such processes, polymerized organometallic materials are formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as discontinuous ALD-like processes in which the metal precursor and counter-reactant are separated either temporally or spatially.

[0045] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant to form a polymerized organometallic material and depositing the organometallic material on the surface of a semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one counter-reactant is included in the vapor stream. As will be appreciated by those skilled in the art, the mixing and deposition aspects of the process can occur simultaneously in a substantially continuous process.

[0046] In an exemplary continuous CVD process, two or more gas streams of organometallic precursor and counter-reactant sources in separate inlet paths are introduced into a deposition chamber of a CVD apparatus, where they mix and react in the vapor phase to form a coagulated polymeric material (e.g., via metal-oxygen-metal bond formation). The streams may be introduced, for example, using separate inlets or a dual-plenum showerhead. The apparatus is configured so that the organometallic precursor and counter-reactant streams mix within the chamber, and the organometallic precursor and counter-reactant react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of this technology, it is believed that the products of such vapor-phase reactions have a heavier molecular weight as metal atoms are crosslinked by the counter-reactant, and subsequently condense or otherwise deposit on a semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of a dense network, producing a smooth, amorphous, low-density film.

[0047] CVD processes are typically carried out at reduced pressures, such as between 10 mTorr (1.33 Pa) and 10 Torr (133.32 Pa). In some embodiments, the process is carried out at between 0.5 and 2 Torr (66.66 and 266.64 Pa). In some embodiments, the temperature of the semiconductor substrate is at or below the temperature of the reactant streams. For example, the substrate temperature can be between 0°C and 250°C, or between ambient temperature (e.g., 23°C) and 150°C. In various processes, deposition of polymerized organometallic material onto the substrate occurs at a rate inversely proportional to the surface temperature.

[0048] In some embodiments, EUV patternable films are created and deposited on semiconductor substrates using wet deposition equipment and processes among those known in the art, for example, organometallic materials are formed by spin coating onto the surface of the semiconductor substrate.

[0049] The thickness of the EUV-patternable film formed on the surface of a semiconductor substrate can vary depending on the surface characteristics, materials used, and processing conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm and can be thick enough to absorb most of the EUV light under EUV patterning conditions. EUV-patternable films can support absorption equal to or greater than 30%, which can result in far fewer EUV photons being available toward the bottom of the EUV-patternable film. Higher EUV absorption results in more crosslinking and densification near the top of the EUV-exposed film compared to the bottom of the EUV-exposed film. In wet development, insufficient crosslinking can make the resist more susceptible to lift-off or collapse, but this risk is not present in dry development. An all-dry lithography approach can facilitate more efficient utilization of EUV photons through a more opaque resist film. While efficient utilization of EUV photons may occur with EUV-patternable films having higher total absorption, it is understood that in some cases, EUV-patternable films may have a total absorption of less than about 30%. By comparison, the maximum total absorption of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), so that the resist material at the bottom of the resist film is fully exposed. In some embodiments, the film thickness is 10 nm to 40 nm or 10 nm to 20 nm. While not limiting the mechanism, function, or utility of the present disclosure, unlike wet spin-coating processes in the art, the disclosed process is believed to have fewer limitations on the surface adhesion characteristics of the substrate and thus be applicable to a wider variety of substrates. Also, as discussed above, the deposited film closely conforms to surface features, which may provide advantages in forming a mask over a substrate, such as a substrate having underlying features, without "filling" or otherwise planarizing such features.

[0050] At block 104, a cleaning process is performed to clean the backside and bevel edge of the semiconductor substrate. This backside and bevel edge cleaning may non-selectively etch the EUV resist film to evenly remove films with various levels of oxidation or crosslinking on the substrate backside and bevel edge. During application of the EUV patternable film, some unintentional deposition of resist material on the substrate bevel edge and / or backside may occur, either by wet or dry deposition processes. This unintentional deposition may result in unwanted particles that later migrate to the top surface of the semiconductor substrate and become particle defects. This bevel edge and backside deposition may also cause downstream processing issues, including contamination of patterning (scanner) and development tools and metrology tools. Traditionally, removal of this bevel edge and backside deposition is performed by wet cleaning techniques. However, the present disclosure provides for removal of this bevel edge and backside deposition by dry cleaning techniques.

[0051] The backside and bevel edge cleaning may be a dry cleaning process. In some embodiments, the dry cleaning process involves vapor and / or plasma with one or more of the following gases: HBr, HCl, HI, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, and HF. In some embodiments, the dry cleaning process may use the same chemistries as the dry developing process described herein. For example, the backside and bevel edge cleaning may use a hydrogen halide developing chemistry. Alternatively, the backside and bevel edge cleaning may use an organic acid, such as trifluoroacetic acid, or other organic vapor. For the backside and bevel edge cleaning process, the vapor and / or plasma needs to be limited to specific areas of the substrate to ensure that only the backside and bevel edge deposits are removed without any film degradation on the front side of the substrate.

[0052] Process conditions may be optimized for backside and bevel edge cleaning. In some embodiments, higher temperatures, higher pressures, and / or higher reactant flow rates may result in increased etch rates. Suitable process conditions for dry bevel edge and backside cleaning range from 100-10,000 sccm (6-600 mL / s) (e.g., 500 sccm (30 mL / s) of HCl, HBr, HI, or H2 and Cl2, Br), depending on the photoresist film and composition and properties. 2、 or I2, BCl3, or H2, or other halogen-containing compounds), a temperature of 20°C to 140°C (e.g., 80°C), a pressure of 20 mTorr (2.66 Pa) to 1000 mTorr (133.32 Pa) (e.g., 100 mTorr (13.33 Pa)) or a pressure of 50 Torr (6666.1 Pa) to 765 Torr (101991.32 Pa) (e.g., 760 Torr (101324.71 Pa)), a plasma power of 0 W to 500 W at high frequency (e.g., 13.56 MHz), and a duration of about 10 to 20 seconds. Bevel and / or backside cleaning can be achieved using a Coronus® tool available from Lam Research Corporation of Fremont, California, although a wider range of process conditions can be used depending on the capabilities of the processing reactor.

[0053] Although the backside and bevel edge cleaning in block 104 is shown before the PAB treatment in block 106, it is understood that the backside and bevel edge cleaning may be performed at any stage after photoresist deposition during process 100. Thus, the backside and bevel edge cleaning may be performed after photoresist deposition, after PAB treatment, after EUV exposure, after PEB treatment, or after development.

[0054] Bevel and / or backside cleaning may alternatively be extended to complete photoresist removal or photoresist “rework,” in which the applied EUV photoresist is removed and the semiconductor substrate is prepared for photoresist reapplication, such as when the original photoresist is damaged or otherwise defective. Because photoresist work should be accomplished without damaging the underlying semiconductor substrate, oxygen-based etches should be avoided. Alternatively, variations of halide-containing or organic vapor chemistries as described herein may be used. It is understood that photoresist work operations may be applied at any stage during process 100. Thus, photoresist work operations may be applied after resist deposition, after bevel edge and / or backside cleaning, after PAB processing, after EUV exposure, after PEB processing, after development, or after a hard bake. In some embodiments, photoresist work may be performed selectively to the underlying layer but for non-selective removal of exposed and unexposed areas of photoresist.

[0055] In some embodiments, the photoresist work process involves vapor and / or plasma with one or more of the following gases: HBr, HCl, HI, BCl, Cl, BBr, H, PCl, CH, methanol, ammonia, formic acid, NF, and HF. In some embodiments, the photoresist work may use the same chemistries as the dry development processes described herein. For example, the photoresist work may use hydrogen halide development chemistries or organic acids such as trifluoroacetic acid or other organic vapors.

[0056] Process conditions may be optimized for photoresist rework. In some embodiments, higher temperatures, higher pressures, and / or higher reactant flow rates may result in increased etch rates. Suitable process conditions for photoresist workup include reactant flow rates of 100-500 sccm (6-30 mL / s) (e.g., 500 sccm (30 mL / s) of HCl, HBr, HI, BCl3 or H2 and Cl2 or Br2) sufficient to completely remove the EUV photoresist, depending on the photoresist film and composition and properties; temperatures of 20°C to 140°C (e.g., 80°C); pressures of 20-1000 mTorr (2.66-133.32 Pa) (e.g., 300 mTorr (40 Pa)) or 50-765 Torr (6666.1-101991.32 Pa) (e.g., 760 Torr (101324.71 Pa)); plasma power of 0 W to 800 W (e.g., 500 W) at high frequency (e.g., 13.56 MHz); and a 0-200 V saturation voltage. b The wafer bias may be about 100 Å (higher biases may be used with harder underlying substrate materials) and a time period of about 20 seconds to 3 minutes. In some embodiments, the photoresist work can be performed without the application of a plasma. The photoresist work can be performed thermally with a halide-containing gas, such as a hydrogen halide (e.g., HBr), at an elevated temperature (e.g., between 80° C. and 120° C.). These conditions are suitable for some processing reactors, such as the Kiyo etch tool available from Lam Research Corporation of Fremont, California, although it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0057] At block 106 of process 100, an optional post-application bake (PAB) is performed after deposition of the EUV-patternable film and before EUV exposure and / or after performing backside and bevel edge cleaning. The PAB process may involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-patternable film and reduce the EUV dose required to develop a pattern in the EUV-patternable film. The PAB process temperature may be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the process temperature may be between about 90°C and about 200°C or between about 150°C and about 190°C. In some embodiments, the PAB process may be performed in a gas atmosphere flowing in the range of 100-10,000 sccm (6-600 mL / s), with a moisture content in the amount of a few percent up to 100% (e.g., 20%-50%), at a pressure between atmospheric and vacuum, and for a process duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PAB treatment is carried out at a temperature of about 100° C. to 230° C. for a time of about 1 to 2 minutes.

[0058] At block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally, the EUV exposure causes changes in the chemical composition and crosslinking of the metal-containing EUV resist film, creating etch selectivity contrasts that can be utilized for subsequent development.

[0059] The metal-containing EUV resist film can then be patterned by exposing regions of the film to EUV light, typically under relatively high vacuum. EUV devices and imaging methods useful herein include those known in the art. In particular, as discussed above, exposed areas of the film are produced through EUV patterning with altered physical or chemical properties relative to unexposed areas. For example, in the exposed areas, metal-carbon bond cleavage can occur through beta-hydride desorption, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxide and bridged metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create chemical contrast for development as a negative-tone resist. Generally, a higher number of beta-Hs in the alkyl group results in a more sensitive film. This can also be explained as weaker Sn-C bonds with more branching. Following exposure, the metal-containing EUV resist film can be baked to induce further crosslinking of the metal oxide film. The difference in properties between the exposed and unexposed areas can be exploited in subsequent processing, such as to dissolve the unexposed areas or to deposit material onto the exposed areas. For example, the pattern can be developed using dry methods to form a metal oxide-containing mask. Methods and apparatus useful in such processes are described in U.S. Patent Application No. 62 / 782,578, filed December 20, 2018, the disclosures of which are incorporated herein by reference.

[0060] In particular, in various embodiments, hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, particularly when exposure is performed in a vacuum using EUV. However, removal of the exposed imaging layer from vacuum to air, or the controlled introduction of oxygen, ozone, HO, or water, can result in oxidation of the surface Sn—H to Sn—OH. The difference in properties between the exposed and unexposed regions may be exploited in subsequent processing, such as by reacting the irradiated regions, the unirradiated regions, or both, with one or more reagents to selectively add or remove material from the imaging layer.

[0061] Without limiting the mechanism, function, or utility of this technology, for example, 10 mJ / cm 2 ~100mJ / cm 2 EUV exposure at a dose of 1000 uV leads to the cleavage of Sn-C bonds, resulting in the loss of alkyl substituents, the relaxation of steric hindrance, and the collapse of low-density films. Furthermore, reactive metal-H bonds generated in beta-hydride elimination reactions can react with neighboring active groups, such as hydroxyls, in the films, leading to further cross-linking and densification, creating chemical contrast between exposed and unexposed regions.

[0062] Following exposure of the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided, which includes EUV-exposed and unexposed regions.

[0063] To further enhance the contrast in etch selectivity of the photopatterned metal-containing EUV resist, an optional post-exposure bake (PEB) is performed at block 110 of process 100. The photopatterned metal-containing EUV resist can be thermally treated in the presence of various chemical species to promote crosslinking of the EUV-exposed regions, or simply baked on a hotplate in ambient air at, for example, between 100° C. and 250° C. for 1-5 minutes (e.g., 190° C. for 2 minutes).

[0064] In various embodiments, the bake strategy involves careful control of the bake atmosphere, the introduction of reactive gases, and / or the ramping rate of the bake temperature. Examples of useful reactive gases include, for example, air, HO, HO vapor, CO, CO, O, O, CH, CHOH, N, H, NH, NO, NO, alcohols, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) promote complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote cross-linking between adjacent Sn-OH groups to form a more densely cross-linked SnO-like network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. A too low PEB temperature results in insufficient cross-linking, resulting in less chemical contrast for development at a given dose. Furthermore, excessively high PEB temperatures can have deleterious effects, including severe oxidation and film shrinkage in unexposed regions (in this example, regions removed by development of the patterned film to form the mask) and undesirable interdiffusion at the junction between the photopatterned metal-containing EUV resist and the underlayer, both of which can contribute to loss of chemical contrast and increased defect density due to insoluble scum. The PEB treatment temperature can be between about 100°C and about 300°C, between about 170°C and about 290°C, or between about 200°C and about 240°C. In some embodiments, the PEB treatment can be performed in a gas atmosphere flowing in the range of 100-10,000 sccm (6-600 mL / s), with a water content of a few percent up to 100% (e.g., 20%-50%), at a pressure between atmospheric and vacuum, and for a treatment duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PEB thermal treatment can be repeated to further enhance etch selectivity.

[0065] At block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, exposed areas are removed (positive tone) or unexposed areas are removed (negative tone). In some embodiments, development may involve selective deposition of photopatterned metal-containing EUV resist onto either the exposed or unexposed areas, followed by an etching operation. In various embodiments, these processes may be dry or wet processes. An example process for development involves subjecting an organotin oxide-containing EUV-sensitive photoresist film (e.g., 10-30 nm thick, such as 20 nm) to an EUV exposure dose and a post-exposure bake, followed by development. The photoresist film may be deposited based on a gas-phase reaction of an organotin precursor, such as isopropyl(tris)(dimethylamino)tin and water vapor, or may be a spin-on film containing tin clusters in an organic matrix. The photopatterned metal-containing EUV resist is developed by exposure to a development chemical. In some embodiments, the development chemistry includes a halide-containing chemical or an organic vapor such as trifluoroacetic acid.

[0066] 2A-2D show cross-sectional schematic views of various processing stages of a conventional backside and bevel edge clean. Conventional backside and bevel edge cleans use wet processing techniques. Deposition of EUV resist material may be performed using wet or dry deposition techniques.

[0067] 2A , EUV resist material 210 may be deposited on the front surface, back surface, and bevel edge of substrate 200. EUV resist material 210 deposited on the back surface and bevel edge increases the likelihood of contamination on the front surface of substrate 200 and of downstream tools. Such EUV resist material 210 is undesirable. It is desirable to remove EUV resist material 210 from the back surface and bevel edge of substrate 200. In some cases, it is desirable to remove some of the EUV resist material 210 deposited on the front surface of substrate 200, including the EUV resist material 210 deposited on the periphery of the front surface of substrate 200.

[0068] As shown in FIG. 2B, the EUV resist material 210 deposited on the bevel edge of the substrate 200 is removed by wet bevel edge cleaning. This leaves EUV resist material 210a on the front surface of the substrate 200 and EUV resist material 210b on the back surface of the substrate 200. In a standard edge bead removal process, an organic solvent such as PGME, PGMEA, or 2-heptanone is dispensed in a first process chamber (Chamber 1) to remove the EUV resist material 210 deposited on the bevel edge. The first process chamber may be a spin-clean tool. The organic solvent may be dispensed at a low / mild temperature, such as about 20°C. Any heating of the flammable solvent poses a significant fire / explosion hazard. The substrate 200 undergoes a rinse / dry operation before proceeding to the second process chamber (Chamber 2).

[0069] As shown in FIG. 2C , the EUV resist material 210b deposited on the backside of the substrate 200 is removed by wet backside cleaning, leaving behind the EUV resist material 210a on the front side of the substrate 200. The wet backside cleaning may be performed in a second process chamber, which may be another spin-cleaning tool capable of cleaning the backside of the substrate 200. For example, the wet backside cleaning may use a cleaning agent such as dHF, dHCl, diluted sulfuric acid, or SC-1. The cleaning agent may be dispensed at a low / mild temperature, such as about 20°C. While the wet backside cleaning may also remove material on the bevel edge region, it is typically not effective in uniformly or completely removing material on the bevel edge region. Therefore, the backside cleaning and the bevel edge cleaning are generally separated between the first and second process chambers. The substrate 200 undergoes a rinse / drying operation before proceeding to the third process chamber (Chamber 3).

[0070] As shown in FIG. 2D, the substrate 200 is transferred to a third process chamber to undergo a PAB thermal treatment. In some embodiments, the third process chamber is an oven or includes a hotplate where the substrate 200 is exposed to an elevated temperature. The PAB thermal treatment increases the substrate temperature to an elevated temperature, such as between about 90° C. and 200° C., thereby stabilizing the lithographic properties of the EUV resist material 210a on the front surface of the substrate 200 for EUV exposure. The PAB thermal treatment is a dry process.

[0071] In contrast to wet backside and bevel edge cleaning techniques, dry backside and bevel edge cleaning techniques may be less costly and more environmentally safe. Dry backside and bevel edge cleaning techniques may consolidate chambers so that dry processing steps can be performed in fewer tools / chambers. Dry backside and bevel edge cleaning techniques may address non-uniformity issues associated with wet backside and bevel edge cleaning techniques.

[0072] Existing dry backside and bevel edge cleaning techniques typically use plasma to remove material from the backside and bevel edge of a substrate. Existing hardware can confine the plasma to the backside and bevel edge of the substrate to remove material. However, the plasma generates light, which exposes the front side of the substrate to stray light and can damage the photosensitive film. Furthermore, existing hardware is ineffective at restricting residual etch gases from reaching the front side of the substrate.

[0073] The present disclosure provides a dry backside and bevel edge cleaning method that does not involve applying a plasma. The dry backside and bevel edge cleaning method utilizes an etch gas that is confined to specific regions of the substrate to remove material (e.g., EUV resist material) from the backside and bevel edge of the substrate. The dry backside and bevel edge cleaning method exposes the substrate to elevated temperatures to promote non-selective removal of material at the backside and bevel edge.

[0074] 3A-3C show cross-sectional schematic views of various processing stages for dry backside and bevel edge cleaning of photoresist material, according to some embodiments. Deposition of the photoresist material (e.g., EUV resist material) may be performed using wet or dry deposition techniques. Wet deposition techniques include spin coating. Dry deposition techniques include chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0075] As shown in FIG. 3A , EUV resist material 310 may be deposited on the front surface, back surface, and bevel edge of substrate 300. The EUV resist material 310 deposited on the back surface and bevel edge increases the likelihood of contamination on the front surface of substrate 300 and of downstream tools. Such EUV resist material 310 is undesirable. It is desirable to remove the EUV resist material 310 from the back surface and bevel edge of substrate 300. In some cases, it is desirable to remove some of the EUV resist material 310 deposited on the front surface of substrate 300, including the EUV resist material 310 deposited on the periphery of the front surface of substrate 300. For example, it may be desirable to remove the EUV resist material 310 from only about a few millimeters (e.g., about 1.5 mm) from the edge on the front surface. In some embodiments, EUV resist material 310 is an organometallic-containing resist material or an organometallic oxide. The EUV resist material 310 may include an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element may have a high patterning radiation absorption cross section. In some embodiments, the element may have a high EUV absorption cross section. In some embodiments, the EUV resist material 310 may generally be composed of Sn, O, and C. For example, the EUV resist material 310 includes an organotin oxide.

[0076] As shown in FIG. 3B, the EUV resist material 310 deposited on the backside and bevel edge of the substrate 300 is removed by dry cleaning. This leaves the EUV resist material 310a on the front side of the substrate 300. The dry cleaning may expose the backside and bevel edge of the substrate 300 to an etch gas. In some embodiments, the etch gas is a hydrogen halide, hydrogen gas, hydrogen gas and a halide gas, or boron trichloride (BCl). In one example, the etch gas is a hydrogen halide such as HCl, HBr, or HI. In another example, the etch gas is hydrogen gas (H). In yet another example, the etch gas is a mixture of H and Cl, Br, or I. In yet another example, the etch gas is BCl. In yet another example, the etch gas is an organic acid such as trifluoroacetic acid. While this disclosure is not limited to any particular theory or mechanism of operation, it is understood that this approach utilizes the chemical reactivity of EUV photoresist materials with cleaning chemicals (e.g., HCl, HBr, HI, H and Cl, Br, or I, BCl) to form volatile products using steam. EUV photoresist materials may be removed using steam at various temperatures, but higher temperatures, pressures, and / or reactant flow rates can further accelerate or enhance the reactivity. In some embodiments, EUV resist materials can be removed at etch rates of up to 1 nm / s. In some embodiments, the etch gas is activated by a remote plasma source, which can further accelerate or enhance the reactivity. In some embodiments, the etch gas is delivered with a carrier gas, such as argon, helium, nitrogen, or other suitable carrier gas.

[0077] In some embodiments, the photoresist material is not an EUV resist material, but is a silicon-based material or a carbon-based material. The etch gas for removal of such materials may be different from that for removal of EUV resist materials. In some embodiments, the etch gas includes an oxidizing gas, such as O, CO, N, O, and the like, for removal of carbon-based materials. In some embodiments, the etch gas includes a C, N, O, or the like, for removal of silicon-based materials. x F y or C x F y H z Or, it includes a fluorine-based gas such as a chlorine-based gas.

[0078] An inert curtain gas may be delivered to the front surface of the substrate 300 to confine the etch gas to the back surface and bevel edge of the substrate 300. The curtain gas may include gases such as nitrogen (N), oxygen (O), water (HO), argon (Ar), helium (He), xenon (Xe), neon (Ne), or mixtures thereof. The curtain gas is flowed over the front surface of the substrate 300 to protect at least a central region of the front surface of the substrate 300 from the etch gas. As the curtain gas is flowed over the front surface, the curtain gas diffuses across the front surface to protect the EUV resist material 310a deposited on the front surface.

[0079] The curtain gas may be flowed simultaneously with the etch gas. A first etch gas flow may be introduced to the backside of the substrate 300. The first etch gas flow may be diffused across the backside of the substrate 300, which may be accessible when the substrate 300 is supported by an MCA support on a carrier ring. In some embodiments, a second etch gas flow may be introduced to the periphery of the front side of the substrate 300. The second etch gas flow may flow along the periphery of the front side and wrap around the bevel edge of the substrate 300. The first etch gas flow may be introduced through one or more bottom gas inlets located below the substrate support, and the second etch gas flow may be introduced through one or more peripheral gas inlets of a gas distributor located above the substrate support. The gas distributor may include a modular ring having one or more peripheral gas inlets. The modular ring may adjust the spacing between the one or more peripheral gas inlets and the front side of the substrate 300. In some embodiments, the curtain gas is flowed from one or more central gas inlets of the gas distributor, and a first gap separating the one or more peripheral gas inlets from the front surface is larger than a second gap separating the one or more central gas inlets from the front surface.

[0080] The substrate 300 may be heated to an elevated temperature during the dry cleaning, the elevated temperature being between about 20°C and about 170°C, between about 20°C and about 140°C, between about 40°C and about 140°C, or about 100°C. In some embodiments, the dry cleaning may be performed under elevated pressure. The pressure in the processing chamber may be between about 0.02 Torr (2.67 Pa) and atmospheric pressure, between 0.1 Torr (13.33 Pa) and atmospheric pressure, or between about 1 Torr (133.32 Pa) and atmospheric pressure. In some embodiments, the dry cleaning may be performed with a high flow rate of an etch gas. The etch gas flow rate can be between about 50 sccm (3 mL / s) and about 10,000 sccm (600 mL / s), between about 100 sccm (6 mL / s) and about 10,000 sccm (600 mL / s), or between about 200 sccm (12 mL / s) and about 5,000 sccm (300 mL / s). Unlike wet cleaning techniques, the non-plasma thermal cleaning techniques of the present disclosure allow for adjustment of process parameters such as temperature, pressure, and gas flow rates to control the etch rate. Higher etch rates can be achieved to remove unexposed EUV resist material at higher temperatures and / or pressures and flow rates.

[0081] Both the backside cleaning and the bevel edge cleaning are performed in the first process chamber (Chamber 1) rather than in separate processing chambers. This reduces the possibility of tool contamination that might otherwise occur between cleaning operations. A single pass may be performed for what are essentially multiple process steps within a single tool. This also reduces costs and increases throughput. No wet cleaning or rinsing / drying operations are performed in the dry backside and bevel edge cleaning of the present disclosure.

[0082] In some embodiments, the dry backside and bevel edge cleaning includes exposure to an etch gas followed by purging. Purging involves introducing a purge gas to pump / purge residual etch gas from the first process chamber. It is understood that purging can be useful to remove residual etch gas or etch by-products from the processing chamber to avoid undesired etching of the front surface of the substrate 300 during substrate transfer. Purging may involve flowing an inert gas and / or a reactive gas. The reactive gas may react with residual etch gas to facilitate ease of removal. The reactive gas may be, for example, a tin-based precursor, such as an organotin precursor. The inert gas may be Ar, He, Ne, Xe, or N2. The chamber pressure may be between about 0.1 Torr (13.33 Pa) and about 6 Torr (799.93 Pa). The purge gas flow may be between about 10 sccm (0.6 mL / s) and about 10,000 sccm (600 mL / s), or between about 50 sccm (3 mL / s) and about 5,000 sccm (300 mL / s). In some embodiments, the pumping / purging may proceed at an elevated temperature, such as between about 20° C. and about 140° C. or between about 80° C. and about 120° C. The elevated temperature may facilitate removal of residual etch gas from the first process chamber. In some embodiments, the chamber walls and other components may be heated to release the residual etch gas. The residual etch gas (e.g., halide gas or halide-containing gas) may be exhausted through an exhaust line during the pumping / purging. In some embodiments, the pumping / purging operation may also be referred to as dehalogenation. Halides may easily adhere to the chamber walls, chamber components, or wafer. If halides are deposited on the wafer, there is an increased risk that the halides (eg, bromine) will be released from the wafer during EUV scanning, thereby corroding or damaging the scanner.

[0083] In some embodiments, the duration of the backside and bevel edge cleaning is between about 10 seconds and about 150 seconds. In some embodiments, the endpoint of the backside and bevel edge cleaning is detected by one or more sensors. The one or more sensors may detect the presence or absence of EUV resist deposits on the backside and bevel edge of the substrate 300. The one or more sensors may include an IR sensor and / or an optical sensor.

[0084] As shown in FIG. 3C , the substrate 300 is exposed to a PAB thermal treatment. In some embodiments, the PAB thermal treatment is performed in the same process chamber (i.e., the first process chamber) as the dry backside and bevel edge clean. As such, the dry backside and bevel edge clean is integrated with the PAB thermal treatment. This may further reduce the potential for contamination, reduce costs, and increase throughput. This may have a minimal or positive impact on lithographic performance. In some embodiments, the PAB thermal treatment is performed in a second process chamber (chamber 2) separate from the dry backside and bevel edge clean. The PAB treatment is a dry process.

[0085] The PAB thermal treatment elevates the substrate temperature to an elevated temperature, such as between about 100°C and about 170°C, or between about 120°C and about 150°C. In some embodiments, the substrate temperature may be controlled using a radiant heat source, such as an IR lamp or one or more LEDs. The radiant heat source may be positioned below the substrate 300. Alternatively, the radiant heat source may be positioned above the substrate 300. The substrate temperature may be actively controlled by a pyrometer in a feedback control loop established with the radiant heat source. The atmosphere during the PAB thermal treatment may be controlled by flowing an inert gas, such as N2, Ar, He, Xe, or Ne, which may be mixed with O2 and / or HO. The flow rate of the inert gas may be between about 10 sccm (0.6 mL / s) and about 10,000 sccm (600 mL / s), or between about 50 sccm (3 mL / s) and about 5,000 sccm (300 mL / s). The pressure during the PAB heat treatment may be controlled to be between about 0.02 Torr (2.67 Pa) and atmospheric pressure, between about 0.1 Torr (13.33 Pa) and atmospheric pressure, or between about 1 Torr (133.32 Pa) and atmospheric pressure. [Device]

[0086] The present disclosure provides hardware components within a processing chamber to enable dry backside and bevel edge cleaning while protecting the center of the front surface of a substrate. These hardware components may be implemented in dry backside and bevel edge cleaning and PAB processing.

[0087] FIG. 4 shows a schematic diagram of a processing chamber for performing dry backside and bevel edge cleaning, according to some embodiments. An apparatus or tool 400 for performing dry backside and bevel edge cleaning may include a processing chamber 410. The processing chamber 410 may be integrated to perform both backside and bevel edge cleaning, as well as PAB processing and / or deposition. The apparatus 400 may include a substrate support 420 within the processing chamber 410 for supporting a substrate 430. In some embodiments, the substrate support 420 may receive the substrate 430 after deposition of material (e.g., EUV resist material 432) on the front surface, backside, and bevel edge of the substrate 430. A plurality of minimum contact area supports (not shown) may be configured to extend from a major surface of the substrate support 420 to elevate the substrate 430 so that etch gases can access the backside of the substrate 430. The apparatus 400 further includes a gas distributor 440 above the substrate support 420 and coupled to the processing chamber 410 for delivering a curtain gas 442 to the front surface of the substrate 430. The apparatus 400 further includes an etch gas delivery source 450 below the substrate support 420 and coupled to the processing chamber 410 for delivering an etch gas 444 to the back surface of the substrate 430. The apparatus 400 may further include a heat source 460, such as a radiant heat source, below the substrate support 420.

[0088] The substrate support 420 may include a carrier ring 422. The carrier ring 422 may include an annular body for supporting the substrate 430. FIG. 5A shows a perspective view of a carrier ring 500 for supporting a substrate 530 in a processing chamber, according to some embodiments. Substrates 530 in the semiconductor industry typically have diameters of 200 mm, 300 mm, or 450 mm. The outer diameter of the carrier ring 500 is larger than the diameter of the substrate 530, and the inner diameter of the annular body is smaller than the diameter of the substrate 530. The inner diameter may be equal to or less than about 280 mm, equal to or less than about 240 mm, or equal to or less than about 200 mm. In other words, the substrate 530 may be held by a ring having a radius equal to or less than about 140 mm. Multiple MCA supports 540 may extend from a major surface of the carrier ring 500 to contact the backside of the substrate 530. In some embodiments, the multiple MCA supports 540 may be symmetrically arranged around the center of the carrier ring 500. For example, the plurality of MCA supports 540 may include three MCA supports, four MCA supports, five MCA supports, six MCA supports, or more. The MCA supports 540 may be pins. The plurality of MCA supports 540 may include any suitable insulating material. The insulating material may be a soft material such as perfluoroalkoxyalkane (PFA) to avoid scratching the substrate 530. Figure 5B shows a cross-sectional schematic view of a carrier ring 500 supporting and contacting the backside of the substrate 530, according to some embodiments.

[0089] The position of the MCA supports 540 may be optimized with respect to a preceding deposition process to avoid contacting the substrate 530 in locations with backside deposition. In other words, the multiple MCA supports 540 may be configured to contact areas of the backside of the substrate 530 in locations with little or no backside deposition (e.g., photoresist deposits). This placement may be determined based on knowledge or data identified from one or more previous deposition operations that indicate locations with little or no backside deposition. For example, the MCA supports 540 may contact the backside of the substrate 530 in areas closer to the center of the substrate 530 than to the edge of the substrate 530. At the same time, the position of the MCA supports 540 does not prevent etch gases from accessing areas with backside deposition.

[0090] The multiple MCA supports 540 provide minimal contact with the backside of the substrate 530. The multiple MCA supports 540 may elevate the substrate 530 to a height above the major surface of the carrier ring 500 to allow gas flow across the backside of the substrate 530. In some embodiments, the height is between about 0.025 mm and about 0.5 mm, or between about 0.05 mm and about 0.25 mm. In some embodiments, the MCA supports 540 are extendable / retractable from the major surface of the substrate support. In some embodiments, the height is adjustable to control the gap size. In some embodiments, the backside of the substrate 530 is supported by the MCA supports 540 with a shifting or rotating mechanism to enable cleaning of areas directly contacted by the MCA supports 540 and the substrate 530. Etch gases may be blocked from accessing areas directly contacting the MCA supports 540. Even if this area is very small relative to the substrate 530, it may still have unacceptable severe metal contamination. Therefore, this area also needs to be cleaned. In other words, the MCA supports 540 may shift or rotate their position to contact different points on the backside of the substrate 530. The shifting mechanism may be incorporated into the lift pins used during substrate transfer. After a first portion of cleaning, which cleans the entire substrate 530 except for the areas touched by the MCA supports 540, the carrier ring 500 may lower the substrate 530 onto the lift pins. The lift pins move the substrate by multiple MCA areas, for example, about tens of microns. The carrier ring 500 is then returned to the process position, and a second cleaning is performed to clean the areas initially touched by the MCA supports 540. In some embodiments, the backside of the substrate 530 is supported by one section of the MCA supports 540, and the carrier ring 500 is divided into two or more sections, each with X number of MCA supports 540, where X is any integer value. In this case, the cleaning process may be divided into multiple time stages. During each time step, one or more of the split ring sections is moved away from the substrate surface to allow cleaning in that section. All sections need to be lifted / cleaned at least once during cleaning.A minimum number of sections need to remain in place to ensure that the substrate 530 is securely maintained in the process position. For example, the carrier ring 500 may be divided into two sections of three pins each. The carrier ring 500 and the plurality of MCA supports 540 may be configured to regulate the etch gas flow at the backside of the substrate 530. Specifically, the height of the MCA supports 540, the inner diameter of the carrier ring 500, the positioning of the MCA supports 540, and other aspects of the carrier ring 500 may be designed to regulate the gas flow between curtain gas from the top and etch gas from the bottom to ensure that both the backside and bevel edge are etched, but that certain areas of the front side of the substrate 530 are not etched.

[0091] Returning to FIG. 4 , an etch gas delivery source 450 and a radiant heat source 460 may be positioned below the substrate support 420 (e.g., a carrier ring). The etch gas delivery source 450 may include one or more bottom gas inlets or nozzles to deliver etch gas 444 to the backside of the substrate 430. The radiant heat source 460 may be spaced away from the backside of the substrate 430 but may heat the substrate 430 to an elevated temperature by radiant heating. The radiant heat source 460 may provide controlled ramp capability, pulsing, and rapid temperature changes. In some embodiments, the radiant heat source 460 includes one or more IR lamps or one or more LEDs. To enable rapid temperature changes, the heat source may be in the range of 1 to 10 kW. In some embodiments, the substrate support 420 may be configured to rotate. For substrate temperature controllability, the one or more IR lamps or one or more LEDs may be separated into multiple zones for controlled heating of various regions of the substrate 430. Additionally, one or more lamps or one or more LEDs may each be independently controllable. By pulsing the LEDs, the temperature ramp-up of the substrate 430 can be controlled. The radiant heat source 460 may also function to block stray light from reaching the front surface of the substrate 430. In some embodiments, the etch gas delivery source 450 includes one or more holes through the radiant heat source 460. In some embodiments, the etch gas delivery source 450 includes one or more holes disposed outside the radiant heat source 460. Because uniformity of the etch gas flow over the backside of the substrate 430 is not important for removing material thereon, the positioning of the one or more holes may not be critical. Thus, the etch gas delivery source 450 may be positioned in any manner such that the etch gas 444 can reach or otherwise access the backside of the substrate 430.

[0092] A gas distributor 440 is disposed above the substrate support 420 to deliver a curtain gas 442 to the front surface of the substrate 430. The gas distributor 440 may include one or more central gas inlets to direct the curtain gas flow toward the center of the front surface of the substrate 430. In some embodiments, the gas distributor 440 may include one or more peripheral gas inlets to direct an etch gas flow 446 toward the periphery of the front surface of the substrate 430. It is understood that the periphery of the front surface of the substrate 430 may occupy 15% or less, 10% or less, or 5% or less of the area of ​​the front surface of the substrate 430. In some embodiments, the gas distributor 440 includes a top plate having a plurality of holes disposed in a central region of the top plate and a plurality of holes disposed in a peripheral region of the top plate. In some embodiments, the gas distributor 440 includes modular rings of different diameters. In some cases, the modular rings may have different shapes. The etch gas 446 may be delivered through one of the modular rings, and the curtain gas 442 may be delivered through another of the modular rings. Thus, the gas distributor 440 includes at least one modular ring for one or more peripheral gas inlets, the at least one modular ring configured to adjust the spacing of the one or more peripheral gas inlets from the front surface of the substrate 430. Removal at the bevel edge can be adjusted by adjusting the spacing of the one or more peripheral gas inlets in the modular rings. Additionally or alternatively, the gas distributor 440 includes one or more nozzles for directing the etch gas flow 446 toward the bevel edge of the substrate 430.

[0093] The gas distributor 440 may be configured such that a first gap separating one or more peripheral gas inlets from the front surface of the substrate 430 is larger than a second gap separating one or more central gas inlets from the front surface of the substrate 430. In some embodiments, the first gap is at least twice as large as the second gap. The second gap may be as small as possible without touching the EUV resist film 432 on the front surface of the substrate 430. As shown in FIG. 4 , the gas distributor 440 may have a stepped design. Thus, the curtain gas flow 442 may be provided at a higher pressure and delivered across a smaller gap at the center of the substrate 430, and the etch gas flow 446 may be provided at a lower pressure and delivered across a longer gap at the periphery of the substrate 430. The etch gas flow 446 delivered from above the substrate support 420 may be referred to as the "second etch gas flow," while the etch gas flow 444 delivered from below the substrate support 420 may be referred to as the "first etch gas flow." The second etch gas flow delivered to the periphery of the substrate 430 may wrap around portions of the front surface and bevel edge region of the substrate 430. For example, the second etch gas flow may wrap around 5 mm or less, 3 mm or less, or 1.5 mm or less of the front surface of the substrate 430. The curtain gas flow 442 prevents the etch gas from reaching the remainder of the front surface of the substrate 430.

[0094] In addition to or as an alternative to the radiant heat source 460, the apparatus 400 may further include one or more heaters. The one or more heaters may provide substrate temperature control. In some embodiments, the one or more heaters are coupled to the gas distributor 440 and are above the substrate 430. The one or more heaters may be radiant heat sources. In some embodiments, the one or more heaters are configured to provide ambient heating within the process chamber 410. In some embodiments, the one or more heaters provide substrate temperature control in the range of 20°C to 170°C or 20°C to 140°C.

[0095] The apparatus 400 may further include one or more sensors for detecting the presence of film deposits on the backside and / or bevel edge of the substrate 430. In some embodiments, the one or more sensors include optical devices such as IR sensors that function as endpoint detection.

[0096] 6 shows a schematic diagram of one embodiment of a process station 600 having a processing chamber body 602 for maintaining a low-pressure environment suitable for performing the described dry backside and bevel edge cleaning embodiments. Multiple process stations 600 may be included in a common low-pressure process tool environment. For example, FIG. 7 shows one embodiment of a multi-station processing tool 700, such as a VECTOR® processing tool available from Lam Research Corporation of Fremont, California. In some embodiments, one or more hardware parameters of the process stations 600, including those discussed in detail below, may be controlled by one or more computer controllers. To La So you can adjust it in the program.

[0097] The process stations may be configured as modules within a cluster tool. Figure 9 illustrates a semiconductor process cluster tool architecture having a vacuum-integrated deposition and patterning module suitable for practicing the embodiments described herein. Such a cluster process tool architecture may include resist deposition, resist exposure (EUV scanner), resist development, and etch modules, as described above and further below with reference to Figures 8 and 9.

[0098] In some embodiments, certain processing functions, such as dry develop and etch, can be performed sequentially in the same module. Embodiments of the present disclosure are also directed to methods and apparatus for subjecting a wafer, including a photo-patterned EUV resist thin film layer disposed on a layer or stack to be etched, to a dry develop / etch chamber following photo-patterning in an EUV scanner; dry developing the photo-patterned EUV resist thin film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0099] Returning to FIG. 6, the process station 600 includes a reactant delivery system 604 for delivering process gases to a distribution showerhead 606. 1 and The reactant delivery system 601a may be in fluid communication with the process station 600. The reactant delivery system 601a may optionally include a mixing vessel 604 for blending and / or conditioning process gases for delivery to the showerhead 606. One or more mixing vessel inlet valves 620 may control the introduction of process gases into the mixing vessel 604. If plasma exposure is used, the plasma may be delivered to the showerhead 606 or may be generated in the process station 600. As noted above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0100] 6 includes an optional vaporization point 603 that vaporizes a liquid reactant to be fed to the mixing vessel 604. In some embodiments, a liquid flow controller (LFC) upstream of the vaporization point 603 may be provided to control the mass flow rate of the liquid for vaporization and delivery to the process station 600. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC, where a plunger valve of the LFC may be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0101] The showerhead 606 distributes process gases toward the substrate 612. In the embodiment shown in Figure 6, the substrate 612 is located below the showerhead 606 and is shown resting on a pedestal 608. The showerhead 606 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 612.

[0102] In some embodiments, the pedestal 608 may raise or lower the substrate 612 to expose the volume between the substrate 612 and the showerhead 606. In some embodiments, the pedestal height can be controlled by a suitable computer controller. To La It is understood that the temperature may be programmably adjusted. In some embodiments, the showerhead 606 may have multiple plenum volumes with multiple temperature controls. In some embodiments, the pedestal 608 may be replaced by a carrier ring to support the substrate 612.

[0103] In some embodiments, the pedestal 608 may be temperature controlled via a heater 610. Alternatively, the substrate 612, supported by a carrier ring, may be heated by a radiant heat source disposed below the substrate 612. In some embodiments, the substrate 612 may be heated to temperatures greater than 0° C. up to 300° C. or higher, such as 50 to 120° C., about 65 to 80° C., during non-plasma thermal exposure of the resist to dry backside and bevel edge cleaning chemistries, such as HBr or HCl, as described in disclosed embodiments. In some embodiments, the heater 610 of the pedestal 608 may include multiple, independently controllable temperature control zones.

[0104] Additionally, in some embodiments, pressure control for the process station 600 may be provided by a butterfly valve 618. As shown in the embodiment of Figure 6, the butterfly valve 618 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the process station 600 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 600.

[0105] In some embodiments, the position of the showerhead 606 may be adjusted relative to the pedestal 608 to vary the volume between the substrate 612 and the showerhead 606. Furthermore, it is understood that the vertical position of the pedestal 608 and / or the showerhead 606 may be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 608 may include a rotation axis for rotating the orientation of the substrate 612. In some embodiments, one or more of these example adjustments may be performed by one or more suitable computer controllers. To La Therefore, it is understood that this may be performed programmatically.

[0106] Where plasma may be used, for example, in gentle plasma-based dry cleaning embodiments and / or etch operations performed in the same chamber, the showerhead 606 and pedestal 608 are in electrical communication with a radio frequency (RF) power source 614 and matching network 616 for powering the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 614 and matching network 616 may be operated at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0107] In some embodiments, the controller La'sInstructions for setting conditions for a process phase may be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process phase may be included in the corresponding recipe phase of a process recipe. In some cases, multiple process recipe phases may be arranged in sequence such that all instructions for a process phase are executed simultaneously with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a recipe phase may include instructions for setting a flow rate of a dry cleaning chemical reactant gas, such as HBr or HCl, and a time delay instruction for the recipe phase. In some embodiments, the controller Ra is , may include any of the features described below with respect to system controller 750 of FIG.

[0108] As described above, one or more process stations may be included in a multi-station processing tool. FIG. 7 shows a schematic diagram of one embodiment of a multi-station processing tool 700 having an inbound load lock 702 and an outbound load lock 704, either or both of which may include a remote plasma source. An atmospheric pressure robot 706 is configured to move wafers from a cassette loaded through a pod 708 into the inbound load lock 702 through an atmospheric port 710. The wafer is placed by the robot 706 on a pedestal 712 in the inbound load lock 702, the atmospheric port 710 is closed, and the load lock is pumped down. If the inbound load lock 702 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment to treat the silicon nitride surface within the load lock before being introduced into the processing chamber 714. Additionally, the wafer may also be heated in the inbound load lock 702, for example, to remove moisture and absorbed gases. A chamber transfer port 716 to the processing chamber 714 is then opened and another robot (not shown) places the wafer into the reactor on the pedestal of the first station shown in the reactor for processing. While the embodiment shown in Figure 7 includes a load lock, it will be understood that in some embodiments direct entry of the wafer into the process station may be provided.

[0109] The illustrated processing chamber 714 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 7 . Each station has a heated pedestal (shown at 718 for station 1) and a gas line inlet. It is understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between dry cleaning and deposition process modes. Additionally or alternatively, in some embodiments, the processing chamber 714 may include one or more matched pairs of dry cleaning and deposition process stations. While the illustrated processing chamber 714 includes four stations, it is understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, and in other embodiments, the processing chamber may have three or fewer stations.

[0110] FIG. 7 illustrates one embodiment of a wafer handling system 790 for transferring wafers within the processing chamber 714. In some embodiments, the wafer handling system 790 may transfer wafers between various process stations and / or between process stations and load locks. It is understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 7 also illustrates one embodiment of a system controller 750 used to control the process conditions and hardware states of the processing tool 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. The processor 752 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0111] In some embodiments, a system controller 750 controls the activities of the processing tool 700. The system controller 750 executes system control software 758 stored on a mass storage device 754, loaded into a memory device 756, and executed on a processor 752. Alternatively, control logic may be hard-coded in the controller 750. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following description, wherever "software" or code is used, functionally equivalent hard-coded logic may be used instead. The system control software 758 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the processing tool 700. The system control software 758 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. System control software 758 may be coded in any suitable computer-readable programming language.

[0112] In some embodiments, the system control software 758 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 754 and / or memory device 756 associated with the system controller 750 may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a pressure control program, a heater control program, and a plasma control program.

[0113] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 718 and to control the spacing between the substrate and other parts of the processing tool 700.

[0114] The pressure control program may include code for controlling the halide-containing gas composition (e.g., HBr or HCl gas as described herein) and flow rate to stabilize the pressure in the process station, and optionally for flowing gas into one or more process stations prior to deposition. The pressure control program may include code for controlling the pressure in the process station by, for example, adjusting a throttle valve in the exhaust system of the process station, gas flow to the process station, etc.

[0115] The heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0116] The plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations according to embodiments herein.

[0117] The pressure control program may include code for maintaining pressure within the reaction chamber according to embodiments herein.

[0118] In some embodiments, there may be a user interface associated with the system controller 750. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0119] In some embodiments, the parameters adjusted by the system controller 750 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface.

[0120] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 750 from various process tool sensors. Signals for controlling the process may be output on analog and digital output connections of the processing tool 700. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Suitably programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0121] The system controller 750 may provide program instructions for carrying out the deposition process described above. The program instructions may control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions may control parameters for operating the develop and / or etch processes according to various embodiments described herein.

[0122] System controller 750 typically includes one or more memory devices and one or more processors configured to execute instructions for the apparatus to perform methods according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to system controller 750.

[0123] In some embodiments, the system controller 750 is part of a system, which may be part of the examples above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after semiconductor wafer or substrate processing. The electronics may be referred to as a "controller," which may control various components or subportions of one or more of the above systems. Depending on the processing conditions and / or type of system, the system controller 750 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools and other transfer tools and / or load locks connected or interfaced with the particular system.

[0124] Generally, system controller 750 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to system controller 1450 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more process steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0125] In some embodiments, the system controller 750 may be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the system controller 750 may reside in the “cloud” or all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of fabrication operations, examine the history of past fabrication operations, and examine trends or performance indicators from multiple fabrication operations, to change parameters of a current process, configure process steps to follow a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 750 receives instructions in the form of data that specify the respective parameters of the process steps to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed and the type of tool that the system controller 750 is configured to interface with or control. Thus, as explained above, the system controller 750 may be distributed, such as by including one or more discrete controllers networked together to function toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such a purpose is one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at or as part of a remote computer platform) that are combined to control the process on the chamber.

[0126] Without limitation, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0127] As noted above, depending on one or more of the process steps to be performed by the tool, the system controller 750 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0128] In certain embodiments, an inductively coupled plasma (ICP) reactor is described herein that may be suitable for etch operations suitable for practicing some embodiments. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0129] 8 shows a schematic cross-sectional view of an inductively coupled plasma apparatus 800 suitable for performing certain embodiments or aspects of embodiments, such as dry backside and bevel edge cleaning, an example of which is the Kiyo® reactor produced by Lam Research Corp. of Fremont, Calif. In other embodiments, other tools or tool types having the functionality to perform the dry backside and bevel edge cleaning described herein may be used for implementation.

[0130] The inductively coupled plasma apparatus 800 includes a total process chamber 824 structurally defined by a chamber wall 801 and a window 811. The chamber wall 801 may be made of stainless steel, aluminum, or plastic. The window 811 may be made of quartz or other dielectric material. An optional internal plasma grid 850 divides the total process chamber into an upper subchamber 802 and a lower subchamber 803. In most embodiments, the plasma grid 850 may be removed, thereby utilizing the chamber space created from the subchambers 802 and 803. A chuck 817 is disposed within the lower subchamber 803 near the bottom interior surface. The chuck 817 is configured to receive and maintain a semiconductor wafer 819 on which etching and deposition processes are performed. If present, the chuck 817 may be an electrostatic chuck for supporting the wafer 819. In some embodiments, an edge ring (not shown) surrounds the chuck 817 and has an upper surface that is generally planar with the upper surface of the wafer 819 when it is above the chuck 817. The chuck 817 also includes an electrostatic electrode for chucking and dechucking the wafer 819. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 819 from the chuck 817 may also be provided. The chuck 817 may be charged using an RF power supply 823. The RF power supply 823 is connected to a matching circuit 821 via connection 827. The matching circuit 821 is connected to the chuck 817 via connection 825. In this manner, the RF power supply 823 is connected to the chuck 817. In various embodiments, the bias power of the electrostatic chuck may be set to approximately 50 V or may be set to a different bias power depending on the process being performed according to the disclosed embodiments. For example, the bias power may be set to approximately 20 Vb and approximately 100 Vb. b or about 30V b and approximately 150V b It may be between.

[0131] The elements for plasma generation include a coil 833 disposed above the window 811. In some embodiments, a coil is not used in the disclosed embodiments. The coil 833 is made of a conductive material and includes at least one complete turn. The example coil 833 shown in FIG. 8 includes three turns. A cross section of the coil 833 is indicated by symbols, with the coil having an "X" extending rotationally toward the inside of the page and the coil having a "●" extending rotationally toward the outside of the page. The elements for plasma generation include an RF power source configured to supply RF power to the coil 833. 8 41. Generally, RF power supply 841 is connected to matching circuit 839 via connection 845. Matching circuit 839 is connected to coil 833 via connection 843. In this manner, RF power supply 841 is connected to coil 833. Optional Faraday shield 84 9 is , which is disposed between the coil 833 and the window 811. The Faraday shield 84 9 is , may be maintained in a spaced apart relationship relative to the coil 833. In some embodiments, the Faraday shield 84 9 is , located immediately above the window 811. In some embodiments, the Faraday shield 84 9 is , between the window 811 and the chuck 817. In some embodiments, the Faraday shield 84 9 is , is not maintained in a spaced relationship with respect to the coil 833. For example, the Faraday shield 84 9 is , may be directly below the window 811 without a gap. 9、 and window 811 may be configured to be substantially parallel to each other. 9 is , may prevent metals or other species from depositing on the window 811 of the processing chamber 824.

[0132] Process gases may be flowed into the processing chamber through one or more main gas inlets 860 and / or one or more side gas inlets 870 disposed within the upper subchamber 802. Similarly, although not explicitly shown, similar gas inlets may be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one- or two-stage mechanical dry pump and / or a turbomolecular pump 840, may be used to draw process gases from the processing chamber 824 and maintain pressure within the processing chamber 824. For example, a vacuum pump may be used to evacuate the lower subchamber 803 during an ALD purge operation. A valve-controlled conduit may be used to fluidly connect the vacuum pump to the processing chamber 824 to selectively control application of the vacuum environment provided by the vacuum pump. This may be done using a closed-loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum pump (not shown), during operating plasma processing. Similarly, a vacuum pump and valve-controlled fluid connection to the capacitively coupled plasma processing chamber may also be used.

[0133] During operation of the apparatus 800, one or more process gases may be supplied through the gas inlets 860 and / or 870. In certain embodiments, the process gases may be supplied exclusively through the main gas inlet 860 or exclusively through the gas inlet 870. In some cases, the gas inlets shown in the figure may be replaced by more complex gas inlets, for example, one or more showerheads. Faraday shield 84 9th grade The Faraday shield 84 and / or the optional grid 850 may include internal channels and holes that allow delivery of process gases to the processing chamber 824. 9th gradeEither or both of the grid 850 and optional grid 850 may function as a showerhead for the delivery of process gases. In some embodiments, a liquid vaporization and delivery system may be positioned upstream of the processing chamber 824 so that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the processing chamber 824 via gas inlets 860 and / or 870.

[0134] Radio frequency power is supplied to the coil 833 from an RF power supply 841, causing an RF current to flow through the coil 833. 8 RF current flowing through coil 833 generates an electromagnetic field around coil 833. The electromagnetic field generates an induced current within upper sub-chamber 802. The various generated ions and radicals physically and chemically interact with wafer 819, etching features in wafer 819 and selectively depositing layers thereon.

[0135] When a plasma grid 850 is used such that both an upper subchamber 802 and a lower subchamber 803 are present, an induced current acts on the gas present in the upper subchamber 802, creating an electron-ion plasma within the upper subchamber 802. The optional internal plasma grid 850 confines the amount of hot electrons to the lower subchamber 803. In some embodiments, the apparatus 800 is designed and operated such that the plasma present in the lower subchamber 803 is an ion-ion plasma.

[0136] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, but the ion-ion plasma has a greater ratio of negative ions to positive ions. Volatile etching and / or deposition byproducts may be removed from the lower subchamber 803 through port 822. The chuck 817 disclosed herein may operate at elevated temperatures ranging between about 10° C. and about 250° C. The temperature depends on the process operation and the particular recipe.

[0137] Apparatus 800 may be coupled to equipment (not shown) when installed in a cleaning room or fabrication facility. The equipment includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. These equipment are coupled to apparatus 800 when installed in a target fabrication facility. Additionally, apparatus 800 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out of apparatus 800 using typical automation.

[0138] In some embodiments, a system controller 830 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 824. The system controller 830 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 800 includes a switching system for controlling flow rates and durations when the disclosed embodiments are implemented. In some embodiments, the apparatus 800 may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on the flow chemistry, the selected recipe, the reactor architecture, and other factors.

[0139] In some embodiments, the system controller 830 is part of a system, which may be part of the examples above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after semiconductor wafer or substrate processing. The electronics may be integrated into the system controller 830, which may control various components or subportions of one or more of the above systems. Depending on the processing parameters and / or type of system, the system controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools and other transfer tools and / or load locks connected or interfaced with the particular system.

[0140] Generally, the system controller 830 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for the system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more process steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die of the wafer.

[0141] In some embodiments, the system controller 830 may be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of fabrication operations, examine the history of past fabrication operations, and examine trends or performance indicators from multiple fabrication operations, to change parameters of a current process, configure process steps to follow a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 830 receives instructions in the form of data that specify the respective parameters of the process steps to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as explained above, the system controller 830 may be distributed, such as by including one or more discrete controllers networked together to function toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at or as part of a remote computer platform) that are combined to control the process on the chamber.

[0142] Without limitation, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0143] As noted above, depending on one or more of the process steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0144] EUVL patterning may be performed using any suitable tool, often referred to as a scanner, such as a TWINSCAN NXE:3300B® platform supplied by ASML of Veldhoven, The Netherlands. The EUVL patterning tool may be a standalone device from which substrates are moved in and out for deposition and etching as described herein. Or, as described below, the EUVL patterning tool may be a module on a larger, multi-component tool. FIG. 9 shows a semiconductor process cluster tool architecture with vacuum-integrated deposition, backside and bevel edge cleaning, EUV patterning, and dry develop / etch modules interfaced with a vacuum transfer module suitable for carrying out the processes described herein. While this process may be carried out without such vacuum-integrated equipment, such equipment may be advantageous in some embodiments.

[0145] 9 illustrates a semiconductor process cluster tool architecture with a vacuum-integrated deposition and patterning module interfaced with a vacuum transfer module suitable for carrying out the processes described herein. This configuration of transfer modules for "transferring" wafers between multiple storage facilities and processing modules may be referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum-integrated according to the requirements of the particular process. Other modules, such as for etch, may also be included on the cluster.

[0146] A vacuum transfer module (VTM) 938 interfaces with four processing modules 920a-920d, which may be individually optimized to perform various fabrication processes. By way of example, processing modules 920a-920d may be implemented to perform deposition, evaporation, ELD, dry develop, etch, strip, and / or other semiconductor processes. For example, module 920a may be an ALD reactor that can be operated to perform non-plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research Corporation of Fremont, California. Module 920b may be a PECVD tool, such as a Lam Vector®. It should be understood that this diagram is not necessarily drawn to scale.

[0147] Airlocks 942 and 946, also known as load locks or transfer modules, interface with the VTM 938 and the patterning module 940. For example, as mentioned above, a suitable patterning module may be a TWINSCAN NXE:3300B® platform supplied by ASML of Veldhoven, The Netherlands. This tool architecture allows workpieces, such as semiconductor substrates or wafers, to be transferred under vacuum to prevent reaction prior to exposure. Integration of the deposition module with the lithography tool is facilitated by the fact that EUVL also requires significantly reduced pressures given the strong absorption of incident photons by atmospheric gases such as HO, O, etc.

[0148] As noted above, this integrated structure is only one possible embodiment of a tool for carrying out the described process. This process may also be implemented in a more conventional standalone EUVL scanner and deposition reactor, such as a Lam Vector tool, either standalone or without an integrated patterning module, but integrated in a cluster architecture with other tools such as etch, strip (e.g., a Lam Kiyo or Gamma tool), etc., as a module, for example, as described with reference to FIG.

[0149] Airlock 942 may be an "exit" load lock, referring to the transfer of substrates out of VTM 938, providing deposition module 920a to patterning module 940, and airlock 946 may be an "entry" load lock, referring to the transfer of substrates from patterning module 940 back into VTM 938. Entry load lock 946 may also provide an interface to the outside of the tool for substrate access and exit. Each process module has a facet that interfaces the module to VTM 938. For example, deposition process module 920a has facet 936. Inside each facet, sensors, e.g., sensors 1-18 as shown, are used to detect the passage of wafer 926 as it is moved between the respective stations. Patterning module 940 and airlocks 942 and 946 may similarly include additional facets and sensors, not shown.

[0150] A main VTM robot 922 transfers wafers 926 between modules, including airlocks 942 and 946. In one embodiment, the robot 922 has one arm, and in another embodiment, the robot 922 has two arms, each arm having an end effector 924 for picking wafers, such as wafer 926, for transfer. A front-end robot 944 is used to transfer wafers 926 from the exit airlock 942 to the patterning module 940 and from the patterning module 940 to the entry airlock 946. The front-end robot 944 may also transfer wafers 926 between the entry loadlock and the exterior of the tool for substrate access and egress. The entry airlock module 946 has the ability to match environments between atmosphere and vacuum, allowing wafers 926 to be moved between the two pressure environments without damage.

[0151] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, the EUVL tool may be used to allow the substrate to be degassed before entering the patterning tool. and It is desirable to improve the vacuum environment for the substrate during transfer between depositions. Exit airlock 942 may provide this function by maintaining the transferred wafer at a lower pressure, below the pressure in patterning module 940, for a period of time and evacuating any off-gassing, thereby preventing the optics of patterning tool 940 from being contaminated by off-gassing from the substrate. A preferred pressure for the exit off-gas airlock is 1E-8 Torr (1.33×10-6 Pa) or less.

[0152] In some embodiments, a system controller 950 (which may include one or more physical or logical controllers) controls some or all of the operation of the cluster tool and / or its individual modules. Note that this controller can be local to the cluster architecture or can be located external to the cluster architecture, at the manufacturing site or at a remote location, and connected to the cluster architecture via a network. The system controller 950 may have one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with the controller, or they may be provided over a network. In certain embodiments, the system controller executes system control software.

[0153] The system control software may include instructions for controlling the timing and / or magnitude of application of any aspect of tool or module operation. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform various process tool processes. The system control software may be coded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions executed by the system controller. For example, instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching phases may be included in the corresponding recipe phase.

[0154] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include process chambers for patterning, depositing, and etching, and a controller including instructions for forming the negative pattern mask. The instructions may include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure in the process chamber to expose a surface of the substrate, developing the photopatterned resist, and etching an underlying layer or stack using the patterned resist as a mask. The development may be performed using a halide-containing chemistry.

[0155] It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture, either at the manufacturing site or at a remote location, and connected to the cluster architecture via a network. The controllers described above with respect to any of Figures 6, 7, or 8 may be implemented with the tool in Figure 9. [Conclusion]

[0156] For example, processes and apparatus for dry developing metal and / or metal oxide photoresists to form patterning masks in the context of EUV patterning are disclosed.

[0157] It is understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes will be suggested to those skilled in the art in light thereof. Various details have been omitted for clarity, but various design alternatives may be implemented. Therefore, the examples are to be considered illustrative rather than limiting, and the disclosure is not limited to the details given herein, but may be modified within the scope of the disclosure.

Claims

1. 1. An apparatus for performing bevel edge and backside cleaning of a substrate, the apparatus comprising: a processing chamber; a substrate support for supporting the substrate within the processing chamber; a plurality of minimum contact area (MCA) supports configured to extend from the substrate support to contact a backside of the substrate; a gas distributor above the substrate support, the gas distributor comprising one or more central gas inlets for directing a curtain gas flow toward a center of a front surface of the substrate and one or more peripheral gas inlets for directing a second etch gas flow toward a periphery of the front surface of the substrate, the one or more peripheral gas inlets being located peripherally of the one or more central gas inlets; an etch gas delivery source below the substrate support for directing a first etch gas flow toward the backside of the substrate; and a radiant heat source below the substrate support An apparatus comprising:

2. 2. The apparatus of claim 1, wherein a first gap separating the one or more peripheral gas inlets from the front surface of the substrate is larger than a second gap separating the one or more central gas inlets from the front surface of the substrate.

3. 3. The apparatus of claim 1, wherein the substrate support comprises a carrier ring including an annular body for supporting the substrate, the carrier ring being configured to shift or rotate the positions of the plurality of MCA supports for supporting the substrate at different contact points on the backside of the substrate.

4. 4. The apparatus of claim 1, wherein the plurality of MCA supports includes a first set of MCA supports and a second set of MCA supports, each of the first set of MCA supports and the second set of MCA supports being extendable / retractable to support the substrate.

5. 5. The apparatus of claim 1, wherein the etch gas delivery source has holes through the radiant heat source or holes disposed outside the radiant heat source.

6. The apparatus of claim 1 , further comprising one or more heaters above the substrate coupled to the gas distributor.

7. 7. The apparatus of claim 1, further comprising one or more sensors in the processing chamber, the one or more sensors configured to detect the presence of film deposits on a bevel edge and a backside of the substrate.

8. a controller configured with instructions to perform bevel edge and backside cleaning of the substrate; and the instructions further comprise: providing the substrate in the processing chamber, wherein the substrate includes a photoresist material deposited on the front surface, bevel edge, and back surface of the substrate; extending the MCA support to lift the substrate above the substrate support; heating the substrate to an elevated temperature using the radiant heat source, wherein the elevated temperature is between 20°C and 170°C; introducing the first etch gas flow to the backside of the substrate; introducing the curtain gas flow at the center of the front surface of the substrate; and 8. The apparatus of claim 1, further comprising: introducing the second etch gas flow to a periphery of the front surface of the substrate, wherein the first etch gas flow and the second etch gas flow have a code for removing at least the photoresist material from the bevel edge and the back surface of the substrate.

9. 9. The apparatus of claim 8, wherein an etch gas in the first etch gas flow and the second etch gas flow comprises a hydrogen halide, hydrogen gas and a halide gas, or boron trichloride, and the photoresist material comprises an EUV resist material.

10. 9. The apparatus of claim 8, wherein the etch gas of the first etch gas flow and the second etch gas flow comprises an oxidizing gas, and the photoresist material comprises a carbon-based material.

11. 9. The apparatus of claim 8, wherein the etch gas of the first etch gas flow and the second etch gas flow comprises a fluorine-containing gas or a chlorine-containing gas, and the photoresist material comprises a silicon-based material.

12. The controller further comprises: performing a post-application bake on the photoresist material by heating the substrate to a desired temperature in the same processing chamber to remove the photoresist material from the bevel edge and backside of the substrate; 12. Apparatus according to any one of claims 8 to 11 configured with instructions including code for:

13. The controller further comprises: dry-depositing the photoresist material on the front surface, bevel edge, and back surface of the substrate, wherein the deposition occurs in the same processing chamber as removing the photoresist material from the bevel edge and back surface of the substrate.

13. Apparatus according to any one of claims 8 to 12, configured with instructions including code for:

14. 1. A method for performing bevel edge and backside cleaning of a substrate, the method comprising: providing a substrate on a substrate support in a processing chamber, the substrate having a photoresist material on a front surface, a bevel edge, and a back surface of the substrate, the substrate being elevated above the substrate support to permit gas flow across the back surface of the substrate; heating the substrate to an elevated temperature, wherein the elevated temperature is between 20°C and 170°C; flowing a curtain gas from a gas distributor above the substrate onto a center of the front surface of the substrate, the curtain gas being flowed through a central gas inlet of the gas distributor; and flowing an etch gas to the backside of the substrate, the etch gas removing at least the photoresist material on the bevel edge and the backside of the substrate, the flowing of the etch gas to the backside of the substrate comprising: directing a first flow of etch gas from gas distribution sources below the substrate to the backside of the substrate; and introducing a second etch gas flow to a periphery of the front surface of the substrate through a peripheral gas inlet of the gas distributor, the peripheral gas inlet being located around the central gas inlet.

15. 15. The method of claim 14, wherein the first etch gas flow is flowed across the backside of the substrate, the second etch gas flow is flowed along the periphery of the frontside of the substrate and the bevel edge of the substrate, and the curtain gas restricts the etch gas flow to a center of the frontside of the substrate.

16. 16. The method of claim 14 or 15, wherein the substrate is heated to the elevated temperature using a radiative heat source below the substrate support.

17. Lifting the substrate above the substrate support using a plurality of MCA supports to create a gap between the substrate support and the backside of the substrate.

17. The method of any one of claims 14 to 16, further comprising:

18. 18. The method of claim 14, wherein the etch gas comprises hydrogen halide, hydrogen gas and a halide gas, or boron trichloride, the photoresist material comprises an EUV resist material, and the curtain gas comprises nitrogen (N), oxygen (O), water (H2O), argon (Ar), helium (He), xenon (Xe), or neon (Ne).

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