Seed substrate for epitaxial growth and method for manufacturing the same, and semiconductor substrate and method for manufacturing the same

Abstract

To provide a seed substrate having less crystal defects, high quality and low cost and for epitaxially and purely growing an III group nitride, such as AlN, AlxGa1-xN (0<X<1) and GaN, and a method for manufacturing the same.SOLUTION: An epitaxial growth seed substrate includes: a support substrate; a flattening layer provided on the upper surface of the support substrate and having a thickness of 0.5-3 μm; and a seed crystal layer provided on the upper surface of the flattening layer. The support substrate includes a polycrystalline ceramic core formed of III group nitride and a sealing layer having a thickness of 0.05-1.5 μm and for sealing the surface voids of the core after being buried and flattened by the oxide, nitride and oxy nitride of Al or Si or the mixtures thereof; and the seed crystal layer is provided by transferring 0.1-1.5 μm of the front surface layer of a Si<111>single crystal having an oxidation induced stacking fault (OSF) of 10 pieces / cm2 or less to a thin film.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a seed substrate for epitaxial growth of high-quality group III nitrides with few surface defects, such as aluminum nitride (AlN), aluminum gallium nitride (Al 1-x Ga 1-x N (where 0 < x < 1), gallium nitride (GaN), and its manufacturing method. More specifically, it relates to a seed substrate for epitaxial growth of group III nitrides such as AlN, Al x Ga 1-x N (0 < X < 1), GaN-based, etc., with extremely few crystal defects, warpage, and voids, and its manufacturing method.

Background Art

[0002] Crystal substrates of group III nitrides such as AlN-based and GaN-based have a wide bandgap and excellent high-frequency characteristics with short-wavelength luminescence and high breakdown voltage. Therefore, substrates of group III nitrides are expected to be applied to devices such as light-emitting diodes (LEDs), lasers, Schottky diodes, power devices, and high-frequency devices. For example, AlN-based crystal substrates, triggered by the recent prevalence of diseases such as the coronavirus, are used for the purpose of removing bacteria and viruses, especially for substrates of light-emitting diodes in the deep ultraviolet region (UVC; 200 - 280 nm) of single crystals of AlN and / or Al x Ga 1-x N (0.5 < X < 1), and the demand is increasing. However, currently, these AlN and / or Al x Ga 1-xA single crystal substrate with N(0.5 < X < 1) has many surface defects, is of low quality, expensive, and even if various devices are fabricated, the expected characteristics cannot be obtained, which restricts the wide spread and expansion of applications of these substrates. On the other hand, with the start of 5G communication and the progress of vehicle electrification, GaN-based crystal substrates are required to have higher high-frequency characteristics and higher breakdown voltage performance. As a result, GaN-based crystal substrates with extremely few crystal defects and low-cost epi and bulk substrates are also in great demand. However, currently, similar to AlN-based crystal substrates, GaN-based crystal substrates also have many surface defects of the crystal, etc., are of low quality, but are expensive, hindering their wide spread to the above-mentioned devices, etc., and further improvement is desired.

[0003] For example, regarding AlN single crystal substrates, as described in Non-Patent Document 1 and Non-Patent Document 2, since AlN does not have a melting point, it is difficult to manufacture by the general melt method such as silicon (Si) single crystal, etc. Usually, silicon carbide (SiC) or AlN is used as a seed crystal and manufactured by the sublimation method (improved Lely method) at 1700 - 2250 °C in an N2 atmosphere, or as disclosed in Patent Document 1 and Non-Patent Document 3, it is made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate or an AlN substrate obtained by the sublimation method. The AlN single crystal by the sublimation method requires high temperature for crystal growth, so currently, due to device limitations, it is at most a small-diameter substrate with a diameter of φ2 - φ4 inches, and is extremely expensive. The dislocation density of the obtained AlN single crystal is <10 5 cm -2 which is relatively small. On the contrary, however, the crystal is colored due to contamination of carbon and metal impurities derived from carbon materials such as crucibles and heat insulators, etc., has a low resistivity, and also has the drawback of low ultraviolet transmittance. On the other hand, the AlN single crystal made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate is relatively inexpensive and has little coloring, but due to the difference in lattice constants between AlN and sapphire, the dislocation density of the AlN crystal is high and has a low resistivity. Also, the AlN crystal obtained by HVPE film formation on an AlN substrate by the sublimation method has a relatively small dislocation density, but is opaque to deep ultraviolet light emission and has a low resistivity due to contamination of coloring substances from the underlying AlN substrate. Moreover, conventionally, the expensive sublimation method AlN crystal is used as it is as the underlying substrate that also serves as a seed crystal, which has the drawback of extremely high cost.

[0004] Regarding GaN substrates, bulk GaN substrates grown in liquids such as liquid ammonia or Na flux are relatively defect-free and high quality, but they are extremely expensive because they require high-temperature, high-pressure equipment. Furthermore, like the AlN substrates grown by the sublimation method described above, they are used directly as a base substrate that also serves as a seed crystal, which results in extremely high costs. On the other hand, heteroepitaxial growth on sapphire substrates using MOCVD or hydride vapor phase epitaxy (HVPE, THVPE), which grow crystals in the vapor phase, is theoretically possible, but in practice, the lattice constants and thermal expansion coefficients of the resulting GaN crystals and the sapphire base substrate differ significantly, resulting in numerous crystal defects and cracks during fabrication and preventing the production of high-quality crystals.

[0005] As one of the solutions to these problems, Patent Document 2 describes a support substrate having an AlN ceramic core and a sealing layer that seals the AlN ceramic core with a multilayer film of SiO2 / P-Si / SiO2 / Si3N4, and a planarization layer of SiO2 or the like on the upper surface of the support substrate. Furthermore, a Si crystal is formed on the upper surface of the planarization layer as a seed crystal. <111> A so-called QST (trade name) substrate is disclosed, which has a seed crystal layer onto which a thin film of

[0006] However, since this method uses polycrystalline ceramics for the core, there are voids on the surface of the ceramics due to solvent volatilization marks, polishing scratches, polycrystalline grain detachment marks, etc., which are inevitably generated during the manufacturing process. During the thin film transfer of the seed crystal, the seed crystal cannot be successfully transferred at the locations with these voids, which causes crystal defects in the subsequent epitaxial growth film. In addition, when using this polycrystalline ceramic as the core, it is easy to cause a difference in the coefficient of thermal expansion between each multilayer film that seals the core, or between the sealing layer, the planarization layer, and the seed crystal layer. Moreover, thermal stress based on the difference in the coefficient of thermal expansion generates cracks, chips, or distortions between the sealing layer, the planarization layer, or the seed crystal layer, or between each layer formed in the subsequent epitaxial film formation process. As a result, it has been found that defects in the seed crystal due to the above-mentioned voids, dirt due to impurity diffusion in the AlN ceramic core, and various distortions also have an adverse effect on the seed crystal, causing various defects in the subsequent epitaxial growth, resulting in a low-performance epitaxial growth film.

[0007] Therefore, it is difficult to obtain AlN and / or Al x Ga 1-x N (0 < X < 1), which has few crystal defects, especially surface defects of the crystal and requires high performance, for example, a substrate for a light-emitting diode used in the deep ultraviolet region (UVC; 200 - 280 nm) of extremely ultra-short waves, or a GaN crystal substrate suitable for high-frequency and high breakdown voltage requirements associated with 5G communication and the electrification of vehicles, with few crystal defects, high quality, and low cost. Furthermore, new solutions have been desired.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0009]

Non-Patent Document 1

[0010] The present inventors have conducted various studies to solve the above problems, and have arrived at the present invention. That is, the present invention provides a seed substrate for epitaxial growth with few defects, especially surface defects, and a method for producing the same, which comprises the steps of (1) filling and flattening the surface voids of a polycrystalline ceramic core with an oxide, nitride, oxynitride of Al or Si, or a mixture thereof, (2) sealing the core with a sealing layer of 0.05 to 1.5 μm, and then (3) forming a seed crystal layer using Si <111> The surface layer of the single crystal is transferred to a thin film of 0.1 to 1.5 μm, and (4) a stress adjustment layer is provided as the bottom layer as required.

[0011] Hitherto, although the role of the substrate as described above as a seed crystal has been somewhat understood, the causal relationship between the properties of the Si<111> seed crystal at the time of its transfer and the subsequent epitaxial film formation has not necessarily been fully understood. Therefore, the present inventors conducted many experiments and found that (1) when surface voids exist in the core polycrystalline ceramic substrate, even if a sealing layer or a planarizing layer is interposed between the ceramic substrate and the seed crystal layer, the influence of the voids cannot be completely removed, and a part of the surface voids also affects the transferred seed crystal and causes defects. In addition, (2) there is a large causal relationship between the original properties of the seed crystal Si<111> and the defects in the epitaxial film formation. Furthermore, (3) the strain due to the thermal stress difference occurring between the layers and the contamination from the core, etc. affect the Si<111> seed crystal and increase the defects in the epitaxial film formation.

[0012] From these experimental results, in order to obtain a seed substrate for epitaxial growth of group III nitrides such as AlN, Al x Ga 1-x N(0 < X < 1), GaN, etc. with few defects, high characteristics, and low cost, it is necessary to reduce the surface voids of the above-mentioned core polycrystalline ceramics, reduce the thermal stress by the optimal film thickness and film quality of various sealing layers, planarizing layers, and seed crystal layers. Furthermore, in addition to strain and contamination, the oxidation-induced stacking fault (OSF) of the seed crystal Si<111> (described in Patent Document 3) is 10 per cm 2 Hereinafter, it was found that the thin film transfer with a thickness of 0.1 to 1.5 μm is extremely good, and the subsequent epitaxial film shows favorable results, and the device characteristics are also good.

[0013] Note that the number of oxidation-induced stacking faults (OSF) of the present invention (per cm 2 ) was measured by the evaluation method of Patent Document 3.

Means for Solving the Problems

[0014] In order to achieve the above object, the present invention provides a seed substrate for epitaxial growth according to an embodiment of the present invention, which comprises a support substrate, a 0.5 to 3 μm planarization layer provided on the upper surface of the support substrate, and a seed crystal layer provided on the upper surface of the planarization layer. The support substrate includes a core planarized by filling surface voids of a group III polycrystalline nitride with an oxide, nitride, oxynitride of Al or Si, or a mixture thereof, and a sealing layer of 0.05 to 1.5 μm that seals the core. The seed crystal layer is made of Si <111> The surface layer of the single crystal is formed by thin film transfer of 0.1 to 1.5 μm. <111> It is provided by thin film transfer of the surface layer of the single crystal to a thickness of 0.1 to 1.5 μm.

[0015] In the present invention, the group III nitride polycrystalline ceramics forming the core are preferably AlN ceramics.

[0016] In the present invention, the sealing layer preferably includes at least a layer of Si3N4.

[0017] In the present invention, the planarization layer is made of SiO2 and / or silicon oxynitride (Si x O y N z ) or AlAs.

[0018] In the present invention, the Si forming the seed crystal layer <111> is an oxidation-induced stacking fault (OSF) density of 10 / cm 2 It would be better if it was below.

[0019] In the present invention, it is preferable to further provide a stress adjustment layer on the bottom surface of the support substrate.

[0020] In the present invention, the sealing layer is preferably formed by the LPCVD method.

[0021] In the present invention, the planarizing layer may be formed on one side or the entire top surface of the support substrate, or AlAs may be formed by plasma CVD, LPCVD, or low-pressure MOCVD.

[0022] In the present invention, the seed crystal layer is Si <111> It is preferable that the single crystal is ion-implanted with hydrogen and / or He, and then a thin film of 0.1 to 1.5 μm is transferred by physical means at 450° C. or less to form the layer.

[0023] In the present invention, the stress adjustment layer is formed of a material selected from SiO2, Si3N4, amorphous Si, polycrystalline Si, etc., alone or in combination, having a thermal expansion coefficient that can be corrected according to the state of warpage after the planarization layer is provided. However, when considering compatibility with an electrostatic chuck, the bottom layer of the support substrate is at least polycrystalline Si prepared by a method selected from the group consisting of sputtering, plasma CVD, and LPCVD, or SiO2 and / or silicon oxynitride (Si) that has affinity with the sealing layer. x O y N z It is preferable to interpose a polycrystalline Si film between the polycrystalline Si layers. When using polycrystalline Si film deposition, which serves both as stress adjustment and electrostatic chuck, the polycrystalline Si itself or amorphous Si may be polycrystallized by heating or laser, etc. The reason for placing the polycrystalline Si film at the bottom is that the electrostatic chucking force is stronger the shorter the distance, as the film has high conductivity.

[0024] A semiconductor substrate according to an embodiment of the present invention is characterized in that a III-V semiconductor thin film is formed on the upper surface of any one of the above seed substrates for epitaxial growth. The III-V semiconductor thin film is preferably a nitride semiconductor thin film containing Ga and / or Al.

[0025] Furthermore, a method for producing a seed substrate for epitaxial growth according to an embodiment of the present invention includes the steps of preparing a core in which surface voids of a group III nitride polycrystalline ceramic are filled with an oxide, nitride, oxynitride of Al or Si, or a mixture thereof, and planarized; forming a sealing layer having a thickness of 0.05 μm to 1.5 μm so as to enclose the core, thereby forming a support substrate; forming a planarization layer having a thickness of 0.5 μm to 3.0 μm on the upper surface of the support substrate; and forming a Si <111> and providing a seed crystal layer by thin-film transferring a surface layer of 0.1 to 1.5 μm of the single crystal.

[0026] In the present invention, the oxidation-induced stacking faults (OSFs) on the top surface of the planarization layer are 10 / cm. 2 Si <111> It is advisable to provide a seed crystal layer by thin-film transferring the surface layer of the single crystal to a thickness of 0.1 to 1.5 μm.

[0027] In the present invention, the sealing layer is preferably formed by the LPCVD method.

[0028] In the present invention, the planarization layer is formed on one side or the entire surface of the upper surface of the support substrate by forming SiO2 and / or silicon oxynitride (Si x O y N z ) or AlAs may be formed by plasma CVD, LPCVD, or low-pressure MOCVD.

[0029] In the present invention, the OSF is 10 / cm 2 Si <111> After hydrogen and / or He ions are implanted into the single crystal, a seed crystal layer may be provided by transferring a thin film of 0.1 to 1.5 μm by physical means at 450° C. or less.

[0030] The present invention may further include a step of providing a stress adjustment layer on the bottom surface of the support substrate, which has a thermal expansion coefficient that enables further correction of warpage after the planarization layer is provided, and is preferably made of polycrystalline silicon formed by at least a method selected from the group consisting of sputtering and LPCVD.

[0031] Furthermore, a method for manufacturing a semiconductor substrate according to an embodiment of the present invention includes the steps of manufacturing a seed substrate for epitaxial growth by any of the methods for manufacturing a seed substrate for epitaxial growth described above, and forming a III-V semiconductor thin film on an upper surface of the seed substrate for epitaxial growth. [Effects of the Invention]

[0032] The present invention provides AlN and / or Al substrates for light-emitting diodes used in the deep ultraviolet region (UVC; 200 to 280 nm). x Ga1-x For N (0 < X < 1), or for epitaxial and bulk epitaxial growth of group III nitrides such as GaN crystal substrates suitable for high frequency and high breakdown voltage accompanying 5G communication and the electrification of vehicles, it is possible to provide a seed substrate with few defects, high quality, and low cost.

Brief Description of Drawings

[0033] [Figure 1] It is a figure showing the cross-sectional structure of the seed substrate 1. [Figure 2] It is a figure showing the procedure for manufacturing the seed substrate 1.

Embodiments for Carrying Out the Invention

[0034] Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

[0035] The cross-sectional structure of the seed substrate 1 for epitaxial growth of group III nitrides according to this embodiment (hereinafter, may be simply referred to as "seed substrate") is shown in FIG. 1. The seed substrate shown in FIG. 1 has a structure in which a planarization layer 4 and a Si <111> seed crystal layer 2 are laminated on a support substrate 3. Further, if necessary, a stress adjustment layer 5 is provided on the surface (lower surface) of the support substrate 3 opposite to the surface on which the planarization layer 4 is laminated.

[0036] The support substrate 3 includes a core 31 serving as the core material of the support substrate 3 and a sealing layer 32 covering the core 31.

[0037] The core 31 is formed from a polycrystalline group-III nitride ceramic. While AlN, Si3N4, GaN, or a mixture of these can be used, polycrystalline AlN ceramics are preferred due to their lattice constant and thermal expansion coefficient, high thermal conductivity, and low cost. From a device processing perspective, mirror-finished wafers with a thickness of 200–1000 μm, which are suitable for semiconductor manufacturing, are recommended. While there are various methods for manufacturing AlN ceramics, the so-called sheet molding / pressureless sintering method is the most common due to its productivity and economical advantages. In this method, AlN powder is mixed with sintering aids, organic binders, and solvents to create a wafer-shaped green sheet, which is then degreased, sintered in a N2 atmosphere, and polished to produce the final product. Sintering aids are selected from Y2O3, Al2O3, CaO, etc., but Y2O3 is typically preferred, as it exhibits the highest thermal conductivity in the sintered substrate.

[0038] The polycrystalline ceramic substrate obtained by the above process usually has surface voids with depths of several hundred nm to several tens of μm due to traces of degreasing during sintering and traces of grain removal during polishing, even if the product is finished to an average smoothness of several nm. As mentioned above, these voids are generated by the seed crystal Si <111> This adversely affects the thin film transfer process and easily causes defects in the subsequent epitaxial growth. Therefore, in this invention, the surface voids of these ceramic substrates are filled with oxides, nitrides, oxynitrides of Al or Si, or a mixture of these, and the surface is flattened before being used as a core. More specifically, a silicone compound and / or a silicone compound containing at least SiO2, Si3N4, or AlN powder is applied to the surface of a polycrystalline ceramic, which is then treated in an N2 atmosphere to fill the surface voids and flatten the surface before being used as a core.

[0039] However, if the embedded and flattened AlN ceramic is used as the core 31 as is, metal impurities in the raw AlN and Y2O3 powders, as well as carbon, oxygen, and other impurities from the insulation, furnace materials, and containers used during sintering, will become sources of contamination and have adverse effects on the target single crystal, such as crystal defects and coloration.

[0040] For this reason, a sealing layer 32 is provided to encase and seal the embedded and flattened polycrystalline ceramic core 31 and protect it from various sources of contamination. When sealing the core 31 with the sealing layer 32, it is necessary to consider the composition and thickness of each layer constituting the sealing layer 32 so that thermal stress is as small as possible and thermal conduction is as large as possible. In the present invention, it is preferable to optimize the total thickness of the sealing layer 32 within the range of 0.05 to 1.5 μm from the viewpoint of manufacturing costs.

[0041] The composition of the sealing layer 32 can be selected appropriately taking into consideration the thermal expansion coefficient and thermal conductivity, but in order to further enhance its ability to prevent impurity diffusion, it is preferable to cover and seal the entire surface with a film made of at least silicon nitride (Si3N4).

[0042] If necessary, for example, if an electrostatic chuck is to be used, p-Si may be provided as a layer for the electrostatic chuck in this sealing layer 32. This p-Si layer may be formed between the AlN ceramic and the Si3N4 layer, or may be provided together with or below the stress adjustment layer 5, which will be described later. In this case, if the adhesiveness between the p-Si and the AlN core and Si3N4 is insufficient, a layer with high adhesive properties such as SiO2 or silicon oxynitride (Si x O y N z ) or other membranes may be used.

[0043] In the case of epitaxial growth seed substrates for III-nitrides such as GaN for high frequency applications, especially for ultra-high frequencies such as giga and millimeter waves, the above-mentioned Si <111> The electrical resistivity (at room temperature) of the seed crystal layer 2 is preferably 1 kΩ·cm or more. This is because the electrical resistivity (at room temperature) of the Si <111> This is because in the seed crystal layer 2, high frequency loss due to giga and millimeter waves increases, causing the device to generate heat and consume large amounts of power, preventing the device from achieving its desired characteristics.

[0044] When providing a p-Si film for electrostatic chucks, a p-Si film with higher resistance is preferable as long as it provides the necessary clamping force. It can be deposited as a lower layer of the core 31 as far away as possible from the seed crystal layer 2 on which the epitaxial film is deposited, or beneath the stress adjustment layer 5 (described below), or it can be deposited simultaneously with the stress adjustment layer 5 as a multilayer film. High-resistivity p-Si has low high-frequency loss, and when placed at the bottom of the support substrate 3, it is close to the electrostatic chuck, generating sufficient electrostatic force even with high resistance. Therefore, sufficient substrate clamping is possible without doping. To further reduce high-frequency loss, it is preferable to remove the p-Si layer by backgrinding the substrate at the end of device fabrication. When providing the stress adjustment layer 5, maintaining the p-Si resistance as high as possible is preferable, but there are no restrictions on the minimum amount of doping with boron (B), phosphorus (P), etc. required to generate the necessary electrostatic force.

[0045] If the thickness of each layer in the sealing layer 32 is too large, the stress between the layers due to the difference in thermal expansion coefficients will increase, resulting in delamination between the layers. Therefore, even if films of various compositions are selected and combined, it is undesirable for the thickness of the sealing layer 32 to be 1.5 μm or more. On the other hand, from the perspective of the function of sealing impurities, a thickness of 0.05 μm or less is insufficient to prevent impurity diffusion. For these reasons, it is preferable that the thickness of the sealing layer 32 be in the range of 0.05 to 1.5 μm. The sealing layer can be formed by a method selected from conventional film formation methods such as MOCVD, atmospheric pressure CVD, LPCVD, and sputtering. However, LPCVD is particularly preferred in terms of film quality, film coverage, and impurity diffusion prevention capabilities.

[0046] A planarization layer 4 having a thickness of 0.5 to 3 μm is laminated on at least the sealing layer 32 on the upper surface of the support substrate 3. This planarization layer 4 is made of SiO2, Al2O3, Si3N4, SiC or silicon oxynitride (Si x O y N z ), or Si, GaAs, AlAs, etc., which are often used as sacrificial layers in etching, etc. However, SiO2 and / or silicon oxynitride (Si), which are easy to grind and polish during planarization and easy to separate when obtaining a pure substrate, etc., are also used.x O y N z ) or AlAs.

[0047] For cost reasons, the planarization layer 4 is typically laminated on only one side of the sealing layer 32. However, if warpage is significant, it can be formed to cover the entire sealing layer 32. The function of the planarization layer 4 is, as the name suggests, to provide a flat surface for thin-film transfer of the seed crystal. Its thickness must be sufficient to fill voids and irregularities in the core 31, sealing layer 32, etc., while still providing a sufficiently flat surface for transfer of the seed crystal. However, a planarization layer 4 that is too thick can cause warping and cracks in the seed substrate 1, making it undesirable. Therefore, it is preferable to provide a planarization layer 4 with a thickness of at least 0.5 to 3 μm on the top surface of the sealing layer. This is because a thickness less than 0.5 μm is insufficient to fill the voids and irregularities in the AlN ceramic core 31 and sealing layer 32, while a thickness greater than 3 μm is likely to cause warpage due to the planarization layer 4. However, as mentioned above, polycrystalline ceramic substrates typically have numerous surface voids with depths ranging from several hundred nanometers to several tens of micrometers. To solve the dilemma between the above constraints and the actual depth of surface voids, the present invention first solves the problem by "filling the surface voids of the ceramic substrate with a silicone compound and / or a silicone compound containing at least one of SiO2, Si3N4, and AlN powder, applying it to the surface of the polycrystalline ceramic, then treating it in an N2 atmosphere to fill the surface voids, flattening it, and then using it as a core." Note that if the silicone compound is an alkoxysilane and / or its condensate, this is particularly effective in filling the voids and facilitating subsequent flattening, making it preferable.

[0048] The method for forming the flattening layer 4 is preferably a plasma CVD method, an LPCVD method, or a low-pressure MOCVD method, from the viewpoint of the required film quality and film formation efficiency. x O y N z ) or AlAs, depending on the state of the film, is subjected to heat treatment for densification and CMP polishing for flattening, in preparation for thin film transfer of the seed crystal layer 2 described below.

[0049] The crystal is a substrate with a crystal structure similar to group III nitrides such as AlN, Al x Ga 1-x N (0 < X < 1), GaN, etc. are selected. Therefore, Si<111>, SiC, SCAM, AlN, AlGaN, sapphire, etc. are considered. However, Si<111> is preferred in terms of ease of increasing the diameter, availability of commercial products, and low cost. Among them, among Si<111> crystals, a Si<111> single crystal with an oxidation-induced stacking fault (OSF) of 10 or less per cm 2 is particularly suitable as described above.

[0050] This is because when the OSF of the Si<111> seed crystal, which serves as the seed for the next-step epitaxial film formation, is 10 or less per cm 2 the epitaxially grown crystal also follows the seed crystal, has few defects, and ultimately the device using it also has high characteristics and high yield, resulting in low cost. On the other hand, when the OSF exceeds 10 per cm 2 the defects in the epitaxially grown crystal increase rapidly, the device characteristics deteriorate, and inevitably the yield also deteriorates, resulting in high cost.

[0051] Also, when using the epi and bulk substrates obtained by epitaxial film formation on the seed substrate 1 for high-frequency devices, especially for high-frequency devices after 5G, it is preferable to select a Si<111> seed crystal with an electrical resistivity (room temperature) of 1 kΩ·cm or more. This is because when the electrical resistivity (room temperature) of the Si<111> seed crystal is less than 1 kΩ·cm, high-frequency loss occurs due to its resistance, the power consumption increases, heat is generated, and the characteristics of the device deteriorate.

[0052] Si <111> The seed crystal is implanted with ions limited to hydrogen and / or helium (He) ions, which have little effect on the electrical resistance of the single crystal substrate, and then Si <111> The ion-implanted surface of the seed crystal is bonded to the top surface of the planarization layer 4, and a thin film of 0.1 to 1.5 μm is peeled and transferred to the planarization layer 4 at 450°C or less using a physical means such as a fingernail, to form the seed crystal layer 2. Unlike heavy elements such as boron (B), light elements such as hydrogen and He are suitable for ion implantation into the seed crystal because they cause little damage to the seed crystal due to ion implantation and do not reduce electrical resistance. Furthermore, by performing peeling and transfer at a low temperature of 450°C or less, it is possible to avoid the formation of Si, which is unavoidable in the thermal peeling and transfer at a high temperature of 700°C or more in the conventional Smart Cut method. <111> This can prevent heat damage to the seed crystal.

[0053] The transfer thickness of the seed crystal layer 2 is preferably 0.1 to 1.5 μm. In ion implantation, the damage layer alone has a thickness of approximately 0.1 μm, and if it is less than 0.1 μm, good seed crystals cannot be obtained. Furthermore, if the transfer thickness is 1.5 μm or more, the ion implanter requires high-output ion energy, which makes the ion implanter huge, requiring a huge investment and making it uneconomical.

[0054] More specifically, hydrogen and / or He ions are implanted into the seed crystal to a depth of 0.2 to 3.5 μm, and then the upper surface of the planarizing layer 4 is bonded to the ion-implanted surface of the seed crystal. Thereafter, the seed crystal may be peeled off at a temperature of 450°C or less by a physical method such as gas pressure or a fingernail.

[0055] The top surface of the transferred thin film is then polished by CMP and / or lightly etched with a chemical solution to remove the layer damaged by the ion implantation, thereby obtaining a seed single crystal thin film (seed crystal layer 2) with a thickness of 0.1 to 1.5 μm. If higher uniformity is required for the ion implantation, it is recommended to form a film of SiO2 or the like on the ion implantation surface of the seed substrate as necessary before the ion implantation.

[0056] In the present invention, a stress adjustment layer 5 may be further added to the bottom surface of the support substrate 3 as needed. For the stress adjustment layer 5, a film material and thickness are selected that have a thermal expansion coefficient that allows for correction of warpage of the seed substrate 1 caused by the formation of the planarization layer 4. Usually, it is preferable to form at least polycrystalline Si (p-Si) as the stress adjustment layer 5, which also serves as a material for use with an electrostatic chuck. From the viewpoint of warpage correction and affinity with the sealing layer 32, SiO2 and / or silicon oxynitride (Si) may be formed between the polycrystalline Si and the sealing layer as part of the stress relaxation layer. x O y N z ) may be inserted.

[0057] Next, the steps of the method for manufacturing the III-nitride-based epitaxial growth seed substrate 1 according to this embodiment will be described with reference to Fig. 2. Note that in cases where a suitable method for forming each layer has already been described together with the configuration of each part of the seed substrate 1, a duplicated description will be omitted here.

[0058] First, a core 31 made of nitride ceramic is prepared (S01 in FIG. 2). Then, the surface voids of the nitride ceramic core are filled and flattened with an oxide, nitride, or oxynitride of Al or Si, or a mixture of these. More specifically, a silicone compound and / or a silicone compound to which at least one of SiO2, Si3N4, or AlN powder is added is applied to the surface of the polycrystalline ceramic, and then the polycrystalline ceramic is treated in an N2 atmosphere to fill and flatten the surface voids, resulting in the core 31. Next, a sealing layer 32 is formed to a thickness of 0.05 μm to 1.5 μm so as to encase the core 31, thereby forming the support substrate 3 (S02 in FIG. 2). At this time, the sealing layer 32 is formed by the LPCVD method and includes at least a layer of Si3N4, and may contain SiO2 or silicon oxynitride (Si) as needed. x O y N z ) may be added. Next, a planarization layer 4 having a thickness of 0.5 μm or more and 3.0 μm or less is formed on the upper surface of the support substrate 3 (S03 in FIG. 2). Furthermore, if necessary, a stress adjustment layer 5 is formed on the lower surface of the support substrate 3 (S04 in FIG. 2). The planarization layer 4 and the stress adjustment layer 5 may be formed simultaneously.

[0059] In addition to S01 to S04, a Si crystal layer is used as a seed crystal for peeling and transferring the seed crystal layer 2. <111> A single crystal substrate 20 is prepared (S11 in FIG. 2). Subsequently, ions are implanted into one surface (ion-implanted surface) of the single crystal substrate 20 to form a separation position (embrittled layer) 21 in the single crystal substrate 20 (S12 in FIG. 2).

[0060] Next, the ion-implanted surface of the single crystal substrate 20 is bonded to the planarization layer 4 formed on the support substrate 3 to form a bonded substrate (S21 in FIG. 2). Then, the single crystal substrate 20 is separated at the separation position 21 of the single crystal substrate 20 in the bonded substrate (S22 in FIG. 2). By doing so, a Si <111> The single crystal film of Si is transferred as a seed crystal layer 2. <111> The remaining portion of the single crystal substrate 20 can be repeatedly used for thin-film transfer of a seed crystal layer when producing another group III nitride-based composite substrate by polishing the surface again to form an ion-implanted surface.

[0061] The structure of the epitaxial growth seed substrate 1 and the manufacturing method thereof have been described above. The present invention is based mainly on the following points: 1) the surface voids of the polycrystalline ceramic substrate, which serves as the core, affect the ceramic substrate and the seed crystal layer, and areas near the voids are the cause of frequent defects; 2) the seed crystal Si <111> The original properties of Si affect epitaxial growth, and the seed crystal Si is also important for reducing crystal defects. <111> Oxidation-induced stacking faults (OSFs) of 10 / cm 2 The present invention is based on the findings that: 1) it is preferable to have a thickness of 1000 nm or less, 2) it is preferable to have a thickness of 1000 nm or less, 3) it is important to select an optimum thickness and film quality for each of the various sealing layers, planarizing layers, and seed crystal layers, and 4) it is possible to balance thermal stresses even in stress adjustment layers, and it is possible to utilize the synergistic effects of each of the above 1) to 4) or a combination of these.The present invention makes it possible to economically obtain seed substrates for epitaxial growth with extremely little warping, voids, crystal defects, etc., as well as epitaxial substrates and solid substrates with extremely little high-frequency loss in devices.

[0062] The substrate of the present invention can significantly improve the properties of devices such as light-emitting diodes used in the deep ultraviolet region (UVC; 200 to 280 nm), high-frequency devices for 5G communications and electric vehicles, or high-voltage devices, and can also significantly improve the manufacturing yield of the devices. [Example]

[0063] The present invention will be explained in more detail below with reference to examples and comparative examples, but the present invention is not limited to these examples.

[0064] [Example 1] (Preparation of support substrate) A support substrate 3 was prepared, having a structure in which a polycrystalline ceramic core 31 was covered with a sealing layer 32. A commercially available AlN substrate was used for the polycrystalline ceramic core 31. For this AlN substrate, 100 parts by weight of AlN powder and 5 parts by weight of Y2O3 as a sintering aid were mixed with an organic binder, solvent, etc. to create a green sheet, which was then degreased and sintered at 1900°C in an N2 atmosphere, and both sides were polished by CMP to prepare a core substrate measuring φ8 inches x thickness 725 μm.

[0065] The substrate surface contained 1,500 voids, each 3 μm deep or larger, that were difficult to fill with a flattening layer. The entire surface of the AlN ceramic substrate was coated with a mixture of alkoxysilane condensate and silica, X-12-2220BC-3 solution (Shin-Etsu Chemical Co., Ltd.; a composition primarily composed of hydrolysis condensate of methyltrimethoxysilane, colloidal silica, and isopropanol; solids concentration: 20%). After drying, the substrate was treated in a N2 atmosphere at 1,000 °C to fill the voids on the substrate surface. The surface was then lightly polished and flattened by CMP. The entire AlN ceramic core 31 was then covered with a 0.1 μm-thick silicon oxynitride layer by LPCVD. A 0.4 μm-thick Si3N4 layer was then deposited on top of this using another LPCVD apparatus to seal the entire surface, forming a sealing layer 32. The total thickness of the sealing layer 32 was 0.5 μm. For the purpose of further planarization, a 6 μm thick SiO2 was laminated on only one side of the upper layer on this Si3N4 layer using the plasma CVD method (ICP-CVD apparatus). After that, it was baked at 1000 °C, and then the SiO2 was planarized to a thickness of 2 μm (Ra = 0.2 nm) by CMP polishing in preparation for thin film transfer of the seed crystal.

[0066] (Seed crystal preparation) The evaluation in Patent Document 3 showed that the number of oxidation-induced stacking faults (OSF) was 9 / cm 2 A φ8-inch, 725 μm-thick Si substrate with an electrical resistivity (room temperature) of 1.3 kΩ·cm. <111> A single crystal substrate was prepared as a seed crystal substrate. Hydrogen was ionized into this Si substrate at 100 keV with a depth of 0.6 μm and a dose of 9 × 10 16 cm -2 The ions were implanted under the following conditions.

[0067] The ion-implanted Si was applied to the planarization layer 4 (thickness: 2 μm) of the support substrate 3 that had been prepared previously. <111> The surface layer of the single crystal (0.6 μm) was transferred to a thin film. <111> The damaged area of ​​the single crystal was lightly polished by CMP, and the Si <111> The single crystal layer had a thickness of 0.4 μm and was used as seed crystal layer 2. The obtained seed substrate 1 was free from cracks, film peeling, and warpage as a result of the film thicknesses between the layers of sealing layer 32, sealing layer 32, planarizing layer 4, and seed crystal layer 2 being balanced with the thermal stresses.

[0068] The remaining Si after thin film transfer <111> By repeatedly performing ion implantation on the single crystal substrate, it can be repeatedly used as a large number of seed crystals, making it extremely economical.

[0069] In this embodiment, a support substrate 3 having a structure of an AlN ceramic core 31 and a sealing layer 32 is provided with a planarization layer 4 having a thickness of 2 μm and a Si <111> A seed substrate 1 was obtained having a single crystal seed crystal layer 2. The properties of this seed substrate 1 as a seed substrate for epitaxial growth of GaN were evaluated simply as follows.

[0070] The seed substrate 1 was placed in the reactor of an MOCVD apparatus, and epitaxial growth was carried out. During this process, AlN and AlGaN were deposited in this order from the seed substrate 1 side toward the growth direction, followed by epitaxial growth of GaN. In this evaluation, an AlN layer of 100 nm and an AlGaN layer of 150 nm were deposited. The total thickness of the epitaxial layers was 10 μm. During epitaxial growth, TMAl (trimethylaluminum) was used as the Al source, TMGa (trimethylgallium) as the Ga source, and NH3 as the N source. The carrier gas was N2 with 10% H2 added, and the process temperature was 1100°C.

[0071] To evaluate the dislocation density, etch pits were generated by molten alkali (KOH) etching and the etch pit density (EPD) was measured. X-ray rocking curve (XRC) measurements were also performed to evaluate the crystallinity.

[0072] As a result, the EPD is 0.1 × 10 4 cm -2The dislocation density was extremely low. Furthermore, the full width at half maximum (FWHM) of the (0002) plane of the substrate measured by XRC (hereinafter simply referred to as "0002 XRC FWHM") was 10 arcsec, indicating that high-quality GaN single crystals were obtained. These results demonstrate that the seed substrate 1 of this example has excellent properties as a seed substrate for epitaxial growth. When an epitaxial substrate having an epitaxial layer formed on this seed substrate 1 was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 39°C, and the temperature rise due to high-frequency loss was small.

[0073] [Comparative Example 1] The AlN ceramic substrate was used as a core substrate without filling or flattening the surface voids, and the epitaxial film was formed under the same conditions as in Example 1. Evaluation was then carried out in the same manner. As a result, crystal defects of a size similar to the voids were observed in the epitaxial film at locations corresponding to the voids, and device failures frequently occurred in those areas. The EPD was 211 x 10 4 cm -2 The dislocation density was 1000 MHz. Furthermore, the full width at half maximum (FWHM) of the (0002) plane of the substrate measured by XRC (hereinafter simply referred to as "0002 XRC FWHM") was 863 arcsec, indicating that a GaN single crystal with poor crystallinity was obtained. These results indicate that the seed substrate for epitaxial growth of seed substrate 1 in this example had many epitaxial defects, including voids. This caused a decrease in yield in subsequent device fabrication. When this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device in the void-free portion, the device surface temperature was 39°C. Although the temperature increase due to high-frequency loss was small, the voided portion of the epitaxial substrate made it difficult to fabricate devices, resulting in a decrease in device yield.

[0074] [Example 2] (Preparation of support substrate) The polycrystalline ceramic core 31 was the same commercially available AlN substrate as in Example 1. Note that the surface of this substrate contained 2,500 voids, each 3 μm deep or larger, that were difficult to fill with a flat layer. A silicone compound containing 5% AlN powder added to Shin-Etsu Chemical's KBM-3103 or X-12-641 was applied to the entire surface of this AlN ceramic substrate. After drying, the AlN powder surface was converted to SiN, filling the voids on the substrate surface. The surface voids were then flattened by CMP polishing. The flattened AlN ceramic core 31 was first completely encapsulated in a 0.3 μm-thick SiO layer using the LPCVD method, and then a 0.8 μm-thick SiN layer was applied on top of that using another LPCVD apparatus to seal the entire surface, forming the sealing layer 32. The total thickness of the sealing layer 32 was 1.1 μm. For the purpose of further planarization, a 5 μm layer of silicon oxynitride was laminated on top of this Si3N4 layer by LPCVD, only on the upper layer of the sealing layer 32. The silicon oxynitride layer was then polished to a thickness of 2.5 μm by CMP. At this stage, the entire substrate had warped significantly, approximately 30 μm. To correct this warpage, a stress adjustment layer 5 of SiO2 5 μm thick and 0.2 μm of undoped polycrystalline Si, which also served as an electrostatic chuck, were applied to the bottom surface by plasma CVD. As a result, the warpage was almost completely eliminated, and the substrate was able to be used as an electrostatic chuck with sufficient adhesion and desorption.

[0075] (Seed crystal preparation) The evaluation in Patent Document 3 showed that the number of oxidation-induced stacking faults (OSF) was 0 / cm 2 A single-crystal Si wafer with a diameter of 8 inches and a thickness of 725 μm has an electrical resistivity (room temperature) of 2.3 kΩ·cm. <111> A substrate was prepared as a seed crystal substrate. Hydrogen was ionized into this Si substrate at 130 keV to a depth of 1.4 μm with a dose of 9.5 × 10 16 cm -2 The ions were implanted under the following conditions.

[0076] The ion-implanted Si was applied to the planarization layer 32 (thickness: 2.5 μm) of the support substrate 3 that had been prepared previously. <111> The surface layer of the single crystal, 1.4 μm thick, was transferred to a thin film. <111> The damaged area of ​​the single crystal was lightly polished by CMP, and the Si <111> The single crystal layer had a thickness of 1 μm and was used as seed crystal layer 2. The thickness of the obtained seed substrate 1 was adjusted so that the thermal stresses between the layers of sealing layer 32, sealing layer 32, planarizing layer 4, and seed crystal layer 2 were balanced, and as a result, there were no cracks, film peeling, or warpage.

[0077] The remaining Si after thin film transfer <111> The single crystal substrate can be repeatedly used as a large number of seed crystals by repeatedly performing ion implantation in the same manner as in Example 1, which is extremely economical.

[0078] In this embodiment, a support substrate 3 having a structure of an AlN ceramic core 31 and a sealing layer 32 is provided with a 2.5 μm thick flattening layer 4 and a 1 μm thick Si <111> A seed substrate 1 was obtained having a single crystal seed crystal layer 2. Using this substrate 1, an AlN thick film single crystal substrate was produced as follows.

[0079] A 600 μm thick AlN single crystal film was grown on this seed substrate 1 using the THVPE method with AlCl3 and NH3 as raw materials. This grown thick AlN single crystal film was cut with a wire saw and polished to create smooth φ8-inch AlN single crystal substrates. Furthermore, these cut AlN single crystal substrates were colorless and had a transmittance of approximately 80% for light with a wavelength of 220 nm when converted to a film thickness of 100 μm. Next, this substrate was simply evaluated as a seed substrate for AlN epitaxial growth.

[0080] A 2 μm thick AlN film was formed on the AlN substrate by MOCVD, and EPD measurements were performed to generate etch pits by molten alkali (KOH) etching to evaluate dislocation density in the same manner as in Example 1. X-ray rocking curve (XRC) measurements were also performed to evaluate crystallinity.

[0081] As a result, the EPD is 0.4 × 10 4 cm -2The result showed an extremely low dislocation density. Furthermore, the FWHM of the 0002XRC was 100 arcsec, and a high-quality AlN single crystal was obtained. This AlN single crystal had extremely few defects as an LED substrate for the deep ultraviolet region, had high device characteristics, and was an economically excellent substrate with no yield reduction due to voids.

[0082] Comparative Example 2 Oxidation-induced stacking faults (OSFs) are 18 / cm 2 , an 8-inch diameter single-crystal Si substrate with an electrical resistivity (room temperature) of 0.5 kΩ·cm <111> A seed substrate 1 was produced under the same conditions as in Example 1, except that a single crystal substrate was used as the seed crystal substrate and a seed crystal layer 2 with a thickness of 1.3 μm was thin-film transferred onto the seed substrate 1. A 5 μm thick GaN film was also formed on this seed substrate 1 by MOCVD, as in Example 1. As a result, the EPD was 65×10 4 cm -2 The result showed an extremely large dislocation density. The FWHM of 0002XRC was 780 arcsec, resulting in a GaN single crystal with poorer crystallinity than that of Example 1. When this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device rose to a high temperature of 130°C due to high-frequency loss, making it impossible to use for a long period of time.

[0083] [Example 3] A seed substrate 1 for epitaxial growth was obtained under the same conditions as in Example 1, except that the planarization layer 4 in Example 1 was a two-layer SiO / AlAs planarization layer 4 having a total thickness of 2.8 μm, which was composed of a 2 μm thick lower AlAs layer and a 0.8 μm thick upper SiO layer.

[0084] The remaining Si after thin film transfer <111> By repeatedly performing ion implantation on the single crystal substrate, it can be repeatedly used as a large number of seed crystals, making it extremely economical.

[0085] In this embodiment, a support substrate 3 having a structure of an AlN ceramic core 31 and a sealing layer 32 is provided with a SiO2 / AlAs composite planarization layer 4 having a total thickness of 2.8 μm, and a 0.9 μm thick Si <111> A seed substrate 1 was obtained having a single crystal seed crystal layer 2. This seed substrate 1 was used as a seed substrate for epitaxial growth of GaN to epitaxially grow a thick GaN film.

[0086] After forming a 180 μm thick GaN film on the seed substrate 1 by MOCVD, the SiO 2 / AlAs planarization layer 4 was dissolved in an HF aqueous solution to obtain a pure GaN substrate having a thickness of approximately 180 μm.

[0087] To evaluate the dislocation density of this pure GaN substrate, etch pits were generated by molten alkali (KOH) etching and EPD measurements were performed, similar to the evaluation in Example 1. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

[0088] As a result, the EPD is 0.1 × 10 4 cm -2 The dislocation density was extremely low. Furthermore, the FWHM of the 0002XRC was 130 arcsec, and high-quality GaN single crystals were obtained. These figures demonstrate that seed substrate 1 of this example is extremely excellent as a seed substrate for epitaxial growth to obtain a pure substrate. When a pure GaN substrate obtained by epitaxial growth using this seed substrate 1 was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 40°C, and heat generation due to high-frequency loss was small, making it an excellent substrate. [Explanation of symbols]

[0089] Type 1 board 2 Seed crystal layer 3 Support substrate 4 Planarization layer 5 Stress adjustment layer 20 Single crystal substrate for seed crystal 21 Peeling position

Claims

1. A support substrate; a 0.5 to 3 μm planarization layer provided on the upper surface of the support substrate; a seed crystal layer provided on an upper surface of the planarization layer; A seed substrate for epitaxial growth comprising: The support substrate is a core having surface voids filled and flattened by an oxide, nitride, oxynitride, or mixture thereof of Al or Si, and a polycrystalline ceramic of a group III nitride; a sealing layer of 0.05 to 1.5 μm that seals the core; the seed crystal layer is provided by thin-film transfer of a surface layer of 0.1 to 1.5 μm of a Si<111> single crystal; The seed crystal layer has an oxidation-induced stacking fault density of 10 / cm ２ A seed substrate for epitaxial growth, characterized in that it is Si<111> as follows:

2. 2. The seed substrate for epitaxial growth according to claim 1, wherein the polycrystalline ceramic is an AlN ceramic.

3. The sealing layer comprises at least Si ３ N ４ 3. The seed substrate for epitaxial growth according to claim 1, further comprising a layer of:

4. The planarization layer is made of SiO ２ , silicon oxynitride (Si ｘ O ｙ N ｚ 4. The seed substrate for epitaxial growth according to claim 1, wherein the seed substrate is made of either SiO 2 / AlAs, or SiO 2 / AlAs, in which SiO 2 is laminated on AlAs.

5. 5. The seed substrate for epitaxial growth according to claim 1, further comprising a stress adjusting layer made of polycrystalline silicon on the bottom surface of the support substrate.

6. The stress adjustment layer is formed by forming a SiO ２ and / or silicon oxynitride (Si ｘ O ｙ N ｚ 6. The seed substrate for epitaxial growth according to claim 5, characterized in that it is made of polycrystalline silicon with intervening interlayers of silicon.

7. 7. A semiconductor substrate comprising the seed substrate for epitaxial growth according to claim 1, and a group III-V semiconductor thin film formed on the upper surface of the seed substrate.

8. 8. The semiconductor substrate according to claim 7, wherein the III-V group semiconductor thin film is a nitride semiconductor thin film containing Ga and / or Al.

9. preparing a planarized core having surface voids filled with an oxide, nitride, oxynitride, or mixture thereof of Al or Si; forming a sealing layer having a thickness of 0.05 μm to 1.5 μm so as to enclose the core, thereby forming a support substrate; forming a planarization layer having a thickness of 0.5 μm to 3.0 μm on an upper surface of the support substrate; providing a seed crystal layer by thin-film transferring a surface layer of 0.1 to 1.5 μm of Si<111> single crystal onto the upper surface of the planarization layer; Equipped with In the step of providing the seed crystal layer, the number of oxidation-induced stacking faults is 10 / cm ２ and then providing the seed crystal layer by transferring a thin film of 0.1 to 1.5 μm by physical means at 450° C. or less.

10. A method for manufacturing a seed substrate for epitaxial growth as described in Claim 9, characterized in that the surface voids of the polycrystalline ceramic are filled and planarized by applying a silicone compound and / or a silicone compound to which at least one of SiO2, Si3N4, and AlN powder has been added to the surface of the polycrystalline ceramic, and then treating it in an N2 atmosphere.

11. The method for producing a seed substrate for epitaxial growth according to claim 10, characterized in that the silicone compound is an alkoxysilane and / or a condensate thereof.

12. 12. The method for producing a seed substrate for epitaxial growth according to claim 9, wherein the sealing layer is formed by an LPCVD method.

13. The planarization layer is formed on one side or the entire upper surface of the support substrate. ２ , silicon oxynitride (Si ｘ O ｙ N ｚ 13. The method for producing a seed substrate for epitaxial growth according to claim 11, wherein either SiO2 / AlAs, which is a layer of SiO2 stacked on AlAs, is deposited by plasma CVD, LPCVD, or low-pressure MOCVD.

14. 14. The method for producing a seed substrate for epitaxial growth according to claim 9, further comprising the step of providing a stress adjustment layer on the bottom surface of the support substrate.

15. 15. The method for producing a seed substrate for epitaxial growth according to claim 14, wherein the stress adjustment layer is made of polycrystalline Si produced by a method selected from the group consisting of sputtering, plasma CVD, and LPCVD, which can further correct the warpage after the planarization layer is provided.

16. a step of producing a seed substrate for epitaxial growth by the method for producing a seed substrate for epitaxial growth according to any one of claims 9 to 15; forming a III-V semiconductor thin film on the upper surface of the epitaxial growth seed substrate; A method for manufacturing a semiconductor substrate comprising:

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