Measuring method for flat band voltage of power semiconductor modules

Abstract

1. A method for measuring a flatband voltage during operation of a power semiconductor module, the method comprising: a. applying a bias voltage to the module such that the module switches between an off state and an on state; b. triggering injection of a gate current from a current source to a gate of the module when an initial gate-emitter / source voltage equals the flatband voltage of the module; c. measuring a voltage across the current source; d. extracting a flatband voltage from the measured voltage across the current source; e. stopping injection of the gate current when a difference between the gate-emitter / source voltage and the flatband voltage becomes greater than a predetermined limit value or when a duration of injection of the gate current exceeds a predetermined duration; and f. storing a value of the extracted flatband voltage V.

Description

[Technical Field]

[0001] The present disclosure relates to the field of monitoring power semiconductors during operation. [Background technology]

[0002] Monitoring and estimating threshold voltage shift during semiconductor operation is a classical activity to evaluate bias temperature instability (BTI) of such components. It is known to monitor BTI for protection, status and health monitoring in metal-oxide semiconductor (MOS) type power semiconductors, parallel-connected MOS type power semiconductors, metal-insulator-semiconductor (MIS) type power semiconductors or parallel-connected MIS type power semiconductors, especially in power semiconductor devices / modules such as multi-chip power modules.

[0003] Many BTI estimation methods are known, but they are not completely satisfactory. Static measurements can be performed to determine threshold voltage shift. However, this leads to an underestimation of the threshold voltage because charge trapping recovers between the end of bias and the measurement. In such cases, the threshold voltage of the power semiconductor can be measured while the converter is idle. By setting the time between stress application and threshold voltage measurement to less than 100 ms, transient bias instability can be measured. This allows the shoot-through current and charge during switching transients to be measured. Trends in voltage, current, and temperature changes as the device ages during accelerated life tests can be used for data collection and online degradation monitoring. Due to settling times imposed by the monitoring system, accurate measurements require a low switching frequency and a high modulation index during monitoring. To this end, digital pulse-width modulation (DPWM) methods have been proposed to improve measurement accuracy by monitoring the device during specific periods when the power switch is not switching. All of these known methods imply stopping normal operation, stopping module switching, or biasing the device under certain conditions. Summary of the Invention

[0004] The present disclosure aims to improve this situation.

[0005] A method for measuring the flat band voltage during operation of a power semiconductor module including at least one semiconductor element selected from the group consisting of a metal oxide semiconductor element and a metal insulator semiconductor element is proposed. a. applying a bias voltage to the module such that the module switches from an off state to an on state or from an on state to an off state; b. The initial gate-emitter / source voltage is the module's flat-band voltage, V fb,h When the voltage is within ±5V of the reference voltage, the gate current I g Triggering the injection of c. The voltage across the current source V ig and measuring d. Measured voltage across the current source V ig to the flat band voltage V fb,h+1 and extracting the e. Gate current I g Injection of Gate-emitter / source voltage and flat band voltage V fb,h becomes greater than a predetermined limit, or gate current I g Infusion duration t inj is a given duration t max When it exceeds To stop and f. Extracted flatband voltage V fb,h+1 and storing the value of Includes.

[0006] In another aspect, there is proposed a power semiconductor module comprising a single metal oxide semiconductor, a single metal insulator semiconductor element, a set of metal oxide semiconductor elements, a set of metal insulator semiconductor elements, or a combination of metal oxide semiconductor elements and metal insulator semiconductor elements, wherein the power semiconductor module is configured to perform a method as defined herein.

[0007] In another aspect, we propose computer software comprising instructions that, when executed by a processor, perform a method as defined herein. In another aspect, we propose a computer-readable non-transitory storage medium having software stored thereon, the software, when executed by a processor, performing a method as defined herein.

[0008] The following features can optionally be implemented separately or in combination with each other.

[0009] The method comprises: The capacitance C of at least one semiconductor element meas To measure Further comprising: Extracted flatband voltage V fb,h+1 is measured by capacitance measurement meas and C meas The measured voltage V across the current source triggered when a transition between ig is.

[0010] Injected gate current I g The sign of depends on the on / off state of the semiconductor element.

[0011] Injected gate current I g The sign of is negative, The measured voltage V ig When the voltage reaches a certain negative voltage, the gate current I g The injection of Time derivative of voltage dV ig / dt is calculated and stored so that it can be used as an input parameter to iterate the method.

[0012] The calculated time derivative of the voltage, dV ig If / dt does not drop beyond a predetermined relative value, then the method g It is repeated using

[0013] Gate current I g The injection trigger is Time t from switching off of the semiconductor device p Only after the positive gate bias flat band voltage V fb,h+1 is extracted, and / or Time t from switching on of semiconductor device n This is done only before the

[0014] Flat band voltage V fb,h+1 is the measured voltage V ig The second time derivative of d 2 V ig / dt 2The gate current I g At the moment injection is triggered, the measured voltage V across the current source ig Extracted from

[0015] The method comprises: Flat band voltage V fb,h+1 bus voltage measurement before extraction; Flat band voltage V fb,h+1 measuring the duration of the on-state and / or the duration of the off-state before extraction; Further includes:

[0016] The sequence is repeated at least once to output the variation of the flatband over time.

[0017] Other features, details and advantages are set forth in the following detailed description and figures. [Brief explanation of the drawings]

[0018] [Figure 1A] Schematic diagram of a physical phenomenon. [Figure 1B] Schematic diagram of a physical phenomenon. [Figure 2] 1 is a graph of oxide capacitance as a function of gate-source voltage VGS for semiconductor modules with different aging. [Figure 3] 4 is a graph of the ratio of the capacitance of the oxide portion to the maximum value of said capacitance as a function of the gate-source voltage VGS of a semiconductor module at different stages of aging. [Figure 4] FIG. 2 illustrates a circuit according to one embodiment. [Figure 5] FIG. 2 illustrates a circuit according to one embodiment. [Figure 6] 1 is a graph of some data obtained during one embodiment. [Figure 7] 1 is a graph of some data obtained during one embodiment. [Figure 8] 1 is a graph of some data obtained during one embodiment. [Figure 9] FIG. 2 illustrates an example of an equivalent circuit used to obtain some data, according to one embodiment. [Figure 10] FIG. 1 shows a combination of various graphs obtained in a first situation. [Figure 11] FIG. 10 shows a combination of various graphs obtained in a second situation. [Figure 12] 1 is a graph of some data obtained according to one embodiment. [Figure 13] 1 is a graph of some data obtained according to one embodiment. [Figure 14] 1 is a schematic diagram of the variation of several indexes during operation of a power semiconductor device; DETAILED DESCRIPTION OF THE INVENTION

[0019] {Main problem to be solved} Bias temperature instability (BTI) is a reliability issue for insulated gate power modules such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and high electron mobility transistors (HEMTs). In SiC power semiconductor devices, this phenomenon is much more problematic (approximately 10 times) for device lifetime than in Si power semiconductor devices because the band offset between the gate oxide and the power semiconductor is reduced and carbon atoms degrade the atomically smooth Si / SiO2 interface. Charge trapping also affects the reliability of GaN HEMT devices due to the complexity of the gate stack structure.

[0020] Charge trapping can be a persistent or transient phenomenon and the main consequences of this reliability problem are: i / "Increase in on-resistance RDS(on)" During operation of the power semiconductor element, this can lead to excessive power dissipation and overheating on the device / module, which can have a devastating effect on the integrity of the material. ii / "Body diode threshold voltage" During operation of a power semiconductor, this can lead to excessive power dissipation and overheating of the device. iii / "Off-state blocking leakage current IDSS(off)" causes additional losses in the device and may even lead to catastrophic failure. iv / "Shoot-through current" The on-time delay and off-time delay are varied. The initial dead time of the power semiconductors may not be sufficient to safely switch the series device, potentially resulting in a catastrophic short-circuit failure.

[0021] In each of the problems mentioned above, the excess loss caused by degradation increases the temperature of the power semiconductor, accelerating degradation. In the RF region, there is also concern about the degradation of the linearity of the MOSFET due to stress.

[0022] Identifying gate oxide degradation under on-line operation of power semiconductors is an important parameter for assessing the reliability of such devices from the standpoint of testing and safety assessment (including standards) as well as delivery / maintenance of power conversion equipment.

[0023] {theory} Flat band voltage V fb is a voltage that generates a flat energy band in the semiconductor when applied to a semiconductor element, and is determined by the following equation (1).

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[0024] Φ MS is the work function difference between the gate metal material and the semiconductor material. C ox is the capacitance of the oxide film. Q ox is the total effective charge in the oxide. The last term in equation (1) is due to the charge density in the oxide.

[0025] Note that the flatband voltage is affected by the presence of charge at the oxide-semiconductor interface. Charges present at this interface are sensitive to the electric field formed above the channel. A positive gate voltage generates a positive electric field, causing negative charge to accumulate in the oxide, and therefore the flatband voltage increases according to equation (1). Conversely, a negative gate voltage generates a negative electric field, causing positive charge to accumulate in the oxide, and therefore the flatband voltage decreases according to equation (1). This phenomenon is called bias temperature instability, or BTI. In the case of a positive electric field, this is called positive temperature bias instability (PBTI). In the case of a negative electric field, this is called negative temperature bias instability (NBTI).

[0026] Figures 1A and 1B are based on figures published in the paper by X. Zhong et al., "Bias Temperature Instability of Silicon Carbide Power MOSFET Under AC Gate Stresses," IEEE Transactions on Power Electronics, vol. 37, no. 2, pp. 1998-2008, Feb. 2022, doi: 10.1109 / TPEL.2021.3105272. Figures 1A and 1B illustrate the phenomenon described above. Figure 1A shows the gate-source voltage V GS corresponds to the situation where the gate-source voltage V GS corresponds to the situation where is less than 0V.

[0027] Despite efforts to avoid charge trapping in the oxide during design, charge is trapped in the gate oxide due to positive or negative electric fields during operation of power semiconductor devices. This phenomenon is largely unavoidable in the case of SiC or GaN semiconductor materials, where more interface states and fixed oxide charges appear after high electric fields are applied. The trapped charge also increases significantly with high switching frequencies and / or high device temperatures.

[0028] One of the main consequences of gate oxide degradation is the threshold voltage V thThis is the fluctuation of the temperature, and is described as the following equations (2) and (3).

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[0029] N a is the acceptor concentration in the substrate. s is the dielectric constant of the semiconductor. k is the Boltzmann constant. T is the temperature. ni is the intrinsic carrier concentration. C ox is the capacity of the oxide.

[0030] The gate and substrate doping and oxide thickness are not affected by the bias voltage, so the threshold voltage V th The significant change in is related to the change in oxide charge and therefore the flat band voltage V fb can be monitored solely by measuring

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[0031] Flat band voltage V fb To measure the change in gate voltage dV g The change in gate charge injected by dQ g is V g <V th In this case, the following formula (5) can be applied.

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[0032] This is due to the gate voltage V g is the flat band voltage V fb is given by the fact that the equivalent capacitor C is a series connection between an oxide capacitor and a depletion capacitor when the gate voltage V is greater than g is the flat band voltage V fbWhen the capacitance C is less than , the capacitance C is related to the gate oxide capacitance only. Therefore, the transition between a constant C and a variable C with gate voltage is called the flat-band voltage V. fb This can be used as an indicator of the

[0033] Figure 2 is based on a figure published in the paper "Temperature-Independent Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Junction Capacitances" by M. Farhadi, F. Yang, S. Pu, B.T. Vankayalapati and B. Akin, in IEEE Transactions on Power Electronics, vol. 36, no. 7, pp. 8308-8324, July 2021. Each curve represents the gate-source voltage V GS Each curve corresponds to a situation with known aging of the power semiconductor device. curve 21:10 hours curve 22:100 hours Curve 23:200 hours curve 24:300 hours

[0034] As can be seen from Figure 2, there is an aging-sensitive region at approximately -10 V to -5 V, which includes the flat-band voltage. The oxide capacitance is highly dependent on the aging of the components.

[0035] Figure 3 is based on a diagram published in the paper by S. Mbarek, F. Fouquet, P. Dherbecourt, M. Masmoudi and O. Latry, “Gate oxide degradation of SiC MOSFETs under short-circuit aging tests,” Microelectronics Reliability, vol. 64, no. https: / / doi.org / 10.1016 / j.microrel.2016.07.132., pp. 415-418, 2016. Each curve represents the gate-source voltage V GS Gate-source capacitance C GS In this case, the maximum C GSmax Gate-source capacitance C GS Curve 31 corresponds to a measurement made before aging the component, and curve 32 corresponds to a measurement made after aging the same component for 250 μs. The two corresponding flat-band voltages V fb The difference between the fb ) and are superimposed on curves 31 and 32.

[0036] {Description of the embodiment} In the following, a power semiconductor module 1 is an assembly comprising a single metal-oxide-semiconductor (MOS) or single metal-insulator-semiconductor (MIS) element or a set of combined MOS and / or MIS elements. Even if the module 1 includes multiple MOS or MIS elements, it will be considered as a single element in the following because of the presence of a common gate G, a common source S, and a common drain D. For this reason, in the following, the single gate, single source, and single drain will be used without distinction between embodiments with single or multiple MOS elements. The term "power" is used in its general sense in the technical field of energy conversion (power electronics).

[0037] The purpose of the following method is to estimate the bias temperature instability (BTI) of a power semiconductor module 1 in order to detect gate oxide degradation. A method is proposed here that is typically used on a test bench, but also in operating conditions when the modules are integrated and interconnected in their operational and industrial environments.

[0038] The method comprises the following operations: a. applying a bias voltage to module 1 such that the module switches from an off state to an on state or from an on state to an off state; b. The initial gate-emitter / source voltage is the module's flat-band voltage, V fb,h When the voltage is within ±5 V of the reference voltage, or less, for example, within ±4 V, the gate current I from the current source 44 to the gate of the module g Triggering the injection of c. The voltage across the current source V ig and measuring d. Measured voltage across the current source V ig to the flat band voltage V fb,h+1 and extracting the e. Gate current I g injection, the gate-emitter / source voltage and the flat band voltage V fb,h When the difference between the current I g Infusion duration t inj is a given duration t max When the speed exceeds f. Extracted flatband voltage V fb,h+1 and storing the value of Includes.

[0039] In one embodiment shown in FIG. 4, module 1 comprises a metal-oxide-semiconductor (MOS) or metal-insulator-semiconductor (MIS) device (hereinafter "semiconductor device 11" or "transistor") and control circuitry 12. Control circuitry 12 includes a gate drive voltage source 41 and a current source 44 that control the gate G of the semiconductor device between an on state and an off state in accordance with a control signal CTRL1. The gate drive voltage value is V g In this example, the voltage on the gate G during the on-state is V cc and is approximately 15 V (typically 10 V to 20 V), and the voltage at the gate G during the off state is V ee and is approximately -5V (typically -20V to 0V). The transition instant between the off and on states is determined by a control signal CTRL1 sent by a controller 43 that alternates within a switching period. In some embodiments, the controller 43 is a component of the module 1. In other embodiments, the controller 43 is external to the module 1. The gate current I g The triggering of the injection (action b) is performed by the controller 43.

[0040] Gate current I g The injection current source 44 is a DC current source. In this example, the current source has a value between -100 mA and 100 mA. The module 1 comprises means by which the injection of current into the gate G can be controlled via a control signal CTRL2. In this example, such means comprises a switch 46. In various embodiments, such means can be other structures adapted to the architecture of the control circuit 12, for example, a set of parallel or series switches.

[0041] The voltage V across the current source 44 ig is V ig =V g -V gs or V ig =V ee -V gs , the gate-source voltage V of the semiconductor element 11 gs The voltage V across the current source 44 igis measured continuously (operation c). The flat band voltage V fb is calculated by the following equations (6) and (7): g is constant during the measurement time t (V ee (equal to the gate voltage V at time t) ig The injected gate charge, which in this example is a DC current I g can be extracted from the fluctuations of

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[0042] A constant measured capacitance C meas and the variable measured capacitance C meas The voltage across the current source 44 between the values ​​V ig The transition of fb In other words, the measured capacitance C meas The voltage V at the moment t at which ig Using the value of (t), the updated flatband voltage V fb,h+1 In such an implementation, the value of the measured capacitance C meas The stable derivative of the estimated flat band voltage V fb,h+1 Voltage V as ee -V ig triggers sampling of (action d).

[0043] In some embodiments, optional additional conditions can be imposed to ensure good reliability of the estimation, for example a minimum frequency and / or a minimum sampling rate of the AC signal can be set.

[0044] Current injection I g satisfies the following conditions: Gate-emitter / source voltage and flat band voltage V fb,h becomes greater than a predetermined limit, for example 4V or 5V, or Gate current I g Infusion duration t injis a given duration t max If the predetermined duration t max is the known capacitance C of the semiconductor element 11. oxeq If dependent on (nominal or previously estimated or measured) is reached (action e).

[0045] In some embodiments, two conditions are provided / configured such that current injection is stopped as soon as one of the two conditions is reached. In various embodiments, only one of the above two conditions is provided / configured, and the other is not. In various embodiments, other conditions can be added. For example, if the measured capacitance C meas The current injection can also be stopped when the derivative of has stabilized.

[0046] In one example, the maximum time t max is determined according to the following equation (8), and the I g is 10mA, and the oxide film capacitance C oxeq is 20nF, and the off-state gate voltage V ee -5V, and estimated flat band voltage V fb is between -2V and -3V, t max is equal to 6 μs.

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[0047] Updated flat band voltage V fb,h+1 is the voltage V across the current source 44 measured at the same instant t as the current injection. g In other words, actions d, e and f can be performed at the same instant t.

[0048] Updated flat band voltage V fb,h+1 The value of is the flat band voltage V as a function of time during module 1 operation. fb The history of the vertices is stored on any suitable support.

[0049] In some embodiments, the above-described method can be looped, with the same procedure repeated several times after the first measurement stored in memory to compare the variation of the flatband voltage over time. In some embodiments, the method can be repeated periodically, for example, over several hours or days.

[0050] In one embodiment shown in Figure 5, the module 1 comprises (at least) two current sources, namely a first current source 54a and a second current source 54b. The current sources 54a, 54b are arranged in series with the same semiconductor element 11 and supply power to the semiconductor element 11. The first current source 54a and the second current source 54b are positive. Each current source 54a, 54b is in parallel with a respective switch 56a, 56b. Such a structure allows the injected gate current I g This is an example where the sign of can be controlled.

[0051] In some embodiments, a series of operations (a-f) are repeated. In this way, multiple flat band voltages V fb,h1 , V fb,h2 , ..., V fb,hN is obtained and stored. From the multiple flatband values, the variation of the flatband over time can be output as an indicator of relative gate oxide damage.

[0052] In some embodiments, the flatband voltage V fb,h is known, and the flat band voltage V fb,h is the off-state voltage V EE , the current source will provide a positive gate current I from, for example, the first current source 54a. g Conversely, the flat band voltage V fb is the off-state voltage V EE , the current source will provide a negative gate current I from, for example, the second current source 54b. g In other words, the gate-emitter / source initial voltage is equal to the flat band voltage V fb,h When the gate current is greater than gis injected into the gate of module 1. For a positive gate current, the current source 54a is driven to at least the flat-band voltage V fb A first current source 54a is connected between the gate drive voltage source and the emitter / source of the semiconductor device. For negative gate currents, the flat band voltage V fb is the off-state voltage V EE Since the gate voltage is lower than the flat band voltage V, the current source 54b is used to fb The second current source 54b is disposed between the emitter / source of the semiconductor device 11 and the gate drive voltage source.

[0053] In the following, we will first consider the flat band voltage V fb We will explain how to determine the use of a current source when V is not known. First, we use a negative current source and V ig The time derivative of is performed (calculated and stored) as described above. ig The voltage is increased until it reaches a value close to the minimum allowable negative voltage of the power semiconductor element 11. For example, the time derivative of the voltage (dV g / dt) does not drop by more than a certain relative value, e.g., 20%, when the flat-band voltage V fb is V EE value, and the positive current source is used in the next switching period, as shown in Figure 8. In such an example, the measured voltage across the current source, V ig to the flat band voltage V fb,h+1 The extraction of is performed at the moment when the next triggering of the gate current begins.

[0054] The circuit configuration of the two current sources is shown in Figure 5. This allows the exact placement of current sources 54a and 54b and the flatband voltage V fb The voltage V used to estimate ig The measurement of is described in detail.

[0055] The acquired waveforms are shown in Figures 6 and 7. In the examples of Figures 6 and 7, the flat band voltage V fbis equal to 4 volts. In Figure 6, the off-state voltage V EE is equal to 5 volts. In Figure 7, the off-state voltage V EE is equal to 0 volts. In Figure 8, V fb1 The flat band voltage, represented by V EE Higher than the current source I g1 and the measured voltage V ig1 is the flat band voltage V from the semiconductor element 11. fb1 On the other hand, the flat band voltage V fb2 V EE If it is lower than g2 and the measured voltage V ig2 and the flat band voltage V from the semiconductor element 11. fb2 Get.

[0056] In some embodiments, the flatband voltage V fb is measured twice in the same switching period. This can be done in combination with the previous explanation. For this, see also Figure 8. For example, the gate current (to the gate) I g The injection trigger is Time t from when the power semiconductor element 11 is switched off p Only after the positive gate bias flat band voltage V fb,h+1 is extracted (output), Time t from when the power semiconductor element 11 is switched on n Just before, negative gate bias flat band voltage V fb,h+1 is extracted (output).

[0057] The variation of the respective flatband of the output can be used as an indicator of gate oxide damage. fb is any possible off-state voltage value V EE With a positive gate bias V fbPB Immediately after and negative gate bias V fbNBFurthermore, conventional two-level gate drive implementations are compatible with such measurements. As a result, few modifications to the gate drive are required to measure BTI according to one such embodiment.

[0058] In practice, a timer is used to time the time t between the falling edge of the gate voltage and the current injection. p The signal can be used to count time t n Alternatively, the previous switching pattern can be used to determine the total length of the off-state, and the current injection is initiated at time t from the total length of the previous off-state. n The draw is determined by triggering a timer that counts down.

[0059] Negative gate bias value V fbNB can be taken just before turn-on, in this way monitoring can be done continuously during the off-time (e.g., within 10 μs between estimates) and the last value before turn-on is taken. Advantageously, only the internal gate control signals are needed, given that in known / existing modules the gate signals are classically separated from the main controller.

[0060] In some embodiments, the flatband voltage V fb,h+1 is the measured voltage V g The second time derivative of d 2 V g / dt 2 The gate current I g At the moment injection is triggered, the measured voltage across the current source, V ig In other words, the second derivative of the current source voltage is the flat-band voltage V according to the following equation (9): fb is used to trigger the measurement of the current injection time Δt.

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[0061] Φ MS is the work function difference between the gate metal material and the semiconductor material.

[0062] A fast sampling rate ADC (analog-to-digital converter) can be used, but is not necessary to detect the derivative of the equivalent capacitor; a simple analog circuit can be used to trigger a fast counter. Higher current source values ​​are possible with shorter measurement times.

[0063] Referring to Figures 6 and 7, V ig The first peak of the second derivative of represents the moment when current is injected into the gate. The second peak represents the moment when V ig Used to trigger measurements. In this application, the second derivative is the threshold V, which is equal to 2V when a gain of 1e-6 is used. thd An example of a circuit using second derivative to generate a trigger is shown in Figure 9. Figure 10 graphically illustrates the method when a positive current source is used. Figure 11 graphically illustrates the method when a negative current source is used.

[0064] In some embodiments, the voltage V across the current source g Measurement of the corresponding flat band voltage V fb,h+1 The extraction of Current source voltage V ig is the threshold V thd The duration of the injection Δt after the moment t is reached (see FIG. 12) inj , or Gate current I g The injection of the given duration t is triggered inj,thd The current source voltage V after ig This is done by the function (see Figure 13).

[0065] In both cases, the measurement (duration or voltage) is the flatband voltage V fbThis allows for low-noise and low-cost estimation of parameters related to flatband voltage. For voltage-based extraction, no ADC is required. For time-based extraction, no hardware is required to set a trigger.

[0066] Current source threshold voltage V thd is the injection time Δt inj When used to trigger the measurement of the voltage V thd is defined to be slightly above or below the expected increase or decrease in flatband voltage drift, respectively. And the injection time Δt inj is measured and the flat band voltage V is calculated by the following equation (10): fb is estimated.

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[0067] Current injection threshold time t inj,thd is the current source voltage V ig When used to trigger the measurement of the flatband voltage V, the value of the time delay is fb is defined as being slightly above or below, respectively, the expected increase or decrease in time to reach

[0068] In some embodiments, the bus voltage measurement is the flatband voltage V fb In some embodiments, the measurement of the on-state duration and / or the off-state duration is performed using the flatband voltage V fb Therefore, the variation in gate oxide degradation can be observed as a function of certain operating parameters such as bus voltage, time under positive gate bias, time under negative gate bias, switching frequency and / or junction temperature. [Industrial Applicability]

[0069] Some known methods use a CV meter to measure the small signal capacitance to determine the DC bias voltage, Vg and a small sine wave signal is applied to the MOS capacitor, and the capacitive current is measured using an AC ammeter. In the above embodiment, the online flat-band voltage V fb Measurements are performed. The method is applicable to any metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) type transistors, such as MOSFETs and IGBTs. Bias temperature instability (BTI) is estimated in insulated gate power semiconductor devices. BTI is measured using a flatband indicator along with in-situ circuit measurements associated with the gate drive control of the power semiconductor device during operation of the power semiconductor in a field application.

[0070] Gate oxide degradation occurs due to the flat band voltage V fb By measuring this, gate charge trapping fluctuations can be detected during power semiconductor operation within a few microseconds after the end of a positive gate voltage bias, and at the end of a negative gate voltage bias. Thus, gate charge trapping fluctuations and gate charge trapping hysteresis can be evaluated during operation of the power semiconductor device in field applications. Furthermore, the current state of the semiconductor module is not changed during the measurement, does not interfere with the normal operation of the module, and is transparent to the user. Finally, online measurements improve and ensure the reliability of power semiconductor modules.

[0071] Positive / negative temperature bias instability (PBTI / NBTI) causes the threshold voltage V th The flat band voltage V fb The variation of can be monitored along the life of the power semiconductor module as shown in FIG.

[0072] The present disclosure is not limited to the methods, modules, circuits, and computer software described herein, which are merely examples, and the present invention encompasses all alternatives that occur to those skilled in the art upon reading this specification. [Explanation of symbols]

[0073] 1: Module 11: Semiconductor element 12: Control circuit 21:10-hour aging curve 22: 100-hour aging curve 23: 200-hour aging curve 24:300 hour aging curve 31: Curve before aging 32: Curve after aging for 250 μs 41: Voltage source 43: Control unit 44: Current source 46: Switch 54a: First current source 54b: Second current source 56a: First switch 56b: Second switch CTRL1: Control signal CTRL2: Control signal

Claims

1. 1. A method for measuring flat band voltage during operation of a module of power semiconductors comprising at least one semiconductor element selected from the group consisting of a metal oxide semiconductor element and a metal insulator semiconductor element, the method comprising: applying a bias voltage to the module such that the module switches from an off state to an on state or from an on state to an off state; b. The initial gate-emitter / source voltage is equal to the flat band voltage V of the module. ｆｂ，ｈ When the voltage is within ±5V of the reference voltage, a gate current I ｇ Triggering the injection of c. The voltage V across the current source ｉｇ and measuring d. The measured voltage across the current source, V ｉｇ to the flat band voltage V ｆｂ，ｈ＋１ and extracting the e. The gate current I ｇ Injection of The gate-emitter / source voltage and the flat band voltage V ｆｂ，ｈ becomes greater than a predetermined limit, or The gate current I ｇ Infusion duration t ｉｎｊ is a predetermined duration t ｍａｘ When it exceeds To stop and f. Extracted flat band voltage V ｆｂ，ｈ＋１ and storing the value of A method comprising:

2. The capacitance C of the at least one semiconductor element ｍｅａｓ To measure Further comprising: The extracted flat band voltage V ｆｂ，ｈ＋１ is the voltage V across the measured current source triggered when a transition between a constant value state and a changing value state for the capacitance C meas is detected from the capacitance measurement. ｉｇ That is, The method of claim 1.

3. The injected gate current I ｇ The method of claim 1 or 2, wherein the sign of depends on the on / off state of the semiconductor element.

4. The injected gate current I ｇ The sign of is negative, The gate current I ｇ The injection of ｉｇ is stopped when it reaches a predetermined negative voltage, The time derivative of the voltage dV ｉｇ / dt is calculated and stored so that it can be used as an input parameter to repeat the method. The method of claim 3.

5. The calculated time derivative of the voltage dV ｉｇ If / dt does not drop beyond a predetermined relative value, the method ｇ It is repeated using The method of claim 4.

6. The gate current I ｇ The injection trigger is The semiconductor device is switched off at time t ｐ After the positive gate bias flat band voltage V ｆｂ，ｈ＋１ is extracted, and / or The semiconductor device is switched on at time t ｎ Only before 3. The method according to claim 1 or 2.

7. The flat band voltage V ｆｂ，ｈ＋１ is the measured voltage V ｉｇ The second time derivative d ２ V ｉｇ / dt ２ Gate current I in response to the condition ｇ At the moment when the injection of ｉｇ The method according to claim 1 or 2, wherein the extract is from

8. The flat band voltage V ｆｂ，ｈ＋１ bus voltage measurement before extraction; The flat band voltage V ｆｂ，ｈ＋１ measuring the duration of the on-state and / or the duration of the off-state before extraction; The method of claim 1 or 2, further comprising:

9. 3. The method according to claim 1, wherein the sequence of operations a. to f. is repeated at least once to output the variation of the flatband over time.

10. A power semiconductor module comprising a single metal oxide semiconductor, or a single metal insulator semiconductor element, or a set of metal oxide semiconductor elements, or a set of metal insulator semiconductor elements, or a combination of metal oxide semiconductor elements and metal insulator semiconductor elements, wherein the power semiconductor module is ｉｇ 3. A power semiconductor module, further comprising measuring means configured to measure the power consumption of the power semiconductor module and configured to perform the method according to claim 1 or 2.

11. Computer software comprising instructions for carrying out the method of claim 1 or 2 when said computer software is executed by a processor.

12. A computer-readable, non-transitory recording medium having stored thereon software that, when executed by a processor, performs the method of claim 1 or 2.

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