Test structure for metal gate transistor

Abstract

The application provides a test structure of a metal gate transistor, comprising: a semiconductor substrate; a plurality of transistor structures sharing one metal gate formed on the substrate; a pad assembly comprising a first pad, a second pad, a third pad, a fourth pad, a fifth pad and a sixth pad, all the sources being electrically connected with the first pad, all the drains being electrically connected with the second pad, one end of the metal gate being electrically connected with the third pad and the fourth pad, and the other end of the metal gate being electrically connected with the fifth pad and the sixth pad; wherein the first pad, the second pad and any one of the third pad, the fourth pad, the fifth pad and the sixth pad form a test end of a reliability test, and the third pad, the fourth pad, the fifth pad and the sixth pad form a test end of an electromigration test. The test structure can integrate the reliability test structure and the electromigration test structure separated from each other in the prior art into one test structure, thereby saving the area of the test structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically to a test structure for a metal gate transistor. Background Technology

[0002] With the miniaturization and integration of semiconductor devices, their performance has been greatly improved. However, the increased integration and shrinkage of size have led to a continuous increase in the internal electric field and current density of the devices. This has resulted in increasingly serious problems such as hot carrier injection (HCI), negative bias temperature instability (NBTI), and electromigration, causing degradation of the device's electrical parameters and even device failure, thus reducing the device's performance.

[0003] Currently, High-Intensity Channel Induction (HCI) and Non-Non-Non-Terminal Transistor Induction (NBTI) are two important issues affecting the reliability of devices (such as metal-gate transistors). HCI refers to the effect or damage of hot carriers generated under a strong electric field on the channel; NBTI refers to the degradation of a series of electrical parameters caused by applying a negative gate voltage to a PMOS transistor at high temperatures. To determine the impact of HCI and NBTI on device reliability, HCI and NBTI tests are typically performed. In the prior art, the HCI and NBTI tests can be performed in a single reliability test structure. Figure 1 The diagram shows a schematic of an existing reliability test structure. This reliability test structure uses a single transistor device structure as the test object, including: a substrate 10, a source 101, a drain 102, and a gate 103, and a first pad 111, a second pad 112, a third pad 113, and a fourth pad 114 electrically connected to the semiconductor substrate 10, the source 101, the drain 102, and the gate 103, respectively. The electrical connections are achieved through conductive plugs 12. Voltages are applied between the pads, and the corresponding electrical parameters (including drain current I) are measured. d Substrate current I sub Due to the influence of HCI and / or NBTI, the electrical parameters of the test object will change, thus obtaining the change curve of the electrical parameters over time. By analyzing and processing the change curve of the electrical parameters over time according to a suitable theoretical model, the reliability parameters of the transistor device (such as HCI failure lifetime, NBTI failure lifetime, etc.) can be obtained.

[0004] Because the gate metal (e.g., aluminum) in metal-gate transistors typically exhibits electromigration, electromigration testing is necessary to determine the electromigration failure lifetime of the gate metal (the lifetime at which the device fails due to electromigration of the gate metal). Figure 2 The diagram shows a schematic of an existing electromigration test structure. This structure includes: a first metal line 201, serving as the metal line under test; a second metal line 202 and a third metal line 203, electrically connected to both ends of the first metal line 201 via conductive plugs 22; a first pad 211 and a second pad 212 connected to the second metal line 202; and a third pad 213 and a fourth pad 214 connected to the third metal line 203. The test principle of this electromigration test structure is as follows: a current is applied between the first pad 211 and the fourth pad 214, and the voltage between the second pad 212 and the third pad 213 is measured to calculate the resistance value of the first metal line 201. During the test, electromigration occurs, and due to this phenomenon, voids 23 gradually form within the first metal line 201, causing the resistance of the first metal line 201 to change over time. Further measurements were taken to obtain the resistance curve of the first metal line 201 over the test time. By analyzing and processing this curve, the electromigration parameters of the device (e.g., electromigration failure lifetime) can be obtained.

[0005] For metal gate transistors, the aforementioned reliability test (including HCI test and NBTI test) structures and electromigration test structures are usually located in different positions on the wafer. These two types of tests occupy a large wafer area due to the separation of the test structures, which reduces the wafer utilization rate. Summary of the Invention

[0006] The present invention aims to solve the problem that in wafer-level testing, the separation of various test structures occupies a large wafer area, thus reducing wafer utilization.

[0007] To achieve the above objectives, the present invention provides a test structure for a metal gate transistor, which can perform multiple tests in one test structure. The test structure for the metal gate transistor includes:

[0008] Semiconductor substrate;

[0009] Multiple transistor structures formed on a semiconductor substrate, each transistor structure including a metal gate and source and drain located on both sides of the metal gate, and multiple transistor structures sharing a metal gate;

[0010] The pad assembly includes a first pad, a second pad, a third pad, a fourth pad, a fifth pad, and a sixth pad. All sources of the multiple transistor structures are electrically connected to the first pad, and all drains of the multiple transistor structures are electrically connected to the second pad. One end of the metal gate is electrically connected to the third and fourth pads, and the other end of the metal gate is electrically connected to the fifth and sixth pads.

[0011] Among them, any one of the third, fourth, fifth, and sixth pads, together with the first and second pads, forms the test end for reliability testing, and the third, fourth, fifth, and sixth pads form the test end for electromigration testing.

[0012] Preferably, the pad assembly further includes a seventh pad, which is electrically connected to the semiconductor substrate.

[0013] Preferably, the test structure further includes: a first metal line, a second metal line, a third metal line, and a fourth metal line. All sources of the multiple transistor structures are electrically connected to the first pad through the first metal line, all drains of the multiple transistor structures are electrically connected to the second pad through the second metal line, one end of the metal gate is electrically connected to the third and fourth pads through the third metal line, and the other end of the metal gate is electrically connected to the fifth and sixth pads through the fourth metal line.

[0014] Preferably, the test structure further includes an insulating medium, and the metal gate, the first metal line, the second metal line, the third metal line and the fourth metal line are all disposed in the insulating medium and isolated by the insulating medium.

[0015] Preferably, all sources of the multiple transistor structures are electrically connected to the first metal line through conductive plugs, all drains of the multiple transistor structures are connected to the second metal line through conductive plugs, one end of the metal gate is connected to the third metal line through a conductive plug, and the other end of the metal gate is electrically connected to the fourth metal line through a conductive plug.

[0016] Preferably, the first metal wire, the second metal wire, the third metal wire, and the fourth metal wire are in direct contact with their corresponding pads, forming a direct contact electrical connection.

[0017] Preferably, the first metal wire, the second metal wire, the third metal wire, and the fourth metal wire are electrically connected to their corresponding pads via conductive plugs.

[0018] Preferably, the first metal line, the second metal line, the third metal line and the fourth metal line are located in the same metal layer.

[0019] Preferably, all sources of the multiple transistor structures are located on one side of the metal gate, and all drains of the multiple transistor structures are located on the other side of the metal gate.

[0020] Preferably, the metal material of the metal gate includes aluminum.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] The test structure for a metal gate transistor provided by this invention includes a test terminal for reliability testing and a test terminal for electromigration testing. The reliability testing terminal can be used to perform conventional reliability tests on the transistor, including hot carrier injection testing and negative bias temperature instability testing. The electromigration testing terminal can be used to perform electromigration testing on the metal gate of the transistor. Therefore, the test structure for a metal gate transistor provided by this invention integrates the previously separate reliability testing structure and electromigration testing structure into a single test structure, saving test structure area and improving wafer utilization. Attached Figure Description

[0023] Figure 1 This is a top view of a reliability testing structure in the prior art;

[0024] Figure 2 This is a cross-sectional view of an electromigration test structure in the prior art;

[0025] Figure 3A A top view of a test structure for a metal gate transistor provided in one embodiment;

[0026] Figure 3B for Figure 3A Cross-sectional view of the test structure obtained by truncating along AA';

[0027] The labels in the attached figures are explained as follows:

[0028] Figure 1 In the diagram, 10 is the semiconductor substrate; 101 is the source; 102 is the drain; 103 is the gate; 111 is the first pad; 112 is the second pad; 113 is the third pad; 114 is the fourth pad; and 12 is the conductive plug.

[0029] Figure 2 In the diagram, 201-first metal line; 202-second metal line; 203-third metal line; 211-first pad; 212-second pad; 213-third pad; 214-fourth pad; 22-conductive plug; 23-void.

[0030] Figure 3A and Figure 3BIn the diagram, 30 is the semiconductor substrate; 301 is the source; 302 is the drain; 303 is the metal gate; 401 is the first pad; 402 is the second pad; 403 is the third pad; 404 is the fourth pad; 405 is the fifth pad; 406 is the sixth pad; 407 is the seventh pad; 501 is the first metal line; 502 is the second metal line; 503 is the third metal line; 504 is the fourth metal line; 60 is the conductive plug; and 70 is the void. Detailed Implementation

[0031] To make the objectives, advantages, and features of the present invention clearer, the test structure of the metal gate transistor provided by the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the explanation of the embodiments of the present invention.

[0032] Please see Figure 3A and Figure 3B The test structure for the metal gate transistor provided by this invention includes:

[0033] A semiconductor substrate 30; a plurality of transistor structures formed on the semiconductor substrate 30, each transistor structure including a source 301, a drain 302, and a metal gate 303, wherein the source 301 and drain 302 are located on both sides of the metal gate 303, and the plurality of transistor structures share a single metal gate 303; a pad assembly including a first pad 401, a second pad 402, a third pad 403, a fourth pad 404, a fifth pad 405, and a sixth pad 406; all sources of the plurality of transistor structures are electrically connected to the first pad 401, and all... The drain is electrically connected to the second pad 402, one end of the metal gate 303 is electrically connected to the third pad 403 and the fourth pad 404, and the other end of the metal gate 303 is electrically connected to the fifth pad 405 and the sixth pad 406; wherein, any one of the third pad 403, the fourth pad 404, the fifth pad 405, and the sixth pad 406, together with the first pad 401 and the second pad 402, forms a test terminal for reliability testing, and the third pad 403, the fourth pad 404, the fifth pad 405, and the sixth pad 406 form a test terminal for electromigration testing.

[0034] In this embodiment, the pad assembly further includes a seventh pad 407, which is electrically connected to the semiconductor substrate 30. The seventh pad 407 can be used as a substrate test terminal as needed for testing.

[0035] In this embodiment, the test structure further includes: a first metal line 501, a second metal line 502, a third metal line 503, and a fourth metal line 504. All sources of the plurality of transistor structures are electrically connected to the first pad 401 via the first metal line 501; all drains of the plurality of transistor structures are electrically connected to the second pad 402 via the second metal line 502; one end of the metal gate 303 is electrically connected to the third pad 403 and the fourth pad 404 via the third metal line 503; and the other end of the metal gate 303 is electrically connected to the fifth pad 405 and the sixth pad 406 via the fourth metal line 504.

[0036] The test structure includes a reliability test structure, comprising: a parallel structure composed of the plurality of transistors, serving as the test object; a first metal line 501 electrically connected to all sources of the plurality of transistors to form the test source of the parallel structure; a first pad 401 electrically connected to the test source as the source test terminal of the parallel structure; a second metal line 502 electrically connected to all drains of the plurality of transistors to form the test drain of the parallel structure; a second pad 402 electrically connected to the test drain as the drain test terminal of the parallel structure; a metal gate 303 as the test gate of the parallel structure; any one of the third pad 403, fourth pad 404, fifth pad 405, and sixth pad 406 electrically connected to the metal gate 303 as the gate test terminal; and a seventh pad 407 electrically connected to the semiconductor substrate 30 as the substrate test terminal. The source test terminal, drain test terminal, gate test terminal, and substrate test terminal constitute the test terminals for reliability testing, enabling reliability testing of the parallel structure.

[0037] The test structure includes an electromigration test structure for performing electromigration tests on the metal gate 303. The electromigration test structure includes: a metal gate 303 as the test metal for electromigration testing; a third metal line 503 and a fourth metal line 504 electrically connected to both ends of the metal gate 303, serving as the cathode / anode for electromigration testing; and a third pad 403 and a fourth pad 404 electrically connected to the third metal line 503, and a fifth pad 405 and a sixth pad 406 electrically connected to the fourth metal line 504, serving as the test terminals for electromigration testing. The electromigration test structure includes four test terminals, corresponding to the industry-standard four-terminal method (or four-probe method) used to test the electromigration properties of the metal gate 303. In this embodiment, the metal gate 303 is a metal wire segment, and its metal material includes aluminum. Due to the excellent properties of aluminum, it is often used as the gate material for high-k-value metal gate transistors. However, because aluminum exhibits electromigration, electromigration testing is required on the aluminum gate. The material of the metal gate 303 is not limited to aluminum, but can also be other suitable metal materials, such as copper.

[0038] In this embodiment, the plurality of transistors is exemplified by three transistors, but it is not limited to this; the number of transistors can be other suitable numbers. Preferably, all sources of the plurality of transistors are located on one side of the metal gate 303 (e.g., Figure 3A (left side of the image), all drains of the plurality of transistor structures are located on the other side of the metal gate 303 (e.g., on the left side of the image). Figure 3A (on the right side of the image) This structure is easier to implement during device manufacturing and can reduce the manufacturing cost of the test structure.

[0039] In this embodiment, the test structure further includes an insulating medium ( Figure 3A and Figure 3B (Not shown in the image), the metal gate 303, the first metal line 501, the second metal line 502, the third metal line 503 and the fourth metal line 504 are all disposed in an insulating medium and are isolated by the insulating medium; the material of the insulating medium includes silicon dioxide.

[0040] In this embodiment, all sources of the plurality of transistor structures are electrically connected to the first metal line 501 via conductive plugs 60, all drains of the plurality of transistor structures are electrically connected to the second metal line 502 via conductive plugs 60, one end of the metal gate 303 is electrically connected to the third metal line 503 via conductive plugs 60, and the other end of the metal gate 303 is electrically connected to the fourth metal line 504 via conductive plugs 60. The semiconductor substrate 30 and the seventh pad 407 are electrically connected via conductive plugs 60. The conductive plugs 60 are formed by filling the vias formed in the insulating medium with conductive material. It should be noted that, for the sake of clarity and simplicity in the drawings, Figure 3A and Figure 3B In the figure, the conductive plugs are not distinguished and are marked with the same reference numeral 60. It can be understood that the aforementioned conductive plugs 60 with different structures do not represent the same conductive plug, and the conductive plugs are generally located in different positions.

[0041] In this embodiment, preferably, the first metal line 501, the second metal line 502, the third metal line 503, and the fourth metal line 504 are located in the same metal layer. In metal interconnect technology, the concept of a metal layer represents the position of a metal line within a wafer. Metal lines within the same metal layer are typically located at the same height on the wafer and formed in a single step. Forming the first metal line 501, the second metal line 502, the third metal line 503, and the fourth metal line 504 within the same metal layer simplifies the process flow for forming the test structure and reduces the manufacturing cost of the test structure.

[0042] In this embodiment, the electrical connection between each pad and the corresponding metal line is achieved through direct contact, such as... Figure 3A and Figure 3B As shown in the diagram. However, it should be noted that the pad assembly, as the external contact of the test structure, is generally formed on the top layer (or surface layer) of the wafer where the test structure is located. Therefore, the electrical connection structure between each pad and its corresponding metal line can be other interconnect structures depending on the actual process requirements. For example, it can be a conductive plug in a via, or a combination of a conductive plug and a metal line in a trench. Similarly, in this embodiment, the semiconductor substrate 30 and the pad 407 are electrically connected through a conductive plug 60. However, in other embodiments, the semiconductor substrate 30 and the pad 407 can also be electrically connected through other forms of interconnect structures, such as a combination of a conductive plug and a metal line.

[0043] The working principle of the above test structure can be briefly described as follows:

[0044] When reliability testing (including HCI testing and / or NBTI testing) is required, the first pad 401 is used as the source test terminal, the second pad 402 as the drain test terminal, any one of the third pad 403, fourth pad 404, fifth pad 405, and sixth pad 406 electrically connected to the metal gate 303 is used as the gate test terminal, and the seventh pad 407 is used as the substrate test terminal and grounded. A test voltage is applied to the source test terminal, drain test terminal, or gate test terminal using probes, and the corresponding electrical parameters (e.g., drain current I) are measured. d Substrate current I sub The reliability test is performed on a parallel structure composed of multiple transistors. In contrast, in existing technologies, reliability testing typically involves a single transistor. Although the test objects differ, the underlying principle remains the same. During the reliability test on the parallel structure, the channel and gate dielectric of the transistor are damaged under test voltage, causing changes in electrical parameters. Therefore, the reliability parameters of the transistor are reflected in the curves showing the changes in these electrical parameters over time. Since the specific process or method of the reliability test is existing technology, it will not be elaborated here. This is because the specific process or method of the reliability test is existing technology.

[0045] When electromigration testing is required, current is applied to the third pad 403 via a probe, and the sixth pad 406 is grounded, thus forming the current in the electromigration test structure. The voltage between the fourth pad 404 and the fifth pad 405 is then detected via a probe, and the resistance value of the metal gate 303 is calculated. During this process, the first pad 401, the second pad 402, and the seventh pad 407 are not connected to external current or voltage sources. Accelerated testing conditions are typically used during the test. Under accelerated testing conditions, the applied current is greater than the safe current of the metal gate 303, which refers to the maximum current that maintains the safe operation of the metal gate transistor without causing a load. Because the applied current causes electromigration in the metal gate 303, voids 70 gradually form within the metal gate 303. Therefore, as the test progresses, the resistance of the metal gate 303 will change over time. Therefore, the resistance value changes over time throughout the entire test process. Data processing of this resistance value change curve yields the time it takes for the resistance of the metal gate 303 to deviate from a predetermined threshold due to electromigration. This time is the electromigration failure lifetime of the metal gate 303 (test metal). By comparing the accelerated test conditions and the normal operating conditions of the metal gate, an acceleration factor can be calculated. Based on the electromigration failure lifetime of the metal gate 303 and the acceleration factor, the actual electromigration failure lifetime of the metal gate is finally obtained. Since the specific process or method of the electromigration test is existing technology, it will not be elaborated here.

[0046] In summary, the test structure for a metal gate transistor provided by this invention includes a reliability testing terminal and an electromigration testing terminal. The reliability testing terminal can be used to perform conventional reliability tests on the transistor, including hot carrier injection testing and negative bias temperature instability testing. The electromigration testing terminal can be used to perform electromigration tests on the metal gate of the transistor. Therefore, the test structure for a metal gate transistor provided by this invention integrates the previously separate reliability testing structure and electromigration testing structure into a single test structure, solving the problem of insufficient test structure quantity caused by separate test structures and limited dicing area, saving test structure area, and improving wafer utilization.

[0047] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention using the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention are still within the scope of protection of the present invention. It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein; these can vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and not to limit the scope of the present invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates the opposite. Therefore, the word “or” should be understood as having a logical “or” definition, not a logical “XOR” definition, unless the context clearly indicates the opposite. The structure described here will be understood as a functional equivalent that also references that structure. Language that can be interpreted as approximate should be understood in that way unless the context explicitly indicates the opposite.

Claims

1. A test structure for a metal gate transistor, characterized in that, include: Semiconductor substrate; Multiple transistor structures formed on the semiconductor substrate, each transistor structure including a metal gate and a source and a drain located on both sides of the metal gate, the multiple transistor structures sharing a single metal gate; A pad assembly, comprising a first pad, a second pad, a third pad, a fourth pad, a fifth pad, and a sixth pad, wherein all sources of the plurality of transistor structures are electrically connected to the first pad, all drains of the plurality of transistor structures are electrically connected to the second pad, one end of the metal gate is electrically connected to the third and fourth pads, and the other end of the metal gate is electrically connected to the fifth and sixth pads; Wherein, any one of the third, fourth, fifth, and sixth pads, together with the first and second pads, forms a test terminal for reliability testing, and the third, fourth, fifth, and sixth pads form a test terminal for electromigration testing.

2. The test structure as described in claim 1, characterized in that, The pad assembly further includes a seventh pad, which is electrically connected to the semiconductor substrate.

3. The test structure as described in claim 1, characterized in that, The test structure further includes: a first metal line, a second metal line, a third metal line, and a fourth metal line. All sources of the plurality of transistor structures are electrically connected to the first pad through the first metal line. All drains of the plurality of transistor structures are electrically connected to the second pad through the second metal line. One end of the metal gate is electrically connected to the third pad and the fourth pad through the third metal line. The other end of the metal gate is electrically connected to the fifth pad and the sixth pad through the fourth metal line.

4. The test structure as described in claim 3, characterized in that, The test structure also includes an insulating medium, and the metal gate, the first metal line, the second metal line, the third metal line and the fourth metal line are all disposed in the insulating medium and isolated by the insulating medium.

5. The test structure as described in claim 3, characterized in that, All sources of the plurality of transistor structures are electrically connected to the first metal line through conductive plugs, all drains of the plurality of transistor structures are connected to the second metal line through conductive plugs, one end of the metal gate is connected to the third metal line through a conductive plug, and the other end of the metal gate is electrically connected to the fourth metal line through a conductive plug.

6. The test structure as described in claim 3, characterized in that, The first, second, third, and fourth metal lines are in direct contact with their corresponding pads, forming a direct contact electrical connection.

7. The test structure as described in claim 3, characterized in that, The first metal line, the second metal line, the third metal line, and the fourth metal line are electrically connected to their corresponding pads via conductive plugs.

8. The test structure as described in claim 3, characterized in that, The first metal line, the second metal line, the third metal line, and the fourth metal line are located in the same metal layer.

9. The test structure as described in claim 1, characterized in that, All sources of the plurality of transistor structures are located on one side of the metal gate, and all drains of the plurality of transistor structures are located on the other side of the metal gate.

10. The test structure as described in claim 1, characterized in that, The metal material of the metal gate includes aluminum.

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