Photoelectric conversion device and driving method thereof

Abstract

To provide technique for improving the performance of a photoelectric conversion device.SOLUTION: A photoelectric conversion device comprises: a pixel that includes a photoelectric conversion unit; an AD conversion unit that performs AD conversion on an analog signal generated in the pixel; and a control unit that controls the AD conversion unit. The control unit is configured to control the AD conversion unit to perform multiple times of AD conversion on the same analog signal generated in the pixel, where a first AD conversion period and a second AD conversion period of the multiple times of AD conversion have different lengths.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] In photoelectric conversion devices such as solid-state imaging devices, there is a demand for reduced noise levels, an expanded dynamic range, and high-speed readout to improve the S / N ratio. To meet these demands, Patent Document 1 discloses a technology for expanding the dynamic range by providing multiple amplifiers that amplify output signals from an imaging element at different amplification factors and selecting / combining the signal outputs of the multiple amplifiers depending on the brightness of the subject. Patent Document 2 also discloses a technology for increasing speed by changing the period for analog-to-digital conversion of the amplifier output signal depending on the amplification factor of the amplifier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-128253 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-054424 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the technology described in Patent Document 1, when multiple output signals are combined to obtain an image, image quality can be degraded due to offsets and gain errors between output signals caused by characteristic variations between signal processing circuits including multiple amplifiers. To address this issue, a configuration in which signals are sequentially processed at different amplification rates using the same signal processing circuit could be considered, but this increases the readout time and is therefore not suitable for speeding up readout. Furthermore, while the technology described in Patent Document 2 is a configuration that can speed up analog-to-digital conversion when the output amplitude of the amplifier is small, it has not been sufficiently considered in terms of S / N ratio and dynamic range.

[0005] An object of the present invention is to provide a technique that is advantageous in improving the performance of a photoelectric conversion device. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel having a photoelectric conversion unit and an analog signal generated in the pixel an amplifier for sequentially amplifying the analog signal amplified by the amplifier at a plurality of different gains using the same amplifier; and an AD conversion unit that performs AD conversion of the analog signal by comparing the level of the analog signal with the level of a reference signal whose level changes over time, and a control unit that controls the AD conversion unit, wherein the control unit controls the AD conversion unit to convert the same analog signal generated in the pixel The analog signal amplified by the amplifier It is configured to perform multiple AD conversions on the AD conversion unit performs AD conversion on the analog signal amplified by a first amplification factor during a first AD conversion period of the plurality of AD conversions, and performs AD conversion on the analog signal amplified by a second amplification factor higher than the first amplification factor during a second AD conversion period of the plurality of AD conversions; before Record number The length of one AD conversion period is Record number There is provided a photoelectric conversion device in which the length of a second AD conversion period is shorter than two AD conversion periods, the rate of change of a reference signal used in the second AD conversion period is smaller than the rate of change of a reference signal used in the first AD conversion period, the potential of the reference signal changes to a first level during the second AD conversion period, and the potential of the reference signal changes to the first level during the first AD conversion period.

[0007] According to another disclosure of the present specification, a pixel having a photoelectric conversion unit and an analog signal generated in the pixel an amplifier for sequentially amplifying the analog signal amplified by the amplifier at a plurality of different gains using the same amplifier; and an AD conversion unit that performs AD conversion of the analog signal by comparing the level of the analog signal with the level of a reference signal whose level changes over time, The analog signal obtained by amplifying performing a plurality of AD conversions with different lengths of AD conversion periods on the image signal, obtaining a plurality of digital signals corresponding to the plurality of AD conversions, and synthesizing the plurality of digital signals to generate an image signal; performing AD conversion on the analog signal amplified by a first amplification factor during a first AD conversion period of the plurality of AD conversions; and performing AD conversion on the analog signal amplified by a second amplification factor higher than the first amplification factor during a second AD conversion period of the plurality of AD conversions; before Record number The length of one AD conversion period is Record numberThere is provided a method for driving a photoelectric conversion device, in which the length of a second AD conversion period is shorter than two AD conversion periods, the rate of change with time of a reference signal used in the second AD conversion period is smaller than the rate of change with time of a reference signal used in the first AD conversion period, the potential of the reference signal changes to a first level during the second AD conversion period, and the potential of the reference signal changes to the first level during the first AD conversion period. [Effects of the Invention]

[0008] According to the present invention, it is possible to realize a photoelectric conversion device that improves the S / N ratio and increases the readout speed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 2] 1 is an equivalent circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Figure 3] 2 is an equivalent circuit diagram showing an example of the configuration of an amplifier in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 4] FIG. 1 is a timing chart (part 1) showing a method for driving a photoelectric conversion device. [Figure 5] FIG. 2 is a timing chart (part 2) showing a method for driving a photoelectric conversion device. [Figure 6] 1 is a graph (part 1) showing an example of digital signal processing in a digital signal processing unit. [Figure 7] 10 is a graph (part 2) showing an example of digital signal processing in the digital signal processing unit. [Figure 8] 10 is a graph (part 3) showing an example of digital signal processing in the digital signal processing unit. [Figure 9] 10 is a graph showing the relationship between the amount of incident light and pixel output signals and optical shot noise. [Figure 10] FIG. 3 is a timing chart (part 1) showing a method for driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 11] 4 is a graph (part 1) showing an example of digital signal processing in the method for driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 12] 6 is a graph (part 2) showing an example of digital signal processing in the method for driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 13] 10 is a graph (part 3) showing an example of digital signal processing in the method for driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 14] FIG. 4 is a timing chart (part 2) showing the method of driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 15] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a second embodiment of the present invention. [Figure 16] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a third embodiment of the present invention. [Figure 17] 10 is a graph (part 1) showing an example of digital signal processing in the method for driving a photoelectric conversion device according to the third embodiment of the present invention. [Figure 18] 10 is a graph (part 2) showing an example of digital signal processing in the method for driving the photoelectric conversion device according to the third embodiment of the present invention. [Figure 19] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 20] 10 is a graph (part 1) showing an example of digital signal processing in a method for driving a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 21] 13 is a graph (part 2) showing an example of digital signal processing in the method for driving the photoelectric conversion device according to the fourth embodiment of the present invention. [Figure 22] FIG. 10 is a diagram illustrating the signal processing content in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 23] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 24] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a sixth embodiment of the present invention. [Figure 25] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a sixth embodiment of the present invention. [Figure 26] FIG. 10 is a diagram illustrating the signal processing content in a photoelectric conversion device according to a sixth embodiment of the present invention. [Figure 27] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a seventh embodiment of the present invention. [Figure 28] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving body according to an eighth embodiment of the present invention. [Figure 29] FIG. 13 is a block diagram showing a schematic configuration of a device according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] The structure of a photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 3. Fig. 1 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. Fig. 2 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Fig. 3 is an equivalent circuit diagram showing an example of the configuration of an amplifier in the photoelectric conversion device according to this embodiment.

[0011] 1, the photoelectric conversion device 100 according to this embodiment includes a pixel section 10, a pixel driving section 20, an amplifier section 30, a comparator section 40, a memory section 50, a horizontal scanning section 60, a digital signal processing section 70, an output section 80, and a timing generation section 90. The photoelectric conversion device 100 also includes a reference signal generation section 46 and a counter section 54.

[0012] The pixel unit 10 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit made up of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. Each pixel 12 may include a color filter having a predetermined spectral sensitivity characteristic. The number of rows and columns of the pixel array arranged in the pixel unit 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel unit 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like.

[0013] Pixel drive signal lines 14 are arranged in each row of the pixel section 10, extending in a first direction (the horizontal direction in FIG. 1). The pixel drive signal lines 14 in each row are connected to the pixels 12 aligned in the first direction, respectively, and serve as signal lines common to these pixels 12. The first direction in which the pixel drive signal lines 14 extend is sometimes referred to as the row direction or horizontal direction. The pixel drive signal lines 14 are connected to a pixel drive section 20.

[0014] In each column of the pixel unit 10, a pixel output line 16 is arranged, extending in a second direction (vertical direction in FIG. 1 ) intersecting the first direction. The pixel output line 16 in each column is connected to the pixels 12 aligned in the second direction and serves as a common signal line for these pixels 12. The second direction in which the pixel output lines 16 extend is sometimes referred to as the column direction or vertical direction. A current source 18 is connected to each of the plurality of pixel output lines 16. The plurality of pixel output lines 16 are also connected to an amplifier unit 30.

[0015] The pixel driving unit 20 is a control circuit unit that receives control signals supplied from the timing generation unit 90, generates control signals for driving the pixels 12, and supplies the control signals to the pixels 12 via pixel driving signal lines 14. The pixel driving unit 20 may use logic circuits such as a shift register or an address decoder. The pixel driving unit 20 may be configured to sequentially supply control signals to the pixel driving signal lines 14 of each row, thereby sequentially driving the pixels 12 of the pixel unit 10 row by row. The signals read out from the pixels 12 row by row are input to the amplifier unit 30 via pixel output lines 16 provided for each column of the pixel unit 10.

[0016] The amplifier unit 30 has a plurality of amplifiers 32 provided corresponding to each column of the pixel unit 10. Each of the plurality of amplifiers 32 has an input node connected to the pixel output line 16 of the corresponding column, and an output node. The output node of each of the plurality of amplifiers 32 is connected to the amplified signal output line 36 of the corresponding column out of a plurality of amplified signal output lines 36 provided corresponding to each column of the pixel unit 10. The plurality of amplified signal output lines 36 are connected to the comparator unit 40.

[0017] The reference signal generating unit 46 is a circuit unit that receives a control signal supplied from the timing generating unit 90, generates a reference signal to be used in analog-to-digital conversion (AD conversion), and outputs the generated reference signal to the comparing unit 40 via a reference signal output line 48. The reference signal is a signal whose signal level changes over time, such as a ramp signal. A ramp signal is a signal whose signal level gradually changes (increases or decreases) from a predetermined value at a constant rate of change over time. In the following description, the rate of change of the reference signal (ramp signal) with respect to time may be referred to as the slope of the reference signal (ramp signal). The reference signal may be any signal having a predetermined amplitude that can be applied to AD conversion, and is not necessarily limited to a ramp signal.

[0018] The comparison unit 40 has a plurality of buffer circuits 42 and a plurality of comparators 44 provided corresponding to each column of the pixel unit 10. Each of the plurality of comparators 44 has a first input node connected to the amplified signal output line 36 of the corresponding column, a second input node connected to the reference signal output line 48 via the buffer circuit 42 of the corresponding column, and an output node. The output node of the comparator 44 is connected to the memory unit 50.

[0019] The counter unit 54 is a circuit unit that receives a control signal supplied from the timing generation unit 90, generates a count signal whose count value transitions at a constant frequency, and outputs the generated count signal to the memory unit 50 via a count signal line 56. The count signal is a signal made up of multiple bits, and the count signal line 56 includes multiple signal lines corresponding to the number of bits of the count signal.

[0020] The memory unit 50 has a plurality of memories 52 provided corresponding to each column of the pixel unit 10. Each of the plurality of memories 52 is a memory configured with a plurality of bits. Each of the plurality of memories 52 has a first input node connected to the output node of the comparator 44 of the corresponding column, a second input node connected to a count signal line 56, a third input node connected to the horizontal scanning unit 60, and an output node connected to a horizontal transfer line 58. The memory 52 is configured to hold a count value indicated by a count signal received at the timing when a latch signal indicating that the magnitude relationship between the level of the output signal of the amplifier 32 and the level of the reference signal has been reversed is output from the comparator 44. The count value thus held in the memory 52 becomes digital data of the pixel signal.

[0021] The horizontal scanning unit 60 is a control circuit unit that receives control signals supplied from the timing generation unit 90, generates control signals for reading digital data of pixel signals from the memory unit 50, and supplies the control signals to the memory unit 50. The control lines of the horizontal scanning unit 60 provided corresponding to each column of the pixel unit 10 are connected to the memories 52 of the corresponding columns. The horizontal transfer lines 58 are connected to the digital signal processing unit 70.

[0022] The digital signal processing unit 70 has the function of performing digital signal processing such as addition / subtraction between data, digital gain, offset addition / subtraction, decoding, and data scrambling on the digital data transferred from the memory unit 50. The digital signal processing unit 70 is connected to the output unit 80.

[0023] The output unit 80 has a function for outputting data processed in the digital signal processing unit 70 to the outside of the photoelectric conversion device 100. For example, the output unit 80 may have an output means that outputs a voltage from a single terminal, such as a buffer circuit, or an output means that uses LVDS (Low Voltage Differential Signaling) technology and has two differential terminals. The output unit 80 may also have a parallel / serial conversion (P / S conversion) function.

[0024] The timing generation unit 90 is a circuit for supplying control signals for controlling the operation and timing of the pixel drive unit 20, the amplifier unit 30, the comparator unit 40, the reference signal generation unit 46, the memory unit 50, the counter unit 54, the horizontal scan unit 60, and the output unit 80. In other words, the timing generation unit 90 serves as a control unit for controlling the pixel drive unit 20, the amplifier unit 30, the comparator unit 40, the reference signal generation unit 46, the memory unit 50, the counter unit 54, the horizontal scan unit 60, and the output unit 80. At least some of these control signals may be supplied from outside the photoelectric conversion device 100.

[0025] Next, an outline of the operation of the photoelectric conversion device 100 according to this embodiment will be described with reference to FIG. Under the control of the timing generation unit 90, the pixel drive unit 20 performs so-called vertical scanning, which drives the multiple pixels 12 that make up the pixel unit 10 row by row, using control signals supplied via pixel drive signal lines 14. As a result, pixel signals from the multiple pixels 12 are output row by row sequentially to the pixel output lines 16 of each column. The pixel signals output from the pixels 12 may include signals (light signals, photoelectric conversion signals) corresponding to signal amounts that depend on the amount of light incident on the photoelectric conversion unit, and signals (reference signals, reset signals) corresponding to noise amounts. The pixel signals output from the pixels 12 to the pixel output lines 16 are input to the amplifier unit 30.

[0026] The pixel signals output from the pixels 12 via the pixel output lines 16 are amplified by the amplifiers 32 for the corresponding columns at a predetermined amplification factor and then input to the comparators 44 for the corresponding columns. The comparators 44 compare the signal level of the pixel signals with the signal level of a reference signal input from the reference signal generators 46 via the buffer circuits 42, and output a latch signal when the magnitude relationship between the signal levels of the pixel signals and the ramp signal is reversed. The count signal supplied from the counter unit 54 and the output signal of the comparator 44 are input to the memory 52. ​​The memory 52 stores the count value indicated by the count signal at the time when the latch signal is received from the comparator 44 as digital data of the pixel signal. In this way, the pixel signals, which are analog signals output from the pixels 12, are converted into digital data (digital pixel signals). The comparators 40, the reference signal generators 46, the memory units 50, and the counter units 54 constitute an AD converter that converts the pixel signals, which are analog signals output from the pixels 12, into digital signals.

[0027] Under the control of the timing generation unit 90, the horizontal scanning unit 60 outputs a control signal to the memory 52 of the memory unit 50 sequentially for each column. Upon receiving the control signal from the horizontal scanning unit 60, the memory 52 outputs the digital pixel signals it holds to the horizontal transfer line 58.

[0028] The digital pixel signals output to the horizontal transfer line 58 undergo predetermined digital signal processing in the digital signal processing unit 70 , and are then output to the outside of the photoelectric conversion device 100 via the output unit 80 .

[0029] Next, an example of the configuration of the pixel 12 in the photoelectric conversion device 100 of this embodiment will be described with reference to FIG. Each pixel 12 may be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in Fig. 2, for example. Each pixel 12 may have a microlens and a color filter arranged on the optical path of incident light leading to the photoelectric conversion element PD. The microlens serves to focus incident light onto the photoelectric conversion element PD. The color filter serves to selectively transmit light of a predetermined color.

[0030] The photoelectric conversion element PD is, for example, a photodiode, with its anode connected to a reference voltage line GND and its cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion portion FD. The floating diffusion portion FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include pn junction capacitance, wiring capacitance, etc. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage line VDD (voltage VDD). The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to a pixel output line 16.

[0031] In the pixel configuration of FIG. 2, the pixel drive signal lines 14 for each row include a signal line connected to the gate of the transfer transistor M1, a signal line connected to the gate of the reset transistor M2, and a signal line connected to the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the pixel drive unit 20 via these signal lines. A control signal PRES is supplied to the gate of the reset transistor M2 from the pixel drive unit 20 via this signal line. A control signal PSEL is supplied to the gate of the selection transistor M4 from the pixel drive unit 20 via this signal line. When each transistor is an N-type MOS transistor, a high-level control signal supplied from the pixel drive unit 20 turns the corresponding transistor on. A low-level control signal supplied from the pixel drive unit 20 turns the corresponding transistor off.

[0032] In this embodiment, the description will be made assuming that electrons, among the electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be referred to by the reverse names.

[0033] The photoelectric conversion element PD converts incident light into an electric charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the floating diffusion region FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the floating diffusion region FD. As a result, the floating diffusion region FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0034] When the selection transistor M4 is turned on, it connects the source of the amplification transistor M3 to the pixel output line 16. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source 18 via the selection transistor M4, forming an amplification unit (source follower circuit) with its gate as an input node. This causes the amplification transistor M3 to output a signal based on the potential of the floating diffusion region FD to the pixel output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal according to the amount of charge held in the floating diffusion region FD.

[0035] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the floating diffusion region FD, which serves as a charge storage region, to the floating diffusion region FD. When the reset transistor M2 is turned on, it resets the floating diffusion region FD to a potential corresponding to the voltage VDD.

[0036] Next, a configuration example of the amplifier 32 in the photoelectric conversion device 100 of this embodiment will be described with reference to FIG. Each of the amplifiers 32 may be configured with an amplifier circuit 34, an input capacitance C0, feedback capacitances C1, C2, and C3, and switches S0, S1, S2, and S3, as shown in FIG. 3 . The amplifier circuit 34 may be, for example, a differential amplifier circuit. The input node of the amplifier circuit 34 is connected to the pixel output line 16 via the input capacitance C0. The output node of the amplifier circuit 34 is connected to an amplified signal output line 36. Connected in parallel between the input node and output node of the amplifier circuit 34 are the switch S0, a series connection of a feedback capacitance C1 and a switch S1, a series connection of a feedback capacitance C2 and a switch S2, and a series connection of a feedback capacitance C3 and a switch S3.

[0037] When the amplifier circuit 34 is an inverting amplifier circuit, the voltage amplification factor of the amplifier 32 is expressed as -(input capacitance (C0) / feedback capacitances (C1 to C3)). The voltage amplification factor of the amplifier 32 can be switched by switching which of the feedback capacitances C1 to C3 to select using the switches S1 to S3 and changing the feedback coefficient determined by the voltage division ratio between the feedback capacitances C1 to C3 and the input capacitance C0. In other words, the amplifier 32 is an amplification unit configured to be able to change the voltage amplification factor. Control signals for the switches S0, S1, S2, and S3 are supplied from the timing generation unit 90.

[0038] Next, a standard driving example of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a timing diagram showing a driving method of the photoelectric conversion device according to this embodiment. Fig. 4 shows temporal changes in the voltage amplification factor of amplifier 32, control signals PRES, PTX, and PSEL, control signals for switches S0, S1, S2, and S3, the output signal of amplifier 32, the ramp signal, the output signal of comparator 44, and the count signal. Switches S0, S1, S2, and S3 are turned on when the corresponding control signal is at a high level, and turned off when the corresponding control signal is at a low level.

[0039] Prior to the readout operation, the photoelectric conversion element PD is exposed to light for a set time (exposure period). Charges corresponding to the amount of light incident on the photoelectric conversion element PD during the exposure period are accumulated. During this time, the control signal PRES is at a high level, the reset transistor M2 is on, and the gate of the amplification transistor M3 and the floating diffusion region FD are in a reset state. Furthermore, the switches S0 to S3 are on, the amplification circuit 34 is in a voltage follower state, and the amplified signal output line 36 is at a potential V0. At this time, both terminals of the feedback capacitances C1 to C3 are short-circuited, and these terminals are also at a potential V0.

[0040] First, the control signals for the switches S2 and S3 are transitioned from high level to low level to turn off the switches S2 and S3, thereby disconnecting the feedback capacitors C2 and C3 from the feedback path of the amplifier circuit .

[0041] Next, the control signal for switch S0 transitions from high to low, turning off switch S0, thereby releasing the reset state of the amplifier circuit 34. Furthermore, the control signal PRES transitions from high to low, turning off reset transistor M2, thereby releasing the reset state of the gate of amplifier transistor M3 and floating diffusion region FD. A potential corresponding to the release of the reset state is maintained in the floating diffusion region FD. At this time, the control signal PSEL is high, the selection transistor M4 is on, and a signal of a potential corresponding to the reset potential of the floating diffusion region FD is output to the pixel output line 16 by the source follower circuit formed by amplifier transistor M3 and current source 18.

[0042] Next, the control signal PTX transitions to a high level for a predetermined period, turning on the transfer transistor M1, thereby transferring the charge accumulated in the photoelectric conversion element PD to the floating diffusion region FD. Here, if the absolute value of the amount of charge transferred to the floating diffusion region FD is Q and the capacitance of the floating diffusion region FD is CFD, the gate potential of the amplifier transistor M3 connected to the floating diffusion region FD drops by Q / CFD. Furthermore, the potential of the pixel output line 16 also changes in response to the change in the gate potential of the amplifier transistor M3. If the gain of the source follower circuit is Gsf, the potential change (amplitude) ΔV1 of the potential V1 of the pixel output line 16 due to the charge transfer from the photoelectric conversion element PD to the floating diffusion region FD is expressed as follows: ΔV1=-Q×Gsf / CFD …(1)

[0043] This potential change amount ΔV1 is amplified by the amplifier 32, which is composed of an amplifier circuit 34, an input capacitance C0, and a feedback capacitance C1. At this time, the potential change amount (amplitude) ΔV2 of the output potential of the amplifier 32 is expressed by the following equation (2). The output potential V2 of the amplifier 32 is expressed by the following equation (3). The voltage amplification factor C0 / C1 set in the amplifier 32 at this time is called Gain1. ΔV2=Q×(Gsf / CFD)×(C0 / C1) …(2) V2=V0+Q×(Gsf / CFD)×(C0 / C1) …(3)

[0044] In the following description, the period from when the control signal PRES and the control signal of the switch S0 transition from high to low until the control signal PTX goes high will be referred to as the pixel noise level readout period. The period after the control signal PTX goes high will be referred to as the pixel signal level readout period. The period during which the comparator 40 compares the pixel signal with the reference signal will be referred to as the comparison period or AD conversion period. The AD conversion period during the pixel noise level readout period will be referred to as the NAD period TN1. The AD conversion period during the pixel signal level readout period will be referred to as the SAD period TS1. The period from the start of the NAD period to the end of the SAD period will be referred to as the AD conversion period T1 for one pixel.

[0045] The comparator 44 performs a comparison operation to compare the potential level of the output signal of the amplifier 32 with the potential level of the reference signal. The comparator 44 outputs a pulse signal (latch signal) indicating the comparison result at the timing when the magnitude relationship between the potential level of the output signal of the amplifier 32 and the potential level of the reference signal is reversed.

[0046] The counter unit 54 starts counting the clock signal (clock pulses) in response to the reference signal generation unit 46 starting to change the potential level of the reference signal. The start of the change in the potential level of the reference signal and the start of counting by the counter unit 54 do not need to coincide perfectly. For example, the counter unit 54 may start counting a predetermined period after the start of the change in the potential level of the reference signal. When the memory 52 receives a latch signal from the comparator 44 during the NAD period TN1, it stores the count value a of the count signal supplied from the count signal line 56 at that time. Similarly, when the memory 52 receives a latch signal from the comparator 44 during the SAD period TS1, it stores the count value b of the count signal supplied from the count signal line 56 at that time. The count values ​​a and b stored in the memory 52 in this manner are AD-converted values ​​(digital data) of the pixel signal. The memory 52 is configured to have multiple memories corresponding to pixel noise level readout and pixel signal level readout, respectively.

[0047] The count value held in the memory 52 is transferred to the digital signal processing unit 70 in response to a control signal from the horizontal scanning unit 60, and after undergoing digital signal processing in the digital signal processing unit 70, is output to the outside via the output unit 80. An example of the digital signal processing in the digital signal processing unit 70 is a process of subtracting the AD conversion value a from the AD conversion value b. By performing this subtraction process, it is possible to remove reset noise of the pixel 12, offset differences occurring in the plurality of amplifiers 32 and the plurality of comparators 44, including the pixel 12, and fixed pattern noise, thereby improving image quality.

[0048] Next, another example of driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a timing diagram showing a method of driving the photoelectric conversion device according to this embodiment. Fig. 5 shows changes over time in the voltage amplification factor of amplifier 32, control signals PRES, PTX, and PSEL, control signals for switches S0, S1, S2, and S3, the output signal of amplifier 32, the ramp signal, the output signal of comparator 44, and the count signal. Switches S0, S1, S2, and S3 are turned on when the corresponding control signal is at a high level, and turned off when the corresponding control signal is at a low level.

[0049] The driving example in Fig. 5 is a standard driving example for expanding the dynamic range. That is, the driving example in Fig. 5 can be applied to the case where an image with an expanded dynamic range is generated using signals obtained by amplifying with different voltage gains. Specifically, pixel signals are amplified with two gains, voltage gain Gain1 and voltage gain Gain2, and then AD converted.

[0050] First, the process is performed up to the SAD period TS1 in the same manner as in the driving example of Fig. 4, and the AD conversion value a and the AD conversion value b are acquired. The voltage amplification factor at this time is Gain1.

[0051] Next, the control signals for switches S2 and S3 transition from low to high, turning on switches S2 and S3. As a result, the feedback capacitance of amplifier circuit 34 becomes (C1+C2+C3), and the voltage gain of amplifier 32 becomes C0 / (C1+C2+C3). The voltage gain at this time is Gain2. The output potential V3 of amplifier 32 at this time is expressed by the following equation (4). V3=V0+Q×(Gsf / CFD)×(C0 / (C1+C2+C3))…(4)

[0052] The comparison unit 40 and memory unit 50 perform AD conversion on the pixel signal amplified by the voltage amplification factor Gain2, as in the SAD period TS1, and store the acquired AD-converted value in the memory 52. ​​This period will be referred to as the SAD period TS2. The memory 52 will store the count value c as the AD-converted value.

[0053] Next, the control signal PRES is transitioned to a high level for a predetermined period to turn on the reset transistor M2 and reset the floating diffusion FD. Also, the control signal for the switch S0 is transitioned to a high level for a predetermined period to turn on the switch S0 and reset the amplifier 32. As a result, a pixel signal at the pixel noise level is output to the pixel output line 16, and a signal obtained by amplifying this pixel signal by a voltage amplification factor Gain2 is output to the amplified signal output line 36.

[0054] The comparison unit 40 and memory unit 50 perform AD conversion on the pixel signal of the pixel noise level amplified by the voltage amplification factor Gain2, as in the NAD period TN1, and store the acquired AD-converted value in the memory 52. ​​This period will be referred to as the NAD period TN2. The memory 52 will store the count value d as the AD-converted value.

[0055] The AD conversion value obtained during the NAD period TN2 contains noise when the reset transistor M2 and the switch S0 are off, but this noise may not match the noise contained in the AD conversion value obtained during the NAD period TN1. The data obtained during the NAD period TN2 may be effective in removing offsets, fixed pattern noise, and the like in the digital signal processing in the digital signal processing unit 70.

[0056] Furthermore, in this driving example, each of the memories 52 may be configured to have a plurality of memories corresponding to the NAD periods TN1 and TN2 and the SAD periods TS1 and TS2, respectively. Alternatively, the AD conversion values ​​held during the AD conversion periods TN1 and TS1 may be transferred to and held in another memory, and a portion of the memory after the AD conversion values ​​have been transferred may be used as a memory for holding the AD conversion values ​​during the AD conversion periods TN2 and TS2. The data held in the other memory during the AD conversion periods TN1 and TS1 may be horizontally transferred during the AD conversion periods TN2 and TS2.

[0057] In this driving example, the period from the start of the NAD period TN1 to the end of the NAD period TN2 is referred to as the AD conversion period T2 for one pixel. In this driving example, the order of AD conversion is AD conversion periods TN1, TS1, TS2, TN2. However, by changing the configuration of the amplifier 32, the order may be changed to AD conversion periods TN1, TN2, TS2, TS1 or TN1, TN2, TS1, TS2. In this embodiment, the AD conversion period is the period from when the potential of the reference signal starts to change to when the potential change ends. From another perspective, the AD conversion period is the period from when the counter unit 54 starts counting to when the counting operation ends. In the drawing, the start of the potential change of the reference signal and the start of the counting operation of the counter unit 54 are assumed to occur simultaneously. Therefore, the period from when the potential of the reference signal starts to change to when the potential change ends coincides with the period from when the counter unit 54 starts counting to when the counting operation ends. However, the period is not limited to this example, and as described above, it can be either the period from the start to the end of the change in the potential of the reference signal or the period from the start to the end of the counting operation of the counter unit 54. Note that although the present embodiment has been described taking AD conversion using a reference signal as an example, the period is not limited to this example. For example, in the case of successive approximation AD conversion, it can be the period from the start to the end of the change in the potential of the reference signal compared with the analog signal.

[0058] The count values ​​a, b, c, and d stored in memory 52 are transferred to the digital signal processing unit 70 in response to a control signal from the horizontal scanning unit 60, and after digital signal processing in the digital signal processing unit 70, are output to the outside via the output unit 80.

[0059] 6 to 8 are graphs illustrating an example of digital signal processing for AD converted values ​​obtained in the driving example shown in FIG.

[0060] FIG. 6 shows the result after subtraction processing in the digital signal processing unit 70. In FIG. 6, the horizontal axis represents the signal amplitude (amount of potential change ΔV1) of the pixel output line 16, and the vertical axis represents the result of subtracting the AD conversion value obtained during the NAD period from the AD conversion value obtained during the SAD period. Here, it is assumed that the maximum value of the amount of potential change ΔV1 of the pixel output line 16 based on equation (1) is 1.0 V, and the maximum value of the difference between the AD conversion values ​​obtained during the AD conversion periods TN1 and TS1 (hereinafter referred to as the AD conversion result) is 4096 LSB. In other words, the resolution of the AD conversion is 12 bits. It is also assumed that the voltage amplification factor Gain1 is C0 / C1=2, and the voltage amplification factor Gain2 is C0 / (C1+C2+C3)=1.

[0061] The slope of the reference signal and the frequency of the counter are set so that the AD conversion result (cd) is 4096 LSB when the voltage amplification factor is Gain2 (=1), the amount of potential change ΔV1 of the pixel output line 16 is 1.0 V, and the amount of potential change ΔV2 of the amplifier 32 is 1.0 V. This is shown by the dashed line in FIG. 6. On the other hand, when the voltage amplification factor is Gain1 (=2) and the amount of potential change ΔV1 of the pixel output line 16 is 0.5 V, the amount of potential change ΔV2 of the amplifier 32 becomes 1.0 V, and the AD conversion result (ba) becomes 4096 LSB. This is shown by the solid line in FIG. 6.

[0062] 6 shows that the amount of change in the AD conversion result with respect to the potential change of the pixel output line 16 varies depending on the voltage amplification factor of the amplifier 32. Specifically, when the voltage amplification factor is Gain1 (=2), the amount of change in the AD conversion result is twice as large as when the voltage amplification factor is Gain2 (=1).

[0063] FIG. 7 is a graph showing the results when the AD conversion result (cd) is multiplied by a 2x digital gain (=(cd)×2). When the voltage amplification factor is Gain2 (=1) and the amount of potential change ΔV1 of the pixel output line 16 is 0.5 V, the value (=(cd)×2) obtained by multiplying the AD conversion result (cd) by a 2x digital gain is 4096 LSB. In other words, the amount of change in the AD conversion result with respect to the amount of potential change ΔV1 of the pixel output line 16 at this time is the same as the amount of change in the AD conversion result (ba) with respect to the amount of potential change ΔV1 of the pixel output line 16 when the voltage amplification factor is Gain1. In this case, the maximum value of the AD conversion value is 8192 LSB.

[0064] 8 is a graph illustrating a method for synthesizing an image using the AD conversion results (ba) and (cd). As shown in FIG. 8, when the amount of potential change ΔV1 of the pixel output line 16 is in the range of 0 V or more and less than 0.5 V (low brightness region), the AD conversion result (ba) of the pixel signal amplified by a voltage gain Gain1 is used as image data. Also, when the amount of potential change ΔV1 of the pixel output line 16 is in the range of 0.5 V or more (high brightness region), the AD conversion result (cd) × 2 of the pixel signal amplified by a voltage gain Gain2 is used as image data.

[0065] Because the voltage amplification factor Gain1 is higher than the voltage amplification factor Gain2, the AD conversion result (ba) is more advantageous than the AD conversion result (cd) in terms of the amount of noise after the amplifier 32. On the other hand, the AD conversion result (cd) is 4096 LSB when the potential change amount ΔV1 of the pixel output line 16 is at its maximum of 1.0 V, so it is more advantageous than the AD conversion result (ba) in terms of input dynamic range. Therefore, the image synthesized as shown in FIG. 8 is an image with an improved S / N ratio and an expanded dynamic range.

[0066] On the other hand, the NAD periods TN1 and TN2, and the SAD periods TS1 and TS2 each require the same processing time, so the AD conversion period T2 for one pixel takes twice as long as the AD conversion period T1 for one pixel described using Fig. 4. Therefore, in the driving example of Fig. 5, the readout time becomes longer and the frame rate decreases.

[0067] Another method for obtaining an image with an expanded dynamic range using two AD conversion results obtained with different voltage gains is to provide two or more signal processing circuits after the amplifier 32 and process the same pixel signal simultaneously in these signal processing circuits. While this configuration example can shorten the readout time, image quality may be degraded due to errors in the two or more signal processing circuits, such as an offset caused by an error in the voltage gain or operating point of the amplifier 32. Furthermore, the circuit size may become larger, which may be disadvantageous in terms of chip size and power supply current capacity.

[0068] Fig. 9 is a diagram illustrating the S / N ratio of pixel signals in the digital signal processing described with reference to Figs. 6 to 8. In Fig. 9, the horizontal axis represents the amount of light incident on the pixel 12, and the vertical axis represents the signal level (pixel output signal) photoelectrically converted in response to the incident light and the optical shot noise, all on a logarithmic scale. In Fig. 9, the solid line represents the relationship between the amount of incident light and the pixel output signal. The dashed line represents the relationship between the amount of incident light and the optical shot noise. The dotted line represents pixel-related noise (including noise caused by the amplifier 32, but excluding noise caused by AD conversion).

[0069] Assuming that the pixel noise is 0.2 mV, the S / N ratio, expressed as the ratio of a signal level of 1.0 V to a pixel noise of 0.2 mV, is 74 dB. Taking into account quantization bit errors, in order to cover this S / N ratio and perform AD conversion of the pixel signal, a resolution higher than 12 bits is required for AD conversion.

[0070] Next, we will explain the relationship between pixel signals and optical shot noise. Here, we assume that the number of photocharges N when the signal level is 1.0 V is 10,000. The amount of optical shot noise is generally expressed as √N. When the large-amplitude signal level of the pixel signal is 1.0 V, the optical shot noise is 100 for 10,000 photocharges, and the S / N ratio at this point is 40 dB. Furthermore, if the small-amplitude signal level is assumed to be 10 mV, the S / N ratio at this point is 20 dB. In other words, it is clear that a resolution that ensures an S / N ratio of just over 40 dB is sufficient at any point in the signal level.

[0071] In Figure 9, the resolution in AD conversion from 8 bits to 12 bits is shown by a dashed line. As shown in Figure 9, depending on the amount of light, the AD conversion resolution can be set low while taking into account optical shot noise and quantization error. In the digital signal processing described with reference to Figures 6 to 8, the resolution is halved to 11 bits by applying a digital gain of 2x to the AD-converted value of the pixel signal amplified by the voltage amplification factor Gain2 (=1). As described with reference to Figure 9, when the potential change amount ΔV1 of the pixel output line 16 is in the range of 0.5 V or more, there is no impact on image quality even if the resolution is set to 11 bits.

[0072] Fig. 10 is a timing diagram showing a driving method in which the readout speed is increased in comparison with the driving example of Fig. 5. Fig. 10 shows temporal changes in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, the output signal of the comparator 44, and the count signal.

[0073] In this driving example, the rate of change of the reference signal generated by the reference signal generation unit 46 with respect to time is doubled during the SAD period TS3 and the NAD period TN3. This makes it possible to compare the maximum value (1.0 V) of the potential change amount ΔV1 of the pixel output line 16 in half the time of the SAD conversion period TS2 in FIG.

[0074] 10, the SAD period TS2 is shortened to half its original length to become an SAD period TS3, and the NAD period TN2 is shortened to half its original length to become an NAD period TN3. By shortening the SAD period TS3 and the NAD period TN3 in this manner, the AD conversion period T3 per pixel can be shortened to 3 / 4 of the AD conversion period T2 per pixel in Fig. 5. In the driving example of Fig. 10, the count value e is held in the memory 52 during the SAD period TS3, and the count value f is held in the memory 52 during the NAD period TN3.

[0075] 11 to 13 are graphs illustrating an example of digital signal processing for AD converted values ​​obtained in the driving example of FIG.

[0076] Fig. 11 shows the result after subtraction processing in the digital signal processing unit 70. In Fig. 11, the horizontal axis shows the signal amplitude (amount of potential change ΔV1) of the pixel output line 16, and the vertical axis shows the result of subtracting the AD conversion value obtained in the NAD period from the AD conversion value obtained in the SAD period. Here, as in the case of Fig. 6, it is assumed that the voltage amplification factor Gain1 is C0 / C1 = 2 and the voltage amplification factor Gain2 is C0 / (C1 + C2 + C3) = 1.

[0077] In FIG. 11, the solid line indicates a signal corresponding to a voltage gain Gain1. When the potential change ΔV1 of the pixel output line 16 is 0.5 V, the potential change ΔV2 of the amplifier 32 is 1.0 V, and the AD conversion result (ba) is 4096 LSB. The dashed line indicates a signal corresponding to a voltage gain Gain2. As described above, when the voltage gain of the amplifier 32 is Gain2 (=1), the reference signal changes twice as much over time, and the time required for AD conversion is halved. In other words, when the potential change ΔV1 of the pixel output line 16 is 1.0 V, the AD conversion result (ef) is 2048 LSB. In other words, the change in the AD conversion result when the voltage gain is Gain1 (=2) is four times the change in the AD conversion result when the voltage gain is Gain2 (=1).

[0078] FIG. 12 is a graph showing the results when the AD conversion result (ef) is multiplied by a 4x digital gain (=(ef)×4). When the voltage amplification factor is Gain2 (=1) and the amount of potential change ΔV1 of the pixel output line 16 is 0.5 V, the value (=(ef)×4) obtained by multiplying the AD conversion result (ef) by a 4x digital gain is 4096 LSB. In other words, the amount of change in the AD conversion result with respect to the amount of potential change ΔV1 of the pixel output line 16 at this time is the same as the amount of change in the AD conversion result (ba) with respect to the amount of potential change ΔV1 of the pixel output line 16 when the voltage amplification factor is Gain1. In this case, the maximum value of the AD conversion value is 8192 LSB.

[0079] Fig. 13 is a graph illustrating a method for synthesizing an image using the AD conversion result (ba) and the AD conversion result (ef). As shown in Fig. 13, when the amount of potential change ΔV1 of the pixel output line 16 is in the range of 0 V or more and less than 0.5 V (low brightness region), the AD conversion result (ba) with a voltage amplification factor of Gain1 is used as image data. Also, when the amount of potential change ΔV1 of the pixel output line 16 is in the range of 0.5 V or more (high brightness region), the AD conversion result (ef) × 4 with a voltage amplification factor of Gain2 is used as image data.

[0080] In the driving example of FIG. 10, the reference signal changes twice as much over time in the comparison operation of the SAD period TS3 and the NAD period TN3, resulting in a halved resolution. Furthermore, by quadrupling the digital gain, the resolution is reduced to a quarter. Therefore, the resolution in the high-brightness region of FIG. 13 is reduced to 1 / 8. However, as explained with reference to FIG. 9, in the high-brightness region where the potential change of the pixel output line 16 is 0.5 V or more, the optical shot noise is large, so even if the resolution is reduced to 1 / 8, the image quality is not affected. In other words, even in the driving example of FIG. 10, an image with an expanded dynamic range can be obtained while improving the S / N ratio. Furthermore, because the lengths of the SAD period TS3 and the NAD period TN3 when the voltage amplification factor is Gain2 (=1) can be reduced to 1 / 2, the readout time is shorter than in the driving example of FIG. 5, thereby suppressing a decrease in frame rate.

[0081] In the driving example of Figure 10, from the perspective of obtaining an image with an expanded dynamic range, a signal amplified by a voltage amplification factor Gain1 and a signal amplified by a voltage amplification factor Gain2 are obtained for the same pixel signal, but the signal may be obtained multiple times with the same voltage amplification factor.

[0082] Figure 14 is a timing diagram showing another driving method in which the readout speed is increased compared to the driving example of Figure 5. Figure 14 shows temporal changes in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, the output signal of the comparator 44, and the count signal. In this driving example, the NAD period TN3 in the driving example of Figure 10 is omitted.

[0083] In the driving example of Figure 10, the AD conversion value f obtained during the NAD period TN3 is subtracted from the AD conversion value e obtained during the SAD period TS3 and used to subtract offset and fixed pattern noise. In this driving example, on the other hand, the NAD period TN3 is omitted, so the AD conversion value f is not obtained. Here, the AD conversion value f obtained during the NAD period TN3 in Figure 10 has a roughly Gain2 / Gain1 relationship with the AD conversion value a obtained during the NAD period TN1, excluding some noise components.

[0084] As explained with reference to FIG. 13, when the potential change amount of the pixel output line 16 is in the range of 0.5 V or more, data of the AD conversion value (ef) × 4 when the voltage amplification factor is Gain2 is used as the image. In this range, the level of optical shot noise is high, and replacing the AD conversion value f obtained during the NAD period TN3 in FIG. 10 with the AD conversion value a × Gain2 / Gain1 may not affect the image quality. Therefore, in the driving example of FIG. 14, the digital signal processing unit 70 calculates the AD conversion value a × Gain2 / Gain1 and subtracts it from the AD conversion value e. In the driving example of FIG. 14, the AD conversion period T4 per pixel can be further shortened compared to the AD conversion period T3 per pixel in the driving example of FIG. 10.

[0085] As explained with reference to Figures 8 and 13, when AD conversion results with different voltage gains are used across a certain luminance (amount of potential change on the pixel output line 16), errors in the voltage gain may occur even with the same signal processing path. This is due to an offset at the boundary between low-luminance and high-luminance areas or an error in linearity between low-luminance and high-luminance areas, and may affect image quality. In such cases, the image can be corrected by obtaining AD conversion values ​​with different voltage gains within a range where the amount of potential change on the pixel output line 16 is less than 0.5 V, processing these signals, and calculating correction values ​​for the offset and linearity.

[0086] For example, AD conversion values ​​obtained at different voltage amplification factors may be subtracted to calculate an offset and perform correction. Alternatively, AD conversion values ​​obtained at different voltage amplification factors may be averaged to generate image data. Furthermore, even in a photoelectric conversion device configured to process signals generated by multiple photoelectric conversion elements and detect a phase difference, AD conversion values ​​obtained at different voltage amplification factors may be used within a range in which the potential change in the pixel output line 16 is less than 0.5 V. For example, a suitable processing result (phase difference detection signal) may be obtained by selecting and processing or averaging AD conversion values ​​obtained at different voltage amplification factors for signals generated by multiple photoelectric conversion elements.

[0087] Furthermore, as in the driving example of this embodiment, when an AD conversion result is selected from multiple AD conversion results according to the level of the pixel signal and used as an image signal, the amount of data to be horizontally transferred from the memory unit 50 and the amount of signal processing data in the digital signal processing unit 70 may be adjusted.

[0088] For example, data less than 2048 LSB is not used in the AD conversion result (cd) obtained during the SAD period TS2 and the NAD period TN2 in the driving example of Fig. 5. Therefore, depending on the required resolution, the lower few bits may not be horizontally transferred from the memory unit 50. Alternatively, the lower few bits may be invalidated during signal processing in the digital signal processing unit 70.

[0089] 10, data of 2048 LSB or more is not used, so the most significant bit does not need to be horizontally transferred from the memory unit 50. Alternatively, it may be invalidated during signal processing by the digital signal processing unit 70. In the driving example of this embodiment, power consumption can be reduced by reducing the amount of data for horizontal transfer and signal processing according to the resolution and the required range of AD conversion values.

[0090] 7 and 12, when digital gain processing is performed by the digital signal processing unit 70, the bit width of the AD converted value increases. In this case, the decrease in read speed can be suppressed by increasing the operating frequency of the output unit 80. Alternatively, the digital signal processing unit 70 may compress the data after various signal processing and then output it to the output unit 80.

[0091] The setting values ​​of the multiple voltage amplification factors and the ratios of the voltage amplification factors described in this embodiment, the resolution of the AD conversion operation, the pixel charge-to-voltage conversion ratio, the optical shot noise, and the numerical values ​​of pixel noise are examples, and the settings can be changed as appropriate in accordance with the concept of the S / N ratio described using FIG. 9.

[0092] As described above, in this embodiment, in a configuration in which pixel signals amplified by a plurality of different voltage amplification factors are AD converted, the AD conversion period for pixel signals amplified by some of the voltage amplification factors is shortened. Therefore, according to this embodiment, it is possible to obtain an image with a high S / N ratio and an expanded dynamic range while suppressing a decrease in frame rate.

[0093] [Second embodiment] A method for driving a photoelectric conversion device according to the second embodiment of the present invention will be described with reference to Fig. 15. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0094] In this embodiment, a method for driving the photoelectric conversion device described in the first embodiment will be described. Fig. 15 is a timing chart showing the method for driving the photoelectric conversion device according to this embodiment. Fig. 15 shows changes over time in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, the output signal of the comparator 44, and the count signal.

[0095] In the driving method of this embodiment, the frequency of the count signal generated by the counter unit 54 during the AD conversion period for the pixel signal amplified by the voltage amplification factor Gain2 is set to a higher frequency than in the driving method of the photoelectric conversion device according to the first embodiment shown in Fig. 10. Specifically, in this embodiment, the frequency of the count signal during the SAD period TS2 and the NAD period TN2 is set to a frequency twice that in the driving example of Fig. 10. In this specification, the frequency of the counter and the frequency of the count signal refer to the frequency at which the count value indicated by the count signal transitions.

[0096] In the driving method of this embodiment, similarly to the driving method shown in FIG. 10, the time of the reference signal in the SAD period TS2 and the NAD period TN2 is change The amount of the reference signal in the NAD period TN1 and the SAD period TS1 is change The amount of the reference signal is set to twice the amount of the reference signal. change If the amount is doubled, the AD conversion period can be shortened, but the resolution of the AD conversion is reduced to half. However, in this embodiment, the frequency of the counter is doubled, so the time change Even when the amount is set to double, the same AD conversion result as in the driving example of FIG. 5 can be obtained for the amount of change in the potential of the pixel output line 16.

[0097] An example of the configuration of the counter unit 54 is a configuration including a PLL (Phase Locked Loop) circuit and a counter circuit driven by a clock output from the PLL circuit. In such a configuration, the counter frequency can be changed by switching the multiplication factor of the output clock of the PLL circuit. Alternatively, a configuration may be adopted in which multiple PLL circuits that generate clocks with different frequencies are provided, and the clock input to the counter circuit is switched. With such a configuration, there is no need to ensure stabilization time associated with switching the multiplication factor, thereby shortening processing time.

[0098] In this embodiment, using such a configuration, a count value g is acquired during the SAD period TS2 and stored in the memory 52, and a count value h is acquired during the NAD period TN2 and stored in the memory 52. ​​If there is no influence of noise, the count values ​​g and h acquired in this manner will be equivalent to the count values ​​c and d obtained in the driving example of FIG.

[0099] In the driving example shown in Figure 10, increasing the change in the reference signal over time reduces the resolution of the AD conversion results in high-brightness areas. For example, assume a large voltage gain ratio, such as Gain1 (=4) and Gain2 (=1). In this case, the range in which the AD-converted pixel signal amplified by Gain2 is used as an image is the range in which the potential change in the pixel output line 16 is 0.25 V or greater, shifting toward lower brightness. This shifts the AD conversion resolution to a lower range, which is the range in which the optical shot noise described with reference to Figure 9 is small. Therefore, it is necessary to minimize the reduction in AD conversion resolution. On the other hand, if the count signal frequency becomes high, the effects of power supply noise and clock jitter may appear in comparison operations, affecting image quality. Therefore, it may be desirable to set the count signal frequency lower in low-brightness areas where optical shot noise is small and to increase the count signal frequency in high-brightness areas where optical shot noise is large.

[0100] As described above, according to this embodiment, it is possible to obtain an image with a high S / N ratio and an expanded dynamic range while suppressing a decrease in the resolution and frame rate of AD conversion.

[0101] [Third embodiment] A method for driving a photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figs. 16 to 18. Fig. 16 is a timing chart showing a method for driving a photoelectric conversion device according to this embodiment. Figs. 17 and 18 are graphs illustrating an example of digital signal processing for AD converted values. Components similar to those in the photoelectric conversion devices according to the first and second embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0102] This embodiment describes a method for driving the photoelectric conversion device described in Embodiment 1. Fig. 16 shows changes over time in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, the output signal of the comparator 44, and the count signal.

[0103] In the driving method of this embodiment, a period (SAD period TS3) for performing AD conversion of pixel signals amplified by a voltage amplification factor Gain3 is added to the driving example of Fig. 14. In this embodiment, an example will be described in which the voltage amplification factor Gain1 is C0 / C1 = 4, the voltage amplification factor Gain2 is C0 / (C1 + C2) = 2, and the voltage amplification factor Gain3 is C0 / (C1 + C2 + C3) = 1.

[0104] 16, the AD conversion periods for pixel signals amplified by voltage amplification factor Gain1 are designated as NAD period TN1 and SAD period TS1. The AD conversion period for pixel signals amplified by voltage amplification factor Gain2 is designated as SAD period TS2, and the AD conversion period for pixel signals amplified by voltage amplification factor Gain3 is designated as SAD period TS3. The amount of change in the reference signal over time during SAD period TS2 and SAD period TS3 is set to twice the amount of change in the reference signal over time during SAD period TS1. During each AD conversion period, count values ​​i, j, k, and l are held in memory 52, as shown in FIG.

[0105] In Figure 17, the solid line shows the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain1, the dashed line shows the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain2, and the dashed line shows the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain3.

[0106] 18 is a graph illustrating a method of combining the AD conversion results of pixel signals amplified by each voltage gain by applying a predetermined digital gain to the results and synthesizing them as an image. The AD conversion results of pixel signals amplified by voltage gain Gain2 have the same slope as when voltage gain Gain1 is applied by applying a digital gain of 4x. The AD conversion results of pixel signals amplified by voltage gain Gain3 have the same slope as when voltage gain Gain1 is applied by applying a digital gain of 8x.

[0107] In the region where the amount of change in potential of the pixel output line 16 is less than 0.25 V, the AD conversion result of the pixel signal amplified by the voltage gain Gain1 is used as the image signal. In the region where the amount of change in potential of the pixel output line 16 is greater than or equal to 0.25 V and less than 0.5 V, the AD conversion result of the pixel signal amplified by the voltage gain Gain2 is used as the image signal. In the region where the amount of change in potential of the pixel output line 16 is greater than or equal to 0.5 V, the AD conversion result of the pixel signal amplified by the voltage gain Gain3 is used as the image signal. The AD conversion results of the pixel signals amplified by the voltage gain Gain2 and the voltage gain Gain3 can be obtained by multiplying the AD conversion value i obtained in the NAD period TN1 by the ratio of the respective voltage gains and subtracting the result from the AD conversion values ​​k and l.

[0108] To improve the S / N ratio, the voltage gain on the low-luminance side is increased. If the ratio between different voltage gains becomes large, it becomes difficult to reduce the resolution of the AD conversion value on the high-luminance side. Therefore, in this embodiment, three voltage gains, Gain1, Gain2, and Gain3, are set, so that the optimal voltage gain and resolution for each luminance can be set. In this embodiment, three voltage gains, Gain1, Gain2, and Gain3, are set, but the set values ​​of the voltage gains are not limited to three and may be four or more.

[0109] It is also possible to adjust the amount of change in the reference signal over time and the counter frequency for the SAD periods TS2 and TS3. For example, the counter frequency can be doubled during the SAD period TS2, and the amount of change in the reference signal over time and the counter frequency can be doubled during the SAD period TS3. By setting them in this way, the resolution and the AD conversion period can be optimized.

[0110] As described above, according to this embodiment, it is possible to further improve the S / N ratio while suppressing a decrease in the frame rate.

[0111] [Fourth embodiment] A method for driving a photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figs. 19 to 21. Fig. 19 is a timing chart showing a method for driving a photoelectric conversion device according to this embodiment. Figs. 20 and 21 are graphs explaining an example of digital signal processing for AD converted values. Components similar to those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0112] This embodiment describes a method for driving the photoelectric conversion device described in Embodiment 1. Fig. 19 shows temporal changes in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, the output signal of the comparator 44, and the count signal.

[0113] The driving method of this embodiment is different from the driving example of the first embodiment in that the AD conversion configuration is changed to achieve even higher speeds. Specifically, an SAD period TS4 is executed instead of the SAD period TS1 in the driving example of FIG. 14. In addition, a determination period TJ is added before the SAD period TS4. As with the first embodiment, the voltage amplification factors of the amplifier 32 will be described taking as an example a case where the voltage amplification factor Gain1 is 2 and the voltage amplification factor Gain2 is 1.

[0114] During the SAD period TS4, AD conversion is performed using reference signals with two different slopes. Here, these two reference signals are ramp signals H and L, and the slope of ramp signal H is twice the slope of ramp signal L. The slope of ramp signal L is the same as the slope of the reference signal during the SAD period TS1 in the driving example of FIG.

[0115] During the determination period TJ, the output level of the amplifier 32 is compared with the maximum level VL of the ramp signal L. If the output level of the amplifier 32 is lower than the level VL, the comparison operation during the SAD period TS4 is performed using the ramp signal L. On the other hand, if the output level of the amplifier 32 is higher than the level VL, the comparison operation during the SAD period TS4 is performed using the ramp signal H. In other words, if the amount of change in potential of the pixel output line 16 is less than 0.25 V, AD conversion is performed with 12-bit resolution using the ramp signal L, and if the amount of change in potential of the pixel output line 16 is 0.25 V or more, AD conversion is performed with 11-bit resolution using the ramp signal H.

[0116] The AD-converted value converted using the ramp signal H is multiplied by a 2x digital gain in the digital signal processing unit 70 and combined with the result of AD conversion using the ramp signal L. As explained with reference to FIG. 9, when the amount of change in potential of the pixel output line 16 is 0.25 V or more, even if the resolution is 10 bits, the impact on image quality is small when optical shot noise is taken into account. Therefore, the SAD period TS1 in the driving example of FIG. 14 can be changed to an SAD period TS4 that is half the time. Meanwhile, in the SAD period TS2, AD conversion is performed using a reference signal with the same slope as the ramp signal H, as in the driving example of FIG. 14.

[0117] A comparison operation is performed on the pixel signal amplified by the voltage amplification factor Gain1 using the ramp signal L or the ramp signal H. Specifically, if the amount of change in potential of the pixel output line 16 is less than 0.25 V, the comparison operation is performed using the ramp signal L. If the amount of change in potential of the pixel output line 16 is 0.25 V or more, the comparison operation is performed using the ramp signal H, and a digital gain of 2x is applied to the AD conversion value obtained thereby. This obtains the AD conversion result for the pixel signal amplified by the voltage amplification factor Gain1.

[0118] 20, the solid line indicates the AD conversion result using ramp signal L of the pixel signal amplified by the voltage amplification factor Gain1, the dashed-dotted line indicates the AD conversion result using ramp signal H of the pixel signal amplified by the voltage amplification factor Gain1, and the dashed line indicates the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain2.

[0119] Fig. 21 is a graph explaining a method of applying a digital gain to the AD conversion results of pixel signals amplified by each voltage gain and combining them into an image. As in the case of Fig. 11, the AD conversion results of pixel signals amplified by voltage gain Gain2 have the same slope as when voltage gain Gain1 is used, by applying a digital gain of 4x.

[0120] Note that, when comparing pixel signals amplified by the voltage gain Gain 2, the slope of the reference signal may be changed, as in the case of comparing pixel signals amplified by the voltage gain Gain 1. Furthermore, the voltage gain and the slope of the ramp signal may be optimally set according to noise and required resolution.

[0121] In this manner, in this embodiment, the slope of the reference signal is switched depending on the output levels of the pixel output line 16 and the amplifier 32. Therefore, according to this embodiment, it is possible to improve the S / N ratio, shorten the readout time, and further suppress a decrease in the frame rate.

[0122] [Fifth embodiment] A photoelectric conversion device and a driving method thereof according to a fifth embodiment of the present invention will be described with reference to Figs. 22 and 23. Fig. 22 is a diagram illustrating the signal processing content in the photoelectric conversion device according to this embodiment. Fig. 23 is a timing chart illustrating a driving method for the photoelectric conversion device according to this embodiment. Components similar to those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0123] The photoelectric conversion device according to this embodiment is configured to be able to adjust the signal processing time and each signal processing. That is, the photoelectric conversion device according to this embodiment is configured to be able to select and execute signal processing (A) to signal processing (D), for example, as shown in Fig. 22.

[0124] Signal processing (A) represents the signal processing described in the first embodiment with reference to Fig. 10. In the driving example of Fig. 10, a comparison operation is performed during a SAD period TS2 of a pixel signal amplified with a voltage gain Gain2, regardless of the result of AD conversion during a SAD period TS1 of a pixel signal amplified with a voltage gain Gain1. As described with reference to Figs. 11 to 13, when the amount of change in potential of the pixel output line 16 is less than 0.5 V, the result of AD conversion of the pixel signal amplified with a voltage gain Gain1 is used for the image, and therefore it is not necessarily necessary to perform the comparison operation with a voltage gain Gain2.

[0125] Signal processing (B) is an example of signal processing in which, if the AD conversion result of the pixel signal amplified by the voltage amplification factor Gain1 does not exceed 4096 LSB, the comparison operation of the pixel signal amplified by the voltage amplification factor Gain2 is not performed and the amplifier 32 and the comparator 44 are controlled to a power-saving state. Note that the power-saving state is a state in which the drive current of the amplifier 32 and the comparator 44 is cut off or reduced.

[0126] Signal processing (C) is an example of signal processing in which the pixel signal amplified by the voltage amplification factor Gain2 is only compared without comparing the pixel signal amplified by the voltage amplification factor Gain1, and the pixel signal is held or placed in a power-saving state. Signal processing (C) can be realized, for example, as shown in Fig. 23, by comparing the output level of the amplifier 32 with the maximum level VH of the ramp signal H during the determination period TJ described in the fourth embodiment. That is, if the output level of the amplifier 32 is compared with the level VH and it is determined that the amount of change in potential of the pixel output line 16 is 0.5 V or more, control may be performed so that the comparison operation is performed only on the pixel signal amplified by the voltage amplification factor Gain2.

[0127] Signal processing (D) is another example of signal processing. For example, if the voltage gain Gain1 is smaller than the voltage gain Gain2, the AD conversion result for the voltage gain Gain2 can be predicted by multiplying the AD conversion result for the SAD period TS1 by Gain2 / Gain1. For example, an SAD period TS3 is executed by shortening the SAD period based on the AD conversion result for the SAD period TS1, and then, as in signal processing (B), each block is controlled to a power-saving state. Since the AD conversion result is obtained from a count value, the amplitude of the pixel output line 16 can be detected from the data stored in specific upper bits of the multiple memories 52.

[0128] In this manner, in this embodiment, the amplitude of the pixel signal is detected based on the results of the AD conversion periods with different voltage amplification factors and the determination means, and the signal processing time and each process are controlled. Therefore, this embodiment can reduce power consumption and the influence of crosstalk, such as noise on other pixel signals, that accompanies AD conversion.

[0129] [Sixth embodiment] A photoelectric conversion device and a driving method thereof according to a sixth embodiment of the present invention will be described with reference to Figs. 24 to 26. Figs. 24 and 25 are timing charts showing a driving method for the photoelectric conversion device according to this embodiment. Fig. 26 is a diagram explaining the contents of signal processing in the photoelectric conversion device according to the embodiment. Components similar to those in the photoelectric conversion devices according to the first to fifth embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0130] In this embodiment, a method for driving the photoelectric conversion device described in the first embodiment will be described. Fig. 24 shows temporal changes in the voltage amplification factor of the amplifier 32, the control signals PRES, PTX, and PSEL, the control signals of the switches S0, S1, S2, and S3, the output signal of the amplifier 32, the ramp signal, and the output signal of the comparator 44. The driving method of this embodiment is configured to enable switching of the voltage amplification factor during the comparison operation in the SAD period TS2.

[0131] 10 and 14 in the first embodiment, if the amount of change in potential of the pixel output line 16 exceeds 0.5 V when the voltage amplification factor Gain1 is 2, the input dynamic range of AD conversion is exceeded in the SAD period TS1. In this case, the AD conversion result in the SAD period TS2, in which the comparison operation of the pixel signal amplified by the voltage amplification factor Gain2 (=1) is performed, becomes valid as the image signal.

[0132] On the other hand, if the amount of change in potential of the pixel output line 16 during the SAD period TS1 is less than 0.5 V, as described in the fifth embodiment, the AD conversion result during the SAD period TS1, in which the comparison operation of the pixel signal amplified by the voltage amplification factor Gain1 (=2) is performed, becomes valid as the image signal. Therefore, the comparison operation during the SAD period TS2 is not necessary.

[0133] If the AD conversion value in the NAD period TN1 is assumed to be 100 LSB, then the full scale of the AD conversion result in the SAD period TS1 is set to 4096 LSB, so the value is configured to be clipped to 100 LSB + 4096 LSB. For example, this configuration can be achieved by adjusting the slopes of the count signal and reference signal.

[0134] In this embodiment, if the AD conversion result in the SAD period TS1 does not exceed the full scale of 4096 LSB+100 LSB, the voltage amplification factor Gain2 in the SAD period TS2 is made variable.

[0135] In the driving example of Fig. 24, if the AD conversion result in SAD period TS1 does not exceed the full scale of 4096LSB+100LSB, driving is performed in SAD period TS2 at a voltage gain of Gain 1. In Fig. 24, for the amplifier output and comparator output in SAD period TS2, the dashed line indicates the case where the voltage gain is Gain 1, and the solid line indicates the case where the voltage gain is Gain 2.

[0136] The results of AD conversion performed at the same voltage amplification factor Gain1 during both SAD periods TS1 and TS2 result in two correlated signals, and the noise components in the AD conversion results can be reduced by performing root mean square processing. For example, as described in the second embodiment, if the AD conversion results have the same resolution and the counter frequency is adjusted, the noise components can be reduced to 1 / √2.

[0137] Figure 25 shows a driving example in which multiple comparison operations are performed during the SAD period TS2 of the driving example described using Figure 24. Figure 25 shows temporal changes in the voltage amplification factor of amplifier 32, control signals PRES, PTX, PSEL, control signals for switches S0, S1, S2, S3, output signal of amplifier 32, ramp signal, and output signal of comparator 44. In Figure 25, two comparison operations are performed during SAD period TS2, but the number of comparison operations is not limited to two.

[0138] The comparison operation during the SAD period TS2 can be determined based on the AD conversion result during the SAD period TS1. For example, if the AD conversion result during the SAD period TS1 is less than half of the full scale, then the comparison operation during the SAD period TS2 can be performed for half the period required to AD convert the full scale, and the number of comparisons can be increased. Increasing the number of comparisons increases the amount of noise reduction achieved by the root mean square process. In particular, the lower the brightness, the more the number of comparisons can be increased, which increases the amount of noise reduction and improves the S / N ratio.

[0139] It should be noted that an increase in the number of comparisons may increase the amount of memory 52 required. In this case, for example, if the memory 52 uses 13 bits at full scale, it is sufficient to configure the memory 52 so that several bits of these are used for each comparison operation. By configuring the memory 52 in this way, it is possible to suppress an increase in the memory 52.

[0140] FIG. 26, like FIG. 22 described in the fifth embodiment, schematically illustrates an example of signal processing that can be performed in the photoelectric conversion device according to this embodiment.

[0141] Signal processing (E) is a driving example in which four comparison operations are performed during the SAD period TS2. Signal processing (F) is an example of a case where the brightness is lower than that of signal processing (E), i.e., the period of the comparison operation is shorter, and is a driving example in which the power saving state is entered after four comparison operations are performed during the SAD period TS2.

[0142] As explained in the first embodiment, the voltage amplification factor and the slope of the reference signal can be set as appropriate. Furthermore, a configuration may be provided that includes a capacitance value adjustment mechanism for the floating diffusion region FD of the pixel 12, and the capacitance value may be switched based on the AD conversion result. Furthermore, the AD conversion period of the SAD period TS1 can also be shortened by combining it with the second or fourth embodiment.

[0143] In this manner, in this embodiment, the voltage amplification factor and the number of comparison operations in another AD conversion period are set based on the AD conversion result, and therefore, according to this embodiment, the S / N ratio can be further improved.

[0144] [Seventh embodiment] An imaging system according to the seventh embodiment of the present invention will be described with reference to Fig. 27. Fig. 27 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0145] The photoelectric conversion device 100 described in the first to sixth embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in imaging systems. Fig. 27 illustrates a block diagram of a digital still camera as an example of such systems.

[0146] 27 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to sixth embodiments, and converts the optical image formed by the lens 202 into image data.

[0147] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0148] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be removable.

[0149] The imaging system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0150] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0151] In this way, according to this embodiment, the first to third 6 An imaging system can be realized to which the photoelectric conversion device 100 according to the embodiment is applied.

[0152] [Eighth embodiment] An imaging system and a moving object according to an eighth embodiment of the present invention will be described with reference to Fig. 28. Fig. 28 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0153] FIG. 28(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to sixth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0154] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0155] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 28(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0156] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0157] [Ninth embodiment] A device according to a ninth embodiment of the present invention will be described with reference to Fig. 29. Fig. 29 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0158] FIG. 29 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any of the first to sixth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0159] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0160] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0161] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0162] The device EQP shown in FIG. 29 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0163] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0164] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0165] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0166] The circuit configuration of the pixel 12 shown in FIG. 2 is an example and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. Alternatively, a single pixel 12 may have multiple photoelectric conversion elements sharing a single microlens to form a pupil-split pixel. The pixel 12 does not necessarily have to include a selection transistor M4. The capacitance value of the floating diffusion FD may be switchable. In this case, the voltage amplification factor of the pixel signal can be set by combining the amplification factor (gain Gsf) of the source follower circuit, which can be switched depending on the capacitance value of the floating diffusion FD, with the amplification factor of the amplifier 32.

[0167] In the above embodiment, one pixel output line 16 is provided for each column, but each column may have two or more pixel output lines 16. In this case, each pixel 12 may be connected to one of the pixel output lines 16 in each column, or may have a number of selection transistors corresponding to the number of pixel output lines 16 in each column.

[0168] Furthermore, the circuit configuration of the amplifier 32 shown in Fig. 3 is an example and can be modified as appropriate. For example, in the configuration example of Fig. 3, three feedback capacitors C1, C2, and C3 can be connected in parallel to the amplifier circuit 34, but the number of feedback capacitors is not limited to this. Also, in the configuration example of Fig. 3, an input capacitor C0 is provided, but the capacitance value of the input capacitor may be configured to be switchable. The circuit configuration of the amplifier 32 can be modified as appropriate depending on the type of voltage amplification factor required, etc.

[0169] Furthermore, the imaging systems shown in the seventh and eighth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 27 and 28.

[0170] Furthermore, the equipment shown in the above ninth embodiment is an example of equipment to which the photoelectric conversion device of the present invention can be applied, and the equipment to which the photoelectric conversion device of the present invention can be applied is not limited to the configuration shown in Figure 14.

[0171] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0172] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0173] 10...Pixel section 12...pixels 30...Amplification section 32...Amplifier 40...Comparison section 44...Comparator 46...Reference signal generation section 50...Memory section 52...Memory 54...Counter section 60...Horizontal scanning section 70...Digital signal processing unit 80...Output section 90...Timing generation unit 100...Photoelectric conversion device

Claims

1. a pixel having a photoelectric conversion unit; an amplifier unit that sequentially amplifies analog signals generated in the pixels by a plurality of different amplification factors using the same amplifier; an AD conversion unit that performs AD conversion of the analog signal by comparing the level of the analog signal amplified by the amplification unit with the level of a reference signal whose level changes over time; a control unit that controls the AD conversion unit, the control unit is configured to control the AD conversion unit to perform AD conversion a plurality of times on the analog signal obtained by amplifying the same analog signal generated in the pixel by the amplification unit, the AD conversion unit performs AD conversion on the analog signal amplified by a first amplification factor during a first AD conversion period of the plurality of AD conversions, and performs AD conversion on the analog signal amplified by a second amplification factor higher than the first amplification factor during a second AD conversion period of the plurality of AD conversions; The length of the first AD conversion period is shorter than the length of the second AD conversion period, a rate of change with respect to time of the reference signal used in the second AD conversion period is smaller than a rate of change with respect to time of the reference signal used in the first AD conversion period; During the second AD conversion period, the potential of the reference signal changes to a first level, During the first AD conversion period, the potential of the reference signal changes to the first level. A photoelectric conversion device characterized by:

2. The AD conversion unit has a comparator that compares the level of the analog signal with the level of the reference signal, the level of which changes over time.

2. The photoelectric conversion device according to claim 1.

3. The AD conversion unit a comparator that compares the level of the analog signal with the level of the reference signal, the level of which changes over time; a counter that starts counting clock signals in response to the start of the comparison operation; The frequency of the counter during the first AD conversion period is different from the frequency of the counter during the second AD conversion period.

2. The photoelectric conversion device according to claim 1.

4. The control unit sets a rate of change of the reference signal with respect to time in at least one of the plurality of AD conversions in accordance with a level of the analog signal.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. The control unit sets a length of an AD conversion period in at least one of the plurality of AD conversions in accordance with an amplification factor of the amplification unit.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. The AD conversion unit is configured to perform AD conversion on each of the signals obtained by amplifying the analog signal with at least three different amplification factors.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. The control unit sets an amplification factor of the analog signal to be AD converted in one of the plurality of AD conversions based on an AD conversion result in another of the plurality of AD conversions.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. The control unit sets a length of an AD conversion period in one of the plurality of AD conversions based on AD conversion results in other of the plurality of AD conversions.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. The control unit controls a drive current of the AD conversion unit in one of the plurality of AD conversions based on an AD conversion result in another of the plurality of AD conversions.

9. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. The control unit sets the number of AD conversions based on an AD conversion result in one AD conversion.

10. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

11. a digital signal processing unit that performs digital signal processing on the digital signal transferred from the AD conversion unit; The AD conversion unit is configured to reduce the number of bits of at least some of the digital signals obtained by the AD conversions performed multiple times and transfer them to the digital signal processing unit.

11. The photoelectric conversion device according to claim 1.

12. a digital signal processing unit that performs digital signal processing on the digital signal transferred from the AD conversion unit; The digital signal processing unit performs digital signal processing on at least some of the plurality of digital signals obtained by the plurality of AD conversions by reducing the number of bits.

12. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. a digital signal processing unit that performs digital signal processing on the digital signal transferred from the AD conversion unit; The digital signal processing unit performs digital gain processing on the digital signal according to an amplification factor of the analog signal.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

14. a digital signal processing unit that performs digital signal processing on the digital signal transferred from the AD conversion unit; The digital signal processing unit performs digital gain processing on the digital signal in accordance with the frequency of the counter.

4. The photoelectric conversion device according to claim 3.

15. The digital signal processing unit generates an image signal by synthesizing the plurality of digital signals obtained by the plurality of AD conversions.

15. The photoelectric conversion device according to claim 11, wherein the first and second electrodes are electrically connected to each other.

16. The digital signal processing unit generates a phase difference detection signal based on the plurality of digital signals obtained by the plurality of AD conversions.

15. The photoelectric conversion device according to claim 11, wherein the first and second electrodes are electrically connected to each other.

17. The digital signal processing unit generates an image signal by performing averaging processing on the plurality of digital signals obtained by the plurality of AD conversions.

15. The photoelectric conversion device according to claim 11, wherein the first and second electrodes are electrically connected to each other.

18. A method for driving a photoelectric conversion device having pixels each having a photoelectric conversion unit, an amplifier unit sequentially amplifying an analog signal generated in the pixel by a plurality of different amplification factors using the same amplifier, and an AD conversion unit performing AD conversion of the analog signal by comparing a level of the analog signal amplified by the amplifier unit with a level of a reference signal whose level changes over time, performing AD conversion a plurality of times with AD conversion periods of different lengths on the analog signal obtained by amplifying the same analog signal generated in the pixel, and obtaining a plurality of digital signals corresponding to the plurality of AD conversions; synthesizing the plurality of digital signals to generate an image signal; In a first AD conversion period of the plurality of AD conversions, AD conversion is performed on the analog signal amplified by a first amplification factor, and in a second AD conversion period of the plurality of AD conversions, AD conversion is performed on the analog signal amplified by a second amplification factor higher than the first amplification factor; The length of the first AD conversion period is shorter than the length of the second AD conversion period, a rate of change with respect to time of the reference signal used in the second AD conversion period is smaller than a rate of change with respect to time of the reference signal used in the first AD conversion period; During the second AD conversion period, the potential of the reference signal changes to a first level, During the first AD conversion period, the potential of the reference signal changes to the first level. A method for driving a photoelectric conversion device.

19. The photoelectric conversion device according to any one of claims 1 to 17, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

20. A mobile object, The photoelectric conversion device according to any one of claims 1 to 17, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

21. The photoelectric conversion device according to any one of claims 1 to 17, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

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