Dynamic power reduction techniques for ultrasound systems.

Abstract

A dynamic power reduction method and apparatus for use in an ultrasound system is described. In one embodiment, the ultrasound system includes an imaging subsystem having a transmit data path having a transmitter that transmits acoustic signals and a receiver data path including a signal acquisition circuit with a receiver that receives acoustic signals representative of echoes, a plurality of real-time signals indicative of a status of imaging operations being performed by the transmit and receive paths, a clock generator that generates one or more clocks for use by the transmit and receive data paths, a clock switching circuit coupled to the clock generator and the transmit and receive paths and having circuitry that switches the clock to at least one of the transmit and receive paths, and a clock switching controller coupled to the clock switching circuit and that controls the circuitry to automatically switch or pass the clock signal to at least one of the transmit and receive paths in response to receiving one or more signals from the plurality of real-time signals.

Description

[Technical Field]

[0001] [Cross reference] This application claims the benefit of the earlier filing date of U.S. Non-Provisional Patent Application No. 16 / 803,726, filed February 27, 2020, entitled "Dynamic Power Reduction Techniques for Ultrasound Systems."

[0002] FIELD OF THE INVENTION Embodiments of the present invention relate generally to ultrasound systems, and more particularly, embodiments of the present invention relate to performing power management within ultrasound systems based on real-time signals. [Background technology]

[0003] System power consumption within ultrasound machines presents significant challenges to designers. There are several adverse effects resulting from high system power consumption. Such ultrasound machines contain larger and more expensive power supplies, have shorter battery life and elevated internal operating temperatures, utilize active cooling components that add to system cost, complexity, and noise, and have an increased physical footprint.

[0004] Power consumption has been addressed at a macro level. More specifically, historically, power consumption issues within ultrasound machines have generally been addressed by defining sleep states for the machine that are under the control of the ultrasound machine's software. In sleep states, parts of the system are placed in a low power state (e.g., a lower power consumption state) by slowing or stopping the digital clocks that control the blocks. The result of placing parts of the system in a lower power state is a reduction, and potentially minimization, of the system's dynamic power. These states are generally defined at a macro level so that they do not occur when performing macro functions such as active imaging, and generally apply when the ultrasound machine is idling.

[0005] Figure 1 illustrates macro-level power usage during an ultrasound examination. In the imaging state, data is acquired and displayed in real time. At this time, system power consumption is generally greatest because most of the electronics are active. When the user stops imaging and reviews the acquired data, the system software can shut down most of the electronics associated with data acquisition while leaving the display and image recall electronics running. This state of the ultrasound machine is often referred to as the freeze state. During an examination, the user may switch between the imaging and freeze states multiple times. Finally, after a certain amount of time in the freeze state, the system software can shut down, terminating the display, and enter an even lower power state, depicted in Figure 1 as idling. Summary of the Invention [Problem to be solved by the invention]

[0006] To take advantage of the sleep state concept, system software must be written to recognize opportunities to go to sleep and events that require the system to wake up. The net effect is that software design and verification to achieve power savings is complex. [Means for solving the problem]

[0007] A dynamic power reduction method and apparatus are described for use in an ultrasound system. In one embodiment, the ultrasound system includes an imaging subsystem having a transmit data path including a transducer assembly and a transmitter for transmitting acoustic signals and a receive data path including a signal acquisition circuit with a receiver for receiving acoustic signals representative of echoes, a plurality of real-time signals indicative of a status of imaging operations being performed by the transmit and receive paths, a clock generator for generating one or more clocks for use by the transmit and receive data paths, a clock switching circuit coupled to the clock generator and the transmit and receive paths and having circuitry for switching the clock to at least one of the transmit and receive paths, and a clock switching controller coupled to the clock switching circuit and controlling the circuitry to automatically switch or pass the clock signal to at least one of the transmit and receive paths in response to receiving one or more signals from the plurality of real-time signals.

[0008] The present invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which should not be construed as limiting the invention to the specific embodiments, but rather are merely for purposes of illustration and understanding. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 illustrates macro-level power usage during an ultrasound examination. [Figure 2] FIG. 1 illustrates one embodiment of an ultrasonic transducer probe having an ultrasonic transducer assembly. [Figure 3] FIG. 1 shows a simplified illustration of frame acquisition for display performed by an ultrasound machine. [Figure 4] FIG. 1 illustrates the activity of one embodiment of an ultrasound machine while imaging. [Figure 5] FIG. 1 illustrates the basic actions of the receive path clock of an ultrasound machine. [Figure 6] FIG. 1 is a block diagram of one embodiment of a portion of an ultrasound machine. [Figure 7]1 is a flow diagram of one embodiment of a process for configuring dynamic power reduction for an ultrasound machine. [Figure 8] 1 is a flow diagram of one embodiment of a power reduction process for use by an ultrasound machine. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, numerous details are set forth to provide a more thorough explanation of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

[0011] An ultrasound system with dynamic power reduction and methods of using the same are disclosed. In one embodiment, the dynamic power reduction is implemented using hardware in the acoustic signal path to automatically detect power savings and transparently control the digital clock without system software intervention. In one embodiment, the hardware-based dynamic power reduction is implemented in conjunction with or in addition to the macro-sleep conditions described above. In one embodiment, the hardware-based dynamic power reduction is configured to reduce power while actively imaging. In one embodiment, the power reduction is equal to or greater than the software-controlled sleep techniques discussed above, with the added benefit of no added software complexity.

[0012] FIG. 2 illustrates one embodiment of an ultrasound transducer probe having an ultrasound transducer assembly configured in accordance with embodiments of the disclosed technology. Referring to FIG. 2, ultrasound transducer probe 200 includes an enclosure 210 extending between a distal end portion 212 and a proximal end portion 214. Enclosure 210 is configured to carry or house system electronics (e.g., one or more processors, integrated circuits, ASICs, FPGAs, beamformers, batteries, and / or other power sources) disposed within an interior portion or cavity of enclosure 210. The system electronics (not shown) are electrically coupled to an ultrasound imaging system 230 through a cable 218 attached to the proximal end of the probe.

[0013] At the probe tip, a transducer assembly 220 having one or more transducer elements is electrically coupled to the system electronics. In operation, the transducer assembly 220 transmits ultrasonic energy from the one or more transducer elements toward a subject and receives ultrasonic echoes from the subject. The ultrasonic echoes are converted into electrical signals by transmit / receive circuitry and electrically transmitted to the system electronics and to electronics (e.g., one or more processors, memory modules, beamformers, FPGAs, etc.) within the ultrasound imaging system 230 configured to process the electrical signals to form one or more ultrasound images.

[0014] Capturing ultrasound data from a subject using an exemplary transducer assembly (e.g., transducer assembly 220) generally involves generating ultrasound waves, transmitting the ultrasound waves to the subject, and receiving the ultrasound waves reflected by the subject. A wide range of ultrasound frequencies can be used to capture ultrasound data, such as low-frequency ultrasound (e.g., less than 15 MHz) and / or high-frequency ultrasound (e.g., greater than or equal to 15 MHz). One skilled in the art can readily determine which frequency range to use based on factors such as, but not limited to, imaging depth and / or desired resolution.

[0015] In one embodiment, ultrasound imaging system 230 includes an ultrasound control subsystem 231 having one or more processors. At least one processor sends electrical current to the transducers of probe 200 to cause them to emit sound waves, and also receives electrical pulses from the probe generated from the returning echoes. The processor processes raw data associated with the received electrical pulses to form an image that is sent to ultrasound imaging subsystem 232, which displays the image on display screen 233. That is, display screen 233 displays an ultrasound image from the ultrasound data processed by the processors of ultrasound control subsystem 231.

[0016] In one embodiment, the ultrasound system also includes one or more user input devices (e.g., keyboard, cursor control device, etc.) that allow data to be entered and measurements to be taken from the display of the ultrasound display subsystem, a disk storage device (e.g., hard disk, floppy disk, compact disk (CD), digital video disk (DVD)) for storing acquired images, and a printer for printing images from the displayed data, which are also not shown in FIG. 2 so as not to obscure the techniques disclosed herein.

[0017] Figure 3 shows a simplified illustration of frame acquisition for display performed by an ultrasound machine. A frame represents the amount of data required to form an image on the display. The continuous acquisition and display of frames of data allows the ultrasound machine to show the motion of the object being observed.

[0018] Referring to FIG. 3, a frame is composed of multiple (N) transmit beams 303 generated by a transducer 301 toward an object of interest 304 located at a depth from the skin line 302, and echo returns from each of the transmit beams 303. In one embodiment, these beams 303 are closely spaced in time to minimize the time to generate a frame. The frame rate, which indicates how often the display is updated, is generally related to the frame acquisition time. In many applications, the ultrasound machine does not need to operate at its maximum frame rate because the display electronics cannot keep up or the user cannot perceive the change from one frame to the next. There is often a gap between the end of one frame and the start of the next, referred to herein as the frame hold-off time. FIG. 4 illustrates the activity of one embodiment of an ultrasound machine during imaging. Referring to FIG. 4, multiple transmit / receive beams are shown for frames 1 through N acquired over time. Between each of these frames is the frame hold-off time.

[0019] Each of the N transmit / receive beams 303 within the frame can be further examined in terms of its activity. For simplicity, the receive path is described below in terms of dynamic power reduction, but it should be understood that the dynamic power reduction techniques disclosed herein can also be applied to the transmit path. In one embodiment, the transmit path refers to the electronics used to excite the individual transducer elements. Some common components for the transmit path are high-voltage driver circuitry used to energize the transducer elements, a set of delay circuits that control the timing of signals to the high-voltage drivers to control the focus of the generated acoustic beam, and a waveform table (e.g., a look-up table (LUT) or other memory) that controls the shape of the signals to the high-voltage drivers. In one embodiment, the receive path comprises electronics used to process low-level echoes detected by the transducer elements in response to the transmit beam. Typical operations performed by the electronics are return signal amplification using both fixed and time-variable amplifiers, filtering, signal conversion from the analog domain to the digital domain, and receive beamforming. This last operation includes a time-variable digital gain that generates a receive aperture with time alignment of the digitally sampled return signals to form a coherent receive beam.

[0020] Figure 5 shows the basic actions of the receive path clock for one embodiment of an ultrasound machine. There are several events that are used to selectively turn the receive path clock on and off dynamically in relation to the timing for a single transmit / receive beam. This is different from the macro control described above because the clock dynamically starts and stops during imaging. In one embodiment, the decision to start and stop the clock is made based on real-time signals during data acquisition.

[0021] Referring to FIG. 5, the receive path clock is off (501). The receive signal path has many parameters unique to each receive channel during a given transmit / receive operation. In one embodiment, the parameters are those discussed with respect to the transmit and receive paths. In one embodiment, the parameters include data controlling individual transmit and receive delays, time-variable gains, and / or channel calibration data for each transmitter and receiver. In one embodiment, the clock to the receive path is active (502) to program the parameters (T1 → T2 in FIG. 5). Once programming is complete, the clock is shut off (503) and remains off until valid echo return data arrives at the transducer (T2 → T3), at which point the clock may remain on (504) for the duration of the data acquisition (T3 → T4). Finally, the clock is shut off (505) and remains off until it is time to reprogram the receive path for the next acquisition.

[0022] Figure 6 is a block diagram of one embodiment of a portion of an ultrasound machine. Referring to Figure 6, the ultrasound machine includes a clock gate control subsystem 601 coupled to a clock generator 602. In one embodiment, the clock generator 602 includes a phase-locked loop (PLL) 603 for generating clock signals. The clock generator 602 provides a free-running clock 606 to a subsystem 607 and an ultrasound control subsystem 610. In one embodiment, the subsystem 607 is part of the imaging subsystem and includes a receive path 608 that receives and processes acoustic signals (e.g., echoes) and a status and control module that provides status and control signals to the clock gate control subsystem 601. In one embodiment, the subsystem 607 includes a transmit path for the ultrasound machine that generates and transmits acoustic signals for the ultrasound machine.

[0023] The ultrasonic control subsystem 610 controls the operation of the ultrasonic machine. In one embodiment, the ultrasonic control subsystem 610 generates status signals. In one embodiment, the ultrasonic control subsystem 610 generates status signals that are sent to and received by the clock gate control subsystem 601.

[0024] In one embodiment, the signals generated by subsystem 607 and ultrasound control subsystem 610 and sent to and received by clock gate control subsystem 601 are real-time signals comprising a first signal (e.g., freeze signal 621) indicating that a user has indicated that they wish to freeze the image currently being displayed on the ultrasound system display, a second signal (e.g., start of line signal 622) indicating the start of a line, a third signal (e.g., programming register signal 623) indicating that a register is being programmed (the register is for the receive path), a fourth signal (e.g., receive_start signal 624) indicating that the receive path has been enabled to receive echo acoustic signals, and a fifth signal (e.g., end of line signal 625) indicating that the end of the line has been reached.

[0025] The clock gating control subsystem 601 uses signals 621-625 to perform clock control by gating / ungating clocks for different portions of the ultrasound machine. In one embodiment, the clock gating control subsystem 601 uses signals 621-625 to perform clock control by gating / ungating clocks for different portions of the ultrasound machine according to a typical transmit / receive beam time sequence during acquisition, as shown in FIG. 5. For example, the clock gating control subsystem 601 controls gate 604 to enable and disable one or more clocks 605 for the receive path 608. For example, in response to freeze signal 621, the clock gating control subsystem 601 controls gate 604 to disable one or more clocks 605 for the receive path 608 because echoes will not be received while the ultrasound machine user freezes the display.

[0026] As another example, in response to the programming register signal 623, the clock gating control subsystem 601 controls the gate 604 to enable one or more clocks 605 for the receive path 608 while the register is being programmed. After programming is complete as indicated by a change in the programming register signal 623, the clock gating control subsystem 601 can control the gate 604 to disable one or more clocks 605 for the receive path 608, placing the receive path 608 in a reduced power consumption state after the transmit section has finished transmitting the beam until a valid echo received on the receive path 608 returns to the transducer.

[0027] As yet another example, in response to the receive start signal 624, the clock gating control subsystem 601 can control the gates 604 to enable one or more clocks 605 for the receive path 608 to power the receive path 608 in order to receive a valid echo return to the transducer to receive, or otherwise disable the clocks 605 to the receive path, placing the receive path in a reduced power consumption state. Similarly, the clock gating control subsystem 601 can use the receive start signal 624 to disable one or more clocks 605 for the transmit path while the receive path 608 is receiving echoes, placing the transmit path in a reduced power consumption state (because the transmit path is not transmitting a beam during that time).

[0028] After finishing receiving the echo and reaching the end of the line as indicated by the end of line signal 625, the clock gating control subsystem 601 can control the gate 604 to disable one or more clocks 605 for the receive path 608 and place it in a reduced power consumption state until a new line is started and / or register programming is performed.

[0029] As yet another example, in response to a start of line signal 622, the clock gating control subsystem 601 can control gate 604 to enable one or more clocks for the transmit path and power the transmit path to transmit the beam from the transducer. In one embodiment, a similar clock gating technique is applied to the transmit path to reduce power (i.e., shut down the transmit logic when not transmitting).

[0030] In one embodiment, the clock gate control subsystem 601 uses signals 621-625 along with one or more conditions (e.g., condition 640) to gate / ungate clocks for different parts of the ultrasound machine. In this case, the clock gate control performed for a particular sequence is different from the time sequence of transmit / receive beams during image acquisition shown in Figure 5. Thus, the clock gate control subsystem 601 handles different control sequences when gate / ungate clocks for different parts of the ultrasound machine.

[0031] In one embodiment, these sequences include one or more of the following:

[0032] 1) An imaging mode in which no reprogramming of registers is required between successive transmit / receive beams, and therefore the time interval T1 → T2 is 0. This is, for example, when reimaging a line into an object to obtain a series of data for use in measuring changes in the motion of an object along the line; there is no need to turn on the clock during the time that the registers are typically programmed when reimaging the line; therefore, the clock remains off until it is time to capture the returning echo values.

[0033] 2) A dummy ping generation when no data is acquired by the receive path 608, but a time delay between the transmit / receive beams is desired. In this case, there is no need to program registers during a "dummy" ping generation, since no transmit or receive occurs. Therefore, the clocks that are typically turned on when programming registers can remain off.

[0034] 3) System initialization or mode changes where no data is acquired by the receive path but register programming is required.

[0035] In imaging modes where register reprogramming between successive transmit / receive beams is not required, the clock gating control subsystem 601 maintains the receive path in a reduced power state from T0 to T3 in Figure 5. This behavior is identified by one of input conditions 640, which represents a deviation from the baseline behavior in which the clock is enabled in response to 623.

[0036] In one embodiment, in the case of dummy ping generation, the clock gating control subsystem 601 uses a clock gating controller to control the clock to the receive path in response to one of the conditions 640 indicating whether the transducer is in ping generation mode. In such a case, since no data is being acquired but a time delay between the transmit / receive beams is desired, when the ultrasound machine is in ping generation mode, the clock gating control subsystem 601 maintains the clock signal to the receive path in a reduced power mode through clock gating when the receive start signal 624 indicates that the receive path 608 is about to receive an echo.

[0037] In one embodiment, during system initialization or mode change, mode change refers to when the imaging mode and type of data displayed changes. An example of this may be switching from grayscale to color imaging, in which case imaging stops and the system is re-initialized to acquire color data, and the clock gate control subsystem 601 uses a clock gate controller to control the clock to the receive path in response to one of conditions 640 indicating whether the ultrasound machine is in system initialization or mode change. In such a case, the clock gate control subsystem 601 enables the clock to the receive path when programming the registers, but does not subsequently re-enable the clock to the receive path in response to the time at which echoes are returned to the transducer according to the timeline of FIG. 5 because data acquisition is not occurring.

[0038] 7 is a flow diagram of one embodiment of a process for configuring dynamic power reduction processes, which may be performed by processing logic comprising hardware (circuitry, dedicated logic, etc.), software (e.g., software running on a chip), firmware, or a combination of the three.

[0039] 7, the process begins by defining the subsystems that may be placed in a low power state and the times and events associated with shutting off their clocks (processing block 701) and all system clocks (processing block 702). In one embodiment, dynamically gated clocks are treated as independent clocks derived from a free-running clock at the same frequency. More specifically, in one embodiment, for each clock, processing logic examines all blocks attached to it and identifies which of these blocks contain logic that can be turned off at some point during normal operation without changing the block's functionality. Next, the events associated with stopping the clock are enumerated.

[0040] Processing continues by grouping registers into clock domains for each subsystem based on activity within the system (processing block 703). After grouping, processing identifies registers that remain active at all times because they interact with system software and may be accessed at any time (processing block 704), and registers that can only go into sleep mode when the system is not imaging. These registers may control other system components that have long awake times (processing block 705), and identifies registers that can be shut off at various times while actively imaging (processing block 706). In one embodiment, these registers reside in the data path or data path control of the subsystem.

[0041] Finally, for each subsystem, the process defines a clock control structure based on the inputs defined by process block 701. In one embodiment, the control structure is timed by a free-running clock and generates real-time control for its corresponding clock switching circuitry.

[0042] 8 is a flow diagram of one embodiment of a power reduction process for use by an ultrasound machine. The process is performed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (e.g., software running on a chip), firmware, or a combination of the three.

[0043] Referring to FIG. 8, processing begins with processing logic monitoring a number of real-time signals indicating the status of imaging operations being performed by the transmit and receive paths of the ultrasound transducer while the ultrasound transducer is in use (processing block 801).

[0044] While monitoring the real-time signals, the processing logic automatically detects conditions in which one or both of the transmit and receive paths of the ultrasonic transducer can be placed into a reduced power consumption state in response to receiving one or more signals from the plurality of real-time signals (processing block 802).

[0045] In response to detecting the condition, the processing logic places one or both of the transmit and receive paths of the ultrasonic transducer into a reduced power consumption state using clock switching circuitry controlled by one or more real-time signals (processing block 803).

[0046] In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer in a reduced power consumption state includes using a clock gating controller to control a clock gating circuit in response to one or more of the plurality of real-time signals to gating a clock to the transmit path after transmitting an acoustic signal for the line to turn off the transmitter of the transmit path, and controlling the clock gating circuit to pass a previously gated second clock signal to the receive path to turn on the receiver when a valid echo signal is expected to arrive at the receiver.

[0047] In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer in a reduced power consumption state includes using a clock gating controller to control a clock gating circuit in response to one or more of the real-time signals to gating clocks to the transmit and receive paths at the end of a frame until another frame is started.

[0048] In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer in a reduced power consumption state includes using a clock gate controller to control the clock gate circuitry in response to a first condition to ignore a first signal of a plurality of real-time signals indicating that one or more receive path registers have been programmed when the imaging mode indicates that there is no need to reprogram one or more receive path registers for transmit and receive operation for successive beams. In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer in a reduced power consumption state includes using a clock gate controller to control the clock gate circuitry in response to a first condition to pass a clock signal to the receive path when programming one or more receive path registers, and thereafter not gate the clock signal to the receive path after programming one or more receive path registers while waiting for a valid echo signal to return to the transducer when the transducer is in an imaging mode that does not require reprogramming one or more receive path registers for transmit and receive operation for successive beams. In one embodiment, the imaging mode includes reimaging a line through an object to obtain a series of data for use in measuring changes in motion of an object along the line.

[0049] In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer in a reduced power consumption state includes using a clock gate controller to control the clock gate circuit by ignoring a first signal of a plurality of real-time signals indicating the start of receive operation in response to a first condition and maintaining the gate of the clock to the receive path after the transmit beam is transmitted from the transducer, the first condition indicating that the transducer is in a ping generation mode.

[0050] In one embodiment, placing one or both of the transmit and receive paths of the ultrasound transducer into a reduced power consumption state comprises using a clock gating controller to control the clock gating circuitry by ignoring a first signal of a plurality of real-time signals indicating the start of receive operation and maintaining gating of the clock to the receive path after register programming in response to a first condition, the first condition indicating that the transducer is in a mode in which valid echo signal acquisition is not expected to occur despite one or more receive path registers being programmed, which in one embodiment is related to system initialization or a mode change.

[0051] In one embodiment, placing one or both of the transmit and receive paths of the ultrasonic transducer into a reduced power consumption state using clock gating circuitry controlled by one or more real-time signals includes controlling the circuitry to gate or pass clock signals without system software intervention.

[0052] In one embodiment, the process further comprises using a clock gate controller to control the circuitry to pass a clock signal to the receive path when programming one or more receive path registers, and then not gate the clock signal to the receive path after programming one or more receive path registers while waiting for a valid echo signal to return to the transducer when the transducer is in an imaging mode where there is no need to reprogram one or more receive path registers for transmit and receive operation for successive beams. In one embodiment, the imaging mode includes reimaging a line into an object to obtain a series of data for use in measuring changes in motion of an object along the line.

[0053] In one embodiment, the plurality of real-time signals comprises a first signal (e.g., freeze signal 621) indicating that a user has indicated that they wish to freeze the image currently being displayed on the ultrasound system display, a second signal (e.g., start of line signal 622) indicating the start of a line, a third signal (e.g., programming register signal 623) indicating that a register (for the receive path) is being programmed, a fourth signal (e.g., start of receive signal 624) indicating that the receive path is configured to receive an echo acoustic signal, and a fifth signal (e.g., end of line signal 625) indicating that the end of the line has been reached.

[0054] As discussed above, power reduction reduces component temperatures for increased reliability, reduces requirements on system power supplies which reduces cost and extends battery life, eliminates / reduces the need for active cooling systems which reduces cost, noise, and complexity, simplifies software control, enables the design of smaller form factor products, and allows for the integration of additional electronics into sealed components such as the transducer handle.

[0055] Unless the context clearly indicates otherwise, throughout this specification and claims, words such as "comprises" and "comprising," etc., shall be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used herein, the terms "connected," "coupled," or any variation thereof, mean either a direct or indirect connection or coupling between two or more elements, and the coupling or connection between the elements may be physical, logical, or a combination thereof. Furthermore, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular parts of this application. Where relevant, in the above detailed description, words using the singular or plural number may also include the plural or singular number, respectively. The word "or" in connection with a list of two or more items includes all of the following interpretations of this word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0056] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. As will be apparent from the following description, unless otherwise specifically stated, descriptions utilizing terms such as "processing" or "operating" or "calculating" or "determining" or "displaying" throughout this specification are recognized to refer to the operation and processing of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in the computer system's registers and memory into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display device.

[0058] The present invention also relates to apparatus for performing the operations herein. This apparatus may include a general-purpose computer, which may be specially constructed for the required purposes, or selectively activated or reconfigured by a computer program stored in the computer. Such computer program may be stored on a computer-readable storage medium such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove advantageous to include more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​can be used to implement the teachings of the present invention as described herein.

[0060] A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include read-only memory ("ROM"), random-access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0061] It is to be understood that, while many alternatives and modifications of the present invention will no doubt become apparent to those skilled in the art after reading the foregoing description, any particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Accordingly, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.

Claims

1. an imaging subsystem having an ultrasound transducer and a transmit data path having a transmitter for transmitting acoustic signals and a receive data path having signal acquisition circuitry with a receiver for receiving acoustic signals representative of echoes; a subsystem for transmitting a plurality of real-time signals indicative of an imaging mode being implemented by the transmit data path and the receive data path; a clock generator for generating one or more clock signals for use by the transmit data path and the receive data path; a clock switching circuit coupled to the clock generator and the transmit data path and the receive data path, the clock switching circuit including circuitry for switching a clock signal to at least one of the transmit data path and the receive data path; a clock gate controller coupled to the clock gate circuitry and controlling the circuitry to automatically gate or pass a clock signal to at least one of the transmit data path and the receive data path in response to receiving one or more real-time signals from the plurality of real-time signals; wherein the plurality of real-time signals comprises: a first signal indicating that a user has indicated a desire to freeze an image currently being displayed on a display of the ultrasound system; a second signal indicating the start of a line; a third signal indicating that a register has been programmed, the register being for the receive data path; and a fourth signal indicating that the receive data path is enabled to receive echo acoustic signals; and a fifth signal indicating that the end of the line has been reached; and Equipped with 1. An ultrasound system comprising:

2. 2. The ultrasound system of claim 1, wherein the clock gating controller is configured to control the clock gating circuit to gating a clock signal to the transmit data path to turn off a transmitter of the transmit data path after transmitting an acoustic signal for a line in response to the one or more real-time signals, and to control the clock gating circuit to pass a previously gating second clock signal to the receive data path to turn on the receiver when a valid echo signal is expected to arrive at the receiver.

3. 2. The ultrasound system of claim 1, wherein the clock switching controller is configured to control the clock switching circuitry to disable a clock signal to the receive data path at the end of a frame until another frame is initiated in response to the one or more real-time signals.

4. 2. The ultrasound system of claim 1, wherein the clock gate controller, in response to a first condition, ignores the third signal of the plurality of real-time signals indicating that one or more receive data path registers have been programmed when the first condition indicates that there is no need to reprogram the one or more receive data path registers for transmit and receive operation for successive beams.

5. 5. The ultrasound system of claim 4, wherein the clock gate controller is configured to control the circuitry to pass a clock signal to the receive data path when programming the one or more receive data path registers, and thereafter disable the clock signal to the receive data path for the successive beams until a valid echo signal returns to the ultrasound transducer when the ultrasound transducer is in the imaging mode without the need to reprogram the one or more receive data path registers for transmit and receive operation for the successive beams.

6. 6. The ultrasound system of claim 5, wherein the imaging mode includes reimaging a line through an object to obtain a series of data for use in measuring changes in motion within the object along the line.

7. 2. The ultrasound system of claim 1, wherein the clock gating controller ignores the fourth signal of the plurality of real-time signals indicating the start of receive operation in response to a first condition, and maintains gating of the clock signal to the receive data path after a transmit beam is transmitted from the ultrasound transducer, the first condition indicating that the ultrasound transducer is in a ping generation mode in which no data is acquired by the receive data path.

8. 2. The ultrasound system of claim 1, wherein the clock gating controller ignores the fourth signal of the plurality of real-time signals indicating the start of receive operation and maintains gating of the clock signal to the receive data path after register programming in response to a first condition, the first condition indicating that the ultrasound transducer is in a mode in which one or more receive data path registers have been programmed but valid echo signal acquisition is not scheduled to occur.

9. The ultrasound system of claim 8 , wherein the mode is associated with a system initialization or a mode change.

10. 10. The ultrasound system of claim 1, wherein the clock gate controller is configured to control the circuitry to gate or pass a clock signal using hardware.

11. monitoring a plurality of real-time signals indicative of an imaging mode being performed by a transmit data path and a receive data path of the ultrasound transducer while the ultrasound transducer is in use; automatically detecting, in response to receiving one or more real-time signals from the plurality of real-time signals and based on the imaging mode being performed by the transmit data path and the receive data path as indicated by the one or more real-time signals, that one or both of the transmit data path and the receive data path of the ultrasound transducer can be placed in a reduced power consumption state; placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state using a clock switching circuit controlled by the one or more real time signals; wherein the plurality of real-time signals comprises: a first signal indicating that a user has indicated a desire to freeze an image currently being displayed on a display of the ultrasound system; a second signal indicating the start of a line; a third signal indicating that a register has been programmed, the register being for the receive data path; and a fourth signal indicating that the receive data path is enabled to receive echo acoustic signals; and a fifth signal indicating that the end of the line has been reached; and Equipped with A method characterized by:

12. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock gating controller to control the clock gating circuit in response to the one or more of the plurality of real-time signals to gating a clock signal to the transmit data path to turn off a transmitter of the transmit data path after transmitting an acoustic signal for a line, and controlling the clock gating circuit to pass a previously gated second clock signal to the receive data path to turn on a receiver when a valid echo signal is expected to arrive at the receiver.

13. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock switching controller to control the clock switching circuit in response to the one or more of the real-time signals to disable a clock signal to the receive data path at the end of a frame until another frame begins.

14. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock gate controller to control the clock gate circuit in response to a first condition by ignoring the third signal of the plurality of real-time signals indicating that one or more receive data path registers have been programmed when the first condition indicates that there is no need to reprogram the one or more receive data path registers for transmit and receive operation for successive beams.

15. 15. The method of claim 14, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock gate controller to control the clock gate circuit in response to the first condition by passing a clock signal to the receive data path when programming the one or more receive data path registers, and thereafter disabling the clock signal to the receive data path for the successive beams until a valid echo signal returns to the ultrasonic transducer when the ultrasonic transducer is in the imaging mode where there is no need to reprogram the one or more receive data path registers for transmit and receive operation for the successive beams.

16. 16. The method of claim 15, wherein the imaging mode includes reimaging a line in an object to obtain a series of data for use in measuring changes in motion in the object along the line.

17. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock gating controller to control the clock gating circuit in response to a first condition by ignoring the fourth signal of the plurality of real-time signals indicating the start of a receive operation and by maintaining off a clock signal to the receive data path after a transmit beam is transmitted from the ultrasonic transducer, the first condition indicating that the ultrasonic transducer is in a ping generation mode in which no data is acquired by the receive data path.

18. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state comprises using a clock gating controller to control the clock gating circuitry by ignoring the fourth signal of the plurality of real-time signals indicating the start of receive operation and maintaining gating of clock signals to the receive data path after register programming in response to a first condition, the first condition indicating that the ultrasonic transducer is in a mode in which one or more receive data path registers have been programmed but valid echo signal acquisition is not scheduled to occur.

19. 20. The method of claim 18, wherein the mode relates to a system initialization or a mode change.

20. 12. The method of claim 11, wherein placing one or both of the transmit data path and the receive data path of the ultrasonic transducer in the reduced power consumption state using clock gating circuitry controlled by the one or more real-time signals comprises controlling the circuitry to gate or pass clock signals using hardware.

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