Systems and methods for automated real-time calibration of qubit chips

Abstract

To provide a device and a method for real-time calibration of a cubit in a quantum processor.SOLUTION: A device include: a quantum processor including a plurality of cubits each having a specific state; a quantum controller for generating a sequence of an electromagnetic (EM) pulse and operating the state of the plurality of cubits on the basis of a set of control parameters; a cubit measurement unit for measuring one or more sensors related to corresponding one or more cubits among the plurality of cubits and generating corresponding one or more values measured; and a machine learning engine for evaluating the one or more measured values according to a machine learning process, and for generating updated control parameters. The quantum controller uses the updated control parameters to generate a subsequent sequence of the EM pulse to operate the state of the plurality of cubits.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate generally to the field of quantum computing. More particularly, these embodiments relate to techniques for automatic real-time calibration of qubit chips. [Background technology]

[0002] Quantum computing refers to the field of study related to computational systems that use quantum mechanical phenomena to manipulate data. Such quantum mechanical phenomena, such as superposition (a quantum variable can exist in many different states simultaneously) and entanglement (multiple quantum variables have correlated states regardless of the distance between them in space or time), have no analogue in the classical computing world and therefore cannot be implemented on classical computing devices. [Brief explanation of the drawings]

[0003] The best understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0004] [Figure 1A] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment. [Figure 1B] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment. [Figure 1C] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment. [Figure 1D] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment. [Figure 1E] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment. [Figure 1F] FIG. 1 is a diagram of an exemplary quantum dot device according to one embodiment.

[0005] [Figure 2] FIG. 1 is a diagram of one embodiment of a processor pipeline for processing quantum and non-quantum instructions.

[0006] [Figure 3] FIG. 1 is a diagram of one embodiment of a processor front-end circuit for processing quantum and non-quantum instructions.

[0007] [Figure 4A] FIG. 1 is a diagram of an embodiment of a quantum-classical processor interface. [Figure 4B] FIG. 1 is a diagram of an embodiment of a quantum-classical processor interface.

[0008] [Figure 5A] FIG. 1 is a diagram of an exemplary quantum circuit and program code for implementing the quantum circuit. [Figure 5B] FIG. 1 is a diagram of an exemplary quantum circuit and program code for implementing the quantum circuit.

[0009] [Figure 6A] This is an example diagram of quantum instructions being generated by a compiler, decoded into uops, and executed within a quantum execution engine. [Figure 6B] This is an example diagram of quantum instructions being generated by a compiler, decoded into uops, and executed within a quantum execution engine.

[0010] [Figure 7] FIG. 1 is a diagram of a method according to one embodiment of the present invention.

[0011] [Figure 8] FIG. 1 is a diagram of one embodiment of a qubit index generator for addressing qubits in a quantum processor.

[0012] [Figure 9] FIG. 10 is a diagram of a method for determining a qubit index value for identifying a qubit.

[0013] [Figure 10A]FIG. 1 is a diagram of an embodiment of an architecture for real-time qubit calibration using machine learning. [Figure 10B] FIG. 1 is a diagram of an embodiment of an architecture for real-time qubit calibration using machine learning.

[0014] [Figure 11] FIG. 1 is a diagram of one embodiment of a method for predicting qubit control parameters.

[0015] [Figure 12] FIG. 1 is a diagram of one embodiment of a method for updating qubit control parameters. DETAILED DESCRIPTION OF THE INVENTION

[0016] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, those skilled in the art will understand that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of embodiments of the invention. [introduction]

[0017] Quantum computers perform calculations using quantum mechanical phenomena such as superposition and entanglement. In contrast to digital computers, which store data in one of two distinct states (0 or 1), quantum computing uses quantum bits (qubits), which may be in a superposition of states. Qubits may be implemented using physically distinguishable quantum states of elementary particles such as electrons and photons. For example, the polarization of a photon may be used where the two states are vertical and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as "spin up" and "spin down."

[0018] The states of a qubit are typically represented by the bracket notation |0> and |1>. In classical computer systems, a bit is exclusively in one state or the other, i.e., "0" or "1." However, in quantum mechanical systems, a qubit can be in a superposition of two states simultaneously, a feature unique to and fundamental to quantum computing.

[0019] A quantum computing system executes an algorithm that involves quantum logic operations performed on qubits. The sequence of operations is statistically compiled into a schedule, and the qubits are addressed using an indexing scheme. The algorithm is then executed a sufficient number of times until the confidence interval of the calculated answer exceeds a threshold (e.g., ~95+%). Hitting the threshold signifies that the desired algorithmic result has been achieved.

[0020] Qubits have been implemented using a variety of different technologies capable of manipulating and reading quantum states. These include, but are not limited to, quantum dot devices (spin-based and spatial-based), trapped ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, helium liquid surface electron quantum computers, resonator quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Thus, while quantum dot devices are described below with reference to specific embodiments of the invention, the underlying principles of the invention may be utilized in conjunction with any type of quantum computer, including, but not limited to, those listed above. The particular physical implementation used for qubits is independent of the embodiments of the invention described herein. [Quantum dot devices]

[0021] Quantum dots are small semiconductor particles, typically a few nanometers in size. Because of their small size, quantum dots behave according to the rules of quantum mechanics and have optical and electronic properties that differ from their macroscopic counterparts. Quantum dots are sometimes called "artificial atoms" to allude to the fact that they are single objects with distinct, confined electronic states, as in the case of atoms or molecules.

[0022] 1A-1F are various views of a quantum dot device 100, which may be used in embodiments of the invention described below. FIG. 1A is a top view of a portion of quantum dot device 100 with some of the material removed so that first gate line 102, second gate line 104, and third gate line 106 are visible. While the figures and many of the descriptions herein may refer to particular sets of lines or gates as "barrier" or "quantum dot" lines or gates, respectively, this is merely for ease of discussion; in other embodiments, the roles of "barrier" and "quantum dot" lines and gates may be interchanged (e.g., barrier gates may instead function as qubit gates, and vice versa). 1B to 1F are cross-sectional side views of the quantum dot device 100 of FIG. 1A, and in particular, FIG. 1B is a view through the BB section of FIG. 1A, FIG. 1C is a view through the CC section of FIG. 1A, FIG. 1D is a view through the DD section of FIG. 1A, FIG. 1E is a view through the EE section of FIG. 1A, and FIG. 1F is a view through the FF section of FIG. 1A.

[0023] 1A-1F may be operated in any of several ways. For example, in some embodiments, an electrical signal, such as a voltage, a current, a radio frequency (RF), and / or a microwave signal, may be provided to one or more of the first gate line 102, the second gate line 104, and / or the third gate line 106 to cause quantum dots (e.g., electron spin-based quantum dots or hole spin-based quantum dots) to form in the quantum well stack 146 beneath the third gate 166 of the third gate line 106. An electrical signal provided to the third gate line 106 may control the potential of the quantum well under the third gate 166 of that third gate line 106, while an electrical signal provided to the first gate line 102 (and / or the second gate line 104) may control the potential energy barrier between adjacent quantum wells under the first gate 162 of that first gate line 102 (and / or the second gate 164 of that second gate line 104). Quantum interactions between quantum dots in different quantum wells in the quantum well stack 146 (e.g., under different qubit gates) may be controlled in part by the potential energy barrier provided by a barrier potential imposed between them (e.g., by intervening barrier gates).

[0024] Generally, the quantum dot device 100 disclosed herein may further include a magnetic field source (not shown) that can be used to create an energy difference in a normally decaying quantum dot state (e.g., the spin state of an electron spin-based quantum dot), and the quantum dot state (e.g., the spin state) may be manipulated by applying electromagnetic energy to the gate line to create a computationally capable qubit. The magnetic field source may be one or more magnet lines, as discussed below. Thus, the quantum dot device 100 disclosed herein may be capable of manipulating the position, number, and quantum state (e.g., spin) of quantum dots in the quantum well stack 146 through the controlled application of electromagnetic energy.

[0025] In the quantum dot device 100 of FIGS. 1A-1F, a gate dielectric 114 may be disposed on a quantum well stack 146. The quantum well stack 146 may include at least one quantum well layer 152 (not shown in FIGS. 1A-1F) in which the quantum dots may be localized during operation of the quantum dot device 100. The gate dielectric 114 may be any suitable material, such as a high-K dielectric material. Multiple parallel first gate lines 102 may be disposed on the gate dielectric 114, and spacer material 118 may be disposed on the sides of the first gate lines 102. In some embodiments, a patterned hard mask 110 may be disposed on the first gate lines 102 (in a pattern corresponding to the pattern of the first gate lines 102), and the spacer material 118 may extend to the sides of the hard mask 110, as shown. Each of the first gate lines 102 may be a first gate 162. Different ones of the first gate lines 102 may be electrically controlled in any desired combination (e.g., each first gate line 102 may be electrically controlled separately, or some or all of the first gate lines 102 may be shorted together in one or more groups, as desired).

[0026] Multiple parallel second gate lines 104 may be disposed over and between the first gate lines 102. As illustrated in FIG. 1A, the second gate lines 104 may be arranged orthogonal to the first gate lines 102. The second gate lines 104 may extend over the hard mask 110 and may include second gates 164 that extend down toward the quantum well stack 146 and contact the gate dielectric 114 between adjacent ones of the first gate lines 102, as illustrated in FIG. 1D. In some embodiments, the second gates 164 may fill the areas between the first gate line 102 / spacer material 118 structures; in other embodiments, an insulating material (not shown) may be present between the first gate line 102 / spacer material 118 structures and adjacent second gates 164. In some embodiments, spacer material 118 may be disposed on the sides of the second gate line 104; in other embodiments, spacer material 118 may not be disposed on the sides of the second gate line 104. In some embodiments, a hard mask 115 may be disposed above the second gate line 104. The multiple gates of the second gates 164 of the second gate line 104 are electrically continuous (due to the shared conductive material of the second gate line 104 on the hard mask 110). Different ones of the second gate lines 104 may be electrically controlled in any desired combination (e.g., each second gate line 104 may be electrically controlled separately, or some or all of the second gate lines 104 may be shorted together in one or more groups, as desired). Overall, the first gate lines 102 and the second gate lines 104 may form a grid, as depicted in FIG. 1A.

[0027] Multiple parallel third gate lines 106 may be disposed over and between the first gate lines 102 and the second gate lines 104. As shown in FIG. 1A , the third gate lines 106 may be arranged diagonally relative to the first gate lines 102 and diagonally relative to the second gate lines 104. Specifically, the third gate lines 106 may be arranged diagonally over openings in the grid formed by the first gate lines 102 and the second gate lines 104. The third gate lines 106 may include third gates 166 that extend down to the gate dielectric 114 within openings in the grid formed by the first gate lines 102 and the second gate lines 104, such that each third gate 166 may be bounded by two different first gate lines 102 and two different second gate lines 104. In some embodiments, the third gates 166 may be bounded by insulating material 128, while in other embodiments the third gates 166 may fill openings in the grid (e.g., in contact with spacer material 118 flanking adjacent first and second gate lines 102 and 104, not shown). Additional insulating material 117 may be disposed over and / or around the third gate lines 106. The multiple gates of the third gates 166 of the third gate lines 106 are electrically continuous (due to the shared conductive material of the third gate lines 106 over the first and second gate lines 102 and 104). Different ones of the third gate lines 106 may be electrically controlled in any desired combination (e.g., each third gate line 106 may be electrically controlled separately, or some or all of the third gate lines 106 may be shorted together in one or more groups, as desired).

[0028] 1A-1F illustrate a particular number of first gate lines 102, second gate lines 104, and third gate lines 106, this is for illustrative purposes only and any number of first gate lines 102, second gate lines 104, and third gate lines 106 may be included in quantum dot device 100. Other example arrangements of first gate lines 102, second gate lines 104, and third gate lines 106 are possible. Electrical interconnects (e.g., vias and conductive lines) may contact first gate lines 102, second gate lines 104, and third gate lines 106 in any desired manner.

[0029] Not shown in FIGS. 1A-1F are accumulation regions that may be electrically coupled to the quantum well layers of the quantum well stack 146 (e.g., laterally adjacent to the quantum well layers). The accumulation regions may be separated from the gate lines by a thin layer of intervening dielectric material. The accumulation regions may be regions where carriers accumulate (e.g., by doping or by the presence of a large electrode that draws carriers into the quantum well layers) and may serve as reservoirs of carriers that can be selectively drawn into areas of the quantum well layers under the third gate 166 (e.g., by controlling voltages on the quantum dot gates, first gate 162 and second gate 164) to form carrier-based quantum dots (e.g., electron or hole quantum dots, including a single charge carrier, a majority of charge carriers, or no charge carriers at all). In other embodiments, the quantum dot device 100 may not include a lateral accumulation region but instead include doped layers within the quantum well stack 146. Such doped layers may provide carriers to the quantum well layers. Any combination of accumulation regions or doped layers (eg, doped or undoped) within the quantum well stack 146 may be used in any of the embodiments of quantum dot device 100 disclosed herein. [Apparatus and method for hybrid classical-quantum computing]

[0030] Since Richard Feynman asked in 1982 whether quantum physics could be efficiently simulated using quantum computers, much effort in quantum computer research has focused on their universality and their efficiency relative to classical computation. One such example is David Deutsch's 1985 quantum Turing machine, which can be programmed to perform any computational task that can be performed by any physical object.

[0031] In contrast to theories and algorithms, quantum physical machines are still in their infancy. Efforts to build quantum information processing systems have so far met with moderate success. Miniature quantum computers, capable of performing a small set of quantum operations on very few qubits, represent the state of the art in quantum computing. In addition, quantum states are fragile, in the sense that they remain coherent for only a limited period of time. This gap between algorithms and physical machines has led to efforts to invent hybrid classical-quantum algorithms. Some recent quantum algorithm developments have focused on short-depth quantum circuits for performing quantum computations, formed as subroutines embedded in larger classical optimization loops, such as the variational eigensolver (PJJ O'Malley, 2016). To address the severe resource constraints in quantum computing, quantum languages, tools, and flows have been developed that provide software layers / stacks to translate and optimize applications into the quantum physical layer (Frederic T. Chong, September 14, 2017).

[0032] On the hardware side, classical computers are used to perform error correction for quantum computations. The "quantum coprocessor" model is the most convenient and widespread execution model, in which a classical CPU controls a quantum processing unit in a manner similar to how a CPU interacts with a GPU in modern computer systems. As described in (X. Fu, May 2016) and (X. Fu, 2018), the microarchitecture for an experimental superconducting quantum coprocessor included features such as an arbiter on the code fetch data path to direct classical instructions to the host CPU and quantum instructions to the quantum coprocessor, an exchange register file to synchronize the register files between the host CPU and the quantum coprocessor, and a quantum instruction cache.

[0033] However, the microarchitecture for such mechanisms is not well defined and lacks explicit support for hybrid classical-quantum programs. As a result, it is unclear how quantum coprocessors will be implemented within quantum computers, particularly those required to run different sets of quantum programs. Flexible, programmable models for running hybrid classical-quantum algorithms remain to be developed.

[0034] One embodiment of the present invention adds a set of quantum instructions to the instruction set architecture (ISA) of a processor, such as a CPU. By way of example, these instructions may be included in an extension to the ISA (e.g., the AVX-512 extension for an x86 platform). Additionally, in one embodiment, a quantum engine is added to the processor's execution units, and new quantum instructions are fetched, decoded, scheduled, and executed on the quantum engine's functional units. In one embodiment, the quantum engine interacts with the classical execution engine using a shared register file and / or system memory. Upon executing quantum instructions (or quantum uops, in certain embodiments described herein), the quantum execution engine generates control signals to manipulate the state of qubits within the quantum processor. The quantum engine also executes instructions to perform measurements on a specified set of qubits and store the results. In these embodiments, a quantum / classical interface provides connectivity between the quantum engine of the classical processor and the quantum engine of the quantum processor.

[0035] 2 illustrates one embodiment of a processor or core 210 that fetches, decodes, and executes quantum instructions 201A and non-quantum instructions 201B utilizing the same pipeline resources as non-quantum instructions 201B. Processor / core 210 of this embodiment supports quantum extensions to the processor / core's 210's existing ISA (e.g., extending the ISA to include quantum instructions 201A). Program code 205C including quantum and non-quantum instructions is generated by compiler 205B from source code 205A written by a programmer (e.g., utilizing the extended ISA). Various source / program code examples are provided below.

[0036] Quantum and non-quantum instructions 201A-B are fetched from memory 205 at the front end of the instruction pipeline and stored in a level 1 (L1) instruction cache 201. Instructions and data may also be stored in a level 2 or level 3 cache within the cache / memory subsystem 215, which manages memory requests and cache coherency.

[0037] Decoder 202 decodes instructions 201A-B into micro-operations or uops 203A, which are scheduled for execution by scheduler 203 and executed by execution circuitry 204. In one embodiment, certain stages of the pipeline are enhanced to include hardware support for processing non-quantum instructions 201B, while other stages remain unchanged. For example, quantum decode circuitry 202A may be added to decoder 202 to decode quantum instructions 201A, just as non-quantum decode circuitry 202B decodes non-quantum instructions 201B. While illustrated as separate components in FIG. 2 for purposes of explanation, quantum decode circuitry 202A and non-quantum decode circuitry 202B may include common or overlapping sets of circuitry and / or microcode. For example, in one embodiment, an existing decoder may be extended to include microcode support for quantum instructions (e.g., in a microcode ROM) to generate a new set of quantum uops. Decoder 202 may include other decoding circuitry, depending on the processor architecture, such as a set of decoding table structures (see, eg, FIG. 3 and associated text).

[0038] In one embodiment, decoder 202 generates a sequence of uops 203A in response to decoding instructions 201A-B. In an implementation with quantum and non-quantum instructions, the uops may include a mix of quantum and non-quantum uops, which are then scheduled for execution by instruction scheduler 203.

[0039] Quantum and non-quantum uops 203A generated by decoder 202 may initially be queued for execution within one or more uops queues of scheduler 203, which dispatches uops from the uops queues according to dependencies and / or execution resource availability. Embodiments of the present invention may be implemented on a variety of different types of processors with different types of schedulers. For example, in one embodiment, a set of execution “ports” couples scheduler 203 to execution circuitry 204, where each execution port is capable of issuing uops to a particular set of functional units 204C-E. In the exemplary architecture shown in FIG. 2, for example, SIMD and floating-point (FP) uops may be issued by scheduler 203 to FP / SIMD execution ports coupled to a set of FP / SIMD functional units 204C, and integer uops may be issued to integer ports coupled to a set of integer functional units 204D. Although only two types of non-quantum functional units are shown for simplicity, the processor / core 210 may include various other / additional non-quantum functional units (e.g., load / store address generation units, branch units, additional SIMD and integer units, etc.).

[0040] 2, quantum engine functional unit 204E shares the same set of register files 204A-B used by legacy processor functional units 204C-D. In this particular example, register files 204A-B include FP / SIMD register file 204A, which stores floating-point and SIMD operands used by FP / SIMD functional unit 204C and integer register file 204B, and integer register file 204B, which stores integer operands for integer functional unit 204D. In one implementation, FP / SIMD register file 204A has 512-bit vector registers, and integer register file 204B comprises 64-bit scalar registers. Of course, different processor architectures use different types of registers shared by quantum engine functional unit 204E. Various other types of registers, such as a set of control / status registers and mask registers, may also be used.

[0041] In one embodiment in which quantum uops are mixed with non-quantum uops, quantum uops are issued across one or more quantum ports to a set of quantum engine functional units 204E, which execute the quantum uops to perform underlying quantum operations. For example, in response to the quantum uops, quantum engine functional units 204E may generate control signals across quantum-classical interface 206 to manipulate and measure qubits of quantum processor 207.

[0042] Quantum-classical interface 206 includes digital-to-analog (DA) circuitry to convert the digital quantum control signals generated by quantum engine functional unit 204E into analog signals needed to control quantum processor 207 (such as a codeword trigger pulse generation (CTPG) unit and arbitrary waveform generator (AWG) described below), and also includes analog-to-digital (AD) circuitry to convert physical qubit measurements into digital result data.

[0043] In one embodiment, quantum-classical interface 206 is integrated on the same semiconductor chip as other components of the instruction processing pipeline (e.g., execution circuitry 204, scheduler 203, decoder 202, etc.). As discussed in more detail below, different types of circuit / logic components may be used depending on the particular physical implementation of quantum processor 207.

[0044] 3 illustrates one embodiment in which quantum instruction processing support is added to a low-power processing pipeline that includes a pre-decode buffer 301B, a two-way decoder 302 with dual sets of quantum / non-quantum decoder circuits 202A-B, a dual lookup table for instruction translation (XLAT), and a ucodeROM 304. In one embodiment, the XLAT components 303, 305 and ucodeROM 304 are extended to support quantum instructions as indicated by logic blocks 303Q-305Q. Pre-decode buffer 301B detects and marks macro-instruction boundaries before full decoding into uops by the two-way decoder 302.

[0045] Operands for quantum and non-quantum uops are stored in a set of shared registers 321 (as described above) and are accessed by quantum functional unit 320 when executing uops. QC interface 320 controls the operation of quantum processor 207 in response to quantum uops.

[0046] Different examples of quantum-classical interface 206 are illustrated in Figures 4A-4B. QC interface 206 in Figure 4A includes multiple uops units 401A-C, which, in response to uops executed by quantum engine functional unit 204E, generate code words for controlling the operation of multiple code word trigger pulse generation (CTPG) units 402A-C. In response, CTPG units 402A-C generate sequences of pulses to control qubits in quantum processor 207. When quantum processor 207 reaches a specified execution state, quantum measurements are taken by one or more of measurement identification units (MDUs) 403A-B.

[0047] 4B includes a set of components for performing microwave composite signal generation, including an RF microwave unit 451, a multi-channel arbitrary waveform generator (AWG) 452, one or more digital-to-analog converters (DACs) 453, and one or more measurement units 454. In one embodiment, the inputs to each of these components include a set of codewords generated by quantum engine functional unit 204E, and the outputs are analog waveforms that manipulate the states of qubits in quantum processor 207. Measurement unit 454 measures the current states associated with one or more qubits at designated times during execution.

[0048] To further guide the analysis and discussion, a concrete example is illustrated in Figure 5A, which shows a quantum circuit for a many-body disordered Hamiltonian to evolve in time. R x and R y Note that the angle by which h rotates is derived from several parameters. In particular, h for k∈{0,1,…,5,6} k z and h k x are randomly generated and used to emulate large many-body systems that require a larger number of qubits than the basic quantum chip supports.

[0049] An example of a quantum program using this circuit for part of its computation is illustrated in Figure 5B, which contains a mix of quantum and non-quantum instructions (as indicated by the comments to the right of the source code). In this example, NR is the number of disordered realizations (i.e., a variety of small random realizations to emulate a large many-body system), NQ is the number of qubits, NP is the number of iterations to achieve the required precision for probability (Pr), NT is the number of Trotter steps, and a[i] accumulates qubit measurements. The probability that a qubit is in state |0> or |1> is obtained by repeating the measurements (NP) and averaging.

[0050] This program structure shows how classical and quantum operations are tightly intertwined and executed on the classical-quantum processing architecture described herein. The most efficient way to execute this program is to process all instructions in a pipeline, such as those described above, and the quantum engine functional unit 204E for controlling the qubits is configured as an execution engine comparable to the other classical execution engines 204A-B (integer, floating point, etc.).

[0051] 6A-6B provide an example of quantum operations performed in response to the program code of FIG. 5A. In particular, FIG. 6A illustrates a portion of quantum assembly language (QASM) code 601 for implementing the highlighted portion 501 of the quantum circuit of FIG. 5A. The QASM code 601 is compiled into hybrid processor program code 602 in memory 205. In this example, registers RBX and RBX+1 from shared register file 321 or 204B are used to hold qubit indices for addressing logical qubits #2 and #3, respectively, in this particular example. The mapping of the relevant portions of QASM code 601 to hybrid processor program code 602 is indicated by arrows.

[0052] 6B illustrates how the quantum macro instruction QCNOTUP (to implement a CNOT gate) is decoded by decoder 202 into a series of uops 605. The uops 605 are executed by quantum engine functional unit 204E to generate a codeword in a specified codeword or command packet format 606. In one particular format, a first data field indicates the qubit on which the operation should be performed (qubit 3 in this example), a second data field indicates the channel over which the operation should be transmitted (channel 4), a third field indicates the command state (e.g., a single command state), and a fourth data field indicates the type of qubit (transmon qubit). Naturally, the underlying principles of the present invention are not limited to any particular encoding format.

[0053] A method according to one embodiment of the present invention is illustrated in Figure 7. The method may be implemented within the context of the processor architectures described above, but is not limited to any particular processor or system architecture.

[0054] At 701, source code containing quantum instructions is compiled to generate runtime program code having quantum and non-quantum instructions. At 702, quantum / non-quantum instructions are fetched from memory and stored in a local cache (e.g., an L1 instruction cache) or instruction buffer. As mentioned, quantum instructions may be freely mixed with non-quantum instructions within the pipeline.

[0055] At 703, the quantum and non-quantum instructions are decoded into sets of quantum uops and sets of non-quantum uops, respectively, and queued prior to execution. At 704, quantum / non-quantum instruction uops are scheduled for execution based on uop and / or resource dependencies. For example, if a first uop is dependent on the result of a second uop, then the first uop may be scheduled for execution only if the data produced by the second uop is available in one of the registers. Similarly, if a particular functional unit is busy, then the scheduler may wait for an indication that the functional unit is available before scheduling a uop that requires that functional unit. Various other / additional scheduling techniques (e.g., scheduling based on priority, register load, etc.) may be implemented.

[0056] At 705, quantum and non-quantum uops execute on their respective functional units within the execution circuitry. As mentioned, a shared register set may be used to store source and destination operands required by these uops.

[0057] At 706, the results produced by the execution of the quantum uops may be used as inputs to an interface unit to control the quantum states of qubits in the quantum processor. In one embodiment, a series of code words or command packs may be generated that identify the quantum channel, one or more qubits in the quantum processor, qubit types, and / or command states. The specific physical operations performed in response to the code words or command packs are based on the underlying type of quantum processor used.

[0058] The embodiments described herein integrate quantum instructions within existing processor pipelines. Because of the tight integration, such embodiments significantly reduce various overheads / bottlenecks associated with current coprocessor designs, including, for example, communication between classical and quantum computation layers / modules in the software stack, and between the classical CPU and the quantum chip via message queues. Given the relatively small size of quantum routines, current GPU-like coprocessor implementations are inefficient.

[0059] Due to the increased classical processing power, the hybrid coprocessor model reduces some of the overhead. In one particular implementation that supports the hybrid coprocessor model, many new microarchitectural features are introduced. However, these microarchitectural features are vaguely defined, as are the boundaries between classical CPUs and quantum coprocessors.

[0060] In contrast, in the hybrid architecture described herein, the classical computation pipeline is equipped to fully support a defined set of quantum instructions, which may be freely mixed with non-quantum instructions both at the front end of the pipeline (i.e., at the microinstruction level) and within the back end of the pipeline (e.g., where quantum uops are mixed with non-quantum uops), and may be executed on execution units within the processor's execution circuitry. Scalable qubit addressing modes for quantum execution engines and / or coprocessors

[0061] In quantum computing, a qubit is a unit of quantum information that is the quantum counterpart of a classical binary bit. Computations are achieved by applying quantum gates, which represent quantum logic operations, directly to the qubits. Mathematically, this computation process is described as the qubit undergoing a single transformation. Once the computation is complete, the qubit is measured to obtain information about the qubit's state.

[0062] Therefore, to describe a quantum operation, it is essential to identify the qubit or set of qubits to which the operation applies. In a quantum program, each quantum instruction must encode both the operation to be performed and the qubit or qubits that perform the operation. In existing quantum instruction set architectures (e.g., QASM, Open QASM, QIS, etc.), register operands are typically encoded in the instruction's opcode. This scheme works only for classical computation because the number of registers is extremely limited (e.g., 16, 32, 64, etc.). However, this scheme is not scalable for quantum computing, because quantum instructions will ultimately need to address an extremely large number of qubits. As a result, encoding qubit addresses in the opcode field of a quantum instruction would significantly increase the instruction width.

[0063] As described above, in one embodiment, quantum and non-quantum instructions are processed together in a shared processor pipeline. Quantum instructions may therefore rely on the same addressing modes available to non-quantum instructions. Qubits in this embodiment are therefore addressed in a similar manner to non-quantum instructions, which access system memory and provide a sufficiently large address space to accommodate a large number of qubits.

[0064] 8, in this embodiment, quantum engine functional unit 204E includes a qubit index generation unit (QIG) 802 that determines a qubit index value or qubit ID in response to one or more uops 805. One or more quantum operation units 801 process the operations specified by the uops. The qubit index value (e.g., 011 for qubit 3 in this example) is then incorporated into a codeword or command packet 606, possibly along with one or more commands generated by quantum operation unit 801 in response to processing uops 805.

[0065] QIG802 may operate according to different addressing modes supported by the processor. In one embodiment, an instruction identifies one of the shared registers 321 that contains a qubit index value (sometimes called a qubit ID). The qubit index value may then be used to identify a qubit in a codeword or command packet 606 and / or to perform an operation using the qubit index value to generate one or more additional qubit index values. For example, it may add the qubit ID value to an integer specified by the uop to generate a second qubit ID.

[0066] The following example illustrates one way that QIG802 generates qubit IDs in response to uops using x86 assembly syntax. These operations may be performed within an x86 pipeline extended to support quantum instructions. However, the same general principles may be implemented on any processor architecture.

[0067] The single qubit instruction "QIROTX[RDI], 1" adds an X gate to the qubit number stored in RDI. So if RDI contains 5, an X gate is added to qubit number 5. In this example, QIG802 determines the qubit ID by simply reading the value stored in RDI (which in this example is one of the shared registers 321). In this embodiment, the RDI value was previously stored by another uop. In another example, if the architectural register RBX contains a value of 2, then the two-qubit instruction “QCNOTUP[RBX+3]” applies a CNOT operation, where qubit 2 (q[2]) is the control qubit and qubit 5 (q[5]) is the target qubit. The control qubit's ID is stored in RBX, and the QIG resolves the [RBX+3] notation when the control qubit's ID is the target qubit ID. In this way, the addressing scheme is extended to allow two different qubits to be addressed with a single instruction (i.e., CNOT). In contrast, in classical computing, only one memory location is addressed per instruction.

[0068] FIG. 8 also illustrates a codeword trigger pulse generator (CTPG) 402A, which includes control logic and an analog-to-digital converter (ADC) to interpret the codeword / command packet 606, identify one or more qubits (Q3 in this example), and generate a sequence of pulses to implement the specified quantum operation. When all of the quantum operations as specified by the program code 205C have been executed, the quantum operation circuit 801 and the QIG 802 generate the codeword / command packet 606 and cause one or more MDUs 403A-B to measure one or more qubits (as specified by the QIG 802, which generates the qubit index). As mentioned, the MDUs include analog-to-digital circuitry to convert analog measurements to digital values, which are then processed by the quantum error correction unit 808 to detect and possibly correct errors. If valid result data is received, it may be stored in one or more of the shared registers 321 and / or accumulated with previous measurement data. In addition to error correction, measurements can also be used for program flow control based on measurement feedback.

[0069] The quantum error correction unit 808 may implement various techniques to detect and correct quantum errors. For example, in one embodiment, an error decoder (within the QEC unit 808) decodes multiple qubit measurements from the quantum processor 207 to determine whether an error occurred and, if so, implements (possibly) corrective action. The error measurements may be obtained from multiple qubits in a manner that does not disturb the quantum information in the encoded state of the qubits (e.g., using ancillary bits). In response, the QEC unit 808 generates error syndrome data, from which it may identify the error that occurred and implement actions to correct it. In one embodiment, the error syndrome data has a stabilizer signature, such as a surface signature. In some cases, the response may simply be to reinitialize the qubits and start over. In other cases, however, modifications to the quantum algorithm implemented in quantum program code 205C may be made to stabilize regions of the quantum processor that are responsible for errors (e.g., in this case, compiler 205B includes a just-in-time (JIT) compiler). In either case, CTPG 402A performs elementary physical operations under control of codeword / command packets 606 generated by QEFU 204E. For example, CTPG 402A may generate an electromagnetic pulse to adjust the phase of one or more qubits according to a detected phase error, or may reset the phase / spin of all qubits if reinitialization is required.

[0070] Addressing qubits in a manner similar to the way classical CPUs address memory provides scalability characteristics / attributes needed for future quantum processor implementations. In particular, the embodiments described above seamlessly integrate within existing processor ISAs and provide qubit indexing that scales to large number of qubit systems. These embodiments also remove pressure from the quantum instruction opcode space, addressing the qubit space, and integrating quantum operations into existing processor pipelines via quantum extensions to x86 or other architectures.

[0071] A method according to one embodiment of the present invention is illustrated in Figure 9. The method may be implemented on the architectures described above, but is not limited to any particular processor or system architecture.

[0072] At 901, quantum and non-quantum instructions from the runtime program code are fetched and decoded to generate quantum uops and non-quantum uops. At 902, an index generation unit evaluates the quantum uops, including register identifiers, and optionally one or more values ​​included with the uops, to determine qubit index values. As described above, the indexes may be generated using a variety of techniques, including reading qubit index values ​​from registers identified by the uops and using integer values ​​included with the uops to generate additional qubit index values.

[0073] At 902, the quantum execution circuit generates a code word specifying a quantum operation to be performed on a qubit identified by the calculated qubit index value. At 905, a qubit measurement is performed in response to another code word generated based on the additional uops. At 906, analog measurements made on one or more of the qubits are converted to digital values. Error correction and / or flow control may then be performed based on the resulting digital result values ​​stored in the processor's register file. Apparatus and method for automated real-time calibration of qubit chips

[0074] One of the key challenges in quantum computer design is ensuring that error rates are maintained below an acceptable threshold. The ideal control strategy for each individual quantum gate depends on the characteristics of the fundamental types of error and on the design of uniquely tailoring the control strategy to each type of error through a calibration process.

[0075] Qubit calibration is currently performed manually before execution. This is problematic because many algorithms can take a long time to run, which means that the original calibration may no longer be applicable. As a result, the fidelity of the qubit gates may be degraded to the point where the entire algorithm cannot be performed. Therefore, it is necessary to calibrate the control parameters during the execution of the algorithm to counteract the effects of noise.

[0076] Real-time, ancillary bit-based calibration has been proposed for trapped ion qubits, but the proposed framework only considers coherent errors in the system and does not provide a fast control algorithm for calibration.

[0077] Additionally, quantum systems have been proposed that implement machine learning techniques for closed-loop quantum control. However, these machine learning methods require measurements of the quantum system and cannot be implemented while the quantum algorithm is running. Furthermore, current open-loop control proposals do not consider real-time, environment-induced errors in quantum systems.

[0078] One embodiment of the present invention implements machine learning techniques to learn and calibrate qubit control parameters in real time while the system is operating (e.g., while the underlying quantum algorithms are running). In particular, classical or quantum models are used to simulate the dynamics of the system, allowing the machine learning engine to predict new control parameters.

[0079] Noisy measurements from sensors close to the data qubits are provided as input to a machine learning engine, which learns how these sensor values ​​relate to the control parameters. The machine learning engine can then use the learned correlations to predict new control parameters (e.g., new / adjusted DC pulses) to compensate for real-time changes in the system. For example, the new control parameters may be implemented in barrier and plunger gate voltages. In one implementation in which a simulated model is used, the model validates whether the new control parameters are reasonable.

[0080] 10A illustrates one embodiment of a machine learning architecture in which a machine learning engine 1030 renders multiple control parameter predictions 1050A-N based on feedback from a physical quantum system 1005. In particular, each instance of control parameter prediction logic 1050A-N executed by the ML engine 1030 evaluates measurement results from sensors 1070A-N for a subset of the quantum system (e.g., a single qubit or a small number of qubits), compares the measured results with estimated values, and determines a difference value. It then predicts a set of control parameters 1060A-N to control the qubits in that portion of the system. One embodiment of the present invention continues to operate in this manner, with the ML engine 1030 receiving measurement feedback 1070A-N from the associated sensors and the control parameter prediction instances 1050A-N rendering new control parameter predictions 1060A-N.

[0081] 10B illustrates one embodiment of an architecture for performing real-time calibration of a quantum system. The physical quantum computing system 1005 of this embodiment may be implemented using any of the different quantum processors and quantum control architectures described herein (e.g., quantum processor 207, CPTG units 402A-B, MDUs 403A-B, etc.). However, it should be noted that the underlying principles of the present invention are not limited to these specific implementations. In one embodiment, quantum processor 207 comprises a quantum dot processor, but the underlying principles of the present invention are not limited to quantum dot processors.

[0082] In one embodiment, physical quantum system 1005 includes quantum processor 207 with multiple qubits Q1-Q6 configured into initial state 1000 via a sequence of RF control pulses (e.g., via CTPG units 402A-C). Once in initial state 1000, qubits Q1-Q6 of quantum system 1005 may be manipulated via additional sequences of RF pulses, DC pulses, or combinations thereof, control pulses according to specified control parameters 1001 to implement a quantum algorithm.

[0083] When control pulses are applied to data qubits to perform quantum gates, unwanted coupling and environmental noise may affect spatially neighboring qubits. To address this issue, one embodiment of the present invention includes a machine learning engine 1030 to optimize and calibrate control parameters 1001 in real time. In particular, measured outputs (y) are collected from sensors on the quantum processor chip such that the states of the data qubits are preserved. For example, a measurement discrimination unit (MDU) may determine the states of the ancillary bits, which can be used to determine the states of the corresponding data qubits in quantum processor 207.

[0084] A set of sensors in a local neighborhood of a data qubit are considered for measurement without disturbing the data qubit. By assigning some nearby sensors to the data qubit, machine learning engine 1030 can determine a correlation between control parameters 1001 applied to the data qubit and the measured output (y) from the sensors. As shown in Figures 10A-10B, this learning model can be used to estimate the measurement output given the estimated control parameters.

[0085] A mathematical / simulated model 1010 is used that implements the time evolution of the system (e.g., capturing the dynamics of the quantum system 1005). For example, the simulated model 1010 may be implemented in program code that runs on a classical computing system. The simulated model 1010 may be used to calculate the estimated control parameters

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[0086] Using the simulated model 1010 and the actual measurements y from the sensors and the estimated measurement outputs y from the ML-based estimator 1030,

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[0087] By way of example, and not limitation, a Markov-based recursive algorithm may be used to calibrate the control parameters in real time. The control algorithm performs predictions and updates the phase such that at each phase, only the results of the previous phase are needed. Thus, the algorithm is fast and does not consume large memory to store previous measurement results or control parameters. The steps of the algorithm are as follows:

[0088] One embodiment of machine learning engine 1030 performs reinforcement learning (RL) to optimize control parameters 1001 in real time. The learning algorithm sends control parameters to the qubit chip environment and observes sensor outputs to determine how close the system is to a target state. It then adjusts the control parameters with the goal of minimizing a cost function or maximizing a reward function. Different implementations may use a model-based or model-free RL framework.

[0089] One embodiment of a method for performing prediction is described with respect to Figure 11. This method may be implemented in the architectures described above, but it is not limited to any particular architecture.

[0090] In operation 1101, the a priori control parameters at time step k-1 are

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[0091] One embodiment of a method for performing control parameter updates is described with respect to Figure 12. This method may be implemented in the architectures described above, but it is not limited to any particular architecture.

[0092] In operation 1201, the estimated a priori error covariance P' k and the measurement noise R are used to determine the control gain K k (e.g., adjustments made to various control parameters). In operation 1202, the control gain K k and the a priori error covariance P' k is used to calculate the a posteriori error covariance P k In operation 1203, the a priori control parameters

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[0093] While embodiments of the present invention can be implemented in a variety of different contexts, one notable application involves real-time calibration of control parameters in quantum processors composed of electrostatically defined, confinement-based semiconductor quantum dots. In such systems, multi-qubit gates are implemented by applying precisely calibrated voltage pulses to the barrier and plunger gates on desired quantum dots. Due to capacitance crosstalk, the electrochemical potential and tunneling coupling of nearby quantum dots are affected.

[0094] In current implementations, quantum systems are calibrated offline, and the effects of cross-capacitance between all gates are calculated and encoded in a crosstalk matrix to generate virtual quantum operations that compensate for the crosstalk. When the system is operating, the pre-calculated crosstalk matrix is ​​used to adjust the control parameters of the multi-qubit gates. However, after a period of time, drift causes the virtual gates to lose calibration, reducing the fidelity of the multi-qubit gates. Embodiments of the invention described herein solve the calibration drift problem by considering some quantum dots as sensors and updating the virtual gates in real time while the extended quantum algorithm runs.

[0095] Another potential application relates to the real-time calibration of control parameters of quantum processors composed of superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interference meters (SQUIDs). In such systems, multi-qubit gates are typically implemented by applying precisely calibrated current pulses to the SQUID loop, either modifying the resonant frequency of a qubit or changing the coupling between two qubits. On-chip crosstalk also affects the resonant frequency and coupling strength of nearby qubits. Embodiments of the present invention address the calibration drift problem by treating some superconducting qubits or superconducting resonators as sensors, updating compensation in real time while extended quantum algorithms are running. Hysteresis present in the control lines can also be a source of apparent drift in system parameters, and the present invention can mitigate such effects.

[0096] In the above detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0097] Various operations may be described as multiple separate acts or operations, ordered in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments. The terms "first," "second," "third," etc. do not imply a particular order unless otherwise specified.

[0098] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used to refer to a range of measurement, includes both ends of the range of measurement. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0099] The description uses the phrases "in one embodiment" or "in an embodiment," which may refer to one or more of the same or different embodiments, respectively. Furthermore, the terms "comprising," "including," "having," etc. are synonymous when used in reference to embodiments of the present disclosure.

[0100] Embodiments of the invention may include various steps, which are described above. The steps may be embodied in machine-executable instructions that may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0101] [Example]

[0102] Below are exemplary implementations of different embodiments of the present invention.

[0103] Example 1 1. An apparatus comprising: a quantum processor including a plurality of qubits, each of the qubits having a particular state; a quantum controller for generating sequences of electromagnetic (EM) pulses to manipulate the states of the plurality of qubits based on a set of control parameters; a qubit measurement unit for measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; and a machine learning engine for evaluating the one or more measured values ​​according to a machine learning process to generate updated control parameters, wherein the quantum controller uses the updated control parameters to generate a subsequent sequence of EM pulses to manipulate the states of the plurality of qubits.

[0104] Example 2 2. The apparatus of example 1, wherein the machine learning engine estimates measurements from the sensors and determines differences between the measured values ​​and corresponding estimated values ​​to determine updated control parameters.

[0105] Example 3 3. The apparatus of example 2, wherein the machine learning engine comprises a machine learning estimator for evaluating the set of estimated control parameters to generate the estimated measurement values.

[0106] Example 4 4. The apparatus of example 3, wherein the machine learning engine further comprises a simulated quantum model for generating the set of estimated control parameters.

[0107] Example 5 2. The apparatus of example 1, wherein the machine learning process comprises a reinforcement learning process.

[0108] Example 6 6. The apparatus of example 5, wherein the reinforcement learning process generates estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and the estimated measurements.

[0109] Example 7 2. The apparatus of example 1, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

[0110] Example 8 2. The apparatus of example 1, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

[0111] Example 9 2. The apparatus of example 1, wherein the sensor comprises a first subset of the plurality of qubits, each qubit in the first subset being associated with at least one other qubit in a second subset of the plurality of qubits.

[0112] Example 10 The apparatus of example 1, wherein the EM pulse comprises a DC pulse.

[0113] Example 11 1. A method comprising: generating a sequence of electromagnetic pulses to manipulate the state of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; and generating a subsequent sequence of pulses using the updated control parameters to manipulate the state of the plurality of qubits.

[0114] Example 12 12. The method of example 11, wherein the machine learning process estimates measurements from sensors and determines differences between measured values ​​and corresponding estimated values ​​to determine the updated control parameters.

[0115] Example 13 13. The method of example 12, wherein the machine learning process further comprises evaluating the set of estimated control parameters to generate estimated measurements.

[0116] Example 14 14. The method of example 13, wherein the machine learning process further comprises generating a set of estimated control parameters in the simulated quantum model.

[0117] Example 15 12. The method of example 11, wherein the machine learning process further comprises a reinforcement learning process.

[0118] Example 16 16. The method of example 15, wherein the reinforcement learning process comprises generating estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and the estimated measurements.

[0119] Example 17 12. The method of example 11, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

[0120] Example 18 12. The method of example 11, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

[0121] Example 19 A machine-readable medium having program code stored thereon that, when executed by a machine, causes the machine to perform the following operations: generating a sequence of electromagnetic pulses (EM) to manipulate the state of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; and generating a subsequent sequence of pulses using the updated control parameters to manipulate the state of the plurality of qubits.

[0122] Example 20 20. The machine-readable medium of example 19, wherein the machine learning process estimates measurements for states of the plurality of qubits and determines differences between the measured values ​​and corresponding estimated values ​​to determine updated control parameters.

[0123] Example 21 21. The machine-readable medium of example 20, wherein the machine learning process further comprises evaluating the set of estimated control parameters to generate estimated measurements.

[0124] Example 22 22. The machine-readable medium of example 21, wherein the machine learning process further comprises generating a set of estimated control parameters in the simulated quantum model.

[0125] Example 23 20. The machine-readable medium of example 19, wherein the machine learning process comprises a reinforcement learning process.

[0126] Example 24 24. The machine-readable medium of example 23, wherein the reinforcement learning process comprises generating estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and the estimated measurements.

[0127] Example 25 20. The machine-readable medium of example 19, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

[0128] Example 26 20. The machine-readable medium of example 19, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

[0129] As described herein, instructions may refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC), configured to perform a particular operation or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the figures may be implemented using code and data stored in and executed by one or more electronic devices (e.g., end stations, network elements, etc.) that store and communicate (internally and / or with other electronic devices over a network) the code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks, optical disks, random access memory, read-only memory, flash memory devices, phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical, or other forms of propagated signals, e.g., carrier waves, infrared signals, digital signals, etc.).

[0130] In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connections. The coupling of the set of processors to the other components is typically via one or more buses and bridges (also called bus controllers). The storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, a storage device of a given electronic device typically stores code and / or data for execution on a set of one or more processors of that electronic device. It should be understood that one or more portions of an embodiment of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. In certain instances, well-known structures and functions have not been described in elaborate detail to avoid obscuring the subject matter of the present invention. Accordingly, the spirit and scope of the invention should be judged in terms of the scope of the claims that follow. [Other possible items] [Item 1] a quantum processor including a plurality of qubits, each of the qubits having a particular state; a quantum controller for generating a sequence of electromagnetic (EM) pulses to manipulate the states of the plurality of qubits based on a set of control parameters; a qubit measurement unit for measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; a machine learning engine for evaluating the one or more measured values ​​according to a machine learning process to generate updated control parameters; Equipped with The quantum controller uses the updated control parameters to generate a subsequent sequence of EM pulses to manipulate the state of the plurality of qubits. [Item 2] Item 10. The apparatus of item 1, wherein the machine learning engine estimates measurements from the sensors and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters. [Item 3] 3. The apparatus of claim 2, wherein the machine learning engine comprises a machine learning estimator for evaluating a set of estimated control parameters to generate the estimated measurement values. [Item 4] Item 4. The apparatus of item 3, wherein the machine learning engine further comprises a simulated quantum model for generating the set of estimated control parameters. [Item 5] Item 10. The apparatus of item 1, wherein the machine learning process comprises a reinforcement learning process. [Item 6] Item 6. The apparatus of item 5, wherein the reinforcement learning process generates the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements. [Item 7] Item 10. The apparatus of item 1, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots. [Item 8] Item 10. The apparatus of item 1, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers. [Item 9] Item 10. The apparatus of item 1, wherein the sensor comprises a first subset of the plurality of qubits, and each qubit in the first subset is associated with at least one other qubit in a second subset of the plurality of qubits. [Item 10] Item 10. The apparatus of item 1, wherein the EM pulse comprises a DC pulse. [Item 11] generating a sequence of electromagnetic pulses to manipulate the states of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; generating a subsequent sequence of pulses using the updated control parameters to manipulate the states of the plurality of qubits; A method for providing [Item 12] Item 12. The method of item 11, wherein the machine learning process estimates measurements from the sensors and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters. [Item 13] 13. The method of claim 12, wherein the machine learning process further comprises evaluating a set of estimated control parameters to generate the estimated measurement values. [Item 14] Item 14. The method of item 13, wherein the machine learning process further comprises generating the set of estimated control parameters with a simulated quantum model. [Item 15] Item 12. The method of item 11, wherein the machine learning process comprises a reinforcement learning process. [Item 16] Item 16. The method of item 15, wherein the reinforcement learning process comprises generating the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements. [Item 17] Item 12. The method of item 11, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots. [Item 18] Item 12. The method of item 11, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers. [Item 19] an operation that, when performed by a machine, causes the machine to generate a sequence of electromagnetic pulses (EM) that manipulate the state of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; and generating a subsequent sequence of pulses using the updated control parameters to manipulate the states of the plurality of qubits; and 20. A machine-readable medium having program code stored thereon for causing the computer to execute a program. [Item 20] 20. The machine-readable medium of claim 19, wherein the machine learning process estimates measurements on states of the plurality of qubits and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters. [Item 21] 21. The machine-readable medium of claim 20, wherein the machine learning process further comprises evaluating a set of estimated control parameters to generate the estimated measurement values. [Item 22] 22. The machine-readable medium of claim 21, wherein the machine learning process further comprises generating the set of estimated control parameters with a simulated quantum model. [Item 23] The machine-readable medium of Item 19, wherein the machine learning process comprises a reinforcement learning process. [Item 24] 24. The machine-readable medium of claim 23, wherein the reinforcement learning process comprises generating the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements. [Item 25] 20. The machine-readable medium of claim 19, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots. [Item 26] 20. The machine-readable medium of claim 19, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

Claims

1. a quantum processor including a plurality of qubits, each of the qubits having a particular state; a quantum controller for generating a sequence of electromagnetic (EM) pulses to manipulate the states of the plurality of qubits based on a set of control parameters; a qubit measurement unit for measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; a machine learning engine for evaluating the one or more measured values ​​according to a machine learning process to generate updated control parameters; Equipped with the machine learning engine estimates measurements from the one or more sensors and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters; The quantum controller uses the updated control parameters to generate a subsequent sequence of EM pulses to manipulate the state of the plurality of qubits.

2. The apparatus of claim 1 , wherein the machine learning engine comprises a machine learning estimator for evaluating a set of estimated control parameters to generate the estimated measurement values.

3. The apparatus of claim 2 , wherein the machine learning engine further comprises a simulated quantum model for generating the set of estimated control parameters.

4. The apparatus of claim 2 or 3, wherein the machine learning process comprises a reinforcement learning process.

5. 5. The apparatus of claim 4, wherein the reinforcement learning process generates the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements.

6. 6. The apparatus of claim 1, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

7. The apparatus of claim 6 , wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

8. 8. The apparatus of claim 6 or 7, wherein the one or more sensors comprise a first subset of the plurality of qubits, each qubit in the first subset being associated with at least one other qubit in a second subset of the plurality of qubits.

9. The apparatus of claim 1 or 8, wherein the EM pulse comprises a DC pulse.

10. generating a sequence of electromagnetic pulses to manipulate the states of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; generating a subsequent sequence of pulses using the updated control parameters to manipulate the states of the plurality of qubits; Equipped with The method of claim 1, wherein the machine learning process estimates measurements from the one or more sensors and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters.

11. The method of claim 10 , wherein the machine learning process further comprises evaluating a set of estimated control parameters to generate the estimated measurement value.

12. The method of claim 11 , wherein the machine learning process further comprises generating the set of estimated control parameters with a simulated quantum model.

13. The method of claim 11 or 12, wherein the machine learning process comprises a reinforcement learning process.

14. 14. The method of claim 13, wherein the reinforcement learning process comprises generating the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements.

15. 15. The method of claim 10 or 14, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

16. 16. The method of claim 10 or 15, wherein the quantum processor comprises superconducting qubits based on Josephson junctions and flux-tuned superconducting quantum interferometers.

17. To the machine, generating a sequence of electromagnetic pulses (EM) to manipulate the state of a plurality of qubits of a quantum processor based on a set of control parameters; measuring one or more sensors associated with corresponding one or more qubits of the plurality of qubits to generate one or more corresponding measured values; evaluating the one or more measured values ​​according to a machine learning process; generating updated control parameters based on the machine learning process; generating a subsequent sequence of pulses using the updated control parameters to manipulate the states of the plurality of qubits; Execute The machine learning process estimates measurements on states of the plurality of qubits and determines differences between the measured values ​​and corresponding estimated values ​​to determine the updated control parameters.

18. 20. The program of claim 17, wherein the machine learning process further comprises evaluating a set of estimated control parameters to generate the estimated measurement.

19. 20. The program of claim 18, wherein the machine learning process further comprises generating the set of estimated control parameters with a simulated quantum model.

20. 20. The program of claim 18 or 19, wherein the machine learning process comprises a reinforcement learning process.

21. 21. The program of claim 20, wherein the reinforcement learning process comprises generating the estimated control parameters to minimize a cost function or maximize a reward function associated with the measured values ​​and estimated measurements.

22. 22. The program of claim 17 or 21, wherein the quantum processor comprises electrostatically defined confinement-based semiconductor quantum dots.

23. A machine-readable medium storing a program according to any one of claims 17 to 22.

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