Semiconductor substrate manufacturing method, semiconductor substrate, and method for forming growth layer

Abstract

The problem to be solved by the present invention is to provide a novel technique for manufacturing a semiconductor substrate having a large diameter. The present invention is a method for manufacturing a semiconductor substrate, including a crystal growing step S30 for forming a grown layer 20 on a base substrate 10 having a through-hole 11. The present invention is also a method for forming a grown layer 20, including a through-hole formation step S10 for forming a through-hole 11 in a base substrate 10 prior to the formation of the grown layer 20 on a surface of the base substrate 10.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a method for forming a growth layer. [Background technology]

[0002] Generally, semiconductor substrates are manufactured by growing a growth layer on a base substrate. However, it has been reported that it is difficult to obtain large-diameter semiconductor substrates depending on the composition of the semiconductor material used for crystal growth.

[0003] For example, there is the case where AlN crystal is grown by sublimation on a base substrate such as an aluminum nitride (AlN) substrate or a silicon carbide (SiC) substrate. When crystal is grown simply by sublimation, there are areas where the AlN crystal does not grow, which makes it difficult to obtain a large-diameter semiconductor substrate with good crystallinity.

[0004] In response to these problems, Patent Document 1 describes a technology known as "a method for growing AlN crystal by vapor phase growth on a seed crystal substrate placed in a crystal growth chamber within a crystal growth vessel provided within a reaction vessel, characterized in that a carbon-containing gas is supplied into the crystal growth chamber during crystal growth." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-55881 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a new technique that enables the manufacture of large-diameter semiconductor substrates. Another problem to be solved by the present invention is to provide a new technique that enables the manufacture of large-diameter semiconductor substrates with good crystallinity. [Means for solving the problem]

[0007] The present invention, which solves the above-mentioned problems, is a method for manufacturing a semiconductor substrate, which includes a crystal growth step of forming a growth layer on a base substrate having a through-hole.

[0008] In this way, by forming a growth layer on a base substrate having a through hole, a semiconductor substrate having a diameter equivalent to that of the base substrate can be manufactured. Therefore, by using a base substrate with a large diameter, a large-diameter semiconductor substrate can be obtained.

[0009] In this specification, the term "large diameter" means that a grown layer having a larger area is obtained compared to when a grown layer is formed on a base substrate that does not have a through-hole.

[0010] In a preferred embodiment of the present invention, the crystal growth step is a step of heating the starting substrate so as to form a temperature gradient along the vertical direction of the starting substrate.

[0011] In a preferred embodiment of the present invention, the crystal growth step is a step of arranging the starting substrate and the source material of the growth layer so as to face each other, and heating the starting substrate and the source material so as to form a temperature gradient between the starting substrate and the source material.

[0012] In a preferred embodiment of the present invention, the crystal growth step includes a lateral growth step in which the growth layer grows in a horizontal direction of the base substrate, and a vertical growth step in which the growth layer grows in a vertical direction of the base substrate.

[0013] In a preferred embodiment of the present invention, a through-hole forming step of forming a through-hole in the base substrate is performed. The method further includes a strained layer removing step of removing the strained layer introduced in the through-hole forming step.

[0014] In a preferred embodiment of the present invention, the through-hole forming step is a step of forming the through-hole by irradiating the base substrate with a laser.

[0015] In a preferred embodiment of the present invention, the strained layer removal step is a step of removing the strained layer of the starting substrate by heat treatment.

[0016] In a preferred embodiment of the present invention, the base substrate is made of silicon carbide, and the strained layer removing step is a step of etching the base substrate in a silicon atmosphere.

[0017] The present invention also relates to a method for forming a growth layer, namely, the present invention, which solves the above-mentioned problems, is a method for forming a growth layer, including a through-hole forming step of forming a through-hole in a base substrate before forming a growth layer on the surface of the base substrate.

[0018] In a preferred embodiment of the present invention, the method further comprises a strained layer removing step of removing the strained layer introduced in the through-hole forming step.

[0019] In a preferred embodiment of the present invention, the strained layer removal step is a step of etching the base substrate by heat treatment. [Effects of the Invention]

[0020] The disclosed technology can provide a novel technology that enables the manufacture of large-diameter semiconductor substrates. Furthermore, the disclosed technology can provide a novel technology that enables the manufacture of large-diameter semiconductor substrates with good crystallinity.

[0021] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and claims. [Brief explanation of the drawings]

[0022] [Figure 1] 1A to 1C are explanatory diagrams illustrating steps of a method for manufacturing a semiconductor substrate according to an embodiment. [Figure 2] 10A to 10C are explanatory views illustrating a through-hole forming step and a strained layer removing step according to the embodiment. [Figure 3] 10A and 10B are explanatory diagrams of a through-hole forming step according to an embodiment; [Figure 4] FIG. 2 is an explanatory diagram illustrating a crystal growth process according to an embodiment. [Figure 5] FIG. 2 is an explanatory diagram illustrating a crystal growth process according to an embodiment. [Figure 6] FIG. 3 is an explanatory view of a through-hole forming step according to the first embodiment. [Figure 7] FIG. 4 is an explanatory diagram of a strained layer removing step according to the first embodiment. [Figure 8] FIG. 2 is an explanatory diagram of a crystal growth process according to Example 1. [Figure 9] FIG. 2 is an explanatory diagram of a crystal growth process according to Example 1. [Figure 10] FIG. 2 is an explanatory diagram of a crystal growth process according to Comparative Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0023] Preferred embodiments of a method for manufacturing a semiconductor substrate according to the present invention will be described in detail below with reference to the accompanying drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and appropriate modifications are possible within the scope of the claims. The accompanying drawings are conceptual diagrams, and the relative dimensions of each component do not limit the present invention. Furthermore, in this specification, for the purpose of explaining the invention, the top and bottom may be referred to based on the top and bottom of the drawings, but this does not limit the top and bottom in relation to the use mode of the semiconductor substrate of the present invention. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0024] <<Method for manufacturing semiconductor substrate>> 1 to 4 are explanatory diagrams illustrating steps of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. The method for manufacturing a semiconductor substrate according to the embodiment may include a through-hole formation process S10 for forming a through-hole 11 in a base substrate 10, a strained layer removal process S20 for removing the strained layer 12 introduced by the through-hole formation process S10, and a crystal growth process S30 for forming a growth layer 20 on the base substrate 10 having the through-hole 11.

[0025] Furthermore, this embodiment can be understood as a method for forming a large-area growth layer 20, which includes a through-hole formation process S10 for forming through-holes 11 in the base substrate 10 before forming the growth layer 20 on the surface of the base substrate 10. Each step of the embodiment will be described in detail below.

[0026] <Through hole formation process> The through hole forming step S10 is a step of forming through holes 11 in the base substrate 10. Naturally, any method capable of forming through holes 11 in the base substrate 10 can be used for this through hole forming step S10.

[0027] The through-holes 11 can be formed, for example, by laser processing, focused ion beam (FIB) system, reactive ion etching (RIE) or other plasma etching. In Fig. 2 showing this embodiment, a means for forming the through-holes 11 by irradiating the base substrate 10 with a laser L is illustrated.

[0028] The base substrate 10 can naturally be made of any material commonly used in manufacturing semiconductor substrates. Examples of the material for the base substrate 10 include known Group IV materials such as silicon (Si), germanium (Ge), and diamond (C). Examples of the material for the base substrate 10 include known Group IV-IV compound materials such as silicon carbide (SiC). Examples of the material for the base substrate 10 include known Group II-VI compound materials such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), and cadmium telluride (CdTe). The material of the base substrate 10 is, for example, a known III-V compound material such as boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb). The material of the base substrate 10 is, for example, an oxide material such as aluminum oxide (Al2O3) or gallium oxide (Ga2O3). The material of the base substrate 10 is, for example, a metal material such as copper (Cu) or nickel (Ni). The base substrate 10 may be appropriately doped with known dopant atoms used depending on the material.

[0029] The base substrate 10 may be a wafer or substrate processed from a bulk crystal, or may be a substrate having a buffer layer made of the semiconductor material described above.

[0030] The through-hole 11 may have any shape suitable for the semiconductor material to be grown, and may be formed in one or more. Also, a through-hole group (pattern) in which a plurality of through-holes 11 are arranged may be used.

[0031] An example of a pattern for growing a hexagonal semiconductor material will now be described in detail.

[0032] FIG. 3 is an explanatory diagram illustrating a pattern 100 according to an embodiment. The line segments of the pattern 100 represent the base substrate 10. The pattern 100 preferably has a three-fold symmetrical, regular hexagonal displaced shape. The "regular hexagonal displaced shape" in the description of this specification will be described in detail below with reference to FIG. 3. The regular hexagonal displaced shape is a dodecagon. The regular hexagonal displaced shape is composed of 12 straight line segments of equal length. The regular hexagonal displaced shape of the pattern 100 contains a reference figure 101 that is a regular triangle, has an area 101a, and includes three vertices 104. Each of the three vertices 104 is included in the vertices of the pattern 100. It can be understood that the three vertices 104 may be located on the line segments that constitute the pattern 100. Pattern 100 includes line segment 102 (corresponding to a first line segment) that extends from and includes vertex 104, and line segment 103 (corresponding to a second line segment) that does not extend from vertex 104 and is adjacent to line segment 102 without including vertex 104. Here, the angle θ formed by the two adjacent line segments 102 in pattern 100 is constant and equal to the angle θ formed by the two adjacent line segments 103 in pattern 100. Note that the term "regular hexagon-displaced shape" in the description herein can be understood to mean a dodecagon formed by displacing (deforming) a regular hexagon while maintaining the area of ​​the regular hexagon based on angle θ, which indicates the degree of irregularity.

[0033] The angle θ is preferably greater than 60°, and is preferably 66° or greater, and is preferably 80° or greater, and is preferably 83° or greater, and is preferably 120° or greater, and is preferably 150° or greater, and is preferably 155° or greater. The angle θ is preferably 180° or less, and is preferably 155° or less, and is preferably 150° or less, and is preferably 120° or less, and is preferably 83° or less, and is preferably 80° or less, and is preferably 66° or less.

[0034] The pattern 100 according to the embodiment may have a configuration of a displaced regular dodecagon with six-fold symmetry, instead of a displaced regular hexagon with three-fold symmetry. The displaced regular dodecagon is a 24-sided polygon. The displaced regular dodecagon is composed of 24 straight line segments of equal length. The pattern 100 having a displaced regular dodecagon contains a reference figure 101 that is a regular hexagon, has an area 101a, and includes six vertices 104. Each of the six vertices 104 is included as a vertex of the pattern 100. As with the displaced regular hexagon, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. In other words, the "regular dodecagon-displaced shape" in the description herein can be understood as a 24-gon obtained by displacing (deforming) a regular dodecagon while maintaining the area of ​​the regular dodecagon based on the angle θ, which indicates the degree of irregularity. Note that the pattern 100 may be configured to present a 2n-gon-displaced shape, which is a 4n-gon obtained by displacing (deforming) a regular 2n-gon while maintaining the area of ​​the regular 2n-gon based on the angle θ, which indicates the degree of irregularity. In this case, the 2n-gon-displaced shape can be understood to include a regular n-gon (corresponding to the reference figure 101). Here, the reference figure 101 can be understood to include n vertices.

[0035] The pattern 100 according to the embodiment may include a displaced regular 2n-gon shape (including a displaced regular hexagon shape and a displaced regular dodecagon shape). The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment (corresponding to a third line segment) connecting the intersection of two adjacent line segments 103 in the displaced regular 2n-gon shape to the center of gravity of the reference figure 101. The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment connecting the intersection of two adjacent line segments 103 in the displaced regular 2n-gon shape to a vertex 104 constituting the reference figure 101. The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment constituting the reference figure 101 included in the displaced regular 2n-gon shape.

[0036] Furthermore, the through-hole forming step S10 is preferably a step of removing 50% or more of the effective area of ​​the base substrate 10. Furthermore, it is more preferably a step of removing 60% or more of the effective area, even more preferably a step of removing 70% or more of the effective area, and even more preferably a step of removing 80% or more of the effective area.

[0037] In this specification, the effective area refers to the surface of the base substrate 10 to which the raw material adheres in the crystal growth step S30. In other words, it refers to the remaining area on the growth surface of the base substrate 10 other than the area removed by the through holes 11.

[0038] The effective area of ​​the base substrate 10 and the shape and pattern of the through holes 11 are preferably set taking into consideration the difference in lattice constant and thermal expansion coefficient between the base substrate 10 and the growth layer 20, the crystal structure of the growth layer 20, and the growth method.

[0039] <Strained layer removal process> The strained layer removal step S20 is a step of removing the strained layer 12 formed on the base substrate 10 in the through-hole formation step S10. An example of this strained layer removal step S20 is a means of etching the base substrate 10 by heat treating the base substrate 10. Furthermore, any means capable of removing the strained layer 12 can be naturally adopted.

[0040] The strained layer 12 can be removed by, for example, a hydrogen etching method using hydrogen gas as an etching gas, a Si-Vapor Etching (SiVE) method in which heating is performed under a Si atmosphere, or an etching method described in Example 1 below.

[0041] <Crystal growth process> The crystal growth step S30 is a step of forming a growth layer 20 on the base substrate 10 in which the through-holes 11 are formed.

[0042] The semiconductor material of the growth layer 20 may be the same as that of the underlying substrate 10 (homoepitaxial growth), or may be a different semiconductor material from that of the underlying substrate 10 (heteroepitaxial growth).

[0043] Naturally, any material that can be epitaxially grown as a semiconductor material can be used as the material for the growth layer 20. The material for the growth layer 20 may be the material for the base substrate 10, or may be a known material that can be used as the material for the base substrate 10, or may be a known material that can be epitaxially grown on the base substrate 10.

[0044] Examples of materials that can be used for the growth layer 20 include Si, Ge, GaN, AlN, InN, ZnS, ZnSe, CdTe, GaP, GaAs, InP, InAs, InSb, and SiC. The combination of the material of the base substrate 10 and the material of the growth layer 20 can be selected appropriately taking into consideration the difference in lattice constant and thermal expansion coefficient between the two materials.

[0045] The crystal growth step S30 can employ known vapor phase growth methods (corresponding to vapor phase epitaxy) such as physical vapor transport (PVT), sublimation recrystallization, modified Rayleigh process, chemical vapor transport (CVT), molecular-organic vapor phase epitaxy (MOVPE), and hydride vapor phase epitaxy (HVPE) as a growth method for the growth layer 20. Note that the crystal growth step S30 can employ physical vapor deposition (PVD) instead of PVT. Note that the crystal growth step S30 can employ chemical vapor deposition (CVD) instead of CVT. Furthermore, the crystal growth step S30 can employ known liquid phase growth methods (equivalent to liquid phase epitaxial methods) such as the TSSG (Top-Seeded Solution Growth) method and the MSE (Metastable Solvent Epitaxy) method as the growth method for the growth layer 20. The crystal growth step S30 can employ the CZ (Czochralski) method as the growth method for the growth layer 20. The crystal growth step S30 can employ an appropriate growth method depending on the materials of the base substrate 10 and the growth layer 20, respectively.

[0046] 3 and 4 are explanatory diagrams illustrating the crystal growth step S30 according to the embodiment. The crystal growth step S30 according to the embodiment is a step of arranging the base substrate 10 and the semiconductor material 40, which is the raw material for the growth layer 20, facing each other in a crucible 30 having a semi-closed space, and heating them. Note that the "semi-closed space" in this specification refers to a space in which the inside of the container can be evacuated, but at least a portion of the vapor generated inside the container can be confined.

[0047] The crystal growth step S30 is a step of heating the base substrate 10 so as to form a temperature gradient along the vertical direction of the base substrate 10. By heating the crucible 30 (base substrate 10 and semiconductor material 40) in this temperature gradient, the raw material is transported from the semiconductor material 40 onto the base substrate 10 via the raw material transport space 31.

[0048] The driving force for transporting the source material can be the temperature gradient described above or the chemical potential difference between the base substrate 10 and the semiconductor material 40 .

[0049] Specifically, within the semi-closed space, vapor consisting of elements sublimated from the semiconductor material 40 is transported by diffusion through the source transport space 31, and condenses in a supersaturated state on the base substrate 10, which is set at a temperature lower than that of the semiconductor material 40. As a result, a growth layer 20 is formed on the base substrate 10.

[0050] The crystal growth step S30 includes a lateral growth step S31 in which the growth layer 20 grows in the horizontal direction of the base substrate 10, and a vertical growth step S32 in which the growth layer 20 grows in the vertical direction of the base substrate 10. In the lateral growth step S31, it is sufficient that the growth component in the horizontal direction is greater than the growth component in the vertical direction, and the growth component in the vertical direction may also be included (growth component: horizontal direction>vertical direction). Furthermore, the vertical growth step S32 may include a horizontal growth component as long as the vertical growth component is greater than the horizontal growth component (growth component: vertical direction>horizontal direction).

[0051] That is, as shown in Figure 4, the lateral growth process S31 is a process in which heat escapes from the through holes 11 in the base substrate 10, forming a horizontal temperature gradient on the surface of the base substrate 10, causing the growth layer 20 to grow toward the through holes 11.

[0052] Thereafter, when a growth layer 20 is formed on the through-hole 11 in the lateral growth step S31, the horizontal temperature gradient on the surface of the base substrate 10 decreases and disappears, and the process automatically moves to the vertical growth step S32.

[0053] In this crystal growth step S30, an inert gas or a doping gas may be introduced into the source material transport space 31 to control the doping concentration of the growth layer 20 and the growth environment.

[0054] According to the present invention, a large-diameter semiconductor substrate can be manufactured by growing a growth layer 20 on a base substrate 10 having through-holes 11. That is, heat escapes from the region where the through-holes 11 are formed, and a growth driving force acts in the horizontal direction of the base substrate 10. As a result, bonding of the growth layer 20 is promoted in the region where the through-holes 11 are formed, and a growth layer 20 having a diameter equivalent to that of the base substrate 10 can be formed. Therefore, by employing a base substrate 10 with a large diameter, a large-diameter semiconductor substrate can be obtained.

[0055] Furthermore, according to the present invention, by forming the growth layer 20 on the region where the through holes 11 are formed, the crystallinity of the growth layer 20 can be improved. In other words, the growth layer 20 formed on the region where the through holes 11 are formed is not located directly above the base substrate 10. Therefore, the growth layer 20 does not inherit threading dislocations (for example, threading screw dislocations, threading edge dislocations, micropipes, etc.) present in the base substrate 10, and threading dislocations in the growth layer 20 can be reduced.

[0056] One embodiment of the method for manufacturing a semiconductor substrate according to the present invention is to grow AlN on a SiC substrate, as shown in the following example. Furthermore, one embodiment of the method for manufacturing a semiconductor substrate according to the present invention does not include a method for growing AlN on a SiC substrate. [Example]

[0057] The present invention will be explained more specifically with reference to Example 1 and Comparative Example 1. In Example 1 and Comparative Example 1, semiconductor substrates were manufactured by growing an AlN growth layer 20 on a SiC base substrate 10.

[0058] Example 1 <Through hole formation process> Under the following conditions, a laser was irradiated onto the base substrate 10 to form through-holes 11.

[0059] (Base substrate 10) Semiconductor material: 4H-SiC Board size: 11mm wide x 11mm long x 524μm thick Growth aspect: Si-face Off-axis angle: on-axis

[0060] (Laser processing conditions) Type: Green laser Wavelength: 532nm Spot diameter: 40 μm Average output power: 4W (at 30kHz)

[0061] (Pattern details) 6A and 6B are explanatory diagrams illustrating the pattern of through holes 11 formed in the through hole forming step S10 according to Example 1. Fig. 6A is an explanatory diagram illustrating an arrangement of a plurality of through holes 11. In Fig. 6A, the black areas indicate the portions of the through holes 11, and the white areas are left as the base substrate 10.

[0062] Fig. 6(b) is an explanatory diagram showing an enlarged view of the through-hole 11 in Fig. 6(a). In Fig. 6(b), the white area indicates the through-hole 11, and the black area is left as the base substrate 10. In the pattern of FIG. 6, 80% or more of the effective area of ​​the starting substrate 10 is removed, thereby reducing the strength of the starting substrate 10.

[0063] <Strained layer removal process S20> FIG. 7 is an explanatory diagram illustrating the strained layer removing step S20 according to the first embodiment. The base substrate 10 in which the through holes 11 were formed in the through hole forming step S10 was housed in a SiC container 50, and the SiC container 50 was then housed in a TaC container 60, and heated under the following conditions.

[0064] (Heating conditions) Heating temperature: 1800℃ Heating time: 2h Etching amount: 8 μm

[0065] (SiC container 50) Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between base substrate 10 and the bottom surface of SiC container 50: 2 mm

[0066] (Details of the SiC container 50) 5, the SiC container 50 is a fitting container having an upper container 51 and a lower container 52 that can fit together. A minute gap 53 is formed at the fitting portion between the upper container 51 and the lower container 52, and the SiC container 50 is configured so that the inside of the SiC container 50 can be evacuated (vacuumed) through this gap 53.

[0067] The SiC container 50 has an etching space 54 formed by placing the starting substrate 10 on the high temperature side of the temperature gradient and a part of the SiC container 50 located on the low temperature side of the temperature gradient opposite the starting substrate 10. This etching space 54 is a space in which Si atoms and C atoms are transported from the starting substrate 10 to the SiC container 50 for etching, using the temperature difference between the starting substrate 10 and the bottom surface of the SiC container 50 as a driving force.

[0068] The SiC vessel 50 also has a substrate holder 55 that holds the base substrate 10 in the hollow to form an etching space 54. Note that this substrate holder 55 may not be provided depending on the direction of the temperature gradient of the heating furnace. For example, if the heating furnace forms a temperature gradient such that the temperature decreases from the lower vessel 52 to the upper vessel 51, the base substrate 10 may be placed on the bottom surface of the lower vessel 52 without providing the substrate holder 55.

[0069] (TaC container 60) Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 64 (Si compound): TaSi2

[0070] (Details of TaC container 60) Similar to the SiC container 50, the TaC container 60 is a fitting container having an upper container 61 and a lower container 62 that can fit together, and is configured to be able to house the SiC container 50. A minute gap 63 is formed at the fitting portion between the upper container 61 and the lower container 62, and the TaC container 60 is configured to be able to be evacuated (vacuumed) through this gap 63.

[0071] The TaC container 60 has a Si vapor supply source 64 capable of supplying vapor pressure of a gaseous species containing Si element into the TaC container 60. The Si vapor supply source 64 may be configured to generate vapor pressure of a gaseous species containing Si element inside the TaC container 60 during heat treatment.

[0072] <Crystal growth process S30> FIG. 8 is an explanatory diagram illustrating the crystal growth step S30 according to the first embodiment. The base substrate 10 from which the strained layer 12 had been removed in the strained layer removing step S20 was placed opposite the semiconductor material 40 and placed in the crucible 30, and heated under the following conditions.

[0073] (Heating conditions) Heating temperature: 2040℃ Heating time: 70h Growth thickness: 500 μm N2 gas pressure: 10kPa

[0074] (crucible 30) Material: Tantalum carbide (TaC) and / or tungsten (W) Container size: 10mm x 10mm x 1.5mm Distance between substrate 10 and semiconductor material 40: 1 mm

[0075] (Details of Crucible 30) The crucible 30 has a source material transport space 31 between the starting substrate 10 and the semiconductor material 40. The source material is transported from the semiconductor material 40 onto the starting substrate 10 via this source material transport space 31.

[0076] 8(a) shows an example of a crucible 30 used in the crystal growth step S30. Similar to the SiC container 50 and the TaC container 60, this crucible 30 is a fitting container including an upper container 32 and a lower container 33 that can fit together. A minute gap 34 is formed at the fitting portion between the upper container 32 and the lower container 33, and the crucible 30 is configured so that the inside of the crucible 30 can be evacuated (evacuated) through this gap 34.

[0077] Furthermore, crucible 30 has a substrate holder 35 that forms raw material transport space 31. This substrate holder 35 is provided between starting substrate 10 and semiconductor material 40, and forms raw material transport space 31 by placing semiconductor material 40 on the high temperature side and starting substrate 10 on the low temperature side.

[0078] Figures 8(b) and 8(c) show other examples of the crucible 30 used in the crystal growth step S30. The temperature gradient in Figures 8(b) and 8(c) is set to be the opposite of that in Figure 8(a), with the base substrate 10 placed on the upper side. That is, similar to Figure 8(a), the semiconductor material 40 is placed on the high-temperature side and the base substrate 10 is placed on the low-temperature side to form the raw material transport space 31.

[0079] FIG. 8(b) shows an example in which starting substrate 10 is fixed to the upper vessel 32 side, thereby forming a source material transport space 31 between the starting substrate 10 and semiconductor material 40. 8(c) shows an example in which a through window is formed in the upper container 32 and a base substrate 10 is placed therein, thereby forming a raw material transport space 31 between the upper container 32 and the lower container 33. Alternatively, as shown in FIG. 8(c), the raw material transport space 31 may be formed by providing an intermediate member 36 between the upper container 32 and the lower container 33.

[0080] (Semiconductor Materials 40) Material: AlN sintered body Size: Width 20mm x Height 20mm x Thickness 5mm

[0081] (Details of Semiconductor Material 40) The AlN sintered body of the semiconductor material 40 was sintered by the following procedure. The AlN powder was placed in the frame of a TaC block and compressed with a moderate force.The compressed AlN powder and TaC block were then placed in a pyrolytic carbon crucible and heated under the following conditions.

[0082] Heating temperature: 1850℃ N2 gas pressure: 10kPa Heating time: 3h

[0083] 9 is a schematic diagram showing the crystal growth step S30 of Example 1. By growing the growth layer 20 on the base substrate 10 with the through-holes 11 formed therein, a temperature gradient is formed in the horizontal direction of the base substrate 10, which can serve as a driving force for the lateral growth of the growth layer 20. In other words, even with a semiconductor material such as AlN, which is difficult to grow crystals from in the horizontal direction, the growth layer 20 can be formed on the region with the through-holes 11 formed therein, and a large-diameter semiconductor substrate can be manufactured.

[0084] In the semiconductor substrate manufactured in Example 1, no threading dislocations were found in the growth layer 20 formed on the region where the through-holes 11 were formed.

[0085] Comparative Example 1 In the base substrate 10 according to Comparative Example 1, grooves 13 were formed instead of the through holes 11 of Example 1. This base substrate 10 was subjected to the crystal growth step S30 under the same conditions as in Example 1. That is, in Comparative Example 1, the through hole formation step S10 was not performed, but the crystal growth step S30 was performed.

[0086] 10 is a schematic diagram showing the crystal growth step S30 of Comparative Example 1. In the semiconductor substrate manufactured in Comparative Example 1, a region was formed above the groove 13 where the growth layer 20 did not grow. That is, when grooves 13 are formed instead of through holes 11, the temperature in the region of grooves 13 does not decrease, and no temperature gradient is formed in the horizontal direction of base substrate 10. As a result, no driving force for growth in the lateral direction is generated, and growth layer 20 is not formed in the region of grooves 13.

[0087] From the results of Example 1 and Comparative Example 1, it can be seen that by forming a growth layer 20 on a base substrate 10 having through-holes 11, a large-diameter semiconductor substrate can be manufactured.

[0088] 10 Base substrate 11 Through hole 12 Strain layer 13 Groove 20 growth layer 30 Crucible 31 Raw material transportation space 40 Semiconductor Materials 50 SiC container 60 TaC container S10 Through hole formation process S20 Strained layer removal process S30 Crystal growth process S31 Lateral growth process S32 Vertical growth process

Claims

1. a crystal growth step of forming a growth layer on a base substrate having a through-hole; A method for manufacturing a semiconductor substrate, wherein the crystal growth process is a process of placing the base substrate and a raw material for the growth layer opposite each other and heating them so that a temperature gradient is formed between the base substrate and the raw material, with the base substrate being on the low temperature side and the raw material being on the high temperature side.

2. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the crystal growth step is a step of heating the base substrate so as to form a temperature gradient along a vertical direction of the base substrate.

3. 3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the crystal growth step comprises a lateral growth step in which the growth layer grows in a horizontal direction of the base substrate, and a vertical growth step in which the growth layer grows in a vertical direction of the base substrate.

4. a through-hole forming step of forming a through-hole in the base substrate; 4. The method for manufacturing a semiconductor substrate according to claim 1, further comprising a strained layer removing step of removing the strained layer introduced in the through-hole forming step.

5. The method for manufacturing a semiconductor substrate according to claim 4 , wherein the through-hole forming step is a step of forming the through-hole by irradiating the base substrate with a laser.

6. 6. The method for manufacturing a semiconductor substrate according to claim 4, wherein the strained layer removing step is a step of removing the strained layer of the base substrate by heat treatment.

7. the base substrate is silicon carbide; 7. The method for manufacturing a semiconductor substrate according to claim 4, wherein the strained layer removing step is a step of etching the base substrate in a silicon atmosphere.

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