Method and apparatus for reducing two-qubit gates in quantum circuits

Abstract

The present disclosure describes methods, apparatus, computer-readable media, and / or means for reducing two-qubit gates in a quantum circuit, which may include receiving a netlist including information related to a first plurality of two-qubit quantum gates forming the quantum circuit; performing controlled gate cancellation operations on the information related to the first plurality of two-qubit quantum gates to generate a second plurality of two-qubit quantum gates that are functionally equivalent to the first plurality of two-qubit quantum gates; generating a new netlist including information related to the second plurality of two-qubit quantum gates; and providing the new netlist to implement functionality of the quantum circuit based on the second plurality of two-qubit quantum gates.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This patent application claims priority to U.S. Non-Provisional Application No. 16 / 678,835, filed November 8, 2019, entitled "Method and Apparatus for Reducing a Two-Qubit Gate in a Quantum Circuit," and U.S. Provisional Patent Application No. 62 / 776,634, filed December 7, 2018, entitled "Method and Apparatus for Reducing a Two-Qubit Gate in a Quantum Circuit," the contents of both applications being incorporated herein by reference in their entireties.

[0002] Aspects of the present disclosure relate generally to circuit optimization, and more particularly to automated optimization of large-scale quantum circuits with continuous parameters. [Background technology]

[0003] Large-scale quantum circuits can be implemented in different ways. The use of trapped atomic ions is one of the quantum information processing (QIP) approaches that has provided universal and fully programmable quantum computing machines. Trapped atomic ions are also a key platform for quantum information networks (QINs). Systems or networks based on trapped atomic ions that can improve the overall communication of such systems or networks are desirable. Summary of the Invention [Problem to be solved by the invention]

[0004] It is therefore desirable to develop efficient techniques that allow better optimization (e.g., fewer gate counts) of large-scale quantum circuits in various types of QIP systems, including QIP systems based on trapped atomic ions and QIP systems based on superconducting circuits. [Means for solving the problem]

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all possible aspects, and is not intended to identify key or critical elements of all aspects or to delineate the scope of some or all aspects. Its purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] Described herein are techniques for automated optimization of large-scale quantum circuits with continuous parameters. For example, aspects of the present disclosure describe implementations of automated methods for optimizing quantum circuits of sizes and types expected to outperform classical computers. The techniques described herein demonstrate how to handle continuous gate parameters and are applicable to a collection of fast algorithms capable of optimizing large-scale quantum circuits. These techniques can provide better optimization in significantly less time than previous approaches, while requiring minimal structural changes to preserve the basic layout of the underlying quantum algorithm. The results provided by these techniques help bridge the gap between computations that can be performed on existing quantum computing hardware and more advanced computations that are more difficult to implement on quantum computing hardware but are expected to outperform those achievable on classical computers.

[0007] In one example, a method for optimizing a quantum circuit is described, the method including the steps of receiving a netlist including information about a first plurality of two-qubit quantum gates forming the quantum circuit; performing a phase polynomial reduction operation on the information about the first list of quantum gates to generate a second list of quantum gates having functional equivalence to the first list of quantum gates, wherein a computational cost, such as the number of quantum gates in the second list of quantum gates, is less than a computational cost, such as the number of quantum gates in the first list of quantum gates; generating a new netlist including the information about the second list of quantum gates; and providing the new netlist for implementing a function of the quantum circuit using the second list of quantum gates.

[0008] In some implementations, a method for reducing two-qubit gates in a quantum circuit may include receiving a netlist including information related to a first plurality of two-qubit quantum gates forming the quantum circuit; performing controlled gate cancellation operations on the information related to the first plurality of two-qubit quantum gates to generate a second plurality of two-qubit quantum gates that are functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of the two-qubit quantum gates in the first plurality of two-qubit quantum gates is greater than a second number of the two-qubit quantum gates in the second plurality of two-qubit quantum gates; generating a new netlist including information related to the second plurality of two-qubit quantum gates; and providing the new netlist to implement functionality of the quantum circuit based on the second plurality of two-qubit quantum gates.

[0009] The accompanying drawings depict only some implementations and therefore should not be considered limiting of the scope. [Brief explanation of the drawings]

[0010] [Figure 1]1 is a diagram illustrating an example of a quantum circuit according to an aspect of the present disclosure. [Figure 2] 1 is a diagram illustrating an example of a quantum circuit for a phase polynomial representation according to an aspect of the present disclosure. [Figure 3] 1 is a chart illustrating an example of rules for Hadamard gate reduction according to aspects of the present disclosure. [Figure 4] 1 is a diagram illustrating an example of a relocation rule according to an aspect of the present disclosure. [Figure 5] 10 is a diagram illustrating an example of a rotation-merge optimization subroutine using a phase polynomial, according to aspects of the present disclosure. [Figure 6] 1 is a diagram illustrating a sub-circuit conforming to a phase polynomial representation according to an aspect of the present disclosure. [Figure 7] 10 is a diagram illustrating an example of a gate count retention rewrite rule according to an aspect of the present disclosure. [Figure 8] 10 is a diagram illustrating an example of a gate count reduction rewrite rule, according to an aspect of the present disclosure. [Figure 9] 6 is a diagram illustrating an example of a further simplification of the circuit in FIG. 5 according to an embodiment of the present disclosure. [Figure 10] 1 is a diagram illustrating an example of a Toffoli gate implementation according to an aspect of the present disclosure. [Figure 11] 1 is a chart illustrating an example of total gate counts for an approximate quantum Fourier transform (QFT), a Quipper library adder, and a Fourier-based adder (QFA), according to an embodiment of the present disclosure. [Figure 12] 10 is a chart illustrating several examples of CNOT gates for a Kuiper library adder circuit, in accordance with aspects of the present disclosure. [Figure 13] 10 is a table illustrating results for a light optimization of summation circuits according to aspects of the present disclosure. [Figure 14] 10 is a table illustrating results of heavy optimization on a Quipper library adder circuit, in accordance with aspects of the present disclosure. [Figure 15] 10 is a chart illustrating an example of total gate count for a product formula algorithm according to aspects of the present disclosure. [Figure 16A] 10 is a table illustrating results for optimizing a product formula algorithm according to aspects of the present disclosure. [Figure 16B] 10 is a table illustrating results for optimizing a product formula algorithm according to aspects of the present disclosure. [Figure 17A] 1 is a table illustrating a comparison of mild and severe T-par optimization for various algorithms, according to an embodiment of the present disclosure. [Figure 17B] 1 is a table illustrating a comparison of mild and severe T-par optimization for various algorithms, according to an embodiment of the present disclosure. [Figure 17C] 1 is a table illustrating a comparison of mild and severe T-par optimization for various algorithms, according to an embodiment of the present disclosure. [Figure 18] FIG. 1 is a block diagram illustrating an example of a device for performing automatic optimization of large-scale quantum circuits with continuous parameters, according to aspects of the present disclosure. [Figure 19] 1 is a flowchart illustrating an example of a method for automatic optimization of large-scale quantum circuits with continuous parameters, according to aspects of the present disclosure. [Figure 20] FIG. 1 is a block diagram illustrating an example of a trapped-ion-based quantum information processing (QIP) system for implementing optimized large-scale quantum circuits, according to aspects of the present disclosure. [Figure 21] FIG. 10 illustrates an example of a rule for two-qubit quantum gate reduction according to an embodiment of the present disclosure. [Figure 22A] FIG. 10 illustrates example rules for controlled gate cancellation according to aspects of the present disclosure. [Figure 22B] FIG. 10 illustrates example rules for controlled gate cancellation according to aspects of the present disclosure. [Figure 23] 1 illustrates a diagram of an equivalent quantum circuit according to an aspect of the present disclosure. [Figure 24] 1 is a flowchart illustrating an example of a method for two-qubit quantum gate reduction in a quantum circuit, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known components are shown in block diagram form to avoid obscuring such concepts.

[0012] This disclosure describes the implementation of an automated method for optimizing quantum circuits of sizes and types expected for quantum computing over classical computers. This disclosure shows how to handle continuous gate parameters and reports a collection of fast algorithms capable of optimizing large-scale quantum circuits. For a set of benchmarks considered, the described techniques can significantly reduce the number of gates. In particular, the disclosed techniques provide better optimization in significantly less time than previous approaches, while requiring minimal structural changes to preserve the basic layout of the underlying quantum algorithm. The results provided by these techniques help bridge the gap between computations that can be performed on existing quantum computing hardware and more advanced computations that are more difficult to implement on quantum computing hardware but are expected to outperform those achievable on classical computers.

[0013] (Prologue) Quantum computers, or quantum information processing (QIP) systems, have the potential to far outperform classical computers in solving certain problems. Perhaps the better-known application of these is the task of integer factorization, for which the fastest known classical algorithm is superpolynomial, Shor's algorithm, which solves this problem in polynomial time and provides a way to attack the widely used RSA cryptosystem.

[0014] Even before the discovery of Shor's algorithm, quantum computers had been proposed to simulate quantum mechanics. By simulating Hamiltonian mechanics, quantum computers can explore condensed matter and high-energy physics, quantum chemistry, and materials science. Useful instances of quantum simulation are more accessible to smaller quantum computers than traditionally difficult instances of the factorization problem.

[0015] These and other potential applications have helped motivate major efforts toward building scalable quantum computers. Two quantum computing technologies, superconducting circuits and trapped ions, have matured sufficiently to enable fully programmable, universal devices, albeit currently of modest size. Several groups, backed by substantial industry and government investment, are actively developing these platforms into larger-scale devices. Thus, quantum computations involving tens or even hundreds of qubits are likely to be performed in the not-too-distant future.

[0016] Experimental quantum information processing remains a challenging technical challenge, and for some time the resources available for quantum computing will be expensive and very limited. It is essential to develop implementations of quantum algorithms that are as efficient as possible (e.g., implemented with the minimum number of gates) in order to make the most of the available hardware.

[0017] Quantum algorithms are typically expressed in terms of quantum circuits, which express computations as sequences of elementary quantum logic gates operating on qubits. There are many ways to implement a given algorithm with the available set of elementary operations, and it is useful to find an implementation that uses the fewest resources. While it is important to develop an efficient algorithm in the abstract sense and to execute that algorithm with an eye toward practical efficiency, large-scale quantum circuits are often complex enough to benefit from techniques that allow for automatic optimization.

[0018] This disclosure describes various techniques that can be implemented as software tools (e.g., quantum circuit optimizers) to reduce the size of quantum circuits, aiming to possibly improve their performance at scales where manual gate-level optimization is no longer practical. Because global optimization of any quantum circuit is QMA-hard, the approach described in this disclosure is to apply a carefully selected set of heuristics in an automated manner to reduce gate count, often resulting in substantial savings.

[0019] The optimization techniques described herein are applicable to several types of quantum circuits. Benchmark circuits include components of quantum algorithms for computing factorization and discrete logarithms, such as quantum Fourier transforms, integer addition circuits, and Galois field multipliers. Also considered are circuits for a product formula approach to Hamiltonian simulation. In each of these cases, the focus was on circuit sizes likely to be useful in applications beyond classical computation. The techniques described herein can help practitioners understand which implementations are most efficient for a given application.

[0020] While there is existing research on quantum circuit optimization, limited research has focused on automated optimization techniques targeting large-scale circuits such as those considered herein. Furthermore, as explained in more detail below, estimates from previously reported runtimes suggest that existing quantum circuit optimizers are unlikely to perform well on such large circuits. Direct comparisons of circuits optimized using the techniques proposed in this disclosure with other approaches show that the proposed techniques generally find smaller circuits in less time. Furthermore, the techniques proposed in this disclosure are used for the automated optimization of quantum circuits with continuous parameters.

[0021] (Overall consideration) This disclosure addresses the problem of efficiently optimizing large-scale quantum circuits, i.e., quantum circuits that emerge in quantum computing beyond the reach of classical computers. This disclosure describes two optimization approaches for light and heavy optimization algorithms (e.g., light and heavy versions of an optimizer) that can be implemented and run as software solutions (e.g., offline solutions to optimizing large-scale quantum circuits). These algorithms are based on a selected sequence of basic optimizations, yet they achieve significant gate count reductions and improvements over more mathematically sophisticated approaches, such as T-par optimization (described in more detail below). The simplicity of the approach is reflected in very fast runtimes, especially by using the light version of the optimizer.

[0022] A heavy version of this optimizer demonstrates that it is possible to optimize larger circuits. To further improve the output, we include some Hadamard gates, possibly including CNOT and R gates. Z By implementing a more extensive (and therefore computationally more demanding) algorithm for constructing gate stages, R ZIt is possible to modify the routine to reduce the count of . Another idea is to incorporate template-based peephole optimization into the algorithm described herein. Another idea is to extend the set of subcircuit rewriting rules (described in more detail below) and examine the performance of the approach on other benchmark circuits. Finally, examining the relative costs of various resources (e.g., various gates, auxiliary qubits) could lead to optimizations that favorably trade off these resources.

[0023] (method) Details regarding the various optimization algorithms proposed in this disclosure and their implementations are provided below. Throughout this disclosure, the term g is used to denote the number of gates that appear in a circuit. The Background section below provides definitions of notations used throughout this disclosure. The section titled Quantum Circuit Representations describes three separate representations of quantum circuits that can be used in conjunction with the techniques described herein. The section titled Preprocessing describes preprocessing steps that can be used in conjunction with the various optimization algorithms described herein. The section titled Optimization Subroutines describes several subroutines that form the basic building blocks of the approach proposed in this disclosure. Furthermore, the section titled General-Purpose Optimization Algorithms describes how these subroutines can be combined to form various versions of the optimization algorithm. Finally, the section titled Special-Purpose Optimization presents two special-purpose optimization techniques that can be used to address specific types of circuits.

[0024] (background) A quantum circuit is a series of quantum gates that operate on a collection of qubits. Quantum circuits are conveniently represented by diagrams in which horizontal wires indicate the time evolution of the qubits, time propagating from left to right, and boxes (or other symbols attached to the wires) represent quantum gates. For example, diagram 100 in Figure 1 represents a simple three-qubit quantum circuit. The circuit in diagram 100 consists of two single-qubit z-rotation gates (110a, 110b), R Z(θ) and R Z (θ′), two single-qubit Hadamard gates (120a, 120b) H, and four two-qubit controlled-NOT gates (130a, 130b, 130c, and 130d) CNOT.

[0025] A simple set of elementary gates for quantum circuits can be considered to consist of a two-qubit CNOT, as well as a single-qubit NOT gate, a single-qubit Hadamard gate, and a single-qubit z-rotate gate, as shown in the circuits in diagram 100. The unitary matrices for these types of gates have expressions of the form

number

[0026] The techniques described herein are Z Although we present primarily quantum circuits with sets of , NOT, and CNOT gates, we can also consider input circuits that can include Toffoli gates. A Toffoli gate (e.g., gate 1010a in diagram 1000 of FIG. 10) is a computation-based state

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[0027] The cost of implementing a given quantum circuit depends on the physical system used to implement it. For example, different cost considerations will be applied depending on whether the physical system is based on superconducting circuits or trapped atomic ions. This cost can also vary significantly between physical-level (unprotected) and logical-level (fault-tolerant) implementations. At the physical level, two-qubit gates are typically more expensive to implement than single-qubit gates. The techniques described herein address this by considering CNOT gate count and optimizing the number of CNOT gates in an optimization algorithm.

[0028] For logical-level fault-tolerant circuits, so-called Clifford operations (generated by Hadamard, topological, and CNOT gates) are often relatively easy to implement, while non-Clifford operations can require significant overhead. Thus, in our optimization algorithm, R Z The number of gates is also considered and attempts are made to optimize their count. Z Gates are typically approximated by a set of discrete gates consisting of Clifford and T gates. Optimal algorithms are known for generating such approximations. Z The number of Clifford+T gates required to approximate a gate depends primarily on the desired accuracy, rather than the specific angle of rotation, and therefore on the R Z It is advisable to optimize the circuit before approximating the gates with Clifford+T fault-tolerant circuits.

[0029] CNOT and R Z By minimizing the count of R, it is possible to optimize for both physical and logical levels of implementation. Trade-offs between these two goals may be expected, and there are instances where such trade-offs have been made. However, the techniques described herein do not rely on the Z Optimization aimed at counting only both CNOT and CNOT is considered.

[0030] (Quantum circuit representation) The following three representations of quantum circuits can be used in conjunction with the optimization techniques or algorithms described herein:

[0031] First, a circuit can be stored as a list of gates to be applied sequentially (a netlist). In some cases, it is convenient to specify a circuit in terms of subroutines (e.g., circuit subroutines), which can be represented as blocks. Each block can be repeated any number of times and can be applied to any subset of the qubits present in the circuit. Representation using blocks can be particularly concise, as many quantum circuits exhibit a significant number of repetitions. A block is specified as a list of gates and qubit addresses.

[0032] Netlist representations can be input and output using the format produced by Quipper, a quantum programming language used to specify several benchmark circuits. This format includes functionality for manipulating blocks. Other quantum programming languages ​​and / or formats with the same functionality can also be used.

[0033] Second, a directed acyclic graph (DAG) representation can be used. The vertices of the DAG are the gates of the circuit, and the edges encode their input / output relationships. The DAG representation has the advantage of making it easy to access the adjacencies between gates.

[0034] Third, a generalization of the topological polynomial representation of {NOT, CNOT, T} circuits can also be used. Unlike the netlist and DAG representations, this last representation is not limited to NOT, CNOT, and R. Z This applies to circuits consisting only of gates. Such circuits can be concisely expressed as a set of linear Boolean transformations and diagonal phase transformations. For example, if C is a set of CNOT gates and R gates, Z (θ1), R Z (θ2), …, R Z (θ i ) is a circuit consisting of only n-qubit-based states |x1,x2,…,x n The action of C on 〉 is an expression of the form:

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[0035] It is possible to convert between any two of the three circuit representations above linearly in time with the number of gates in the circuit. Given a netlist, it is possible to create a corresponding DAG for each gate. Conversely, it is also possible to convert a DAG to a netlist by standard topological classification. Z}Conversion to and from a topological polynomial representation of a circuit is possible, for example, by using a straightforward generalization described in connection with meet-in-the-middle algorithms used for fast synthesis of depth-optimal quantum circuits.

[0036] (Pretreatment) Before executing the main optimization procedure (e.g., optimization algorithm), the circuit can be preprocessed to make it amenable to further optimization. The optimizer supports H and R gates in addition to NOT, CNOT, and Toffoli gates. Z Since it can handle (θ) gates, this preprocessing can handle NOT, CNOT, Toffoli, H, and / or R ZThis can be applied to input circuits consisting of (θ) gates. Some examples are the benchmarks for Kuiper adder circuits and T-par circuits, which are described in more detail below. For example, a NOT gate can be pushed as far right as possible by swapping them through the Toffoli gate control and the target of the Toffoli gate and CNOT gate. When a NOT gate is pushed through a Toffoli gate control, its control becomes negated (or, if it was originally negated, its negation is removed). If this procedure extends to a pair of adjacent NOT gates, the NOT gate can be removed from the circuit. If no such cancellation is found, the change in control negation can be reversed, and the NOT gate can be returned to its original position. Furthermore, this transposition relationship between a NOT gate and an H gate is such that a NOT followed by an H is followed by a Z gate, and a Z gate is followed by an R gate. Z (θ=π). Also, R Z NOT followed by (θ) is R followed by NOT Z (-θ). Therefore, NOT, CNOT, Toffoli, H, and R Z For a standard set of gates consisting of gates, CNOT and R Z As part of the preprocessing step, the NOT gates can be moved to the beginning or end of a given circuit, with further details explained below relating to reducing all affine functions of phase to linear functions by using propagation of NOT through the gates.

[0037] This NOT gate propagation takes advantage of two aspects of the proposed optimizer or optimization algorithm. First, it accepts Toffoli gates that may have negation controls, and as explained in more detail below, it also uses the T / T † By taking advantage of the freedom of polarity selection, it is possible to optimize the decomposition of the gate into a Clifford + T circuit. Secondly, the cancellation of the NOT gate is achieved by modifying the phase polynomial expression (the function f in the phase polynomial expression (Equation 3)). iSince this simplifies (by making part of ) linear instead of the original affine, such a cancellation makes subroutines 4 and 5, described below, more likely to find an optimization (since these subroutines rely on finding matching terms in the phase polynomial representation).

[0038] The complexity of this preprocessing step is O(g) since this step only makes a single pass through the circuit.

[0039] (optimization subroutine) The optimization algorithm of this disclosure relies on various subroutines, which are described in more detail below. For each item, the worst-case time complexity is reported as a function of the number of gates g in the circuit (for simplicity, dependence on the number of qubits and other parameters is ignored). However, in practice, the runtime of the software can be optimized by carefully ordering and constraining these subroutines, as described further below.

[0040] (Subroutine 1: Hadamard gate reduction) Hadamard gates do not participate in phase polynomial optimization (subroutines 4 and 5, below) and tend to discourage gate replacement. Thus, circuit identities or rules depicted in diagram 300 of FIG. 3 are used to reduce the count of Hadamard gates. These identities or rules include rules 310a and 310b at the bottom of diagram 300 and rules 320a, 320b, and 320c at the top of diagram 300. Rules 310a and 310b are applicable even if the middle CNOT is randomly replaced with a circuit comprising many CNOT gates, all of which share the target of the original CNOT gate.

[0041] The application of each of these rules reduces the count of H by an upper bound of 4. For a given Hadamard gate, it is possible to periodically check whether it fits one of these circuit identities using the DAG representation. Thus, it is possible to implement this subroutine with complexity O(g) by making a single pass through all the Hadamard gates in the circuit.

[0042] (Subroutine 2: Cancellation of single-qubit gates) In general, the DAG representation of a quantum circuit is used to directly determine whether a gate and its inverse are adjacent. If so, it is possible to remove both gates to reduce the gate count. More generally, two single-qubit gates U and U are separated by a subcircuit A that commutes with gate U. † In general, determining whether a gate U commutes with a circuit A can be computationally intensive. Instead, it is possible to apply a specific set of rules that provide conditions for sufficient (but not necessary) transformations. This approach is fast and appears to find many possible transformations that can be used to simplify quantum circuits.

[0043] Specifically, for each gate U in the circuit, the optimizer or optimization algorithm calculates U † To do this, the approach is to repeatedly check whether U commutes through a set of successive gates, as demonstrated by one of the patterns in diagram 400 of Figure 4. Diagram 400 shows that R Z The rules include repositioning rules such as the upper rules 410a, 410b, and 410c for repositioning gates to the right, and rules 420a, 420b, and 420c for repositioning CNOT gates to the right. If at any stage U cannot be moved to the right due to the allowed communication patterns, then there is a U that matches U. †cannot be offset with U and the original configuration is restored. † will be successful. The transposition scheme described above need not only be applied in a specific direction to the right, but may also be applied in a specific direction to the left.

[0044] For each of the g gates U, the subroutine checks whether it commutes with the successor position through O(g). Thus, the complexity of the overall gate cancellation rule is O(g 2 ) This complexity could be made linear in g by considering only transpositions through a fixed number of subsequent gates, but in practice this has proven unnecessary.

[0045] With a slight variation of this subroutine, it is possible to merge rotation gates rather than cancelling opposing gates. Specifically, two rotation R Z (θ1) and R Z (θ2)) into a single rotation R Z By combining it with (θ1+θ2), one RZ gate can be eliminated.

[0046] (Subroutine 3: Cancellation of two-qubit gates) This subroutine is similar to subroutine 2, except that U is a two-qubit gate, and in the considered circuit, these gates are general CNOTs. Similarly, the complexity of this subroutine is O(g 2 ), but can be reduced to O(g) by forcing subcircuit A to take on a maximum size.

[0047] (Subroutine 4: Rotation and merging using phase polynomials) In this case, NOT, CNOT, and R Z Consider a subcircuit consisting of gates whose two distinct terms of the phase polynomial are:

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[0048] In other words, this phase polynomial representation of the circuit is the sum of two rotations, in this case R Z (θ1) and R Z (θ4) are applied to the same affine function at the input, even though they appear in different parts of the circuit. These rotations can then be combined into a single rotation, improving the circuit. In this particular example, the simplification could alternatively be achieved using the transposition technique described above, although this is not generally applicable. There is flexibility to place the combining rotation at any point in the circuit where the associated affine function appears. Specifically, the combining rotation is placed in the place of the first (leftmost) such rotation.

[0049] To apply subroutine 4, the subcircuit must be {NOT, CNOT, R Z} gates. This subcircuit is constructed one qubit at a time, starting with a given CNOT gate. For the first qubit in this gate, we use the DAG representation to find all preceding and succeeding NOT, CNOT, and R gates that operate on this qubit. ZA scan is performed through the gates and they are added to the subcircuit. If a Hadamard gate is encountered at the beginning or end of the circuit, its endpoint is marked and the search in that direction is stopped (so that each qubit has one beginning and one ending endpoint). For each CNOT gate between this qubit and any qubit not yet encountered, the anchor point at which that gate will act on the newly encountered qubit is marked. This process is performed for the second qubit acted upon by the first CNOT gate, and the process is repeated, starting from every anchor point, until no new qubits are encountered.

[0050] The resulting subcircuits are NOT, CNOT, and R Z Although the netlist consists solely of gates, this may not have a polynomial topological representation; in particular, intermediate Hadamard gates on wires exiting and re-entering the subcircuit can prevent this. In order to apply the topological polynomial format, it is necessary to use the following pruning procedure to prevent this from happening: Starting with a given initial CNOT gate, both the gates before and after it in the netlist are considered successively until an endpoint is encountered. Note that any NOT and R gates reached in this process are Z Only CNOT gates need be considered, since gates can be included without preventing the phase polynomial from being applied. This procedure may continue if both the control and target qubits of the CNOT gate encountered are within the edge boundary. If the control qubit is outside the edge boundary but the target qubit is inside, the edge point of the target qubit is moved so that the CNOT gate under test is outside the boundary and the gate and any subsequent gates acting on that target qubit are excluded from the subcircuit. On the other hand, if the control is inside the boundary and the target is outside, an exception is made and the edge points are not moved (even though the CNOT gate is not included in the subcircuit). This exception is made by using a larger {NOT,CNOT,R} that fits the phase polynomial representation, as shown in diagram 600 of FIG. 6. Z} subcircuit.

[0051] In the example specified for the circuit in diagram 600, one can start the search from the first CNOT gate (e.g., CNOT gate 630a) acting on the top (q1) and middle (q2) qubits. Going left from q1, one finds an H gate (e.g., 620a), which marks the end point. Going right from q1, two CNOT gates (e.g., CNOT gates 630b and 630c) are found, which leads to one R Z Gates (e.g., R Z A CNOT gate (e.g., gate 610a) is found, and then an H gate (e.g., H gate 620b) is found, where the endpoints are marked. None of the CNOT gates encountered connects q1 or q2 to the remaining qubit q3. The same procedure is repeated on q2 from the original CNOT gate (e.g., CNOT gate 630a). On the left, R Z If the gate (e.g., R Z 6. Continuing to the right, a CNOT gate (e.g., CNOT gate 610b) is found, followed by an H gate (e.g., H gate 620c), where an endpoint is marked. Continuing to the right, a CNOT gate (e.g., CNOT gate 630d) acting on q2 and q3 is found. This CNOT gate exhibits an additional connection, and therefore an anchor point is marked at q3 on the q3 (target) side of this CNOT gate. Further to the right on the q2 wire are three CNOT gates (e.g., CNOT gates 630b, 630e, and 630c), none of which exhibit an additional connection, and an R Z Gates (e.g., R Z qubit 610c) and finally an H gate (e.g., H gate 620d), where an endpoint is marked. The next q3 is explored starting from the aforementioned anchor point. Going left, an H gate (e.g., H gate 620e) with no further connections to other qubits is found, and an endpoint is marked. Going right, an H gate (e.g., H gate 620f) is found immediately, and an endpoint is marked.

[0052] Once the subcircuit is constructed, it then examines the netlist representation and prunes it. In this path, a fourth CNOT gate operating on q2 and q3 is encountered (e.g., CNOT gate 630e), whose control is within the bounds of the subcircuit but whose target is outside. In this case, the exception handling described in this pruning procedure applies. This is because the {NOT, CNOT, R Z} ensure that the last CNOT gate in the region is included, but the fourth CNOT gate is excluded (as indicated by the dotted border in diagram 600). Thus, the last R Z The gate can be relocated to the right of the first, leftmost H on the q2 line of the circuit, and as will be explained in more detail below, Z This allows for a topological polynomial based on the merging of

[0053] Valid {NOT, CNOT, R Z Once the subcircuits have been identified, the phase polynomials for the subcircuits can be generated. Z For each gate, it is possible to determine the associated affine function to which the topology applies, and the position in the circuit to which each gate applies. The list of recorded affine functions is then sorted. Finally, all R Z Find and merge gate repetitions, and merge the merged R Z can be placed in the first position in the subcircuit that computes the desired linear function.

[0054] This procedure considers O(g) subcircuits, and the cost of processing each of them is dominated by a classification task with complexity O(g log g), imposing an overall complexity of O(g log g) on ​​subroutine 4. However, in practice, these subcircuits are usually smaller the more subcircuits considered, and therefore the actual complexity is lower. Furthermore, {NOT, CNOT, R Z In identifying a subcircuit, the process typically involves identifying any previously identified {NOT, CNOT, R Z} We start with CNOT gates that are not already contained in any subcircuit, so the number of subcircuits can in practice be much smaller than g. If desired, the overall complexity can be reduced to O(g) by limiting the maximum size of the subcircuits.

[0055] As a final step, it is possible to reduce all affine functions of the phase to linear functions, which are:

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[0056] Applying this procedure, each affine function

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number

[0057] (Subroutine 5: Floating R Z gate) In subroutine 4, R Z We traced the affine functions associated with the gates. More generally, R Z All affine functions occurring in the subcircuit, regardless of the presence of gates, and their respective positions were recorded. Z The gate is not already in the circuit, and R Z It is possible to identify all possible positions where the gate can be placed. This "floating" R Z Three optimization sub-subroutines can be used in constructing gate configurations: two-qubit gate cancellation, gate-count-preserving rewrite rule, and gate-count-reducing rewrite rule.

[0058] The first of these sub-subroutines is R Z This is essentially the same as Subroutine 4, except that the gates are floating and the focus is on the specific subcircuit being identified. This approach is similar to R Z The gate is then passed through all possible R Z By knowing the location of the gate, various R Z It allows you to place gates. Z If two CNOT gates can be canceled out without placing a gate, then the position is R Z It is removed from the list of possible gate locations and a CNOT cancellation is performed instead.

[0059] The following gate count-preserving rewrite rules (see, for example, diagram 700 in FIG. 7) are applied in an attempt to find further optimizations. For example, diagram 700 includes gate count-preserving rules 710a and 710b. These replacements do not remove gates, but modify the circuit to allow optimizations elsewhere. These rewrite rules are provided by external library files, and subcircuits are identified using a DAG representation to which the rules can be applied. These replacements are made because they are based on the floating R Z These rewrite rules are applied only if they lead to a reduction in the two-qubit gate count through another round of the two-qubit cancellation subroutine by gate. Note that these rewrite rules are applied only if they lead to a reduction in the two-qubit gate count through another round of the two-qubit cancellation subroutine by gate. Z This subroutine is applicable to floating R gates only. Z Using gates, R leads to a reduction in gate count Z Select these combinations of gate locations.

[0060] The final sub-subroutine applies rewrite rules that reduce gate count (see, for example, diagram 800 in FIG. 8 for the gate count reduction rewrite rules used in Subroutine 5). Diagram 800 includes gate count reduction rewrite rules 810a, 810b, 810c, 810d, and 810e. These rules may also be provided via an external library file. Because these rules themselves reduce gate count, this rewrite is generally performed whenever a suitable pattern is found. The complexity of this three-step subroutine (i.e., the three optimization sub-subroutines in Subroutine 5) is O(g) for the number of subcircuits, and within each subcircuit, the two-qubit cancellation (Subroutine 3) is O(g 2 ), so the upper bound is O(g 3 ). These rewrite rules (e.g., the gate-count-preserving rewrite rule in Figure 7 and the gate-count-reducing rewrite rule in Figure 8) can be applied with complexity O(g) because a single pass through the gates in the circuit, as in subroutine 1, is sufficient. Again, in practice, the number of subcircuits and their size are usually inversely related, which reduces the observed complexity by a factor of about g. This complexity can be reduced by limiting the maximum size of a subcircuit to O(g 2 ) In practice, this complexity can be further reduced to O(g log g) by limiting the maximum size of subcircuit A in canceling two-qubit gates (the sorting task would still have complexity O(g log g)).

[0061] To illustrate an example of how this optimization works, consider the right-hand circuit in diagram 500 of FIG. Z Observe that (θ2) (e.g., gate 510a) can be implemented in the final part of the circuit of the upper qubit to allow the cancellation of the first two CNOTs, leading to the optimized circuit shown on the right-hand side in diagram 900 of FIG. 9, which is a three R ZIt is further simplified by including gates 910a, 910b, and 910c and a single CNOT gate 930a.

[0062] (general purpose optimization algorithm) The optimization algorithm or technique described in this disclosure simply applies the various subroutines described above in a carefully selected order. There are two versions of the optimizer or optimization algorithm, referred to as the light version (or simply light) and the heavy version (or simply heavy). In general, the heavy version applies more subroutines and produces better optimization results at the expense of longer runtime. A preprocessing step can be used in both the light and heavy versions of the optimizer.

[0063] A lightweight version of the optimizer applies the optimization subroutines in the following sequence or order: 1, 3, 2, 3, 1, 2, 4, 3, 2.

[0064] This sequence is then repeated until no further optimization is achieved. The sequence begins with a Hadamard gate reduction {CNOT, R Z Based at least in part on the principle of exposing gates (subroutine 1), cancellation routines allow for larger reductions (subroutines 3, 2, 3), in particular freeing up two CNOT gates to facilitate reduction of single-qubit gates, and vice versa. After the first four optimization subroutines, further reductions can be enabled by applying a replacement rule (subroutine 1). Further single-qubit cancellations and mergers are then explored (subroutine 2). This allows for further R Z {NOT, CNOT, R} to find count optimizations Z} This allows for quicker identification of subcircuit regions (subroutine 4), after which the process checks for remaining gate cancellations (subroutines 3, 2).

[0065] A heavy version of the optimizer applies the following sequence or order: 1, 3, 2, 3, 1, 2, 5.

[0066] Similarly, this sequence is repeated until no further optimization is achieved. The first six steps of this optimization sequence for the heavy version of the optimizer are the same as those for the light version of the optimizer. The difference is that in the heavy version of the optimizer, the approach used is a floating R Z Utilizing gates (subroutine 5) allows further reduction of CNOT gates, including using gate count preserving rewrite rules to expose further gate cancellations and gate count reducing rewrite rules to remove any remaining inefficiencies. Z The purpose is to enable location discovery relative to the gate.

[0067] The orders or sequences described above are presented for illustrative purposes; other orders or sequences involving fewer or more subroutines than those described above may be used as well.

[0068] Note that the computational overhead incurred by transforming the circuit representation is often negligible. All transformations can be performed in time proportional to the size of the circuit (see, for example, the section entitled Representing Quantum Circuits for details). The representations need only be consistent as needed. In subroutines 1 through 3, the DAG representation can be used to access individual gates for rapid reduction identification. This allows only the DAG representation to be updated to record gate count reductions before continuing the optimization process. In subroutines 4 and 5, both representations can be updated simultaneously and dynamically whenever a reduction is identified, maintaining the consistency of both the DAG and netlist representations. This is useful because both routines identify subcircuits suitable for reduction using a topological polynomial representation. This identification process requires an up-to-date DAG representation, and generating a topological polynomial representation requires an up-to-date netlist representation. Note that the topological polynomial representation is used only to assist optimization within the identified subcircuit; there is no need to convert the topological polynomial representation back to either a netlist or a DAG. This phase polynomial representation may then be safely purged when the corresponding subcircuit optimization process is complete.

[0069] (Special purpose optimization) In addition to the general purpose optimizers (eg, general purpose optimization algorithms) mentioned above, two specialized optimizations can be used to improve circuits with specific structures.

[0070] LCR Optimizer: Some quantum algorithms, such as the product formula simulation algorithm, involve multiple repetitions of certain blocks. To optimize such a circuit, it may be best to first run an optimizer on a single block to obtain an optimized version of it, O. To find simplifications across multiple blocks, we first run an optimizer on the circuit O. 2 can be optimized, and the result can be called LR, where L is O 2The next step is to optimize O 3 This is an optimization of O under the condition that the optimization is performed near the boundary between blocks. 3 It is possible to remove the prefix L and suffix R from an optimized version of O, and call the remaining circuit C. If such an L, C, and R are discoverable (which is possible in practice), then O t LC t-2 It can be simplified to R.

[0071] Toffoli Decomposition: Many quantum algorithms are naturally explained using Toffoli gates. The optimizer or optimization algorithm described in this disclosure is able to handle Toffoli gates with both positive and negative control. The goal is to find a set of gates {NOT, CNOT, H, R Z}, the Toffoli gates are decomposed in terms of these elementary gates. The techniques described herein take advantage of various ways of doing this to improve the quality of the optimization.

[0072] Specifically, the Toffoli gate can be extended to include related one-qubit and two-qubit gates using the features shown in diagram 1000 of FIG. 10, whose circuit decompositions include T and T (because the Toffoli gate is self-inverting). † Keep in mind that it is also possible to obtain the desired Toffoli gate by exchanging T / T. As previously mentioned, the features in diagram 1000 include Toffoli gate 1010a, Toffoli gate 1010b with a negation control on top, and Toffoli gate 1010c where both are negation controls. The optimizer initially considers, in each Toffoli decomposition, † The polarity of (i.e., the choice of which gate contains the dagger and which does not) is left undetermined. The optimizer then selects the undetermined T and T † Gates are manipulated symbolically by simply moving their positions within a given quantum circuit while preserving their relative polarities. This optimization is performed on these undetermined T and T †It is considered complete when the gate count can no longer be reduced by moving gates. Finally, the polarity of each Toffoli gate can be chosen (subject to a fixed relationship between them) with the goal of minimizing the T count in the optimized circuit. This minimization is done in a greedy way, and the associated T / T count in the nearly optimized circuit is † The polarity for each Toffoli gate is chosen so that the count of T is reduced as much as possible in the order of appearance of the gates.

[0073] Overall, this polarity selection process takes O(g) time. After selecting the polarity, it is possible to execute subroutine 3 and subroutine 2, since a particular polarity selection may lead to additional cancellations of CNOT gates and single-qubit gates that would not otherwise be possible due to the presence of undetermined gates that would have blocked the desired position transposition.

[0074] (Optimization result) Example implementations of aspects of the optimizer or optimization algorithms described herein were written using the Fortran programming language and tested using three sets of benchmark circuits. All results presented in this disclosure were obtained using a machine with a 2.9 GHz Intel Core i5 processor and 8 GB of 1867 MHz DDDR4 memory, running OS X 10.1 Capitan. Of course, these results are presented for illustrative purposes to show relative performance, and these results may vary when run using different hardware configurations.

[0075] As part of the testing, we considered various quantum circuits, including components of Shor's integer factorization algorithm, specifically the quantum Fourier transform (QFT) and integer addition circuits. We also considered quantum circuits for the product formula (PF) approach to Hamiltonian simulation. In both cases, the focus of the testing was on quantum circuits of sizes that could potentially be useful in applications beyond classical computation, and experiments were performed with various types of addition circuits and product formulas. Finally, we also considered a set of benchmark quantum circuits consisting of various arithmetic circuits (including a family of Galois field multiplication circuits) and implementations of multiply controlled Toffoli gates. For comparison, data files describing these circuits before and after optimization are available.

[0076] The accuracy of the optimizer or optimization algorithm was checked by verifying the functional equivalence (i.e., the equality of the corresponding unitary matrices) of various test circuits before and after optimization. Such tests are generally feasible for circuits using a small number of qubits. These tests were performed on all 8-qubit benchmarks in Table 1 shown in diagram 1300 of FIG. 13 and Table 2 shown in diagram 1400 of FIG. 14. Table 1 includes a light optimization of the adder circuit, with results for an in-place adder circuit based on QFT (or QFA) in the upper row and results for the Kuiper library adder circuit in the lower row. These tests were also performed on all 10-qubit benchmarks in Tables 3A and 3B shown in diagrams 1600a and 1600b of FIGS. 16A and 16B, respectively. Table 3A shows the optimization of the product formula algorithm by reducing the number of CNOT gates, and Table 3B shows the optimization of the R ZOptimization of the product formula algorithm by gate count reduction is shown. Software runtimes range from 0.004 seconds (first order, n=10) to 0.137 seconds (sixth order, n=100). Clifford gate reduction ranges from 62.5% for Hadamard and 75% for phase gates (for first order formulas, regardless of n) to 75% for Hadamard and 85% for phase gates (for sixth order formulas, also regardless of n). The symbol "(×1000)" indicates that the gate count for first order formulas is in thousands (without roundoff error). The symbol "(L)" indicates the standard mild version of the optimization described above.

[0077] Furthermore, Tables 4A to 4C shown in charts 1700a to 1700c of FIGS. 17A to 17C show the performance of the following benchmarks: Mod54, VBE-Adder3, CSLA-MUX3, RC-Adder6, Mod-Red 21 , Mod-Mult 55 , Toff-Barenco 3..5 , Toff-NC 3..5 , GF(2 4 )-Mult, and GF(2 5 )-Mult. For example, Tables 4A-4C include a comparison with T-par (discussed in more detail below), and the algorithm names for these benchmarks are well-known, except that Toff-Barenco and Toff-NC are used to indicate the implementation of the multiplication-controlled Toffoli gate. The symbol "(L)" indicates the standard light version of the optimization, while the symbol "(H)" indicates the standard heavy version of the optimization. The symbol -||- indicates no improvement in the heavy version of the optimization over the light version of the optimization.

[0078] (QFT and adder circuits) QFT is a fundamental subroutine in quantum computing and appears in many quantum algorithms due to its exponential speedup. The standard circuit for an exact n-qubit QFT is R ZIt uses gates, some of which have angles exponentially smaller than n. It is well known that high-precision approximate QFTs can be performed by omitting gates with very small rotation angles. For the purposes of the optimizer or optimization algorithm of this disclosure, the maximum rotation angle is π / 2. 13 Rotations up to an angle of 0.001 can be omitted, ensuring a sufficiently accurate approximate QFT for quantum circuits of size below the target. These small rotations are removed before optimization, as their omission does not contribute to the improvement reported in the results.

[0079] The chart shown in diagram 1100 of FIG. 11 shows the gate counts for the Approximate Quantum Fourier Transform (QFT, inset), the Kuiper Library adder, and the Fourier-based adder (QFA). The white / black symbols represent the gate counts before / after optimization, and the square / circle / triangle symbols represent the gate counts for the Kuiper Library adder / QFA / QFT, respectively. A savings rate of over 36% is observed for QFTs with 512 or more qubits. This optimization is primarily due to the R, which is the most expensive resource for fault-tolerant implementations. Z This comes from a reduction in the number of gates.

[0080] As shown in the chart in diagram 1100 of FIG. 11, there are two types of integer addition circuits: in-place modulo 2 as implemented in the Kuiper library. q We considered an addition circuit and an in-place addition circuit based on QFT (or QFA). As mentioned above, the QFA circuit has a π / 2 13We use an approximate QFT in which rotations by smaller angles are removed. Adder circuits are a fundamental component of Shor's quantum algorithm for integer factorization. The results presented report gate counts before and after optimization for the Kuiper adder circuit and for QFA of circuits operating on 2L qubits, where L ranges from 4 to 11. For example, Shor's integer factorization algorithm for factoring 1,024-bit numbers uses an adder circuit with L=10. The related challenge to RSA-1024 has not yet been solved.

[0081] The results of a light optimization of the adder circuit are shown in Figures 11 and 13. For the Kuiper library adder circuit, the full Light optimizer was used. For the QFA optimization, a modified Light optimizer was used instead, which omitted the last three subroutines 4, 3, 2 of the standard Light optimizer and had the subroutine sequence 1, 3, 2, 3, 1, 2. This was done when no further gate savings were found from those subroutines in small instances (n < 256).

[0082] The simplified Kuiper library adder circuit outperforms QFA by a large margin, suggesting that it may be preferred in practice. A reduction in the T-gate count of up to 5.2 times was observed for this Kuiper library adder circuit. This reduction was obtained entirely by automated means (i.e., by an optimization algorithm) without any prior knowledge of the circuit structure. Because Shor's integer factorization algorithm is dominated by the cost of modular exponentiation, which in turn relies primarily on integer addition, this optimization reduces the cost of running the global factorization algorithm by more than 5 times.

[0083] The heavy optimizer was also applied to the QFT and adder circuits. For the QFT and QFA circuits, the heavy setting did not improve the gate count. The results of the heavy optimization for the Quipper adder circuit are shown in Table 2 in Figure 14. The CNOT count reduction was found to be 2.7 times, compared to only 1.7 times with light optimization. The chart in Figure 1200 of Figure 12 shows the total CNOT count of the Quipper library adder circuit before optimization (e.g., pre-optimization), after light optimization, and after heavy optimization, illustrating the CNOT count reduction with these two types of optimization. The white / dot pattern / black square symbols represent the gate count with pre-optimization / post-light optimization / post-heavy optimization, respectively. Quantum Simulation

[0084] The first explicit polynomial-time quantum algorithms for simulating Hamiltonian dynamics were introduced, and the approach was later generalized to higher-order product formulas (PFs), resulting in improved asymptotic complexity. This disclosure reports gate counts before and after optimization for PF algorithms of orders 1, 2, 4, and 6 (for orders higher than 1, the order of the standard Suzuki product formula construction is even). Specifically, these algorithms were implemented for a one-dimensional Heisenberg model in a magnetic field with periodic boundary conditions, evolving the system for a time proportional to its size, and the parameters of the algorithms were chosen to guarantee a Hamiltonian simulation error of at most 10-3, using known bounds on the error of the product formula approximation.

[0085] The results of light optimization of the product formula algorithms are reported in Tables 3A and 3B (e.g., in Figures 16A and 16B) and illustrated in the chart in diagram 1500 of Figure 15. The white / black symbols in this figure represent the gate count before / after optimization, respectively, and the square / circle symbols represent the gate count for second / fourth order. For these product formula algorithms, heavy optimization did not show any further improvement over light optimization. The second, fourth, and sixth order algorithms showed an approximately 33.3% reduction in CNOT count, R Z A reduction of approximately 28.5% in counts is observed, roughly corresponding to the reduction associated with the physical and logical level implementation. The first order formal algorithms are CNOT or R Z No gate optimization was demonstrated. In all product formula algorithms, the number of phase gates and Hadamard gates was significantly reduced, roughly by a factor of 3 to 6.

[0086] (Compared to other approaches) Quantum circuit optimization is a well-known field. However, previous work on circuit optimization has not considered large-scale quantum circuits of the type considered in this disclosure that can outperform classical computers. For example, Amy, Maslov, and Mosca ("Polynomial-time T-depth optimization of Clifford +T circuits via matroid partitioning," IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 33, pp. 1476-1489 (2014)) reported that the complexity of optimizing a g gate circuit is O(g 3), making the optimization of large-scale circuits impractical. While examples of execution times ranging from 0.07 to 1.883 seconds for qubit counts n = 10 to 35 and gate counts 60 to 368 exist, the optimization algorithm described herein performed in a similar time range when optimizing a Quipper adder circuit with approximately 23,000 gates up to the upper limit of n = 256, as shown in Table 1 (Figure 13). Other examples of quantum circuit optimization are based on peep-hole optimization using optimal gate libraries, but this is expensive and can take longer than 100 seconds for a 20-qubit, 1,000-gate circuit.

[0087] To compare the results generated using the optimization algorithm proposed in this disclosure with previously reported results, we considered weighted combinations of T and CNOT counts. While T-gates can be significantly more expensive to implement fault-tolerantly using state distillation, ignoring the cost of CNOT gates may lead to significant underestimation. Analysis suggests that fault-tolerant T-gates can be 46-350 times more expensive to implement than locally fault-tolerant CNOT gates, with at least one recommendation for a cost ratio of 1:50. The actual overhead depends on many details, including the fault-tolerance scheme, error model, size of computation, architectural limitations, the degree to which the T-gate implementation can be optimized, and whether T-state generation can be done offline so that its cost can be (partially) discounted. One approach for a rough comparison is to work around a total cost metric defined as #T+0.01·log n·#CNOT, where #T is the number of T gates used, 0.01 is the relative efficiency ratio of CNOT gates to T gates, n is the number of qubits in the computation, and #CNOT is the number of CNOT gates used. In this formula, the factor of log n underestimates the typical cost of implementing gates between qubits in realistic architectures (the actual cost is 100 sq ft in three dimensions). 3 (It may be √n, or closer to √n in two dimensions. Because the approach described herein preserves the structure of the original circuit, this metric should provide a conservative comparison to other approaches (such as the T-par approach described below) that may introduce long-range gates. Therefore, demonstrating this total cost advantage provides a rough demonstration of the merit of the proposed optimization techniques described in this disclosure.

[0088] Results using the techniques described in this disclosure can be directly compared to those reported by Amy, Maslov, and Mosca, who aimed to reduce the count of T and the depth of T using a technique based on matroid partitioning, an approach referred to in this disclosure as T-par. Results from using the techniques described in this disclosure were used to optimize a set of benchmarks that appeared in the above paper, and the results were compared to the T-par optimization, as shown in Tables 4A-4C (Figures 17A-17C).

[0089] These benchmark circuits are divided into three categories. The first set (Table 4A in Figure 17A) consists of a selection of arithmetic operations. For these circuits, we obtained better or matching T counts compared to the benchmarks, while also obtaining fairly good CNOT counts. Note that the circuit CSLA-MUX3 was excluded from the comparison because T-par was believed to optimize it incorrectly. To illustrate the benefits of the optimization techniques described herein, using the aggregate cost metric mentioned above, the proposed technique reduced the cost of the RC-Adder6 circuit from 71.91 to 49.70. The cost improvement, therefore, was approximately 31%, mostly attributable to the reduced T-gate count.

[0090] The second set of benchmarks consists of multiplication-controlled Toffoli gates (Table 4B in Figure 17B). The proposed optimizer is comparable to the T-count obtained by the T-par optimizer and significantly reduces the CNOT count, but neither the proposed optimizer nor previous approaches were able to find the best-known implementation. This is not surprising, given that the best-known implementation uses a very different circuit structure.

[0091] The third set of benchmarks involves Galois field multiplication circuits (Table 4C in Figure 17C). In one example, the heavy optimizer was terminated when its runtime exceeded 200 times the runtime of the light optimizer. Such a timeout occurred when applying the heavy optimizer to the four largest instances of a Galois field multiplication circuit. In the tested case, the heavy optimizer offered no advantage over the light optimizer, and therefore was not applied to the four largest instances (the corresponding entries are the blank spaces to the left in Table 4C). The T count was again comparable to the T-par optimizer, but the CNOT count was significantly lower, resulting in a clearly preferred circuit. For example, the optimized GF(2 64 ) multiplier circuit showed the use of 180,892 CNOT gates, while the optimized implementation resulting from the techniques of this disclosure used only 24,765 CNOT gates, and the total cost was reduced from 30,168.59 to 18,326.42, or about 39%, despite no change in T-count. This reduction comes mostly or entirely from CNOT gates. This comparison demonstrates that the discrepancy between T-count and theoretically predicted realistic total cost estimates is also shown in practice. The efficiency of the lightweight optimizer is demonstrated by the remaining unsolved instances of the elliptic curve discrete logarithm problem in GF(2 131 ) and GF(2 163 ) enabled the optimization of multiplication quantum circuits. Given the reported T-par optimization runtimes, instances of this size appear intractable for T-par optimizers.

[0092] A new tool for T-count optimization has been proposed (Heyfron and Campbell). The approach used in this new tool relies on measurements and conventional feedback, in contrast to the fully unitary circuits considered in this disclosure. Furthermore, this new tool does not provide counting for CNOT gates, and direct comparison with tools that provide counting for both T and CNOT gates is not possible. Again, this tool is focused solely on optimizing T-count, and the techniques of this disclosure deviate from this simple cost metric. For example, a QFT4 circuit optimized based on this new T-count optimization tool implements a 4-qubit QFT transformation using 44 qubits, suggesting that the overhead of CNOT gates must be significant. Another important difference is scalability. While the techniques described herein are suitable and applicable for optimizing large-scale circuits, the novel T-count optimization tool only handles very small circuits; for example, the largest GF multiplication circuit compiled with this tool is the 7-bit case, while the one described herein is capable of tackling CF multiplication with 131 and 163 bits, addressing the outstanding Certicom challenge. Another difference is that the technique proposed herein only uses interactions between qubits already available in the input circuit. This allows optimized circuits in the same architecture to be implemented as input circuits, which may be more useful quantum computers than limited architectures. In contrast, the novel T-count optimization tool introduces new interactions. Finally, the technique proposed herein can be used to optimize arbitrary R Z Although it can handle circuits via gates, the new T-count optimization tool is limited to Clifford+T circuits.

[0093] (Overall Performance) Examples of numerical optimization results generated by the optimization algorithm described in this disclosure are presented in Tables 1, 2, 3A and 3B, and 4A-4C. These tables encompass benchmarks related to practical quantum computing beyond the reach of conventional computers. Tables 1 and 2 include 1,024- and 2,048-qubit QFT and integer addition circuits used in classically intractable instances of Shor's integer factorization algorithm. Tables 3A and 3B include all instances of n≧50 that are currently infeasible through direct classical simulation of quantum mechanics. Tables 4A-4C include Galois field multiplication circuits for binary fields of size 131 and 163, which are relevant to quantum attacks on the unsolved Certicom ECC challenge problem. This demonstrates the ability of the proposed optimizer or optimization algorithm to handle quantum circuits large enough for practical use.

[0094] The proposed optimizer or optimization algorithm is more broadly applicable than previous work on circuit optimization. It readily accommodates complex gates such as Toffoli gates (which may have negation controls). It also inherently addresses R, including Hamiltonian simulation and factorization. Z We deal with gates with continuous parameters, which are useful features for algorithms that use gates. Many quantum information processing technologies, including both trapped ions and superconducting circuits, natively support such gates, and thus the proposed approach described here can be useful for optimizing physical-level circuits.

[0095] Fault-tolerant quantum computation generally relies on a set of discrete gates, such as Clifford+T, with optimal R ZClifford+T implementations of gates are already known. Even so, the ability to optimize circuits with continuous parameters in a fault-tolerant setting is similarly valuable, since optimizing over a set of continuously parameterized natural gates before organizing them into a discrete fault-tolerant set is likely to result in a smaller final circuit.

[0096] Finally, unlike previous approaches, the optimizer proposed in this disclosure is configured to preserve the structure of the original quantum circuit. Specifically, the set of two-qubit interactions used by the optimized quantum circuit is a subset of those used in the original quantum circuit. This is possible because neither the preprocessing step nor the optimization algorithm introduces any new two-qubit gates. By keeping the types of interactions used under control (in stark contrast to, e.g., T-parameters, which dramatically increase the set of interactions used), the optimized implementation resulting from the proposed optimization algorithm is better suited to architectures with limited connectivity. Specifically, given the layout of an original quantum circuit on hardware with limited connectivity, this property allows the same layout to be used for the optimized quantum circuit. Furthermore, unlike other optimization tools (e.g., the novel T-count optimization tool described above), the optimizer proposed in this disclosure does not increase the number of CNOT gates used. This may be a relevant practical consideration. This is because long-range CNOT gates can even be more expensive than T gates, and focusing only on optimizing T can result in circuits whose cost is dominated by CNOT gates.

[0097] Referring now to diagram 1800 of FIG. 18 , an exemplary computing device 1810 according to one implementation is shown, which can be used to execute the various optimization algorithms described above, including various optimization subroutines and light and heavy versions of the optimizer. The computing device 1810 may represent, for example, a single computing device, multiple computing devices, or a distributed computing system. The computing device 1810 may be configured to perform or implement automated optimization of quantum circuits, including automated optimization of large-scale quantum circuits with continuous parameters, as described herein. Additionally, the computing device 1810 can be configured to receive information (e.g., a netlist) about a quantum circuit, optimize the number of quantum gates required to implement the quantum circuit (or the function of the quantum circuit) to be fewer than the number of quantum gates originally required (e.g., before optimization) to implement the quantum circuit (or the function of the quantum circuit), and then generate new information (e.g., a new netlist).

[0098] In one example, computing device 1810 may include a processor 1848 that performs processing functions related to one or more optimization functions or operations described herein. Processor 1848 may include a single or multiple set of processors or multi-core processors. Furthermore, processor 1848 may be implemented as an integrated and / or distributed processing system. In one implementation, processor 1848 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), or a combination of one or more of these types of units, which may be configured to perform one or more of the optimization functions or operations described herein.

[0099] In one example, computing device 1810 may include memory 1850 that stores instructions executable by processor 1848 to perform the functions described herein. In one implementation, memory 1850 may correspond to a computer-readable storage medium that stores, for example, code or instructions for performing one or more of the optimization functions or operations described herein.

[0100] Additionally, computing device 1810 may include a communications component 1852 that provides for establishing and maintaining communications with one or more parties using the hardware, software, and services described herein. Communications component 1852 may carry communications between components on computing device 1810 and between computing device 1810 and external devices, such as devices located across a communications network and / or devices serially or locally coupled to computing device 1810. In one example, communications component 1852 may provide for communication of information between computing device 1810 and a quantum information processing (QIP) system, such that an optimized netlist or similar information is generated by computing device 1810 and then provided to the QIP system. In another example, communications component 1852 may include one or more buses and may further include transmit chain and receive chain components associated with transmitters and receivers, respectively, and operable to interface external devices.

[0101] Additionally, computing device 1810 may include data store 1854, which may be any suitable combination of hardware and / or software that provides mass storage of information, databases, and programs used in connection with the implementations described herein. For example, data store 1854 may be a data repository for operating system 1840 and / or optimization application 1830. In one implementation, data store 1854 may include memory 1850.

[0102] The data store 1854 and / or memory 1850 may be used to store information related to the pre-optimized circuit, the optimized circuit, intermediate information generated during the optimization process, optimization algorithms including subroutines and various versions of the optimizer, and any rules related to the optimization operations described herein.

[0103] The computing device 1810 may also include a user interface component 1856 operable to receive input from a user of the computing device 1810 and further operable to generate output for presentation to the user. The user interface component 1856 may include one or more input devices, including, but not limited to, a keyboard, a numeric keypad, a mouse, a touch-sensitive display, a digitizer, navigation keys, function keys, a microphone, a voice recognition component, any other mechanism capable of receiving input from a user, or any combination thereof. The user interface component 1856 may also include one or more output devices, including, but not limited to, a display, a speaker, a haptic feedback mechanism, a printer, any other mechanism capable of presenting output to a user, or any combination thereof.

[0104] In one implementation, user interface component 1856 can send and / or receive messages corresponding to the operation of operating system 1840 and / or optimization application 1830. Furthermore, processor 1840 can execute, and memory 1850 or data store 1854 can store, operating system 1840 and / or optimization application 1830. Furthermore, optimization application 1830 can execute based on stored code or instructions to perform one or more of the optimization functions or operations described herein. For example, optimization application 1830 can select between a light version of an optimizer or a heavy version of an optimizer, thereby executing the appropriate sequence of subroutines (and any operations within each of the subroutines).

[0105] 19 is a flowchart illustrating a process or method 1900 for performing automatic optimization of a quantum circuit according to aspects of the present disclosure. Aspects of the method 1900 may be performed by hardware and / or software in the computing device 1810 shown in FIG.

[0106] At block 1905, the method 1900 includes receiving a netlist that includes information about a first list of quantum gates that form the quantum circuit. The list of quantum gates may allow for repetition of elements, as a quantum circuit may have duplicates of the same quantum gate.

[0107] At block 1910, the method 1900 includes performing a topological polynomial reduction operation on information about the first list of quantum gates to generate a second list of quantum gates that have functional equivalence to the first list of quantum gates, wherein a computational cost, such as the number of quantum gates in the second list of quantum gates, is less than a computational cost, such as the number of quantum gates in the first list of quantum gates.

[0108] At block 1915, the method 1900 includes generating a new netlist that includes information about the second list of quantum gates.

[0109] At block 1920, the method 1900 includes providing a new netlist to implement the functionality of the quantum circuit using the second list of quantum gates.

[0110] In another aspect of the method 1900, a pre-processing operation can be performed before performing the phase polynomial reduction operation. This pre-processing operation can include NOT gates, CNOT gates, Toffoli gates, Hadamard gates, and R Z It can be applied to gates.

[0111] In another aspect of the method 1900, a Hadamard gate reduction operation may be performed before performing the phase polynomial reduction operation.

[0112] In another aspect of method 1900, a cancellation operation of a single qubit gate can be performed before performing a phase polynomial reduction operation.

[0113] In another aspect of method 1900, a two-qubit gate cancellation operation can be performed before performing the phase polynomial reduction operation.

[0114] In another aspect of the method 1900, performing the phase polynomial reduction operation may include executing a set of rewrite rules, which may include one or both of a gate count preserving rewrite rule or a gate count reducing rewrite rule.

[0115] In another aspect of the method 1900, one or more gate cancellation or gate reduction operations may be performed iteratively along with the phase polynomial reduction operation.

[0116] In another aspect of the method 1900, a fixed sequence of optimization operations including a phase polynomial reduction operation may be performed repeatedly, with the phase polynomial reduction operation being performed only once in the fixed sequence rather than as the first optimization operation in the fixed sequence.

[0117] FIG. 20 shows a diagram 2000 illustrating an example of a QIP system 2005 according to an embodiment of the present disclosure. The QIP system 2005 may also be referred to as a quantum computing system, a quantum computing network, or a computing device. In one embodiment, the QIP system 2005 may be used to implement or execute quantum computing operations or algorithms, and the suitability of the implemented quantum gate for the system depends, for example, on the ability to have a regulated and stable laser output applied to trapped ions used as qubits. The QIP system 2005 may correspond to a quantum computer implementation of the computing device 1810 in FIG. 18 and / or a quantum computer that received or implemented optimization results generated by executing the optimization application 1830 (e.g., the proposed optimizer or optimization algorithm) in the computing device 1810 in FIG. 18.

[0118] This QIP system 2005 represents a trapped atomic ion version of a quantum computer and can include a source 2060 that supplies atomic species to a chamber 2050 having an ion trap 2070 that captures atomic species (e.g., trapped ions) ionized by an optical controller 2020. A light source 230 in the optical controller 2020 can include one or more laser sources that can be used to ionize the atomic species, control (e.g., phase control) the atomic species, and fluorescently emit the atomic ions, which can be monitored and tracked by image processing algorithms running in an imaging system 2040 in the optical controller 2020.

[0119] Imaging system 2040 can include a high resolution imager (e.g., a CCD camera) to monitor the atomic ions while they are being delivered to ion trap 2070 (to count them) or after they have been delivered to ion trap 2070 (to monitor their state). In one embodiment, imaging system 2040 can be implemented separate from light controller 2020, although the use of fluorescent emissions to detect, identify, and label atomic ions using image processing algorithms may need to be coordinated with light controller 2020.

[0120] QIP system 2005 may also include an algorithm component 2010 that can operate with other portions of QIP system 2005 (not shown) to perform quantum algorithms (e.g., QFT, quantum simulation) using the optimization techniques described above. Algorithm component 2010 can provide instructions to various components of QIP system 2005 (e.g., to optical controller 2020) to enable the implementation of quantum circuits or their equivalents. That is, algorithm component 2010 can enable the mapping of various computing primitives to physical representations, for example, using trapped ions in ion trap 2070 as qubits.

[0121] The QIP system 2005 and / or algorithm component 2010 may also be used to implement quantum simulations related to chemical or molecular applications. For example, the Hamiltonian of a quantum object, such as a molecule, is typically:

number

[0122] where p, q, r, and s represent integers and / or labels of electron orbitals,

number

number

[0123] For small t (e.g., significantly less than 1), the transformation is such that the linear expression

number

[0124] When t is large, the formula becomes

number

[0125] Thus, the bracketed

number

number

number

[0126] In some implementations, implementing the molecular Hamiltonian may involve the use of various gates, such as two-qubit quantum gates. Two-qubit quantum gates, such as two-qubit CNOT gates, may be more resource-intensive at the physical level of implementation than one-qubit quantum gates, such as Hadamard gates. Therefore, reducing the number of two-qubit quantum gates may be important for pre-fault-tolerant quantum computing.

[0127] In Figure 21, the effective Hamiltonian operator, which frequently arises in quantum chemical simulations,

number

[0128] (Subroutine 6; Controlled Gate Cancellation (2)) In some implementations, addend 2110h of sequence 2150 can lead to quantum circuit 2200 shown in FIG. 22A.

[0129] In some implementations, addend 2110g in sequence 2150 can lead to quantum circuit 2230 of FIG. 22A. FIGS. 22A-B illustrate a cancellation routine for a two-qubit quantum gate according to one embodiment of the present disclosure. The cancellation routine may retain functionality. The first quantum circuit 2200 may include six CNOT gates and a single-qubit z-rotate gate, and the second quantum circuit 2230 may include six CNOT gates and a single-qubit z-rotate gate. If the original term is assigned to a particular qubit,

number

number

[0130] Continuing to refer to FIG. 22A , in a non-limiting example, two adjacent H gates 2260 may be cancelled using an H gate cancellation operation. Similarly, two adjacent H gates 2262 may be cancelled using an H gate cancellation operation. Next, CNOT gate 2264 may be (temporarily) swapped with a first H gate, P gate, and second H gate combination 2266 using an HPH swap operation. The HPH swap can switch the order of execution between HPH gate combination 2266 and CNOT gate 2264. After the swap of CNOT gate 2264 and HPH gate combination 2266, the control qubit of CNOT gate 2264 may be adjacent to the control qubit of CNOT gate 2268. The target qubit of CNOT gate 2264 may be adjacent to the target qubit of CNOT gate 2268. Both CNOT gates 2264, 2268 may be cancelled using a CNOT gate cancellation operation.

[0131] 22B, in a particular example, the two-qubit quantum gates in first quantum circuit 2200 and second quantum circuit 2230 can be cancelled out. HPH gate combination 2266 can be swapped with CNOT gate 2270 using an HPH swap position operation. After CNOT gate 2270 swaps positions and HPH gate combination 2266, the control qubit of CNOT gate 2270 can be adjacent to the control qubit of CNOT gate 2272. The target qubit of CNOT gate 2270 can be adjacent to the target qubit of CNOT gate 2272. Both CNOT gates 2270, 2272 can be cancelled out using a CNOT gate cancellation operation.

[0132] Continuing with reference to FIG. 22B, in some implementations, the first H gate, P † gate, and a second H gate (i.e., HP † H) combination is HP † H conversion (HP †The first phase gate 2274 can be swapped with a CNOT gate 2278, and the second P gate 2276 can be swapped with a CNOT gate 2280 separately using a P gate swap operation. After the two P gate swap operations, the combination 2282 of the CNOT gate 2278, H gate, and CNOT gate 2280 can be transformed into three H gates, a P gate, an H gate, and a P gate 2282 using a CNOT gate permutation. † The first H gate, the second P gate, and the second H gate (i.e., HPH) can be replaced by a combination 2284 including a gate, a CNOT gate, and two P gates. In a particular example, the first H gate, the P gate, and the second H gate (i.e., HPH) can be replaced by a combination 2284 including a HPH transformation (HPH → P † HP † ) in the first P † gate, H gate, and second P gate † Gate (P † HP † ) can be converted into P † Using gate position exchange, P † The gate can be swapped with a CNOT gate (not shown).

[0133] In this non-limiting example shown in Figures 22A-B, six CNOT gates (i.e., two-qubit quantum gates) were reduced to one CNOT gate (a 6:1 reduction ratio). Other reduction ratios, such as 5:1, 4:1, 3:1, or 2:1, are possible, for example, if a different order is used or if certain operations cannot be replaced due to hardware constraints. A controlled gate cancellation subroutine can reduce the number of two-qubit quantum gates (e.g., CNOT gates) while maintaining the functionality of the quantum circuit. Reducing the number of two-qubit quantum gates potentially saves resources used to implement the quantum circuit.

[0134] In some implementations, directly implementing a controlled gate such as a CNOT gate in hardware may be difficult or inefficient. As shown in Figure 23, for example, one or more Mϕlmer-Sϕrensen (MS) gates and / or one or more single-qubit rotation gates may be used to implement a CNOT gate based on Equation 2300, where s = ±1 is the sign of the interaction parameter to which the gate ions are applied, and v = ±1 can be chosen arbitrarily. Similarly, an MS gate may be implemented with four H gates, two CNOT gates, and a single-qubit z-rotation gate based on Equation 2350.

[0135] In some instances, it may be desirable to implement a second equivalent circuit if it can apply small-angle MS gates more frequently while reducing the number of CNOT gates (or large-angle MS gates, such as π / 2) compared to the first original circuit, even if the number of two-qubit gates remains the same or may even increase. For example, the second circuit may exhibit better performance in the presence of one or more realistic noise sources, including thermal noise, imprecise control, etc., if the small-angle MS gates contribute less error than the large-angle MS gates.

[0136] Other examples of implementing the above operations may also reduce the number of two-qubit quantum gates. The subroutines and operations described above may be implemented by, for example, computing device 1810 and / or QIP system 2005.

[0137] 24 is a flowchart illustrating a process or method 2400 for reducing a two-qubit quantum gate in a quantum circuit according to an embodiment of the present disclosure. Embodiments of method 2400 may be performed by hardware and / or software in computing device 1810 shown in FIG. 18 and / or by QIP system 2005 of FIG. 20.

[0138] At block 2405, method 2400 includes receiving a netlist that includes information related to a first plurality of two-qubit quantum gates that form a quantum circuit. This information includes a controlled gate, R Z The netlist may include information related to one or more of a quantum gate, a Hadamard gate, a phase gate, or an antiphase gate. For example, the computing device 1810 may receive a netlist that includes information related to quantum circuitry.

[0139] At block 2410, method 2400 includes performing a controlled gate cancellation operation on information associated with the first plurality of two-qubit quantum gates to generate a second plurality of two-qubit quantum gates that are functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is greater than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates. Examples of controlled gate cancellation operations may include operations associated with Figures 22A-B. Optimization application 1830 may perform operations associated with Figures 22A-B to reduce the number of two-qubit quantum gates.

[0140] At block 2415, the method 2400 includes generating a new netlist that includes information about the second plurality of two-qubit quantum gates.

[0141] At block 2420, method 2400 includes providing a new netlist for implementing functionality of a quantum circuit based on the second plurality of two-qubit quantum gates.

[0142] In an alternative implementation, the method 2400 includes performing one or more H-gate cancellation operations.

[0143] In an alternative implementation, the method 2400 includes performing one or more HPH location exchange operations.

[0144] In an alternative implementation, the method 2400 includes performing one or more CNOT gate cancellation operations.

[0145] In an alternative implementation, the method 2400 may include one or more HP † Performing an H transformation.

[0146] In an alternative implementation, the method 2400 includes performing one or more P-gate position swap operations.

[0147] In an alternative implementation, the method 2400 includes performing one or more HPH transformations.

[0148] In an alternative implementation, the method 2400 may include one or more P † The step of performing a gate position exchange operation is included.

[0149] In an alternative implementation, the method 2400 includes performing one or more CNOT gate permutations.

[0150] While this disclosure has been presented in terms of illustrated implementations, those skilled in the art will readily recognize that there can be variations to these embodiments that would fall within the scope of this disclosure. Accordingly, those skilled in the art will be able to make numerous modifications without departing from the scope of the appended claims.

Claims

1. A method for reducing two-qubit quantum gates in a quantum circuit that realizes a Hamiltonian dynamics simulation, the quantum circuit corresponding to a sequence of addends having Hamiltonian operators as addends, comprising: receiving a netlist including information relating to a first plurality of two-qubit quantum gates forming the quantum circuit; performing, on the information associated with the first plurality of two-qubit quantum gates, two-qubit quantum gate cancellation operations including at least a CNOT gate cancellation operation, and one or more CNOT gate substitutions that replace a combination of a first CNOT gate, one H gate, and a second CNOT gate with a combination including three H gates, one P† gate, one CNOT gate, and two P gates, to generate a second plurality of two-qubit quantum gates that are functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is greater than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates; generating a new netlist containing information about the second plurality of two-qubit quantum gates; providing the new netlist for implementing functionality of the quantum circuit based on the second plurality of two-qubit quantum gates; Including, a method.

2. 2. The method of claim 1, wherein the information includes information related to one or more of a controlled gate, an RZ gate, an H gate, a P gate, or a P† gate.

3. In an alternative implementation, the method of claim 1, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more H-gate cancellation operations.

4. In an alternative implementation, the method of claim 1, wherein the step of performing the two-qubit quantum gate cancellation operation further includes performing one or more HPH position swap operations.

5. In an alternative implementation, the method of claim 4, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more CNT gate cancellation operations.

6. In an alternative implementation, the method of claim 1, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more HP†H transformations.

7. In an alternative implementation, the method of claim 6, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more P-gate position swap operations.

8. In an alternative implementation, the method of claim 1, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more HPH transformations.

9. In an alternative implementation, the method of claim 8, wherein the step of performing the two-qubit quantum gate cancellation operation further includes the step of performing one or more P† gate position swap operations.

10. When executed by one or more processors, the one or more processors receiving a netlist including information related to a first plurality of two-qubit quantum gates forming a quantum circuit that implements a Hamiltonian dynamics simulation, the quantum circuit corresponding to a sequence of addends with Hamiltonian operators as addends; performing, on the information associated with the first plurality of two-qubit quantum gates, two-qubit quantum gate cancellation operations including at least a CNOT gate cancellation operation, and one or more CNOT gate substitutions that replace a combination of a first CNOT gate, one H gate, and a second CNOT gate with a combination including three H gates, one P† gate, one CNOT gate, and two P gates, to generate a second plurality of two-qubit quantum gates functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is greater than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates; generating a new netlist containing information about the second plurality of two-qubit quantum gates; providing the new netlist for implementing functionality of the quantum circuit based on the second plurality of two-qubit quantum gates; 10. A computer-readable medium having instructions for inducing

11. 11. The computer-readable medium of claim 10, wherein the information includes information related to one or more of a controlled gate, an RZ gate, an H gate, a P gate, or a P† gate.

12. In an alternative implementation, the computer-readable medium of claim 10, wherein performing the two-qubit quantum gate cancellation operation further comprises performing one or more H-gate cancellation operations.

13. In an alternative implementation, the computer-readable medium of claim 10, wherein performing the two-qubit quantum gate cancellation operation further includes performing one or more HPH position swap operations.

14. In an alternative implementation, the computer-readable medium of claim 13, wherein performing the two-qubit quantum gate cancellation operation further comprises performing one or more CNOT gate cancellation operations.

15. In an alternative implementation, the computer-readable medium of claim 10, wherein performing the two-qubit quantum gate cancellation operation further comprises performing one or more HP†H transformations.

16. In an alternative implementation, the computer-readable medium of claim 15, wherein performing the two-qubit quantum gate cancellation operation further comprises performing one or more P-gate position swap operations.

17. In an alternative implementation, the computer-readable medium of claim 10, wherein performing the two-qubit quantum gate cancellation operation further includes performing one or more HPH transformations.

18. In an alternative implementation, the computer-readable medium of claim 17, wherein performing the two-qubit quantum gate cancellation operation further comprises performing one or more inverse P-gate position swap operations.

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