Memory calibration system and method

Abstract

A method for implementing a stutter of a dynamic random access memory (DRAM), in which a system-on-chip (SOC) initiates a burst of requests to the DRAM to fill a buffer to allow the DRAM to self-refresh, is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to a memory controller to initiate a stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, and periodically issuing, by the SMU, power platform threshold (PPT) requests to the memory controller. Sending the ForceZQCal command before the PPT request can ensure that a retrain occurs after ZQ calibration. The ForceZQCal command issued before the PPT request can reduce stutter latency. The method can further include issuing a ForceZQCal command before each periodic retrain.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 16 / 938,855, filed July 24, 2020, the contents of which are incorporated herein by reference. [Background technology]

[0002] Dynamic random-access memory (DRAM) is a commonly used type of memory used in computer systems. DRAM is a volatile memory that requires proper initialization and periodic calibration to maintain performance, including proper interface impedance for interface performance.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example device in which one or more features of the present disclosure may be implemented. [Figure 2] FIG. 1 illustrates the state machines for power-down, auto-refresh, and ZQCal (SPAZ). [Figure 3] FIG. 3 shows a method for ZQCS sequences implemented in the SPAZ of FIG. 2. [Figure 4] FIG. 10 shows two groups, each group sent by SPAZ for Tzq. [Figure 5] 3 illustrates a method for periodic calibration to maintain proper performance of a dynamic random access memory (DRAM) implemented by the arbiter and SPAZ of FIG. 2. [Figure 6] FIG. 1 illustrates a method for implementing power management for a system. [Figure 7]FIG. 1 illustrates a method for implementing stuttering. [Figure 8] FIG. 10 illustrates a method supported by SPAZ to initiate a ZQCal cycle for all ranks. DETAILED DESCRIPTION OF THE INVENTION

[0005] The following method and system are provided for performing periodic calibration to maintain proper performance of dynamic random access memory (DRAM).

[0006] A system and method for a power-down, auto-refresh, and ZQCal (SPAZ) state machine for periodic calibration to maintain proper performance of DRAM is disclosed. The system and method include power-down logic (PD), auto-refresh logic (REF) including per-bank refresh, a ZQ state machine (ZQ) for calibration, and thermal logic (THM) for monitoring thermal conditions. The SPAZ links to a back-end queue (BEQ) and an arbiter (ARB). The arbiter and SPAZ check whether a ZQ interval counter has expired during memory controller control of the memory, wait until the arbiter has control of the memory before issuing a ZQCal Start command, send a ZQCal Latch from the SPAZ / arbiter if the tZQCAL counter has expired, and hand over control to the Self-Refresh State Machine (SRSM) after the ZQCal Latch has completed, subject to control by the SRSM.

[0007] A method for performing a stutter of a DRAM, in which a system on a chip (SOC) initiates a burst of requests to the DRAM to fill a buffer to allow the DRAM to self-refresh, is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to a memory controller to initiate a stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request; periodically issuing, by the SMU, power platform threshold (PPT) requests to the memory controller; and sending the ForceZQCal command before a PPT request to ensure that a retrain occurs after ZQ calibration. The ForceZQCal command issued before a PPT request can reduce stutter latency. The method can further include issuing a ForceZQCal command before each periodic retrain.

[0008] A method for initiating a ZQCal cycle supported by SPAZ for all ranks across multiple groups is disclosed. The method includes, by an SMU, setting a ForceZQCal bit, initiating a ZQ start, and resetting a SPAZ counter to start counting from 0 upon receiving ForceZQCal start. Setting the ForceZQCal bit by the SMU allows the SMU to control the ZQCal cycle. SPAZ can initiate a ZQStart. At ZQ start, a latch may be considered atomic. If ForceZQCal occurs while a SPAZ procedure is in progress, the ongoing procedure terminates the ZQ command for any of the multiple groups for which the hardware-initiated ZQStart / Latch is active. The method further includes sending the ZQ command sent by the SPAZ to the remaining groups.

[0009] 1 is a block diagram of an example device 100 in which one or more features of the present disclosure may be implemented. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, memory 104, storage 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include additional components not shown in FIG. 1 .

[0010] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0011] The storage devices 106 include fixed or removable storage devices (e.g., hard disk drives, solid state drives, optical disks, flash drives). The input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). The output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0012] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. Note that the input driver 112 and the output driver 114 are optional components, and that the device 100 can be operated in the same manner without the input driver 112 and the output driver 114. DRAM is a type of random-access semiconductor memory that stores each bit of data in a memory cell consisting of a small capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can be charged or discharged to represent two values ​​of a bit, conventionally called 0 and 1. The charge on the capacitor slowly leaks away, so without intervention, the data on the chip will quickly be lost. To prevent this, DRAM requires an external memory refresh circuit that periodically rewrites the data on the capacitor and restores the capacitor to its original charge. This refreshing process is a defining characteristic of dynamic random-access memory, as opposed to static random-access memory (SRAM), which does not require data to be refreshed.

[0013] DRAM typically takes the form of an integrated circuit chip, which can contain tens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where large amounts of computer memory are needed at low cost. One of the largest uses of DRAM is as the main memory (colloquially called "RAM") in modern computers and graphics cards (where "main memory" is also called graphics memory). It is also used in many portable devices and video game consoles.

[0014] Generally, there are four steps to preparing a DRAM for use in a computer system: power-up and initialization, ZQ calibration, Vref DQ calibration, and read / write training, as described below.

[0015] Power-up and initialization is a well-defined sequence of steps that involves applying power to the DRAM, at which point the DRAM on a dual in-line memory module (DIMM) is operating at a set frequency and has defined column access strobe (CAS) latency (CL), CAS write latency (CWL), and other timing parameters.

[0016] For example, ZQ calibration for a type of DRAM called Double Data Rate Synchronous Random-Access Memory (DDR4) involves a data pin and a set of parallel resistor legs. In one example, these resistor legs are 240 Ω, although other resistance values ​​may be used. Due to the nature of complementary metal-oxide-semiconductor (CMOS) devices, these resistors are never exactly the desired resistance, such as 240 Ω in this example. The resistance is affected by changes in voltage and temperature, among other factors. To adjust these resistors to exactly or substantially the desired value, such as 240 Ω in this example, each DRAM has a special block called the DQ calibration control block and the ZQ pins to which the resistors are connected. This external precision resistor is the “reference” and remains the desired value, such as the 240 Ω value in this example, at all temperatures. When a ZQCal command is issued during initialization, this DQ calibration control block is enabled and generates the adjustment value. This adjustment value is then copied to the internal circuitry of each DQ.

[0017] In DDR4, an internal voltage reference is used to determine whether the signal on the data line is a 0 or a 1. This voltage reference is called VrefDQ. VrefDQ may be set using a mode register and must be set correctly by the memory controller during a VrefDQ calibration phase.

[0018] Once these power-up and initialization steps are performed, the system is in idle mode and ready to operate. Additional requirements for using DRAM may include periodic calibration.

[0019] Low-Power Double Data Rate Synchronous Dynamic Access Memory (LPDDR4) devices, as mentioned above, require periodic ZQ calibration (impedance) to compensate for voltage and temperature impedance drift. LPDDR4 devices, like other DDR4 devices, support a specific command to start device calibration. However, LPDDR4 devices support separate commands to start the calibration and actually perform impedance updates based on that calibration. The ZQStart command notifies the device to calibrate, and the ZQLatch notifies the device to apply the values ​​from the calibration.

[0020] In this embodiment of LPDDR4, two 16-bit devices can be grouped together as one 32-bit LPDDR4 channel because the minimum LPDDR4 resolution of a memory controller channel is 32 bits. ZQ calibration is performed by the two supported ranks per channel, with each rank having its own calibration resistor. The physical interface (PHY) issues a ZQCal command to the memory controller before retraining, which is performed by the PHY when exiting a PHY power-gated (registered trademark) scenario if the MstateCtrl.ConvertD2toPHYLP3 bit is set, and both ranks are ZQ-calibrated simultaneously per subchannel. The memory controller issues ZQCal commands to each rank independently. When in Virtual Controller Mode (VCM), where each 32-bit subchannel independently ZQ-calibrates, two independent channels can be supported by one memory controller channel, but ZQ calibration can still be performed simultaneously. VCM occurs when one DRAM controller runs two separate, independent channels, satisfying the needs of two separate DRAM controllers. Per device specifications, ZQStart or ZQLatch commands cannot be sent to an LPDDR4 device when the device is in power-down mode. However, power-down of an LPDDR4 device may occur during ZQ calibration. Traffic can be sent to an LPDDR4 device between ZQStart and ZQLatch with a minimum delay of 1 μs between ZQStart and ZQLatch.

[0021] The SPAZ logic may support a ZQ calibration interval timer. The interval is configurable, for example, from 32 ms to 256 ms, and is specified as Tzq (ZqCsInterval). For multiple ranks, the Tzq interval may be set, for example, to half. The interval counter resides in the always-on (AON) domain, so the count is not affected by power gating. Each ZQ command is sent when the command bus is available. That is, in-flight transactions may be able to complete before the ZQStart calibration is sent. When SPAZ sends ZQStart, it can atomically send ZQLatch before returning control to the memory controller. ZQ calibration and corresponding updates are performed during periodic updates during mission mode, stutter, and S3 sleep states, as described below.

[0022] The SPAZ contains a ZQ interval timer that must reside in the AON region. The ZQ interval is divided into two groups, each with a x32 subchannel. The SPAZ can send commands to each group based on an interval, such as (ZQ interval) / 2.

[0023] 2 shows a state machine for power-down, auto-refresh, and ZQcal (SPAZ) 200 for DRAM. SPAZ 200 includes power-down logic (PD) 210, auto-refresh logic (REF) 220, which may include per-bank refresh capability, a ZQ state machine (ZQ) 230 for calibration, and thermal logic (THM) 240. SPAZ 200 may also include links to a back-end queue (BEQ) 250 and an arbiter (ARB) 260.

[0024] The power-down logic 210 enables the memory controller to support full and partial channel power-down. A partial channel power-down occurs when some ranks are placed in power-down mode. A full channel power-down occurs when all ranks are placed in power-down mode. The power-down logic 210 communicates with the arbiter 260 to monitor bus / rank status and determine whether and which ranks are allowed to be powered down. Proactive power-down can also be implemented to save passive waiting time for a page to be closed. The power-down logic 210 can optionally enable power-down channel staggering to prevent all channels from entering or exiting power-down at the same time due to power-down logic channel staggering.

[0025] Auto-refresh logic 220 enables the memory controller to periodically refresh the DRAM with an auto-refresh command. The auto-refresh logic 220 may be limited, for example, by only allowing selection of a single rank, one bank, or multiple banks at a time. Fine-granularity auto-refresh may be included in the auto-refresh logic 220 and may be utilized for DDR4 memory products. The auto-refresh logic 220 may include logic to track when a refresh is needed and, based on the tracking, may send a refresh command request to the arbiter 260 for subsequent transmission to the DRAM. The auto-refresh logic 220 may enable per-bank refresh as supported in accepted DRAM technologies, such as LPDDR4 / HBM.

[0026] ZQ230 can be used to calibrate DRAM and on-die termination (ODT) values. As will be appreciated by those skilled in the art, DRAM often requires a longer time (ZQCL) to calibrate output drivers and ODT circuits during initialization and when exiting self-refresh, and a relatively shorter time (ZQCS) to perform periodic calibrations that account for voltage and temperature variations. ZQ230 can handle the generation of ZQCS calibration commands. The memory controller can send the long version (ZQCL) of ZQ commands during initialization and while exiting self-refresh, and the short version (ZQCS) of ZQ commands to perform periodic calibrations. SPAZ200 supports ZQCS, while ZQCL can be supported by the PHY / memory controller during initialization or while exiting self-refresh.

[0027] Thermal logic 240 can monitor DRAM thermal status in some products by monitoring a temperature port from the board and capturing results from periodic mode register readings. Based on these inputs, thermal logic 240 can take actions including dynamically changing the refresh rate by increasing or decreasing the rate, throttling commands by capping the DRAM interface bandwidth, derating command isolation timing, powering down ranks, and logging machine check memory temperature hot (MCA) errors.

[0028] The back-end queue 250 manages address, data, and control signaling for the channels directed to the physical layer (PHY). The back-end queue 250 can manage the movement of write data from the write data buffer to the channels, and can move read data responses back to the front-end interface (FEI).

[0029] As shown, power-down logic 210 can receive inputs from thermal logic 240, auto-refresh logic 220, ZQ 230, back-end queue 250, and arbiter 260, and can output to ZQ 230, auto-refresh logic 220, back-end queue 250, and arbiter 260. ZQ 230 is in communication with auto-refresh logic 220, power-down logic 210, and arbiter 260. Thermal logic 240 outputs to auto-refresh logic 220, power-down logic 210, and arbiter 260. For completeness, auto-refresh logic 220 is in communication with arbiter 260, thermal logic 240, power-down logic 210, and ZQ 230. Back-end queue 250 is in communication with power-down logic 210. Arbiter 260 is in communication with auto-refresh logic 220, thermal logic 240, ZQ 230, and power-down logic 210.

[0030] During ZQCS, the DDR bus may be idle while the DRAM performs ZQ calibration. Some systems can send calibration commands to several ranks independently by sharing ZQ resistors between devices. For example, two ranks in a Digital Dynamics Processor (DDP) perform ZQCS at different times. As a further example, all ranks in a Three Dimensional Dual-Screen (3DS) package can perform ZQ calibration with a single command. Periodic calibration is performed using a long counter that counts up to a configurable interval (e.g., 1 / 4 of the interval) to select one ZQ group, and if the selected group is configured with the entered rank, a ZQCS sequence can be started.

[0031] FIG. 3 illustrates a method 300 for implementing a ZQCS sequence in the SPAZ 200. Method 300 includes, in step 310, skipping method 300 if the corresponding ZQ group does not have a posted rank. In step 320, the arbiter (element 260 in FIG. 2) and other SPAZ (element 200 in FIG. 2) blocks are notified that a ZQCS sequence is pending. Based on the notification, most commands are postponed, followed by a delay to allow the back-end queue (element 250 in FIG. 2) to drain. In step 330, the power-down logic block (element 210 in FIG. 2) is notified to exit the power-down state for the entire channel, and method 300 must block any entering / exiting power-down while the ZQCS sequence is complete. In step 340, the open page of the posted rank in the ZQ group is precharged. In step 350, method 300 sends any pending urgent refreshes to the entire channel. Again, no other refresh commands can be sent during the ZQCS sequence. In step 360, method 300 sends a ZQCS command to the ranks in the ZQ group. In step 370, SPAZ waits (for a time period of length Tzqcs), during which time the channel is idle.

[0032] Figure 4 shows two groups (Grp0, Grp1) sent by SPAZ based on Tzq interval / 2. SPAZ (element 200 in Figure 2) can simultaneously command both sub-channels separately for ZQStart and ZQLatch. SPAZ (element 200 in Figure 2) keeps track of the start per sub-channel using a separate ZQCAL counter (1 μs) for each sub-channel. The arbiter (element 260 in Figure 2) can route normal traffic between ZQStart and ZQLatch commands to maintain atomicity before handing control over to the memory controller.

[0033] Upon exiting S3 sleep state or connected standby, video and audio are disabled, so additional ZQ calibrations across all ranks are expected and retraining is expected. In this configuration, since the system is inactive for potentially long periods of time and the DRAM is not periodically ZQ calibrated or trained during this time, the SMU signals ZQ calibration and periodic training via configuration to retrain ZQCal before any PHY-initiated accesses may be required. Generally, there is no traffic between ZQStart and ZQLatch. Back-to-back ZQ calibrations of the "group" for both x32 subchannels total 1 μs + 30 ns + 1 μs + 30 ns = 2.06 μs. When exiting connected standby, the SMU can set a control bit such as MstateCtrl.ConvertD2toPHYLP3 before entering connected standby so that the memory controller can convert requests for awake state based on normal C-state requests (e.g., D2 requests) to LP3 state so that the PHY will initiate a ZQCal before retraining on exit occurs.

[0034] Exiting S3 / Connected Standby using the PHY LP3 state can be handled separately. The SRSM adds a bit to do an extended Cstate in response to a D2 request in LP3 state so the PHY is initiated (already done for D3). This CFG bit must be set by the SMU before the C-state request to convert D2-LP2 to D2-LP3 to the PHY. This CFG bit is called ConvertD2toPHYLP3. This can be associated with a long idle Vmin "Whisper" mode, for example.

[0035] FIG. 5 shows a method 500 for periodic calibration to maintain proper performance of a DRAM, performed by the arbiter and SPAZ of FIG. 2. The arbiter and SPAZ perform the method 500 of FIG. 5 for periodic atomic calibration. Method 500 includes checking whether a ZQ interval counter expires during memory controller control of the memory, in step 510, and then waiting until the arbiter gains control before issuing a ZQCal Start (ZQStart) command, in step 520. Method 500 includes sending a ZQCal Latch (ZQLatch) from the SPAZ / arbiter, in step 530, when the tZQCAL counter expires. The arbiter returns control to the SRSM after the ZQCal Latch procedure is performed, in step 540.

[0036] Generally, embodiments of the present invention enable starting the ZQ calibration process before entering an event (e.g., entering a low power mode, entering self-refresh, etc.) to avoid sending a ZQ calibration during event exit. After the event exits (e.g., a lower power mode exists, exiting self-refresh mode), embodiments of the present invention perform the calibration that was started before entering the event (i.e., the calibration process was started before the event, but the calibration actually occurs after the event). Starting the ZQ calibration before entering the event may result in a reduced cost of entering the event (e.g., reduced cost of entering a low power mode or a lower power mode, i.e., improved power management). Furthermore, starting the ZQ calibration before entering the event may also reduce bus utilization after the event ends (e.g., lower bus utilization after exiting a lower power mode or exiting self-refresh mode). Either or both of these benefits may result in a system (e.g., an SoC, an SoC combined with off-die memory, etc.) entering lower power modes more frequently, thus reducing overall system power consumption (and improving power management).

[0037] 6 illustrates a method 600 for implementing power management for a system. Method 600 includes initiating a calibration in step 610. In one embodiment, such initiation may occur before entering an event. Method 600 may include entering an event in step 620. The event may include, for example, a lower power mode such as a memory self-refresh mode. Method 600 may include performing a calibration in step 630. According to one embodiment, performing the calibration in step 630 may be responsive to the calibration initiated in step 610. According to one embodiment, performing the calibration in step 630 may be performed at the end of the event.

[0038] According to one embodiment, the SPAZ can incorporate counters to track activity. These counters include a first counter (Tzq) for monitoring the calibration period and a second counter (Tzqcal) for monitoring the duration between ZQStart and ZQLatch (approximately 1 μs). These counters can be located within the SPAZ, for example, as a sub-block ZQCTR. ZQCTR can be located, for example, in the AON region. The SPAZ can detect when a ZQStart command is sent and then start the Tzqcal counter. The SPAZ then terminates the ZQ sequence by sending a ZQLatch command.

[0039] Stuttering is a process that essentially allows the SOC to initiate a burst of requests to the DRAM to fill the buffer and then put the DRAM into self-refresh. The SMU maintains a counter based on a periodic cycle that coincides with the memory controller's periodic ZQCal timer. Upon the SMU's ZQCal timeout request, the SMU issues a ForceZQCal request to the memory controller before the stutter. Periodically during the stutter, the SMU issues a PPT request to the memory controller. According to one embodiment, a ForceZQCal request is sent before a PPT request to reduce latency (e.g., reduce the latency of the stutter) to ensure that the retrain occurs along with the preceding ZQ calibration. In one embodiment, the SMU may not implement a ZQCal timer and may provide a ForceZQCal request before each periodic retrain. Generally, the SMU waits 1.03 μs before sending an instruction (1 μs between the ZQStart command and the ZQLatch command, with an actual latch overhead of 30 ns). Stutter is a periodic D2 process.

[0040] SPAZ supports a way to initiate a ZQCal cycle for all ranks. This is done by the SMU setting the ForceZQCal bit. This bit gives the SMU control of the ZQCal cycle. SPAZ initiates the ZQ start and latch and is considered atomic. If a ForceZQCal request occurs while SPAZ is in the process of a hardware start ZQStart / Latch, this calibration group may not have a ZQ command sent again (SPAZ needs to send ZQ commands to the remaining groups). Upon receiving ForceZQCal, SPAZ counters are reset and can start their count from 0.

[0041] FIG. 7 illustrates a method 700 for implementing a stutter procedure. Generally, as described above, the SMU maintains a counter based on a periodic cycle that coincides with the memory controller's periodic ZQCal timer. Upon the SMU's ZQCal timeout request, in step 710, the SMU issues a ForceZQCal command to the memory controller before the stutter procedure. Periodically during the stutter procedure, the SMU issues a PPT request to the memory controller in step 720. According to one aspect, to ensure that retraining occurs along with the preceding ZQ calibration, in step 730, the ForceZQCal command is sent before the PPT request to reduce the latency of the stutter procedure. In one embodiment, the SMU does not implement a ZQCal timer and instead provides a ForceZQCal command before each periodic retraining in step 740.

[0042] 8 shows a method 800 supported by SPAZ to initiate a ZQCal cycle for all ranks. Method 800 includes, in step 810, an SMU setting the ForceZQCal bit to control ZQ calibration. In step 820, SPAZ initiates ZQStart and ZQLatch, which are considered atomic. If a ForceZQCal command occurs while SPAZ is in the process of hardware-initiated ZQStart / Latch, this calibration group may not have a ZQ command sent again in step 830 because SPAZ may need to send ZQ commands to the remaining groups in step 840. Upon receiving the ForceZQCal command, the SPAZ counter is reset in step 850 and allowed to start counting from 0.

[0043] The SRSM uses two configuration bits: the first to specify that a command to begin retraining should be sent to the SMU, and the second to specify that the PHY should send ZQStart and ZQLatch commands as part of the sequence. The SMU can identify to the SRSM the functionality it provides based on how the bits are set. The SRSM monitors the state of the two configuration bits, which can be set by the SMU. If the first bit is set, a command to begin retraining is sent to the SMU, and if the second bit is set, the SRSM sends the encoding for PPT training LP2 to the PHY.

[0044] The PHY logic resides in the AON domain to enable the logic necessary to terminate the memory controller channel from the PG and issue PHY LP2 in parallel, along with the termination of PHY LP2, etc.

[0045] The systems and methods described herein allow for triggering ZQ calibrations during a period prior to entering self-refresh to avoid sending ZQ calibrations while exiting self-refresh. In this system and method, ZQ calibrations occurring before entering self-refresh do not block traffic during tZQCal(1 us). In each situation, bus utilization is improved.

[0046] Based on the duration, the SMU determines whether ZQ calibration is necessary, which the SMU can specify before signaling the memory controller to enter self-refresh. For example, if the system is powered on for a long time, the SMU can specify whether ZQ calibration needs to be initiated along with periodic retraining. The SMU keeps the memory controller awake for at least 2.06 us for ZQStart and ZQLatch.

[0047] The PHY may support a configuration bit written by the memory controller channel to specify whether ZQ calibration precedes PHY retraining. This configuration bit state may be specified before both periodic retraining and frequency changes.

[0048] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0049] The various functional units shown and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, compute unit 132, SIMD unit 138, SPAZ 200, power-down logic 210, auto-refresh logic 220, ZQ 230, thermal logic 240, back-end queue 250, and arbiter 260) may be implemented as a general-purpose computer, processor, or processor core, or as a program, software, or firmware stored on a non-transitory computer-readable storage medium or other medium executable by a general-purpose computer, processor, or processor core. The provided methods may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such processors may be fabricated by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data such as a netlist (such instructions may be stored on a computer-readable medium). The result of such processing may be a mask work that is used in subsequent semiconductor manufacturing processes to produce a processor implementing features of the present disclosure.

[0050] The methods or flow diagrams provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (e.g., internal hard disks and removable disks), magneto-optical media, and optical media (e.g., CD-ROM disks and digital versatile disks (DVDs)).

Claims

1. 1. A method of power management for a system, comprising: Start calibration before entering the event, performing a calibration upon exiting an event and in response to initiating the calibration before entering the event; method.

2. said initiating including sending a calibration command prior to entering said event; The method of power management of claim 1.

3. The event includes a low power mode. The power management method of claim 2.

4. the low power mode includes a self-refresh mode of the memory; The power management method of claim 3.

5. The calibration command includes issuing a ForceZQCal command. The power management method of claim 2.

6. A system management unit (SMU) issues the ForceZQCal command. The power management method of claim 5.

7. The calibration command initiates a stutter procedure. The power management method of claim 2.

8. The calibration command being issued before the event request reduces the latency of the stutter procedure. The power management method of claim 7.

9. and initiating the calibration before each periodic retraining. The method of power management of claim 1.

10. The initiating is supported by the Power Down, Auto Refresh, and ZQCal (SPAZ) state machines. The method of power management of claim 1.

11. 1. A method for initiating an initialization cycle, comprising: setting an initialization cycle control bit; Initiating an initialization cycle start, said initiating including sending a calibration command before entering the event; resetting the counter and starting the count when an initialization cycle start command is received; method.

12. The initialization cycle is supported by the Power-Down, Auto-Refresh, and ZQCal (SPAZ) state machines. The method of claim 11.

13. a system management unit (SMU) setting the initialization cycle control bit; The method of claim 11.

14. the SMU sets the initialization cycle control bit, thereby enabling the SMU to control the initialization cycle; 14. The method of claim 13.

15. SPAZ initiates the initialization cycle start. The method of claim 11.

16. Starting includes sending an initialization command before entering the event. The method of claim 11.

17. The event includes a low power mode.

17. The method of claim 16.

18. the low power mode includes a self-refresh mode of the memory; 18. The method of claim 17.

19. and terminating the initialization command when a system management unit (SMU) issues a calibration command. The method of claim 11.

20. The calibration command includes issuing a ForceZQCal command.

20. The method of claim 19.

Images