Semiconductor module and method for manufacturing the same

Abstract

Provided are a semiconductor module and a method for manufacturing the semiconductor module that make it possible to prevent voids from occurring by means of a joining layer formed of solder. The semiconductor module comprises a laminated substrate (5) on which is mounted a semiconductor element (1) that has a Ni film formed on a rear surface thereof, the rear surface of the semiconductor element (1) being joined to the laminated substrate (5) by solder that has a composition that includes more than 6 mass% but no more than 8.5 mass% of Sb, 2–4.5 mass% of Ag, 1.25–2.0 mass% of Cu, and a remainder made up of Sn and inevitable impurities.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. [Background technology]

[0002] A power semiconductor module is a power semiconductor device that incorporates one or more power semiconductor chips (also referred to as semiconductor elements) to form part or all of a conversion connection, and has a structure in which the power semiconductor chip is electrically isolated from the laminated substrate with the conductive wiring plate, and from the metal substrate that serves as a heat sink. Power semiconductor modules are used in industrial applications such as motor drive control inverters for elevators, etc. In recent years, they have also become widely used in automotive motor drive control inverters. Automotive inverters require compactness and weight reduction to improve fuel efficiency, and long-term reliability under high-temperature operation is required because they are placed near the drive motor in the engine compartment.

[0003] Compared to industrial power semiconductor modules, automotive power semiconductor modules are required to be smaller and lighter due to the constraints of installation space. Furthermore, as the output power density for driving motors increases, the semiconductor chip temperature rises during operation, and high thermal stress occurs, which increases the demand for long-term reliability during high-temperature operation. Therefore, there is a demand for a power semiconductor module structure that can operate at high temperatures and has long-term reliability.

[0004] Fig. 5 is a cross-sectional view showing the configuration of a power semiconductor module with a conventional structure. As shown in Fig. 5, power semiconductor module 150 includes power semiconductor chip 101, laminated substrate 105, and cooler 126. Power semiconductor chip 101 is a power semiconductor chip such as a MOSFET, IGBT, or diode, and is bonded to laminated substrate 105 with chip bonding layer 127 made of solder. Laminated substrate 105 is formed by providing insulating substrate 102, such as a ceramic substrate, with first conductive plate 103 made of copper or the like on the front surface and second conductive plate 104 made of copper or the like on the back surface. Cooler 126 is bonded to laminated substrate 105 with cooler bonding layer 128 made of solder.

[0005] Although not shown, the power semiconductor module 150 is bonded to a case (not shown) and includes metal terminals (not shown) for extracting signals to the outside, and metal wires (not shown) for electrically connecting the power semiconductor chip 101 to the metal terminals. Furthermore, in the case of a MOSFET, a source electrode pad is formed on the surface of the power semiconductor chip 101 as a power terminal electrode pad (current supply terminal). A conductive connection member such as a lead frame or metal wire is then disposed as an output terminal from the power terminal electrode pad. In the case of a lead frame, it is bonded to the power semiconductor chip 101 by a bonding layer such as solder. A plurality of these members may be mounted on a single semiconductor device. A case is bonded to the power semiconductor module 150, and a lid (not shown) is attached, through which the metal terminals pass and protrude to the outside. The case is filled with a sealing material (sealing resin, not shown) that insulates and protects the laminated substrate 105 and the power semiconductor chip 101 on the substrate.

[0006] Also, a solder joint is known that has a solder alloy layer having an alloy composition consisting of, in mass %, 2-4% Ag, 0.6-2% Cu, 9.0-12% Sb, 0.005-1% Ni, and the remainder Sn, which suppresses peeling between the back metal and the solder alloy when forming the solder joint, as well as preventing non-wetting of the solder alloy, splashing of molten solder, and damage to electronic components due to chip cracking (see Patent Document 1 below). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2019 / 088068 Summary of the Invention [Problem to be solved by the invention]

[0008] Fig. 6 is an enlarged view of region S in Fig. 5 of a power semiconductor module with a conventional structure. Fig. 6 shows the structure between power semiconductor chip 101 and chip bonding layer 127. On the back surface of power semiconductor chip 101, a metal electrode 129 made of AlSi (aluminum silicon alloy) is provided when the semiconductor is silicon (Si), and a metal electrode 129 made of Ni (nickel) is provided when the semiconductor is silicon carbide (SiC), and a Ti (titanium) layer 130, a Ni layer 131, and an Au (gold) layer 132 are laminated in this order between metal electrode 129 and chip bonding layer 127.

[0009] The Ti layer 130 is a barrier layer that prevents reaction between the chip bonding layer 127 and the upper metal electrode 129, and is provided with a thickness of, for example, about 0.1 μm to 0.8 μm. The Ni layer 131 is provided with a thickness of about 0.2 μm to 1.2 μm to ensure the wettability of the chip bonding layer 127. The Au layer 132 is provided with a thickness of about 20 nm to 100 nm to prevent oxidation. The chip bonding layer 127 is a solder containing Sn (tin).

[0010] Figure 7 is a cross-sectional view of the solder bonding layer between the power semiconductor chip and the first conductive plate of a conventional power semiconductor module under normal conditions. In this case, as shown by the arrows in Figure 7, Cu diffuses from the first conductive plate 103, forming a SnCu alloy 133 between the Ni layer 131 (134) and the chip bonding layer 127. This suppresses the diffusion of the Ni layer 131 (134), leaving a Ni residual film 134 of 0.1 µm or more. The Au layer 132 becomes 20 nm or less and is almost completely removed at the time of bonding.

[0011] FIG. 8 is a cross-sectional view of a conventional power semiconductor module showing a soldered bonding layer between a power semiconductor chip and a first conductive plate during a malfunction. In this case, Cu diffusion from the first conductive plate 103, indicated by the arrows in FIG. 8, is slow, resulting in insufficient SnCu alloy 133 between the Ni layer 131 (134) and the chip bonding layer 127. Alternatively, Ni diffuses rapidly from the Ni layer 131 (134) into the chip bonding layer 127 (Sn solder), forming a SnNi alloy and partially eliminating the Ni residual film 134. As a result, the Ti layer 130, which has poor solderability (solder wettability), comes into contact with the solder, forming voids 135, resulting in reduced reliability of the power semiconductor module. This phenomenon is particularly pronounced in the case of a first conductive plate 103 with a Ni alloy layer (plated layer) formed on its surface, which makes it difficult for Cu to be supplied to the chip bonding layer 127.

[0012] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor module and a method for manufacturing the semiconductor module that can prevent the occurrence of voids in a solder joint layer. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor module according to the present invention has the following features: The semiconductor module includes a laminated substrate on which a semiconductor element having a Ni layer formed on the back surface is mounted. The back surface of the semiconductor element is formed of Sb. 6.1% by mass or more, The laminated substrate is joined with a solder having a composition consisting of 8.5% by mass or less of Sn, 2% by mass or more and 4.5% by mass or less of Ag, 1.25% by mass or more and 2.0% by mass or less of Cu, and the remainder being Sn and unavoidable impurities.

[0014] Moreover, in the semiconductor module according to the present invention, the solder does not contain Ni in its composition.

[0015] In addition, in the semiconductor module according to the present invention, the laminated substrate has a conductive plate made of copper or copper alloy on the semiconductor element side.

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor module according to the present invention has the following features: 6.1% by mass or more, The method includes a step of applying solder to a laminated substrate, the solder having a composition containing 8.5% by mass or less of Ni, 2% by mass or more and 4.5% by mass or less of Ag, 1.25% by mass or more and 2.0% by mass or less of Cu, and the remainder being Sn and unavoidable impurities, and then a step of placing a semiconductor element having a Ni layer formed on its back surface on the solder and bonding the back surface of the semiconductor element to the laminated substrate.

[0017] According to the above-mentioned invention, the laminated substrate and the power semiconductor chip are joined with solder having a composition of Sn-(6-8.5)Sb-[2-4.5]Ag-[1.25-2.0]Cu. As a result, Cu from the solder reaches the interface of the Ni layer, and a SnCu alloy is generated at the interface of the Ni layer, which acts as a protective layer for the Ni layer and can suppress the diffusion of Ni. Therefore, Ni does not disappear, and a Ni residual film remains. This Ni residual film This ensures the wettability of the solder and prevents the occurrence of voids. Note that a solder with a composition containing more than 6% by mass and up to 8.5% by mass of Sb, 2% by mass to 4.5% by mass of Ag, 1.25% by mass to 2.0% by mass of Cu, and the remainder being Sn and unavoidable impurities is expressed as Sn-(6-8.5)Sb-[2-4.5]Ag-[1.25-2.0]Cu, and other compositions will be expressed in the same manner hereinafter. [Effects of the Invention]

[0018] The semiconductor module and the method for manufacturing the semiconductor module according to the present invention have the advantage of being able to prevent voids from occurring in the solder joint layer. [Brief explanation of the drawings]

[0019] [Figure 1]FIG. 1 is a cross-sectional view showing a configuration of a power semiconductor module according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a solder bonding layer between a power semiconductor chip and a first conductive plate of the power semiconductor module according to the embodiment. [Figure 3A] FIG. 3A is a cross-sectional view showing a residual Ni film in a bonding layer formed by solder in which 0 mass % of Cu is added to Sn—Sb—Ag solder. [Figure 3B] FIG. 3B is a cross-sectional view showing a residual Ni film in a bonding layer made of Sn—Sb—Ag solder to which 0.9 mass % of Cu has been added. [Figure 3C] FIG. 3C is a cross-sectional view showing a residual Ni film in a bonding layer made of Sn—Sb—Ag solder to which 2.0 mass % of Cu has been added. [Figure 4] FIG. 4 is a table showing the evaluation results of the power semiconductor modules of the examples and comparative examples for each solder composition. [Figure 5] FIG. 5 is a cross-sectional view showing the configuration of a power semiconductor module having a conventional structure. [Figure 6] FIG. 6 is an enlarged view of a region S in FIG. 5 of a power semiconductor module having a conventional structure. [Figure 7] FIG. 7 is a cross-sectional view showing a solder joint layer between a power semiconductor chip and a first conductive plate in a conventional power semiconductor module in a normal state. [Figure 8] FIG. 8 is a cross-sectional view showing a solder joint layer between a power semiconductor chip and a first conductive plate in a conventional power semiconductor module when a malfunction occurs. DETAILED DESCRIPTION OF THE INVENTION

[0020] Preferred embodiments of a semiconductor module and a method for manufacturing a semiconductor module according to the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0021] (Embodiment) 1 is a cross-sectional view showing the configuration of a power semiconductor module according to an embodiment. In power semiconductor module 50, a first conductive plate 3 made of copper or the like is disposed on one surface (front side) of insulating substrate 2, and a second conductive plate 4 made of copper or the like is disposed on the other surface (back side) to form a laminated substrate 5. A plurality of power semiconductor chips 1 are mounted on the front surface of first conductive plate 3 of laminated substrate 5 via chip bonding layer 27. A cooler 26 is mounted on the back side of second conductive plate 4 of laminated substrate 5 via cooler bonding layer 28.

[0022] In the power semiconductor module 50, metal terminals (not shown) for extracting signals to the outside are bonded to the inside of the case (not shown). Furthermore, a conductive connecting member such as a pin terminal or a lead frame is attached to the front surface (e.g., source electrode pad) of the power semiconductor chip 1 via a metal wire (not shown) (bonding wire) such as aluminum wire or a bonding layer (not shown). The power semiconductor chip 1 and the metal terminal are electrically connected via a metal wire such as aluminum wire. A lead frame may also be used. A primer layer may be laminated on the sealed components, such as the power semiconductor chip 1, the laminated substrate 5, the chip bonding layer 27, the cooler bonding layer 28, and the metal wire, to improve adhesion. Furthermore, a sealing resin (not shown) is filled inside the case. The illustrated configuration of the power semiconductor module 50 is merely an example, and the present invention is not limited to this configuration.

[0023] (Power semiconductor chip 1) In the embodiment, the power semiconductor chip 1 is a power chip such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or an SBD (Schottky Barrier Diode) made of Si or SiC, and a device using Si or SiC can be used as the semiconductor substrate. The number of power semiconductor chips 1 mounted may be one or more.

[0024] As in the past, an AlSi metal electrode is provided on the back surface of the power semiconductor chip 1 when the semiconductor substrate is Si, or a Ni metal electrode is provided when the semiconductor substrate is SiC (in both cases, the metal electrode is not shown), and a Ti layer and a Ni layer are laminated in this order between the metal electrode and the solder chip bonding layer 27. Furthermore, an Au layer may be laminated between the Ni layer and the chip bonding layer 27 (see FIG. 6).

[0025] (Laminated substrate 5) The laminated substrate 5 may be composed of an insulating substrate 2, a first conductive plate 3 formed in a predetermined shape on one of its main surfaces, and a second conductive plate 4 formed on the other main surface. The first conductive plate 3 is formed with a predetermined circuit pattern on the front surface (first main surface) of the insulating substrate 2. The second conductive plate 4 may be a metal foil formed on the entire back surface of the insulating substrate 2. The insulating substrate 2 may be made of a material with excellent electrical insulation and thermal conductivity. Examples of materials for the insulating substrate 2 include Al2O3, AlN, and SiN. In particular, for high-voltage applications, a material that combines electrical insulation and thermal conductivity is preferable, and AlN and SiN can be used, but are not limited to these. The first conductive plate 3 and the second conductive plate 4 may be made of Cu (copper) or a Cu alloy, which has excellent processability. Note that a Cu alloy is an alloy containing 80% or more Cu. Among such conductive plates made of Cu or a Cu alloy, the conductive plate not in contact with the power semiconductor chip 1 is sometimes referred to as a back copper foil or a back conductive plate. Direct copper bonding or active metal brazing can be used as a method for disposing a conductive plate on the insulating substrate 2. Alternatively, the surface of the conductive substrate may be plated with Ni (nickel) or the like to form Ni or a Ni alloy.

[0026] (Cooler 26) The cooler 26 has a heat sink plate, for example, of a substantially rectangular planar shape, made of a metal such as Cu or Al that has excellent thermal conductivity, and a plurality of heat sink fins. The surface of the heat sink plate of the cooler 26 may be covered with a Ni film or Ni alloy film that has an anti-corrosion effect. The back surface of the heat sink of the cooler 26 is bonded to the heat sink fins. The cooler 26 is a cooling device that uses the plurality of heat sink fins to dissipate heat generated in the power semiconductor chip 1 and transmitted through the laminate substrate 5.

[0027] (Cooler bonding layer 28) The cooler bonding layer 28 can be formed using lead-free solder. Examples of solder that can be used include, but are not limited to, Sn-Sb (antimony), Sn-Cu, Sn-Ag (silver), and Sn-Sb-Ag. A solder containing 5-10% by mass of Sb, 2-5% by mass of Ag, 0.1-0.4% by mass of Ni, and 0.001-0.1% by mass of Ge, with the remainder being Sn, is particularly preferred. It is even more preferred for the solder to contain 0-2% by mass of Cu. A Cu content of 2% by mass or less is also preferred because it promotes the formation of a Cu-Sn compound phase. The cooler bonding layer 28 can also be formed using a connecting material containing fine metal particles, such as a sintered body of nano-silver particles. Thermal grease, etc., can also be used.

[0028] (Chip bonding layer 27) The chip bonding layer 27 is formed using lead-free solder. The solder has a composition of Sn-(6-8.5)Sb-[2-4.5]Ag-[1.25-2.0]Cu. This composition is composed of more than 6% by mass but not more than 8.5% by mass of Sb, 2% by mass but not more than 4.5% by mass of Ag, 1.25% by mass but not more than 2.0% by mass of Cu, and the remainder being Sn. Incidental impurities may be included, and more than 0.001% by mass but not more than 0.1% by mass of Ge (germanium) and P (phosphorus) may be added. The solder material with the above composition may be a sheet solder material melted to achieve the specified composition, or a cream solder made by mixing a flux material with a reducing effect and granular solder material.

[0029] FIG. 2 is a cross-sectional view showing a solder joint layer between a power semiconductor chip and a first conductive plate of a power semiconductor module according to an embodiment. In this embodiment, Cu is added to the solder. Cu diffuses from the solder as indicated by the arrows in FIG. 2. Because the diffusion rate of Cu is faster than that of Ni, Cu from the solder reaches the interface of the Ni layer, forming a SnCu alloy 33 at the interface. The SnCu alloy 33 acts as a protective layer for the Ni layer, suppressing Ni diffusion (SnNi alloying). Therefore, Ni does not disappear, and a Ni residual film 34 remains. It is believed that this Ni residual film 34 ensures the wettability of the solder and prevents voids from occurring. Cu and Sn in the solder are more likely to form a SnCu alloy at the Ni interface than to form a SnCu alloy in the solder. The Ni layer corresponds to the Ni layer 131 in FIG. 6 or the Ni residual film 134 in FIG. 7. Furthermore, a first conductive plate 3 having Cu (copper) or a Cu alloy exposed on its surface is more likely to produce the effects of the present invention than a first conductive plate 3 having a Ni alloy layer (plated layer) formed on its surface, since Cu is supplied to the chip bonding layer 27 (solder).

[0030] In particular, when the first conductive plate 3 is Cu or a Cu alloy, the Cu contained in the first conductive plate 3 also diffuses upward (toward the power semiconductor chip 1) and generates a SnCu alloy 33 at the interface of the Ni layer, so that more SnCu alloy 33 is generated and the diffusion of Ni can be further suppressed.

[0031] 3A to 3C are cross-sectional views showing the residual Ni film in the bonding layer formed by Sn—Sb—Ag solder with Cu added. The thickness of the Ni layer before bonding is 0.7 μm. FIG. 3A shows the case where 0 mass% Cu was added, FIG. 3B shows the case where 0.9 mass% Cu was added, and FIG. 3C shows the case where 2.0 mass% Cu was added. These figures show the results of Ni mapping performed using an SEM (scanning electron microscope) equipped with an EDX (energy dispersive X-ray spectroscopy).

[0032] 3A, when no Cu is added, there are many areas where the Ni residual film 34 has disappeared, and even when 0.9 mass % Cu is added as shown in FIG. 3B, there are areas where the Ni residual film 34 has disappeared. On the other hand, as shown in FIG. 3C, when 2.0 mass % Cu is added, the Ni residual film 34 has not disappeared, and it is possible to ensure a stable Ni residual film 34 by increasing the amount of Cu added.

[0033] The reliability of the power semiconductor module according to the embodiment was confirmed by a power cycle test. Here, the reliability was evaluated by the power cycle resistance (TjP / C resistance) relative to the amount of Cu added to the solder. The power cycle test was conducted at 50 to 150°C (ΔTj = 100°C) to determine the number of cycles until the electrical characteristics reached abnormal values. Specifically, electricity was applied from 50°C to 150°C, and a failure was determined when the thermal resistance value increased by 20% from the initial value. A power cycle test (P / C) was conducted on multiple power semiconductor modules, and the number of cycles at which the cumulative failure rate, which is the cumulative percentage of failed modules, reached 1% was defined as the P / C resistance. A P / C resistance of 60k cycles or more was determined to be reliable, and a P / C resistance of less than 60k cycles was determined to be unreliable.

[0034] For example, the results of power cycle tests using solder with a composition of Sn-8Sb-3Ag-1.3Cu-0.003Ge and Sn-8Sb-3Ag-0.9Cu-0.003Ge are shown below. The number of cycles at which the cumulative failure rate reaches 1% is approximately 85,000 for Sn-8Sb-3Ag-1.3Cu-0.003Ge and approximately 100,000 for Sn-8Sb-3Ag-0.9Cu-0.003Ge. In both cases, the reliability of the power semiconductor module is good. While both are reliable, the number of cycles at which the cumulative failure rate reaches 1% decreases as the Cu content increases. This shows that adding too much Cu reduces the P / C tolerance of the power semiconductor module.

[0035] Figure 4 is a table showing the evaluation results of power semiconductor modules of examples and comparative examples for each solder composition. In Figure 4, the Ni layer was evaluated based on the thickness of the Ni remaining film after bonding. Wettability to Ni (chip backside) was evaluated by observing voids in the chip bonding layer 27 using SAT (ultrasonic testing). Poor wettability is undesirable because voids and other defects occur at the interface with the bonded surface, increasing the initial thermal resistance. Voids exceeding 1.3% of the bonding surface area of ​​the power semiconductor chip 1 were rated as "X" because they increase thermal resistance, while voids of 0.3% or less were rated as "O." Voids greater than 0.3% but less than 1.3% were not currently a major problem, but were rated as "△" because there was a risk of increased thermal resistance with larger capacity. Furthermore, for the P / C (power cycle test) evaluation, a P / C withstand capacity of 60k cycles or more was rated as reliable (O), and one less than 60k cycles was rated as unreliable (X).

[0036] In Examples 1 and 2 and Comparative Examples 1 to 3, the solder composition was Sn-8.3Sb-3.2Ag-xCu, and the effect of Cu addition was evaluated. Comparative Example 1 had a Cu addition amount of 0 mass %. As described above, when the Cu addition amount was small, the SnCu alloy was not formed, the Ni residual film disappeared, and the Ni wettability was evaluated as ×. Comparative Example 2 had a Cu addition amount of 0.9 mass %, and here too, the Ni residual film disappeared partially, and the Ni wettability was evaluated as △. The P / C was evaluated as ○, but there were some areas where the Ni film disappeared, and if the P / C becomes more severe, there is a high possibility that reliability will decrease. Comparative Example 3 had a Cu addition amount of 3 mass %, and when the Cu addition amount was large, the SnCu alloy coarsened, the strength decreased, and cracks occurred. Therefore, the P / C was evaluated as ×.

[0037] In Examples 1 and 2, the Cu content was 1.25 mass % and 2 mass %, respectively, and both were evaluated as good for wettability to Ni and P / C. From the above results, the solder of the embodiment contains Cu in a composition percentage range of 1.25 mass % or more and 2.0 mass % or less.

[0038] In Examples 1 and 3 and Comparative Examples 4 and 5, the solder composition was Sn-xSb-3.2Ag-1.25Cu, and the effect of Sb addition was evaluated. Example 1 contained 8.3 mass% Sb, and Example 3 contained 6.1 mass% Sb. In both examples, the residual Ni film was not lost, and the Ni wettability and P / C evaluations were rated as good. This is presumably because an appropriate amount of Sb generates an SnSb alloy, reducing the SnNi alloy and reducing Ni erosion. In Comparative Example 4, the Sb addition amount was 9.5 mass%, and some of the residual Ni film was lost. The Ni wettability was rated fair, and the P / C evaluation was poor. This is presumably because too much Sb generated a large amount of SnSb alloy, making it difficult to generate an SnCu alloy on the backside of the chip, resulting in Ni erosion and poor wettability. Furthermore, when the Sb content is high, Sb3Sn2 compounds crystallize in the SnSb peritectic structure with Sb as the nucleus when joining at a cooling rate of 20°C / sec or less, as is typical for solder joints. This crystallization of Sb3Sn2 compounds improves strength but reduces ductility. Furthermore, when thermal deformation and strain due to heat generation are applied, these compounds migrate to the grain boundaries, where the SbSn compounds coarsen due to interdiffusion with Sn. These coarse compounds reduce the grain boundary strength of the crystals and easily promote grain boundary sliding, which creates cavities at the grain boundaries, resulting in a loss of ductility and a decrease in strength. It is presumed that this failure to achieve both strength and ductility resulted in a P / C rating of ×. Comparative Example 5, with an Sb content of 5.2 mass%, partially lost the residual Ni film, resulting in a Ni wettability rating of △ and a P / C rating of ×. This is presumably because when there is little Sb, the SnSb alloy is less produced, and the SnNi alloy is more likely to be produced, which increases Ni erosion and worsens wettability. Furthermore, because there is little SnSb alloy produced, the joint strength is reduced, and the P / C rating is presumably poor. Based on these results, the solder of the embodiment contains Sb in a composition percentage range of more than 6 mass % to 8.5 mass %.

[0039] In Examples 1, 4, and 5 and Comparative Examples 6 and 7, the solder composition was Sn-8.3Sb-xAg-1.25Cu, and the effect of Ag addition was evaluated. Examples 1, 4, and 5 had Ag addition amounts of 3.2 mass%, 2 mass%, and 4.5 mass%, respectively. There was no loss of the Ni residual film, and the Ni wettability was evaluated as ○, and the P / C was evaluated as ○. Comparative Example 6 had an Ag addition amount of 1.5 mass%, there was no loss of the Ni residual film, the Ni wettability was evaluated as △, and the P / C was evaluated as ×. This is because low Ag content results in poor Ni wettability, a reduced SnAg alloy, and reduced strength. Comparative Example 7 had an Ag addition amount of 5.5 mass%, there was no loss of the Ni residual film, the Ni wettability was evaluated as △, and the P / C was evaluated as ×. This is because too much Ag reduces the wettability of the Ni film. Furthermore, adding more than 5.0% Ag by mass results in a hypereutectic composition, where the eutectic structure of Ag3Sn and βSn becomes denser and the precipitation-strengthened structure becomes excessive. Furthermore, the Ag3Sn and βSn network structure shortens the distance between Ag3Sn and βSn, resulting in the Ag3Sn appearing as large compounds, resulting in scattered hard, large compounds. These Ag3Sn-like aggregates undergo interdiffusion between Sn and Ag upon heat treatment or external force, forming large Ag3Sn compounds. This presumably prevents a stable, uniform solidification structure, resulting in a loss of both strength and ductility, a failure to improve joint strength, and brittleness. Based on these results, the solder of the present embodiment contains Ag in a compositional percentage range of 2% to 4.5% by mass.

[0040] In Comparative Example 8, the solder composition was Sn-8.3Sb-3.2Ag-1.25Cu-0.25Ni, and the effect of Ni addition was evaluated. In Comparative Example 8, the Ni addition amount was 0.25 mass%, and the Ni residual film partially disappeared, resulting in a Ni wettability evaluation of △ and a P / C evaluation of ×. This is presumably because the presence of Ni causes SnNi alloy to form on the first conductive plate side, inhibiting Cu diffusion from the first conductive plate side and making it difficult to form SnCu alloy, which is not a countermeasure against Ni disappearance. It is also presumed that the addition of Ni makes the solder brittle and reduces reliability. Based on these results, the solder of the embodiment does not contain Ni beyond the amount of unavoidable impurities.

[0041] (Method of manufacturing a power semiconductor module according to an embodiment) Next, a method for manufacturing the power semiconductor module according to the embodiment will be described. First, the cooler 26 is joined to the second conductive plate 4 of the laminated substrate 5 by the cooler joining layer 28. Next, solder having a composition of Sn-(6-8.5)Sb-[2-4.5]Ag-[1.25-2.0]Cu is applied or placed on the first conductive plate 3 of the laminated substrate 5. Next, the power semiconductor chip 1 is placed on this solder. At this time, pressure may be applied from above the semiconductor chip 1. The pressure is preferably 1 kPa to 20 kPa, and more preferably 5 kPa to 10 kPa. Applying pressure within this range reduces voids and prevents Ni diffusion. In this manner, the power semiconductor chip 1 is heated and bonded to the first conductive plate 3 of the laminated substrate 5 via the chip bonding layer 27. The temperature rise rate for this heat treatment can be about 1°C / sec, and the temperature fall rate is preferably 5°C / sec or higher, and more preferably 8°C / sec to 15°C / sec inclusive, in order to refine the crystals and improve the bonding strength.

[0042] Thereafter, the case is attached to the cooler 26, and then the lead frame is joined and wire-bonded with metal wires. A primer layer may then be formed. Next, the case is filled with sealing resin, which is temporarily cured at 100 to 120°C for 10 to 120 minutes, and then fully cured at about 175 to 185°C for 1 to 2 hours. This completes the manufacture of the power semiconductor module according to the embodiment.

[0043] As described above, according to the solder, semiconductor module, and semiconductor module manufacturing method of the embodiments, the first conductive plate and the power semiconductor chip are joined with solder having a composition of Sn-(6-8.5]Sb-[2-4.5]Ag-[1.25-2.0]Cu. This allows Cu from the solder to reach the interface of the Ni layer, and an SnCu alloy is formed at the interface of the Ni layer, which acts as a protective layer for the Ni layer and suppresses diffusion of Ni. As a result, the Ni does not disappear, and a residual Ni film remains. This residual Ni film ensures the wettability of the solder and prevents voids from occurring.

[0044] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are set in various ways according to the required specifications, etc. [Industrial Applicability]

[0045] As described above, the semiconductor module and the method for manufacturing the semiconductor module according to the present invention are useful for power semiconductor modules used in power conversion devices such as inverters, power supply devices for various industrial machines, and automotive igniters. [Explanation of symbols]

[0046] 1, 101 Power semiconductor chip 2, 102 insulating substrate 3, 103 First conductive plate 4, 104 Second conductive plate 5, 105 laminated board 26, 126 cooler 27, 127 Chip bonding layer 28, 128 Cooler bonding layer 33, 133 SnCu alloy 34, 134 Ni residual film 50, 150 Power Semiconductor Module 129 Metal electrode 130 Ti layer 131 Ni layer 132 Au layer 135 Poverty

Claims

1. a laminated substrate having a semiconductor element with a Ni layer formed on the back surface thereof; The back surface of the semiconductor element is Contains 6.1 mass% or more and 8.5 mass% or less of Sb, Contains 2% by mass or more and 4.5% by mass or less of Ag, A semiconductor module, characterized in that it is joined to the laminated substrate with solder having a composition containing 1.25 mass % or more and 2.0 mass % or less of Cu, with the remainder being Sn and unavoidable impurities.

2. 2. The semiconductor module according to claim 1, wherein the composition of the solder does not include Ni.

3. 2. The semiconductor module according to claim 1, wherein the laminated substrate has a conductive plate made of copper or copper alloy on the semiconductor element side.

4. Contains 6.1 mass% or more and 8.5 mass% or less of Sb, Contains 2% by mass or more and 4.5% by mass or less of Ag, a step of applying solder to a laminate substrate, the solder having a composition containing 1.25 mass % or more and 2.0 mass % or less of Cu, with the remainder being Sn and unavoidable impurities; a step of placing a semiconductor element having a Ni layer formed on its back surface on the solder and bonding the back surface of the semiconductor element to the laminated substrate; 2. A method for manufacturing a semiconductor module, comprising:

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