Semiconductor device manufacturing method

Abstract

To improve the performance of a semiconductor device.SOLUTION: To manufacture a semiconductor device, a semiconductor chip CPH is mounted on a die pad DPH of a lead frame LF through a conductive paste type adhesive BHD and a first thermal process is performed to cure the adhesive BDH. After that, a metal plate MP1 is disposed on a pad PDHS of the semiconductor chip CPH so as to face the pad PHDS of the semiconductor chip CPH through a conductive paste type adhesive BD1, and then a second thermal process is performed to cure the adhesive BDH and the adhesive BD1. A thermal process time of the first thermal process is shorter than that of the second thermal process. The adhesive BDH is further cured by the second thermal process after being cured in the first thermal process.SELECTED DRAWING: Figure 21

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used, for example, in a method for manufacturing a semiconductor device in which die bonding is performed using a conductive paste adhesive. [Background technology]

[0002] Japanese Patent Application Laid-Open Publication No. 2018-121035 (Patent Document 1) describes a technology related to a semiconductor device that encapsulates a semiconductor chip including a field effect transistor for a high-side switch, a semiconductor chip including a field effect transistor for a low-side switch, and a semiconductor chip that controls them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-121035 Summary of the Invention [Problem to be solved by the invention]

[0004] When manufacturing a semiconductor device using a semiconductor chip with a back electrode, the semiconductor chip is mounted on a die pad of a lead frame via a die bonding material. In this case, the semiconductor chip is mounted so that the back electrode of the semiconductor chip faces the die pad, and a conductive paste-type adhesive is used as the die bonding material to electrically connect the back electrode of the semiconductor chip to the die pad. However, if the conductive filler contained in the conductive paste-type adhesive interposed between the back electrode of the semiconductor chip and the die pad settles during the manufacturing process of the semiconductor device, the electrical resistance and thermal resistance between the back electrode of the semiconductor chip and the die pad increase. Increased electrical resistance and thermal resistance between the back electrode of the semiconductor chip and the die pad is undesirable because it leads to a decrease in the performance of the semiconductor device.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of mounting a first semiconductor chip on a first chip mounting portion of a lead frame via a first adhesive material of a conductive paste type containing a conductive filler, followed by a first heat treatment process to harden the first adhesive material, and then arranging a first metal plate so as to face a first surface electrode of the first semiconductor chip via a second adhesive material of a conductive paste type containing a conductive filler. The method for manufacturing a semiconductor device further includes, after the step of arranging the first metal plate, a second heat treatment process to harden the first adhesive material and the second adhesive material. The heat treatment time of the first heat treatment is shorter than the heat treatment time of the second heat treatment. After hardening by the first heat treatment, the first adhesive material is further hardened by the second heat treatment. [Effects of the Invention]

[0007] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating an inverter circuit using a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a top view of a semiconductor device according to an embodiment; [Figure 3] FIG. 2 is a bottom view of the semiconductor device according to the embodiment; [Figure 4] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 5] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 6] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 7] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 8] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 9] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 10] FIG. 2 is a process flow diagram showing a manufacturing process of a semiconductor device according to an embodiment. [Figure 11] FIG. 2 is a plan view of the semiconductor device according to the embodiment during the manufacturing process; [Figure 12] 12 is a plan view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 12. FIG. [Figure 14] FIG. 14 is a cross-sectional view of the same semiconductor device as in FIG. 13 during the manufacturing process. [Figure 15] 14 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 13. FIG. [Figure 16] 16 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 15. FIG. [Figure 17] FIG. 17 is a cross-sectional view of the same semiconductor device as in FIG. 16 during the manufacturing process. [Figure 18] FIG. 17 is a cross-sectional view of the same semiconductor device as in FIG. 16 during the manufacturing process. [Figure 19] FIG. 17 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 20] 19. FIG. 20 is a plan view of the semiconductor device during the manufacturing process, subsequent to FIG. [Figure 21] 21 is a cross-sectional view of the same semiconductor device as in FIG. 20 during the manufacturing process. [Figure 22] 21 is a cross-sectional view of the same semiconductor device as in FIG. 20 during the manufacturing process. [Figure 23] FIG. 21 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 20. [Figure 24] FIG. 24 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view of the same semiconductor device as in FIG. 24 during the manufacturing process. [Figure 26] FIG. 25 is a cross-sectional view of the same semiconductor device as in FIG. 24 during the manufacturing process. [Figure 27]FIG. 25 is a cross-sectional view of the same semiconductor device as in FIG. 24 during the manufacturing process. [Figure 28] FIG. 1 is a process flow diagram showing a manufacturing process of a semiconductor device according to a study example. [Figure 29] FIG. 18 is a partially enlarged cross-sectional view showing a part of FIG. 17 in an enlarged manner. [Figure 30] FIG. 2 is a cross-sectional view of a lead frame. [Figure 31] FIG. 2 is a cross-sectional view of a lead frame. [Figure 32] FIG. 2 is a cross-sectional view of a lead frame. [Figure 33] FIG. 10 is a process flow diagram showing a manufacturing process of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0010] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0011] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0012] In addition, in this application, a field effect transistor is referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or simply as a MOS, but this does not exclude a non-oxide film as the gate insulating film. That is, in this application, the term MOSFET includes not only a MISFET (Metal Insulator Semiconductor Field Effect Transistor: MIS type field effect transistor) that uses an oxide film (silicon oxide film) as the gate insulating film, but also a MISFET that uses an insulating film other than an oxide film (silicon oxide film) as the gate insulating film.

[0013] (Embodiment 1) <Circuit configuration> Fig. 1 is a circuit diagram showing an inverter circuit INV using a semiconductor device (semiconductor package, electronic device) PKG of this embodiment. In Fig. 1, the part surrounded by a dotted line and marked with a symbol CPH is formed in the semiconductor chip CPH, the part surrounded by a dotted line and marked with a symbol CPL is formed in the semiconductor chip CPL, the part surrounded by a dotted line and marked with a symbol CPC is formed in the semiconductor chip CPC, and the part surrounded by a dashed line and marked with a symbol PKG is formed in the semiconductor device PKG.

[0014] 1 includes two power MOSFETs 1 and 2 and a control circuit CLC. The control circuit CLC is formed in a semiconductor chip CPC, the power MOSFET 1 is formed in a semiconductor chip CPH, and the power MOSFET 2 is formed in a semiconductor chip CPL. These three semiconductor chips CPC, CPH, and CPL are sealed in one and the same package to form the semiconductor device PKG.

[0015] The control circuit CLC includes a high-side driver circuit that controls the potential of the gate of the power MOSFET 1 and a low-side driver circuit that controls the potential of the gate of the power MOSFET 2. The control circuit CLC is a circuit that controls the potential of each of the gates of the power MOSFETs 1 and 2 in response to a signal or the like supplied to the control circuit CLC from a control circuit CT external to the semiconductor device PKG, and controls the operation of each of the power MOSFETs 1 and 2.

[0016] The gate of power MOSFET 1 is connected to the high-side driver circuit of the control circuit CLC, and the gate of power MOSFET 2 is connected to the low-side driver circuit of the control circuit CLC. The drain of power MOSFET 1 is connected to terminal TE1, the source of power MOSFET 1 is connected to terminal TE2, the drain of power MOSFET 2 is connected to terminal TE3, and the source of power MOSFET 2 is connected to terminal TE4. In Fig. 1, symbol D1 indicates the drain of power MOSFET 1, symbol S1 indicates the source of power MOSFET 1, symbol D2 indicates the drain of power MOSFET 2, and symbol S2 indicates the source of power MOSFET 2. The control circuit CLC is connected to terminal TE5, and this terminal TE5 is connected to a control circuit CT provided outside the semiconductor device PKG.

[0017] The terminals TE1, TE2, TE3, TE4, and TE5 are all external connection terminals of the semiconductor device PKG, and are formed by leads LD, which will be described later. Of these, the terminal TE1 is a terminal for supplying a power supply potential, and a lead LD1, which will be described later, corresponds to the terminal TE1. The terminal TE4 is a terminal for supplying a reference potential, and a lead LD4, which will be described later, corresponds to the terminal TE4. The terminal TE1 (lead LD1) for supplying the power supply potential is supplied with a potential (power supply potential) VIN on the high potential side of a power supply external to the semiconductor device PKG, and the terminal TE4 (lead LD4) for supplying the reference potential is supplied with a reference potential lower than the potential VIN supplied to the terminal TE1 for supplying the power supply potential, for example, a ground potential (earth potential) GND.

[0018] Furthermore, a lead LD2, which will be described later, corresponds to the terminal TE2, and a lead LD3, which will be described later, corresponds to the terminal TE3. The terminal TE2 (lead LD2) and the terminal TE3 (lead LD3) are electrically connected outside the semiconductor device PKG. That is, the source of the power MOSFET 1 and the drain of the power MOSFET 2 are electrically connected via a conductive path provided outside the semiconductor device PKG (for example, a conductive path provided on a wiring board on which the semiconductor device PKG is mounted). Therefore, the power MOSFET 1 and the power MOSFET 2 are connected in series between the terminal TE1 for supplying a power supply potential and the terminal TE4 for supplying a reference potential. The power MOSFET 1 corresponds to a high-side MOSFET, and the power MOSFET 2 corresponds to a low-side MOSFET. That is, the power MOSFET 1 is a field-effect transistor for a high-side switch (high-potential side switch), and the power MOSFET 2 is a field-effect transistor for a low-side switch (low-potential side switch). The power MOSFETs 1 and 2 can each be considered as power transistors for switching.

[0019] A connection point TE6 between (the source of) the power MOSFET1 and (the drain of) the power MOSFET2 is provided outside the semiconductor device PKG (for example, on a wiring board on which the semiconductor device PKG is mounted), and this connection point TE6 is connected to a load (here, the coil CL of the motor MOT). DC power supplied to the inverter circuit INV using the semiconductor device PKG is converted into AC power by the inverter circuit INV and supplied to the load (here, the coil CL of the motor MOT).

[0020] Also, a lead LD5, which will be described later, corresponds to the terminal TE5. Although only one terminal TE5 is shown in Fig. 1, in reality, a plurality of leads LD5 corresponding to the terminal TE5 are provided in the semiconductor device PKG. The control circuit CLC in the semiconductor device PKG is connected to the control circuit CT provided outside the semiconductor device PKG via the terminal TE5 (lead LD5) and wiring of a wiring board on which the semiconductor device PKG is mounted, etc.

[0021] <About the structure of semiconductor devices> Fig. 2 is a top view of the semiconductor device PKG of this embodiment, Fig. 3 is a bottom view (rear view) of the semiconductor device PKG, Figs. 4 and 5 are planar perspective views of the semiconductor device PKG, and Figs. 6 to 9 are cross-sectional views of the semiconductor device PKG. Fig. 4 shows a planar perspective view of the semiconductor device PKG seen from the bottom side, looking through the sealing portion MR. Fig. 5 shows a planar perspective view of the bottom side of the semiconductor device PKG, looking through the wire BW and metal plates MP1 and MP2 (omitted) in Fig. 4. In Figs. 4 and 5, the position of the outer periphery of the sealing portion MR is indicated by a dotted line. 2 to 4 substantially corresponds to Fig. 6, the cross section of the semiconductor device PKG taken along line A2-A2 in Fig. 2 to 4 substantially corresponds to Fig. 7, the cross section of the semiconductor device PKG taken along line A3-A3 in Fig. 2 to 4 substantially corresponds to Fig. 8, and the cross section of the semiconductor device PKG taken along line A4-A4 in Fig. 2 to 4 substantially corresponds to Fig. 9. The X and Y directions shown in each plan view are orthogonal to each other.

[0022] The semiconductor device PKG of the present embodiment shown in Figures 1 to 9 is a semiconductor device in the form of a resin-sealed semiconductor package, and in this case, is a semiconductor device in the form of an SOP (Small Outline Package). The configuration of the semiconductor device PKG will be described below with reference to Figures 2 to 9.

[0023] The semiconductor device PKG of this embodiment shown in Figures 2 to 9 has die pads (chip mounting portions) DPC, DPH, and DPL, semiconductor chips CPC, CPH, and CPL mounted on the main surfaces of each of the die pads DPC, DPH, and DPL, metal plates MP1 and MP2, a plurality of wires (bonding wires) BW, a plurality of leads LD, and a sealing portion (sealing body) MR that seals these.

[0024] The sealing portion MR as a resin sealing portion is made of a resin material such as a thermosetting resin material, and may contain a filler, etc. For example, the sealing portion MR can be formed using an epoxy resin containing a filler.

[0025] The sealing portion MR has a main surface (upper surface) MRa, a back surface (lower surface) MRb opposite to the main surface MRa, and side surfaces MRc1, MRc2, MRc3, and MRc4 intersecting the main surface MRa and the back surface MRb. The side surfaces MRc1 and MRc3 are approximately parallel to the X direction, and the side surfaces MRc2 and MRc4 are approximately parallel to the Y direction. The main surface MRa and the back surface MRb are each parallel to both the X direction and the Y direction. The planar shape of the sealing portion MR, i.e., the planar shapes of the main surface MRa and the back surface MRb of the sealing portion MR, is, for example, rectangular (oblong), and the dimension of the sealing portion MR in the X direction is greater than the dimension of the sealing portion MR in the Y direction.

[0026] A portion of each of the leads LD is sealed within the sealing portion MR, and another portion protrudes from the side surface of the sealing portion MR to the outside of the sealing portion MR. Hereinafter, the portion of the lead LD located within the sealing portion MR will be referred to as an inner lead portion, and the portion of the lead LD located outside the sealing portion MR will be referred to as an outer lead portion. A plating layer (not shown), such as a solder plating layer, may be formed on the outer lead portion of the lead LD.

[0027] The semiconductor device PKG of this embodiment has a structure in which a part of each lead LD (outer lead part) protrudes from the side surface of the sealing part MR, and the following description will be based on this structure, but is not limited to this structure. For example, it is also possible to adopt a structure in which each lead LD hardly protrudes from the side surface of the sealing part MR and each lead LD is partially exposed on the back surface MRb of the sealing part MR (SON (Small Outline Nonleaded Package) type structure).

[0028] The plurality of leads LD of the semiconductor device PKG are configured by a plurality of leads LD arranged on the side surface MRc1 of the sealing portion MR and a plurality of leads LD arranged on the side surface MRc3 of the sealing portion MR.

[0029] Each outer lead portion of the multiple leads LD arranged on the side surface MRc1 of the sealing portion MR protrudes from the side surface MRc1 of the sealing portion MR to the outside of the sealing portion MR. Also, each outer lead portion of the multiple leads LD arranged on the side surface MRc3 of the sealing portion MR protrudes from the side surface MRc3 of the sealing portion MR to the outside of the sealing portion MR. The outer lead portion of each lead LD is bent so that the lower surface near the end of the outer lead portion is positioned on approximately the same plane as the back surface MRb of the sealing portion MR. The outer lead portion of the lead LD functions as an external connection terminal portion (external terminal) of the semiconductor device PKG. The multiple leads LD of the semiconductor device PKG include leads LD1, LD2, LD3, LD4, LD5, LD6, LD7, and LD8, which will be described later.

[0030] The die pad DPC is a chip mounting portion on which the semiconductor chip CPC is mounted, the die pad DPH is a chip mounting portion on which the semiconductor chip CPH is mounted, and the die pad DPL is a chip mounting portion on which the semiconductor chip CPL is mounted. The planar shape of each of the die pads DPC, DPH, and DPL is, for example, a rectangle having sides parallel to the X direction and sides parallel to the Y direction.

[0031] The die pads DPH, DPC, and DPL are arranged side by side in this order in the X direction. Therefore, the die pad DPC is arranged between the die pads DPH and DPL in the X direction. The die pads DPH, DPC, and DPL are spaced apart from one another at a predetermined interval, with a part of the sealing portion MR interposed between them.

[0032] The die pads DPC, DPH, DPL and the leads LD are made of a conductor, preferably a metal material such as copper (Cu) or a copper alloy. The die pads DPC, DPH, DPL and the leads LD are preferably made of the same material (the same metal material), which makes it easier to fabricate a lead frame LF (described later) in which the die pads DPC, DPH, DPL and the leads LD are connected, and also makes it easier to manufacture a semiconductor device PKG using the lead frame LF.

[0033] The die pad DPC has a main surface DPCa on the side where the semiconductor chip CPC is mounted and a back surface DPCb on the opposite side. The die pad DPH has a main surface DPHa on the side where the semiconductor chip CPH is mounted and a back surface DPHb on the opposite side. The die pad DPL has a main surface DPLa on the side where the semiconductor chip CPL is mounted and a back surface DPLb on the opposite side.

[0034] At least a portion of each die pad DPC, DPH, DPL is sealed by the sealing portion MR, but in this embodiment, the back surfaces DPCb, DPLb, DPHb of the die pads DPC, DPL, DPH are exposed from the main surface MRa of the sealing portion MR, which allows heat generated during operation of the semiconductor chips CPC, CPH, CPL to be dissipated to the outside of the semiconductor device PKG through the die pads DPC, DPH, DPL.

[0035] In addition, in the die pads DPC, DPH, DPL, leads LD and lead connection portions LB2, LB4, a plating layer (not shown) made of silver (Ag) or the like can be formed in the areas where the semiconductor chips CPC, CPH, CPL are mounted, the areas where the wires BW are connected, and the areas where the metal plates MP1, MP2 are connected.

[0036] Each of the semiconductor chips DPC, DPH, and DPL has a front surface which is one main surface and a back surface which is the opposite main surface.

[0037] A back electrode BEH is formed on the back surface (entire back surface) of the semiconductor chip CPH, and the semiconductor chip CPH is mounted on the main surface DPHa of the die pad DPH via a conductive adhesive material BDH with the back electrode BEH of the semiconductor chip CPH facing the die pad DPH. The back electrode BEH of the semiconductor chip CPH is electrically connected to the die pad DPH via the conductive adhesive material BDH.

[0038] A back electrode BEL is formed on the back surface (entire back surface) of the semiconductor chip CPL, and the semiconductor chip CPL is mounted on the main surface DPLa of the die pad DPL via a conductive adhesive material BDL with the back electrode BEL of the semiconductor chip CPL facing the die pad DPL. The back electrode BEL of the semiconductor chip CPL is electrically connected to the die pad DPL via the conductive adhesive material BDL.

[0039] The semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC via a conductive adhesive BDC, with the back surface of the semiconductor chip CPC facing the die pad DPC. No back surface electrode is formed on the back surface of the semiconductor chip CPC. In this embodiment, the adhesive BDC for the semiconductor chip CPC is conductive, but since the semiconductor chip CPC does not have a back surface electrode, the adhesive BDC for the semiconductor chip CPC may be insulating.

[0040] The semiconductor chips CPC, CPH, and CPL each have a rectangular planar shape, for example. In plan view, the semiconductor chip CPH is included in the main surface DPHa of the die pad DPH, the semiconductor chip CPL is included in the main surface DPLa of the die pad DPHL, and the semiconductor chip CPC is included in the main surface DPCa of the die pad DPC. The semiconductor chips CPC, CPH, and CPL are sealed within the sealing portion MR and are not exposed from the sealing portion MR.

[0041] The back surface electrode BEH of the semiconductor chip CPH is a drain electrode and is electrically connected to the drain of the power MOSFET 1 formed in the semiconductor chip CPH. The back surface electrode BEL of the semiconductor chip CPL is a drain electrode and is electrically connected to the drain of the power MOSFET 2 formed in the semiconductor chip CPL. The adhesive materials BDH and BDL can be a conductive paste-type adhesive material such as silver paste.

[0042] A plurality of pads PDH including a source pad PDHS and a gate pad PDHG are formed on the surface of the semiconductor chip CPH. A plurality of pads PDL including a source pad PDLS and a gate pad PDLG are formed on the surface of the semiconductor chip CPL. A plurality of pads PDC are formed on the surface of the semiconductor chip CPC. Note that the terms "bonding pad," "bonding pad electrode," "pad electrode," or "electrode" will be simply referred to as "pad." The pad PDH including the source pad PDHS is located on the opposite side of the semiconductor chip CPH from the back surface electrode BEH, and therefore can be regarded as a front surface electrode of the semiconductor chip CPH. The pad PDL including the source pad PDLS is located on the opposite side of the semiconductor chip CPL from the back surface electrode BEL, and therefore can be regarded as a front surface electrode of the semiconductor chip CPL. The pad PDC can be regarded as a front surface electrode of the semiconductor chip CPC.

[0043] The gate pad PDHG of the semiconductor chip CPH is electrically connected to the gate electrode of the power MOSFET 1 formed in the semiconductor chip CPH. The source pad PDHS of the semiconductor chip CPH is electrically connected to the source of the power MOSFET 1 formed in the semiconductor chip CPH. In the semiconductor chip CPH, the planar dimensions (area) of the source pad PDHS are larger than the planar dimensions of each of the pads PDH other than the pad PDHS.

[0044] The gate pad PDLG of the semiconductor chip CPL is electrically connected to the gate electrode of the power MOSFET 2 formed in the semiconductor chip CPL. The source pad PDLS of the semiconductor chip CPL is electrically connected to the source of the power MOSFET 2 formed in the semiconductor chip CPL. In the semiconductor chip CPL, the planar dimensions (area) of the source pad PDLS are larger than the planar dimensions of each of the pads PDL other than the pad PDLS.

[0045] The pads PDC of the semiconductor chip CPC are electrically connected to the control circuit CLC formed within the semiconductor chip CPC through the internal wiring of the semiconductor chip CPC.

[0046] Note that a plurality of unit transistor cells constituting the power MOSFET 1 are formed on the semiconductor substrate constituting the semiconductor chip CPH, and the power MOSFET 1 is formed by connecting these plurality of unit transistor cells in parallel. Also, a plurality of unit transistor cells constituting the power MOSFET 2 are formed on the semiconductor substrate constituting the semiconductor chip CPL, and the power MOSFET 2 is formed by connecting these plurality of unit transistor cells in parallel. Each unit transistor cell is, for example, a trench-gate MISFET. In each of the semiconductor chips CPH and CPL, current between the source and drain of the power MOSFET flows in the thickness direction of the semiconductor substrate constituting the semiconductor chip.

[0047] The pads PDH (including the gate pad PDHG) other than the source pad PDHS of the semiconductor chip CPH are each electrically connected to the pad PDC of the semiconductor chip CPC via a wire BW. That is, one end of the wire BW is connected to each of the pads PDH other than the source pad PDHS, and the other end of the wire BW is connected to the pad PDC of the semiconductor chip CPC. The pads PDL (including the gate pad PDLG) other than the source pad PDLS of the semiconductor chip CPL are each electrically connected to the pad PDC of the semiconductor chip CPC via a wire BW. That is, one end of the wire BW is connected to each of the pads PDL other than the source pad PDLS, and the other end of the wire BW is connected to the pad PDC of the semiconductor chip CPC.

[0048] The wire (bonding wire) BW is a conductive wire. Specifically, the wire BW is made of metal, and gold (Au) wire, copper (Cu) wire, or aluminum (Al) wire can be suitably used. The wire BW is sealed within the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD, the connection point of the wire BW is an inner lead portion located within the sealing portion MR.

[0049] The source pad PDHS of the semiconductor chip CPH is electrically connected to the lead connecting portion (conductor portion) LB2 through the metal plate MP1. That is, the metal plate MP1 is bonded to the source pad PDHS of the semiconductor chip CPH through a conductive adhesive material BD1, and is also bonded to the lead connecting portion LB2 through a conductive adhesive material BD2.

[0050] The source pad PDLS of the semiconductor chip CPL is electrically connected to the lead connecting portion (conductor portion) LB4 through the metal plate MP2. That is, the metal plate MP2 is bonded to the source pad PDLS of the semiconductor chip CPL via a conductive adhesive material BD3, and is also bonded to the lead connecting portion LB4 via a conductive adhesive material BD4.

[0051] By using the metal plate MP1 instead of a wire to electrically connect the source pad PDHS of the semiconductor chip CPH to the lead LD2, it is possible to reduce the on-resistance of the power MOSFET 1. Also, by using the metal plate MP2 instead of a wire to electrically connect the source pad PDLS of the semiconductor chip CPL to the lead LD4, it is possible to reduce the on-resistance of the power MOSFET 2. This makes it possible to reduce the package resistance and the conduction loss.

[0052] The metal plates MP1 and MP2 are conductive plates made of a conductor, preferably made of a metal material with high electrical and thermal conductivity, such as copper (Cu), a copper (Cu) alloy, aluminum (Al), or an aluminum (Al) alloy. The dimensions (width) of each of the metal plates MP1 and MP2 in the X and Y directions are greater than the diameter of the wire BW. The adhesives BD1, BD2, BD3, and BD4 can be conductive paste-type adhesives, such as silver paste.

[0053] Among the multiple pads PDC of the semiconductor chip CPC, the pads PDC that are not connected to either the pads PDH of the semiconductor chip CPH or the pads PDL of the semiconductor chip CPL are electrically connected to leads LD5 of the multiple leads LD of the semiconductor device PKG through wires BW. That is, one end of a wire BW is connected to each of the pads PDC of the semiconductor chip CPC that are not connected to either the pads PDH of the semiconductor chip CPH or the pads PDL of the semiconductor chip CPL, and the other end of the wire BW is connected to the inner lead portion of the lead LD5. Each lead LD5 is an isolated lead that is not connected via a conductor to any of the die pads DPC, DPH, DPL, leads LD1, LD2, LD3, LD4, or lead connecting portions LB1, LB2, LB3, LB4.

[0054] The lead connection portion LB2 is integrally connected to a plurality of leads LD2 among the plurality of leads LD of the semiconductor device PKG. Therefore, the lead connection portion LB2 is a conductor portion that connects the inner lead portions of the plurality of leads LD2 to one another and also serves as a conductor portion that connects the metal plate MP1. The plurality of leads LD2 and the lead connection portion LB2 are electrically connected to the source pad PDHS of the semiconductor chip CPH via the metal plate MP1 and conductive adhesives BD1 and BD2, and are therefore electrically connected to the source of the power MOSFET 1 formed within the semiconductor chip CPH. Therefore, the plurality of leads LD2 are leads for the source of the high-side power MOSFET 1 and correspond to the terminal TE2.

[0055] The lead connection portion LB4 is integrally connected to a plurality of leads LD4 among the plurality of leads LD of the semiconductor device PKG. Therefore, the lead connection portion LB4 is a conductor portion that connects the inner lead portions of the plurality of leads LD4 to each other and also serves as a conductor portion that connects the metal plate MP2. The plurality of leads LD4 and the lead connection portion LB4 are electrically connected to the source pad PDLS of the semiconductor chip CPL through the metal plate MP2 and conductive adhesives BD3 and BD4, and are therefore electrically connected to the source of the power MOSFET 2 formed in the semiconductor chip CPL. Therefore, the plurality of leads LD4 are source leads of the power MOSFET 2 for the low side and correspond to the terminal TE4. The lead connection portions LB2 and LB4 are sealed within the sealing portion MR and are not exposed from the sealing portion MR.

[0056] By connecting the multiple leads LD2 together to the lead connecting portion LB2, the volume can be increased compared to when the multiple leads LD2 are divided, thereby reducing the wiring resistance and the conduction loss of the power MOSFET 1. Furthermore, by connecting the multiple leads LD4 together to the lead connecting portion LB4, the volume can be increased compared to when the multiple leads LD4 are divided, thereby reducing the wiring resistance and the conduction loss of the power MOSFET 2.

[0057] Among the leads LD of the semiconductor device PKG, the leads LD1 are integrally formed with the die pad DPH. Therefore, the leads LD1 are electrically connected to the die pad DPH and electrically connected to the back electrode BEH of the semiconductor chip CPH via the die pad DPH and the conductive adhesive material BDH. Therefore, the leads LD1 are leads for the drain of the high-side power MOSFET 1 and correspond to the terminal TE1.

[0058] Furthermore, among the multiple leads LD of the semiconductor device PKG, the multiple leads LD3 are integrally formed with the die pad DPL. Therefore, the multiple leads LD3 are electrically connected to the die pad DPL and electrically connected to the back electrode BEL of the semiconductor chip CPL via the die pad DPL and the conductive adhesive BDL. Therefore, the multiple leads LD3 are drain leads of the above-mentioned low-side power MOSFET 2 and correspond to the above-mentioned terminal TE3. Therefore, when the semiconductor device PKG is viewed alone, the multiple leads LD2 and the multiple leads LD4 of the semiconductor device PKG are not electrically connected. However, when the semiconductor device PKG is mounted on a wiring board or the like to form the inverter circuit INV with the semiconductor device PKG, the multiple leads LD2 and the multiple leads LD4 of the semiconductor device PKG are electrically connected via the wiring of the wiring board or the like.

[0059] Furthermore, a plurality of leads LD8 are integrally connected to the die pad DPC. These leads LD8 are used to support the die pad DPC on the frame of a lead frame LF (described later) when manufacturing the semiconductor device PKG. Therefore, the leads LD8 are not electrically connected to any of the pads of the semiconductor chips CPC, CPH, and CPL, and are also not electrically connected to the back electrodes BEH and BEL of the semiconductor chips CPH and CPL.

[0060] Furthermore, a lead LD6 is integrally connected to the die pad DPH, and a lead LD7 arranged on the side surface MRc1 of the sealing portion MR is integrally connected to the die pad DPL. Furthermore, a suspension lead TL is integrally connected to each of the die pads DPH and DPL. The leads LD6 and LD7 and the suspension lead TL are used to support the die pads DPH and DPL on the frame of a lead frame LF (described later) when manufacturing the semiconductor device PKG. The suspension lead TL does not protrude from the side surface of the sealing portion MR.

[0061] <About the manufacturing process of semiconductor devices> Next, a manufacturing process (assembly process) of the semiconductor device PKG of this embodiment will be described. FIG. 10 is a process flow diagram showing the manufacturing process of the semiconductor device PKG of this embodiment. FIGS. 11 to 27 are plan views or cross-sectional views of the semiconductor device PKG of this embodiment during the manufacturing process. Of these, FIGS. 11 to 13, 15, 16, 19, 20, 23, and 24 are plan views. FIGS. 14 and 27 are cross-sectional views taken along the line A3-A3 in FIGS. 2 to 4, FIGS. 17, 21, and 25 are cross-sectional views taken along the line A1-A1 in FIGS. 2 to 4, and FIGS. 18, 22, and 26 are cross-sectional views taken along the line A2-A2 in FIGS. 2 to 4.

[0062] To manufacture the semiconductor device PKG, first, a lead frame LF is prepared (step S1 in FIG. 10), and then the semiconductor chips CPC, CPH, and CPL are prepared (step S2 in FIG. 10). Either the lead frame LF or the semiconductor chips CPC, CPH, and CPL may be prepared first, or they may be prepared simultaneously.

[0063] As shown in FIG. 11 , the lead frame LF integrally includes a frame (not shown), die pads DPC, DPH, and DPL, multiple leads LD, lead connecting portions LB1, LB2, LB3, and LB4, and a suspension lead TL. One end of each lead LD is connected to the frame. Each die pad DPC, DPH, and DPL is connected to the frame via some of the leads LD. Specifically, the die pad DPC is connected to the frame by a lead LD8, the die pad DPH is connected to the frame by leads LD1 and LD6 and a suspension lead TL, and the die pad DPL is connected to the frame by leads LD3 and LD7 and a suspension lead TL. The lead frame LF is made of a metal material primarily composed of copper (Cu), for example, and more specifically, copper (Cu) or a copper (Cu) alloy. FIG. 11 shows a region of the lead frame LF from which one semiconductor device PKG is manufactured.

[0064] Until the molding process in step S12 described below is performed to form the sealing portion MR, the lead frame LF undergoes the following manufacturing process (assembly process) with the main surfaces DPCa, DPHa, DPLa of the die pads DPC, DPH, DPL facing upward.

[0065] Next, as shown in Fig. 12, adhesive material BDC, which is a die bonding material, is supplied (applied) onto the main surface DPCa of the die pad DPC of the lead frame LF (step S3 in Fig. 10). Note that in the case of Fig. 12, adhesive material BDC is supplied to one location on the main surface DPCa of the die pad DPC, but adhesive material BDC can also be supplied to multiple locations on the main surface DPCa of the die pad DPC.

[0066] 13 and 14, the semiconductor chip CPC is mounted (placed) on the main surface DPCa of the die pad DPC of the lead frame LF via the adhesive material BDC (step S4 in FIG. 10). In step S4, the semiconductor chip CPC is mounted so that its back surface faces the main surface DPCa of the die pad DPC. As a result, when step S4 is performed, the adhesive material BDC is interposed between the back surface of the semiconductor chip CPC and the main surface DPCa of the die pad DPC of the lead frame LF.

[0067] The adhesive BDC is a conductive paste-type adhesive, and silver paste can be suitably used. The adhesive BDC is a thermosetting adhesive, but at the stages of steps S3 and S4, the adhesive BDC has not yet hardened and is in a paste state. Note that an insulating paste-type adhesive can also be used for the adhesive BDC.

[0068] 15, an adhesive material BDH, which is a die bonding material, is supplied (applied) onto the main surface DPHa of the die pad DPH of the lead frame LF, and an adhesive material BDL, which is a die bonding material, is supplied (applied) onto the main surface DPLa of the die pad DPL of the lead frame LF (step S5 in FIG. 10). In step S5, either the adhesive material BDH or the adhesive material BDL may be supplied first.

[0069] 15, the adhesive material BDH is supplied to one location on the main surface DPHa of the die pad DPH, but it is also possible to supply the adhesive material BDH to multiple locations on the main surface DPHa of the die pad DPH. Also, in the case of Fig. 15, the adhesive material BDL is supplied to one location on the main surface DPLa of the die pad DPL, but it is also possible to supply the adhesive material BDL to multiple locations on the main surface DPLa of the die pad DPL.

[0070] Next, as shown in Figures 16 to 18, the semiconductor chip CPH is mounted (placed) on the main surface DPHa of the die pad DPH of the lead frame LF via adhesive material BDH, and the semiconductor chip CPL is mounted (placed) on the main surface DPLa of the die pad DPL of the lead frame LF via adhesive material BDL (step S6 of Figure 10).

[0071] In step S6, the semiconductor chip CPH is mounted so that the back electrode BEH of the semiconductor chip CPH faces the main surface DPHa of the die pad DPH, and the semiconductor chip CPL is mounted so that the back electrode BEL of the semiconductor chip CPL faces the main surface DPLa of the die pad DPL. Thus, when step S6 is performed, the adhesive material BDH is interposed between the back electrode BEH of the semiconductor chip CPH and the main surface DPHa of the die pad DPH of the lead frame LF, and the adhesive material BDL is interposed between the back electrode BEL of the semiconductor chip CPL and the main surface DPLa of the die pad DPL of the lead frame LF. In step S6, either the semiconductor chip CPH or the semiconductor chip CPL may be mounted first.

[0072] The adhesives BDH and BDL are conductive paste-type adhesives, and silver paste can be suitably used. The adhesives BDH and BDL are thermosetting adhesives, but at the stages of steps S5 and S6, the adhesives BDH and BDL are not yet hardened and are in a paste state.

[0073] Furthermore, the adhesive materials BDH and BDL may be different types of adhesive materials (adhesives made of different materials), but are preferably the same type of adhesive material (adhesives made of the same material). This facilitates the die bonding process of the semiconductor chips CPH and CPL and reduces the manufacturing cost of the semiconductor device. Furthermore, since the back electrodes BEH and BEL of the semiconductor chips CPH and CPL need to be electrically connected to the die pads DPH and DPL, respectively, the adhesive materials BDH and BDL need to be conductive adhesive materials. On the other hand, since the semiconductor chip CPC does not have a back electrode, it is not essential to electrically connect the back surface of the semiconductor chip CPC to the die pad DPC. Therefore, the adhesive material BDC for the semiconductor chip CPC may be conductive or insulating. Therefore, the adhesive material BDC may be a different type of adhesive material (adhesives made of different materials) from the adhesive materials BDH and BDL. However, if adhesive BDC, adhesive BDH, and adhesive BDL are the same type of adhesive (adhesive made of the same material), only one type of adhesive is required for die bonding of the semiconductor chips CPC, CPH, and CPL, making it easier to perform the die bonding process of the semiconductor chips CPC, CPH, and CPL and reducing the manufacturing costs of the semiconductor device.

[0074] For this reason, it is more preferable to use the same type of conductive paste adhesive for the adhesives BDC, BDH, and BDL, and silver paste can be suitably used.

[0075] Next, heat treatment is performed to harden the adhesive materials BDC, BDH, and BDL (step S7 in FIG. 10). Immediately before the heat treatment of step S7, the adhesive materials BDC, BDH, and BDL are barely hardened and remain in a paste-like state. However, the heat treatment of step S7 hardens the adhesive materials BDC, BDH, and BDL. However, at the stage where the heat treatment of step S7 is completed, the adhesive materials BDC, BDH, and BDL are not completely (sufficiently) hardened but are in a semi-hardened state. When the heat treatment of step S7 is performed, the adhesive materials BDC, BDH, and BDL are in a semi-hardened state. Therefore, the semiconductor chip CPC is fixed to the die pad DPC by the semi-hardened adhesive BDC, the semiconductor chip CPH is fixed to the die pad DPH by the semi-hardened adhesive BDH, and the semiconductor chip CPL is fixed to the die pad DPL by the semi-hardened adhesive BDL.

[0076] The adhesives BDC, BDH, and BDL that have been hardened (semi-hardened) by the heat treatment in step S7 can be further hardened by the heat treatment in the subsequent step S10, so the heat treatment in step S7 can be performed in a shorter time and at a lower temperature than the heat treatment in the subsequent step S10.

[0077] 19, an adhesive material BD1 is supplied (applied) onto the source pads PDHS of the semiconductor chip CPH, an adhesive material BD3 is supplied (applied) onto the source pads PDHL of the semiconductor chip CPL, an adhesive material BD2 is supplied (applied) onto the lead coupling portions LB2, and an adhesive material BD4 is supplied (applied) onto the lead coupling portions LB4 (step S8 in FIG. 10). In step S8, the adhesive materials BD1, BD2, BD3, and BD4 can be supplied in any order.

[0078] In the case of Fig. 19, the adhesive material BD1 is supplied to one location on the surface of the source pad PDHS of the semiconductor chip CPH, but the adhesive material BD1 can also be supplied to multiple locations. Also, in the case of Fig. 19, the adhesive material BD3 is supplied to one location on the surface of the source pad PDHS of the semiconductor chip CPL, but the adhesive material BD3 can also be supplied to multiple locations. Also, in the case of Fig. 19, the adhesive material BD2 is supplied to one location on the surface of the lead coupling portion LB2, but the adhesive material BD2 can also be supplied to multiple locations. Also, in the case of Fig. 19, the adhesive material BD4 is supplied to one location on the surface of the lead coupling portion LB4, but the adhesive material BD4 can also be supplied to multiple locations.

[0079] Next, as shown in FIGS. 20 to 22, metal plates MP1 and MP2 are arranged (mounted) (step S9 in FIG. 10). In step S9, the metal plate MP1 is arranged so that it faces the source pad PDHS of the semiconductor chip CPH via the adhesive material BD1, and so that it faces the lead coupling portion LB2 via the adhesive material BD2. In addition, in step S9, the metal plate MP2 is arranged so that it faces the source pad PDLS of the semiconductor chip CPL via the adhesive material BD3, and so that it faces the lead coupling portion LB4 via the adhesive material BD4. The metal plate MP1 is arranged over the source pad PDHS and the lead coupling portion LB2 of the semiconductor chip CPH, and the metal plate MP2 is arranged over the source pad PDLS and the lead coupling portion LB4 of the semiconductor chip CPL. As a result, when step S9 is performed, an adhesive material BD1 is interposed between the metal plate MP1 and the source pad PDHS of the semiconductor chip CPH, an adhesive material BD2 is interposed between the metal plate MP1 and the lead connecting portion LB2, an adhesive material BD3 is interposed between the metal plate MP2 and the source pad PDHL of the semiconductor chip CPL, and an adhesive material BD4 is interposed between the metal plate MP2 and the lead connecting portion LB4. In step S9, either the metal plate MP1 or the metal plate MP2 may be placed first.

[0080] The adhesives BD1, BD2, BD3, and BD4 are conductive paste-type adhesives, and silver paste is preferably used. The adhesives BD1, BD2, BD3, and BD4 are thermosetting adhesives, but at the stage of steps S8 and S9, the adhesives BD1, BD2, BD3, and BD4 have not yet hardened.

[0081] Furthermore, adhesives BD1, BD2, BD3, and BD4 may be different types of adhesives (adhesives made of different materials), but are preferably the same type of adhesives (adhesives made of the same material), which facilitates the mounting process of metal plates MP1 and MP2 and reduces the manufacturing cost of the semiconductor device.

[0082] Next, a heat treatment is performed to harden the adhesive materials BD1, BD2, BD3, BD4, BDC, BDH, and BDL (Step S10 in FIG. 10).

[0083] The heat treatment in step S10 hardens the adhesive materials BD1, BD2, BD3, and BD4, and they become sufficiently hardened (cured). Therefore, when the heat treatment in step S10 is performed, the metal plate MP1 is fixed (bonded) to the source pad PDHS of the semiconductor chip CPH by the hardened adhesive material BD1, and is fixed (bonded) to the lead coupling portion LB2 by the hardened adhesive material BD2. Furthermore, when the heat treatment in step S10 is performed, the metal plate MP2 is fixed (bonded) to the source pad PDHL of the semiconductor chip CPL by the hardened adhesive material BD3, and is fixed (bonded) to the lead coupling portion LB4 by the hardened adhesive material BD4. The metal plate MP1 is electrically connected to the source pad PDHS of the semiconductor chip CPH via the conductive adhesive material BD1, and is electrically connected to the lead coupling portion LB2 via the conductive adhesive material BD2. The metal plate MP2 is electrically connected to the source pad PDLS of the semiconductor chip CPL via a conductive adhesive material BD3, and is also electrically connected to the lead connecting portion LB4 via a conductive adhesive material BD4. As a result, the source pad PDHS of the semiconductor chip CPH is electrically connected to the lead connecting portion LB2 and the plurality of lead portions LD2 integrally connected thereto via the conductive adhesive materials BD1 and BD2 and the metal plate MP1. The source pad PDLS of the semiconductor chip CPL is electrically connected to the lead connecting portion LB4 and the plurality of lead portions LD4 integrally connected thereto via the conductive adhesive materials BD3 and BD4 and the metal plate MP2.

[0084] The adhesive materials BDC, BDH, and BDL are semi-cured by the heat treatment in step S7, and maintain the semi-cured state until immediately before the heat treatment in step S10. Then, the heat treatment in step S10 further hardens the adhesive materials BDC, BDH, and BDL, and they reach a sufficiently (completely) cured state (cured state). Therefore, when the heat treatment in step S10 is performed, the semiconductor chip CPC is firmly fixed (bonded) to the die pad DPC by the cured adhesive material BDC, the semiconductor chip CPH is firmly fixed (bonded) to the die pad DPH by the cured adhesive material BDH, and the semiconductor chip CPL is firmly fixed (bonded) to the die pad DPL by the cured adhesive material BDL. The back electrode BEH of the semiconductor chip CPH is electrically connected to the die pad DPH via the conductive adhesive material BDH, and the back electrode BEL of the semiconductor chip CPL is electrically connected to the die pad DPL via the conductive adhesive material BDL.

[0085] The heat treatment in step S10 is performed for a longer time and at a higher temperature than the heat treatment in step S7. This allows the adhesive materials BD1, BD2, BD3, BD4, BDC, BDH, and BDL to be sufficiently hardened by the heat treatment in step S10, so that the wire bonding step in step S11 and the molding step in step S12, which will be described later, can be performed in a state in which the semiconductor chips CPC, CPH, and CPL and the metal plates MP1 and MP2 are firmly fixed. This allows the wire bonding step in step S11 and the molding step in step S12, which will be described later, to be performed accurately.

[0086] Next, as shown in Fig. 23, a wire bonding step is performed (step S11 in Fig. 10). In the wire bonding step of step S11, the pads PDH (pads PDH other than pads PDHS) of the semiconductor chip CPH and the pads PDC of the semiconductor chip CPC, the pads PDL (pads PDL other than pads PDLS) of the semiconductor chip CPL and the pads PDC of the semiconductor chip CPC, and the pads PDC of the semiconductor chip CPC and the leads LD5 of the lead frame LF are electrically connected via wires BW, respectively.

[0087] A plurality of types of wires made of different materials can also be used as the wires BW. For example, the pads PDC of the semiconductor chip CPC and the leads LD5 of the lead frame LF are electrically connected to each other via wires BW made of copper (Cu). The pads PDH of the semiconductor chip CPH and the pads PDC of the semiconductor chip CPC, and the pads PDL of the semiconductor chip CPL and the pads PDC of the semiconductor chip CPC are electrically connected to each other via wires BW made of gold (Au).

[0088] Next, resin sealing is performed by a molding process (resin molding process), and as shown in Figures 24 to 27, the semiconductor chips CPC, CPH, and CPL, the multiple wires BW connected thereto, and the metal plates MP1 and MP2 are sealed with a sealing portion MR (step S12 in Figure 10). The molding process of step S12 forms the sealing portion MR that seals the semiconductor chips CPC, CPH, and CPL, the die pads DPC, DPH, and DPL, the multiple wires BW, the metal plates MP1 and MP2, the lead connecting portions LB1, LB2, LB3, and LB4, and the inner lead portions of the multiple leads LD. In the molding process of step S12, the sealing portion MR is formed so that the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are exposed from the main surface MRa of the sealing portion MR.

[0089] Note that the steps up to the molding step in step S12 are performed with the main surfaces DPCa, DPHa, and DPLa of the die pads DPC, DPH, and DPL facing upward. Therefore, at the stage where the molding step in step S12 is performed to form the sealing portion MR, the back surface MRb of the sealing portion MR faces upward. However, when the manufactured semiconductor device PKG is mounted on a wiring board or the like, the semiconductor device PKG is mounted on the wiring board so that the back surface MRb of the sealing portion MR faces the wiring board.

[0090] Next, a plating layer (not shown) is formed as needed on the outer lead portion of the lead LD exposed from the sealing portion MR. After that, the lead frame LF is turned upside down (front and back) together with the sealing portion MR, and then the leads LD are cut at predetermined positions outside the sealing portion MR to separate them from the frame of the lead frame LF (step S13 in FIG. 10).

[0091] Next, the outer lead portions of the leads LD protruding from the sealing portion MR are bent (lead processing, lead forming) (step S14 in FIG. 10).

[0092] In this manner, the semiconductor device PKG shown in FIGS. 2 to 9 is manufactured.

[0093] <About the process of the review> FIG. 28 is a process flow diagram showing the manufacturing process of a semiconductor device in an example studied by the present inventors, and corresponds to FIG. 10 above.

[0094] The example in Fig. 28 differs from the present embodiment (Fig. 10) in that the example in Fig. 28 does not include the heat treatment step of step S7. That is, in the example in Fig. 28, not only the adhesives BD1, BD2, BD3, and BD4 but also the adhesives BDC, BDH, and BDL described above are barely hardened and maintain a paste state until immediately before the heat treatment of step S10, and the heat treatment of step S10 causes the paste-like adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL to sufficiently harden and reach a hardened state.

[0095] However, according to the study by the present inventors, it has been found that the following problem occurs in the case of the study example of FIG.

[0096] That is, the back electrode BEH of the semiconductor chip CPH and the die pad DPH are electrically connected via a conductive adhesive material BDH, but in the case of the example shown in Fig. 28, there is a risk that the electrical resistance and thermal resistance between the back electrode BEH of the semiconductor chip CPH and the die pad DPH will increase. Also, the back electrode BEL of the semiconductor chip CPL and the die pad DPL are electrically connected via a conductive adhesive material BDL, but in the case of the example shown in Fig. 28, there is a risk that the electrical resistance and thermal resistance between the back electrode BEL of the semiconductor chip CPL and the die pad DPL will increase. The reason for this will be explained below.

[0097] The adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL are all conductive paste-type adhesives. Conductive paste-type adhesives contain a resin material (more specifically, a thermosetting resin material) and multiple conductive fillers (conductive particles), and have a configuration in which the multiple conductive fillers (conductive particles) are dispersed in the resin material (thermosetting resin material). For this reason, solder paste is not a conductive paste-type adhesive.

[0098] 29 is a partially enlarged cross-sectional view of a portion of FIG. 17, showing the state in which the semiconductor chip CPH is mounted on the die pad DPH via a conductive paste-type adhesive BDH in step S6. In FIG. 29, the conductive paste-type adhesive BDH is interposed between the back electrode BEH of the semiconductor chip CPH and the die pad DPH, and the adhesive BDH includes a resin material (thermosetting resin material) RS and a plurality of conductive fillers (conductive particles) FL dispersed in the resin material RS. Electrical connection is achieved through the plurality of conductive fillers in the adhesive. For example, the back electrode BEH of the semiconductor chip CPH and the die pad DPH are electrically connected through the plurality of conductive fillers FL contained in the adhesive BDH.

[0099] The structure in which multiple conductive fillers FL are dispersed in a resin material RS is common not only to the adhesive BDH but also to the adhesives BD1, BD2, BD3, BD4, BDC, and BDL. The conductive fillers FL are made of conductive particles (preferably metal particles). When the conductive paste-type adhesive is a silver paste, the conductive fillers FL are silver fillers made of silver. The shape of the conductive fillers FL can be selected from various shapes, such as spherical or flake-like, as needed. However, since conductivity is not essential for the adhesive BDC, it may not contain the conductive fillers FL.

[0100] After mounting the semiconductor chips CPH, CPL on the die pads DPH, DPL via the adhesive materials BDH, BDL in step S6, it takes a considerable amount of time before starting the heat treatment in step S10. This is because, after mounting the semiconductor chips CPH, CPL in step S6 and before the heat treatment in step S10, there are two steps, a step of supplying adhesive materials BD1, BD2, BD3, BD4 in step S8 and a step of arranging metal plates MP1, MP2 in step S9, and these steps require a considerable amount of time.

[0101] When step S6 is performed, an adhesive material BDH is interposed between the back electrode BEH of the semiconductor chip CPH and the die pad DPH, and an adhesive material BDL is interposed between the back electrode BEL of the semiconductor chip CPL and the die pad DPL (see FIGS. 17, 18, and 29). In the case of an example (FIG. 28) in which the heat treatment of step S7 is not performed, the adhesive materials BDH and BDL remain paste-like until the heat treatment of step S10 is performed. Therefore, after step S6 and before the heat treatment of step S10, the conductive filler FL gradually settles in the paste-like adhesive BDH interposed between the back electrode BEH of the semiconductor chip CPH and the die pad DPH. Furthermore, the conductive filler FL gradually settles in the paste-like adhesive BDL interposed between the back electrode BEL of the semiconductor chip CPL and the die pad DPL. 28, the heat treatment in step S10 is performed after the conductive filler FL has settled to a certain extent in the adhesive BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL, thereby hardening the thermosetting resin contained in the adhesive BDH, BDL. As a result, in the semiconductor device manufactured according to the example of FIG. 28, the adhesive BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL has a lower conductive filler content on the side closer to the back electrodes BEH, BEL of the semiconductor chips CPH, CPL than on the side closer to the die pads DPH, DPL. This increases the electrical resistance and thermal resistance between the back electrodes BEH of the semiconductor chip CPH and the die pad DPH, and also increases the electrical resistance and thermal resistance between the back electrodes BEL of the semiconductor chip CPL and the die pad DPL. This leads to a decrease in the performance of the semiconductor device PKG. In order to improve the performance of the semiconductor device PKG, it is desirable to reduce the electrical resistance and thermal resistance between the back electrode BEH of the semiconductor chip CPH and the die pad DPH, and also to reduce the electrical resistance and thermal resistance between the back electrode BEL of the semiconductor chip CPL and the die pad DPL.

[0102] <Main features and effects> One of the main features of this embodiment is that in the manufacturing process of the semiconductor device of this embodiment, after the semiconductor chips CPH, CPL are mounted on the die pads DPH, DPL via adhesive materials BDH, BDL in step S6 so that the back electrodes BEH, BEL of the semiconductor chips CPH, CPL face the die pads DPH, DPL, heat treatment is performed in step S7 before steps S8 and S9 are performed. The adhesive materials BDH, BDL are hardened by the heat treatment in step S7 and then further hardened by the heat treatment in step S10.

[0103] The heat treatment in step S7 is performed to harden to some extent the adhesive materials BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL. Because the heat treatment in step S7 hardens the adhesive materials BDH, BDL to some extent, it is possible to prevent the conductive filler FL from settling in the adhesive materials BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL between the end of the heat treatment in step S7 and the heat treatment in step S10. Therefore, even if a considerable amount of time is required between the heat treatment in step S7 and the heat treatment in step S10 due to the execution of steps S8 and S9, it is possible to prevent the conductive filler FL from settling in the adhesive materials BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL. Therefore, when the conductive filler FL is dispersed almost uniformly in the adhesive materials BDH and BDL, the heat treatment in step S10 can be performed to sufficiently harden the resin material (thermosetting resin) RS contained in the adhesive materials BDH and BDL.

[0104] Therefore, in the semiconductor device PKG manufactured according to this embodiment, the conductive filler is dispersed almost uniformly in each of the adhesive materials BDH and BDL interposed between the back electrodes BEH and BEL of the semiconductor chips CPH and CPL and the die pads DPH and DPL. The ratio of the conductive filler can be made almost the same on the side closer to the back electrodes BEH and BEL of the semiconductor chips CPH and CPL and on the side closer to the die pads DPH and DPL. This reduces the electrical resistance and thermal resistance between the back electrode BEH of the semiconductor chip CPH and the die pad DPH, and also reduces the electrical resistance and thermal resistance between the back electrode BEL of the semiconductor chip CPL and the die pad DPL. This improves the performance of the semiconductor device PKG. For example, the conduction resistance (on-resistance) when the power MOSFET 1 in the semiconductor chip CPH is turned on can be reduced. Furthermore, the conduction resistance (on-resistance) when the power MOSFET 2 in the semiconductor chip CPL is turned on can be reduced. Furthermore, heat generated in the semiconductor chips CPH, CPL is easily conducted to the die pads DPH, DPL via the adhesive materials BDH, BDL, and is easily dissipated from the die pads DPH, DPL to the outside of the semiconductor device PKG. This improves the heat dissipation characteristics of the semiconductor device PKG. Furthermore, it is possible to suppress or prevent the characteristics of the semiconductor device PKG from varying (fluctuations) for each semiconductor device PKG. Furthermore, it is possible to suppress or prevent the characteristics of the semiconductor device PKG from fluctuating with temperature.

[0105] However, if the heat treatment in step S7 takes too long, the manufacturing time for the semiconductor device will be extended, resulting in a decrease in throughput. Since the adhesive materials BDH and BDL can be hardened to a certain extent by the heat treatment in step S7 and then further hardened by the heat treatment in step S10 to a sufficiently hardened state, the heat treatment in step S7 only needs to harden the adhesive materials BDH and BDL to an extent that prevents the conductive filler from settling in the adhesive materials BDH and BDL.

[0106] Therefore, in this embodiment, the heat treatment time of step S7 is set shorter than that of step S10. More specifically, the heat treatment time of step S7 is preferably set to be half or less of that of step S10. This shortens the time required for the heat treatment of step S7, thereby reducing the manufacturing time of the semiconductor device and preventing a decrease in throughput. Furthermore, even if the heat treatment time of step S7 is shorter than that of step S10, and the adhesives BDH and BDL are cured to a lower degree by the heat treatment of step S7, this does not pose a problem as long as it prevents the conductive filler from settling in the adhesives BDH and BDL, and the adhesives BDH and BDL can be further cured by the heat treatment of step S10. The heat treatment in step S10 allows the adhesive materials BDH and BDL to be sufficiently hardened, and the wire bonding process in step S11 and the molding process in step S12 can be performed with the adhesive materials BDH and BDL in a sufficiently hardened state, so that the wire bonding process in step S11 and the molding process in step S12 can be performed accurately.

[0107] Furthermore, in this embodiment, the heat treatment temperature in step S7 is lower than that in step S10. This makes it possible to suppress or prevent the disappearance (volatilization) of the medicinal layer YZ on the surface of the lead frame LF when the medicinal layer YZ is formed on the surface of the lead frame LF as shown in Figure 30. Therefore, the effect of the medicinal layer YZ on the surface of the lead frame LF can be obtained until the heat treatment in step S10 is performed.

[0108] 30 to 32 are cross-sectional views of the lead frame LF. Of these, Fig. 30 is a cross-sectional view of the lead frame LF prepared in step S1, Fig. 31 is a cross-sectional view of the lead frame LF after the heat treatment in step S7 and before the heat treatment in step S10, and Fig. 32 is a cross-sectional view of the lead frame LF immediately after the heat treatment in step S10.

[0109] A medicinal layer YZ is formed on the surface of the lead frame LF prepared in step S1, as shown in Figure 30. Because the heat treatment temperature in step S7 is low, even after the heat treatment in step S7, the medicinal layer YZ on the surface of the lead frame LF does not disappear and remains almost entirely, as shown in Figure 31. On the other hand, because the heat treatment temperature in step S10 is high, when the heat treatment in step S10 is performed, the medicinal layer YZ on the surface of the lead frame LF disappears (volatilizes), as can be seen in Figure 32, and no medicinal layer YZ remains on the surface of the lead frame LF.

[0110] The medicinal layer YZ on the surface of the lead frame LF is made of, for example, a bleed-out prevention material that prevents the adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL from spreading. Forming the medicinal layer YZ made of a bleed-out prevention material on the surface of the lead frame LF (die pads DPC, DPH, and DPL and lead connecting portions LB2 and LB4) can prevent the adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL supplied to the surfaces of the die pads DPC, DPH, and DPL and lead connecting portions LB2 and LB4 of the lead frame LF from seeping out (preventing adhesive bleed-out). That is, if the temperature of the heat treatment in step S7 is too high, the medicinal layer YZ on the surfaces of the lead connecting portions LB2 and LB4 may disappear due to the heat treatment in step S7, which may cause the adhesives BD2 and BD4 supplied to the lead connecting portions LB2 and LB4 in step S8 to seep out (leading to adhesive bleed-out). This is undesirable because the seeped adhesive may impair the adhesion of the sealing resin (sealing portion MR) or may even reach the back surface of the lead frame LF, resulting in poor appearance of the semiconductor device. Therefore, if a medicinal layer YZ made of a bleed-out prevention material is formed on the surface of the lead frame LF, it is desirable that the medicinal layer YZ remain on the surface of the lead frame LF when steps S8 and S9 are performed. In this embodiment, the heat treatment temperature in step S7 is lowered to prevent or suppress the disappearance of the medicinal layer YZ on the surface of the lead frame LF during the heat treatment in step S7. Therefore, steps S8 and S9 can be performed with the medicinal layer YZ remaining on the surface of the lead frame LF. This, for example, can prevent or suppress deviation of the positions of the metal plates MP1 and MP2, which were placed in step S9 and fixed in step S10, from their predetermined design positions.

[0111] Furthermore, because the heat treatment temperature in step S10 is higher than that in step S7, there is a high possibility that the medicinal layer YZ on the surface of the lead frame LF will disappear (volatilize) due to the heat treatment in step S10. However, because the adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL are sufficiently cured in step S10, no particular problem occurs even if the medicinal layer YZ (e.g., bleed-out prevention material) on the surface of the lead frame LF does not remain after the heat treatment in step S10 is completed. Furthermore, by setting the heat treatment temperature in step S10 higher than that in step S7, the adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL can be sufficiently cured by the heat treatment in step S10, so that the wire bonding process in step S11 and the molding process in step S12 can be performed accurately.

[0112] To give an example of the heat treatment times for steps S7 and S10, in step S7, the heat treatment time can be, for example, about 1 hour to 2.5 hours, and the heat treatment temperature can be, for example, about 80°C to 120°C, while in step S10, the heat treatment time can be, for example, about 2 hours to 5 hours, and the heat treatment temperature can be, for example, about 160°C to 250°C.

[0113] (Embodiment 2) 33 is a process flow diagram showing the manufacturing process of the semiconductor device PKG of the present embodiment 2, and corresponds to Fig. 10 of the above-mentioned embodiment 1. The structure of the semiconductor device PKG of the present embodiment 2 is similar to that of the semiconductor device PKG of the above-mentioned embodiment 1, so repeated explanation thereof will be omitted here.

[0114] The manufacturing process of the second embodiment (FIG. 33) will be described below, focusing on the differences from the manufacturing process of the first embodiment (FIG. 10).

[0115] In the second embodiment, similarly to the first embodiment, a lead frame LF is prepared in step S1, and semiconductor chips CPC, CPH, and CPL are prepared in step S2.

[0116] Next, in the present embodiment 2, after steps S1 and S2 and before steps S3 and S4, step S5 (adhesive material BDH, BDL supplying step) and step S6 (semiconductor chip CPH, CPL mounting step) are performed in order. Steps S5 and S6 in the present embodiment 2 are the same as those in the above embodiment 1, so repeated explanations thereof will be omitted here.

[0117] In this embodiment, after step S6, a heat treatment is performed to harden the adhesive materials BDH and BDL (step S7a in FIG. 33). The heat treatment in step S7a is basically the same as the heat treatment in step S7 in the first embodiment, but differs from the heat treatment in step S7 in the first embodiment in the following points.

[0118] That is, in the first embodiment, the heat treatment in step S7 is performed with not only the semiconductor chips CPH and CPL but also the semiconductor chip CPC mounted, so that the heat treatment in step S7 hardens not only the adhesive materials BDH and BDL but also the adhesive material BDC. In contrast, in the second embodiment, the heat treatment in step S7a is performed with the semiconductor chips CPH and CPL mounted but not the semiconductor chip CPC mounted, so that the heat treatment in step S7a hardens the adhesive materials BDH and BDL, but the adhesive material BDC is not present on the die pad DPC, and therefore the adhesive material BDC does not harden. Other than that, the heat treatment in step S7a is the same as the heat treatment in step S7 in the first embodiment.

[0119] For this reason, the adhesive materials BDH and BDL are barely hardened and remain in a paste-like state until immediately before the heat treatment of step S7a, but the heat treatment of step S7a hardens the adhesive materials BDH and BDL. However, at the stage when the heat treatment of step S7a is completed, the adhesive materials BDH and BDL are not completely (sufficiently) hardened but are in a semi-hardened state. When the heat treatment of step S7a is performed, the adhesive materials BDH and BDL are in a semi-hardened state, so that the semiconductor chip CPH is fixed to the die pad DPH by the semi-hardened adhesive material BDH, and the semiconductor chip CPL is fixed to the die pad DPL by the semi-hardened adhesive material BDL.

[0120] The adhesives BDH and BDL that have been hardened (semi-hardened) by the heat treatment in step S7a can be further hardened by the heat treatment in the subsequent step S10a, so the heat treatment in step S7a can be performed in a shorter time and at a lower temperature than the heat treatment in the subsequent step S10a.

[0121] In this second embodiment, after the heat treatment step of step S7a, step S3 (adhesive material BDC supply step) and step S4 (semiconductor chip CPC mounting step) are performed in this order. Steps S3 and S4 are the same in this second embodiment as in the first embodiment, so repeated explanations thereof will be omitted here.

[0122] In the second embodiment, after step S4 (semiconductor chip CPC mounting step), step S8 (adhesive material BD1, BD2, BD3, BD4 supply step) and step S9 (metal plate MP1, MP2 placement step) are performed in this order. There is no need to perform the heat treatment step of step S7 between step S4 and step S8. Steps S8 and S9 in the second embodiment are the same as those in the first embodiment, so a repeated explanation thereof will be omitted here.

[0123] In the second embodiment, after step S9 (the metal plates MP1 and MP2 placement process), a heat treatment is performed to harden the adhesives BD1, BD2, BD3, BD4, BDC, BDH, and BDL (step S10a in FIG. 33). The heat treatment in step S10a is basically the same as the heat treatment in step S10 in the first embodiment, but differs from the heat treatment in step S10 in the first embodiment in the following points.

[0124] That is, in the first embodiment, not only the adhesive materials BDH and BDL but also the adhesive material BDC are semi-cured by the heat treatment in step S7, and the heat treatment in step S10 is performed in that state. Therefore, in the first embodiment, the semi-cured adhesive material BDC is further cured by the heat treatment in step S10, and becomes a fully cured (cured) adhesive material BDC. In contrast, in the second embodiment, the heat treatment in step S7a is not performed on the adhesive material BDC, and the paste-like adhesive material BDC is cured by the heat treatment in step S10a, and becomes a fully cured (cured) adhesive material BDC. Otherwise, the heat treatment in step S10a is the same as the heat treatment in step S10 in the first embodiment.

[0125] The heat treatment in step S10a is performed for a longer time and at a higher temperature than the heat treatment in step S7a. This allows the adhesive materials BD1, BD2, BD3, BD4, BDC, BDH, and BDL to be sufficiently hardened by the heat treatment in step S10a, so that the wire bonding step in step S11 and the molding step in step S12 can be performed with the semiconductor chips CPC, CPH, and CPL and the metal plates MP1 and MP2 firmly fixed in place. This allows the wire bonding step in step S11 and the molding step in step S12 to be performed accurately.

[0126] In the present embodiment 2, after the heat treatment step of step S10a, step S11 (wire bonding step), step S12 (molding step), step S13 (cutting step), and step S14 (lead processing step) are performed in this order. Steps S11, S12, S13, and S14 are the same in the present embodiment 2 as in the above-mentioned embodiment 1, so repeated explanations thereof will be omitted here.

[0127] In this second embodiment, steps S5 and S6 are performed to mount the semiconductor chips CPH and CPL on the die pads DPH and DPL via adhesive materials BDH and BDL, and then steps S3 and S4 are performed to mount the semiconductor chip CPC on the die pad DPC via adhesive material BDC.

[0128] Therefore, unlike the second embodiment, if the heat treatment of step S7a is not performed, there is a concern that the conductive filler will settle in the paste-like adhesive BDH, BDL interposed between the back electrodes BEH, BEL of the semiconductor chips CPH, CPL and the die pads DPH, DPL due to the time required for steps S3 and S4.

[0129] In contrast, in the second embodiment, after steps S5 and S6 are performed to mount the semiconductor chips CPH and CPL on the die pads DPH and DPL via the adhesive materials BDH and BDL, a heat treatment step of step S7a is performed to harden (semi-harden) the adhesive materials BDH and BDL before steps S3 and S4 (the adhesive material BDC supply step and the semiconductor chip CPC mounting step). Therefore, even if steps S3 and S4 require time after the heat treatment step S7a, it is possible to prevent the conductive filler from settling in the adhesive materials BDH and BDL interposed between the back electrodes BEH and BEL of the semiconductor chips CPH and CPL and the die pads DPH and DPL. Therefore, the heat treatment step of step S10a can be performed with the conductive filler dispersed almost uniformly in the adhesive materials BDH and BDL to sufficiently harden the thermosetting resin contained in the adhesive materials BDH and BDL.

[0130] Therefore, in the semiconductor device PKG manufactured according to the second embodiment, the conductive filler is dispersed almost uniformly in each of the adhesive materials BDH and BDL interposed between the back electrodes BEH and BEL of the semiconductor chips CPH and CPL and the die pads DPH and DPL. The ratio of the conductive filler can be made almost the same on the side closer to the back electrodes BEH and BEL of the semiconductor chips CPH and CPL and on the side closer to the die pads DPH and DPL. This reduces the electrical resistance and thermal resistance between the back electrode BEH of the semiconductor chip CPH and the die pad DPH, and also reduces the electrical resistance and thermal resistance between the back electrode BEL of the semiconductor chip CPL and the die pad DPL. This improves the performance of the semiconductor device PKG.

[0131] Furthermore, similar to the relationship between the heat treatment in step S7 and the heat treatment in step S10 in the first embodiment, the heat treatment in step S7a in the second embodiment has a shorter heat treatment time than the heat treatment in step S10a. More specifically, the heat treatment time in step S7a is preferably set to half or less of the heat treatment time in step S10a. This shortens the time required for the heat treatment in step S7a, thereby reducing the manufacturing time of the semiconductor device and preventing a decrease in throughput.

[0132] Furthermore, similar to the relationship between the heat treatment in step S7 and the heat treatment in step S10 in the above-mentioned embodiment 1, in the present embodiment 2, the heat treatment temperature in step S7a is lower than that in step S10a. As a result, if a medicinal layer YZ is formed on the surface of the lead frame LF as shown in Figure 30 above, it is possible to suppress or prevent the medicinal layer YZ on the surface of the lead frame LF from disappearing during the heat treatment in step S7a. Therefore, similar to the above-mentioned embodiment 1, in the present embodiment 2, the effect of the medicinal layer YZ on the surface of the lead frame LF can be obtained until the heat treatment in step S10a is performed.

[0133] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0134] For example, the above-described first and second embodiments have been described with reference to the case where the semiconductor device PKG includes the semiconductor chips CPC, CPH, and CPL. The technical ideas of the above-described first and second embodiments can also be applied to the case where the semiconductor device PKG includes one of the semiconductor chips CPH and CPL and the semiconductor chip CPC but does not include the other of the semiconductor chips CPH and CPL, or the case where the semiconductor device PKG includes one of the semiconductor chips CPH and CPL but does not include the other of the semiconductor chips CPH and CPL and the semiconductor chip CPC.

[0135] For example, if the semiconductor device PKG includes a semiconductor chip CPH but not a semiconductor chip CPL, the lead frame LF does not have a die pad DPL, leads LD3, LD4, or lead connecting portions LB3, LB4. In this case, in step S5, the adhesive material BDL is not supplied onto the die pad DPL, and in step S6, the semiconductor chip CPL is not mounted on the die pad DPL via the adhesive material BDL. In this case, in the heat treatment in step S7, the adhesive materials BDC and BDH are hardened (semi-hardened), and in the heat treatment in step S7a, the adhesive material BDH is hardened (semi-hardened). [Explanation of symbols]

[0136] 1,2 Power MOSFET BD1,BD2,BD3,BD4,BDC,BDH,BDL Adhesive BEH,BEL Back electrode BW Wire CL coil CLC, CT control circuit CPC, CPH, CPL semiconductor chips DPC, DPH, DPL die pad DPCa, DPHa, DPLa main surface DPCb, DPHb, DPLb back side FL conductive filler INV Inverter circuit LB1, LB2, LB3, LB4 lead connection part LD,LD1,LD2,LD3,LD4,LD5,LD6,LD7,LD8 lead LF lead frame MOT motor MR sealing part MRa main surface MRb back side MRc1,MRc2,MRc3,MRc4 Side PDC, PDH, PDHS, PDHG, PDL, PDLS, PDLG pads PKG semiconductor device RS resin material TE1, TE2, TE3, TE4, TE5 terminals TL Hanging Lead

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a lead frame having a first chip mounting portion and a second chip mounting portion; (b) supplying a conductive paste-type first adhesive material containing a conductive filler onto the first chip mounting portion; (c) after the step (b), mounting a first semiconductor chip having a first front surface electrode and a first back surface electrode positioned opposite to each other on the first chip mounting portion via the first adhesive material so that the first back surface electrode faces the first chip mounting portion; (d) supplying a paste-type third adhesive material onto the second chip mounting portion; (e) after the step (d), a step of mounting a second semiconductor chip having a second surface electrode on the second chip mounting portion via the third adhesive; (f) performing a first heat treatment to harden the first adhesive material and the third adhesive material after the steps (c) and (e); (g) after the step (f), supplying a conductive paste-type second adhesive material containing a conductive filler onto the first surface electrodes of the first semiconductor chip; (h) after the step (g), placing a first metal plate on the first surface electrode of the first semiconductor chip so as to face the first surface electrode of the first semiconductor chip via the second adhesive; (i) after the step (h), performing a second heat treatment to harden the first adhesive material, the second adhesive material, and the third adhesive material; where: a heat treatment time of the first heat treatment is shorter than a heat treatment time of the second heat treatment, The first adhesive is hardened by the first heat treatment in the step (f) and then further hardened by the second heat treatment in the step (i).

2. 2. The method of manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein a heat treatment temperature of the first heat treatment is lower than a heat treatment temperature of the second heat treatment.

3. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the first adhesive and the second adhesive are each made of silver paste.

4. 2. The method of manufacturing a semiconductor device according to claim 1, the first back surface electrode of the first semiconductor chip is electrically connected to the first chip mounting portion via the first adhesive; The first surface electrode of the first semiconductor chip is electrically connected to the first metal plate via the second adhesive.

5. 2. The method of manufacturing a semiconductor device according to claim 1, the first semiconductor chip includes a first field effect transistor for a switch; the first surface electrode is for the source of the first field effect transistor; The method for manufacturing a semiconductor device, wherein the first back surface electrode is for a drain of the first field effect transistor.

6. 2. The method of manufacturing a semiconductor device according to claim 1, The lead frame prepared in step (a) further includes a first conductor portion, In the step (g), the second adhesive is supplied onto the first surface electrode of the first semiconductor chip, and a fourth adhesive of a conductive paste type is supplied onto the first conductor portion; In the step (h), the first metal plate is disposed so as to face the first surface electrode of the first semiconductor chip via the second adhesive material and to face the first conductor portion via the fourth adhesive material; The method for manufacturing a semiconductor device, wherein in the step (i), the second heat treatment is performed to harden the first adhesive, the second adhesive, the third adhesive, and the fourth adhesive.

7. 7. The method for manufacturing a semiconductor device according to claim 6, the first back surface electrode of the first semiconductor chip is electrically connected to the first chip mounting portion via the first adhesive; a first surface electrode of the first semiconductor chip electrically connected to the first conductor portion via the second adhesive, the first metal plate, and the fourth adhesive;

8. 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the lead frame prepared in the step (a) has a plurality of lead portions integrally connected to the first conductor portion.

9. 2. The method of manufacturing a semiconductor device according to claim 1, the first semiconductor chip further has a third surface electrode; (j) after the step (i), electrically connecting the third surface electrodes of the first semiconductor chip and the second surface electrodes of the second semiconductor chip via conductive wires; The method for manufacturing a semiconductor device further comprises:

10. 2. The method of manufacturing a semiconductor device according to claim 1, (k) after the step (i), forming a sealing portion that seals the first semiconductor chip, the second semiconductor chip, the first metal plate, the first chip mounting portion, and the second chip mounting portion; The method for manufacturing a semiconductor device further comprises:

11. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a lead frame having a first chip mounting portion, a second chip mounting portion, and a first conductor portion; (b) supplying a conductive paste-type first adhesive material containing a conductive filler onto the first chip mounting portion; (c) after the step (b), mounting a first semiconductor chip having a first front surface electrode and a first back surface electrode positioned opposite to each other on the first chip mounting portion via the first adhesive material so that the first back surface electrode faces the first chip mounting portion; (d) after the step (c), performing a first heat treatment to harden the first adhesive; (e) after the step (d), supplying a paste-type second adhesive material onto the second chip mounting portion; (f) after the step (e), a step of mounting a second semiconductor chip on the second chip mounting portion via the second adhesive; (g) after the step (f), supplying a third adhesive material of a conductive paste type onto the first surface electrode of the first semiconductor chip and supplying a fourth adhesive material of a conductive paste type onto the first conductor portion; (h) after the step (g), a step of arranging a first metal plate so as to face the first surface electrode of the first semiconductor chip via the third adhesive material and to face the first conductor portion via the fourth adhesive material; (i) after the step (h), performing a second heat treatment to harden the first adhesive material, the second adhesive material, the third adhesive material, and the fourth adhesive material; where: a heat treatment time of the first heat treatment is shorter than a heat treatment time of the second heat treatment, The first adhesive is hardened by the first heat treatment in the step (d), and then further hardened by the second heat treatment in the step (i).

12. 12. The method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein a heat treatment temperature of the first heat treatment is lower than a heat treatment temperature of the second heat treatment.

13. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the first adhesive and the second adhesive are each made of silver paste.

14. 12. The method for manufacturing a semiconductor device according to claim 11, the first back surface electrode of the first semiconductor chip is electrically connected to the first chip mounting portion via the first adhesive; a first surface electrode of the first semiconductor chip electrically connected to the first conductor portion via the third adhesive, the first metal plate, and the fourth adhesive;

15. 15. The method for manufacturing a semiconductor device according to claim 14, The method for manufacturing a semiconductor device, wherein the lead frame prepared in the step (a) has a plurality of lead portions integrally connected to the first conductor portion.

16. 12. The method for manufacturing a semiconductor device according to claim 11, the first semiconductor chip includes a first field effect transistor for a switch; the first surface electrode is for the source of the first field effect transistor; The method for manufacturing a semiconductor device, wherein the first back surface electrode is for a drain of the first field effect transistor.

17. 12. The method for manufacturing a semiconductor device according to claim 11, (j) after the step (i), forming a sealing portion that seals the first semiconductor chip, the second semiconductor chip, the first chip mounting portion, the second chip mounting portion, the first metal plate, and the first conductor portion; The method for manufacturing a semiconductor device further comprises:

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