Multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module

Abstract

The invention belongs to the technical field of semiconductors, and discloses a multi-loop vertical commutation type low-parasitic-parameter three-level power semiconductor module which is suitable for a three-level ANPC topology and comprises a three-level power module composed of six switch tubes S1 to S6, and the module has three bus levels of positive level, zero level and negative level; wherein the zero level is divided into two types, the zero level can be switched with a positive level or a negative level to form four types of commutation loops, the four types of commutation loops comprise two small commutation loops and two large commutation loops, and the module structure design is used for suppressing parasitic inductance in the commutation loops; the multi-loop low-inductance integration of the three-level ANPC module is realized; the method is suitable for various packaging schemes, including PCB-on-DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module three-dimensional stacked PCB-on-DBC as an example, integration of low thermal resistance and high power density is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module. Background Technology

[0002] In the field of power electronics, power semiconductor devices are core components for achieving efficient power conversion and control. Third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) and gallium nitride (GaN), have emerged, bringing revolutionary improvements to converter performance with their superior electrical properties. Gallium nitride (GaN), in particular, exhibits even better performance due to its unique two-dimensional electron gas structure. The application of GaN devices has begun to penetrate multiple industries. In the automotive industry, some leading automakers have started using GaN devices to manufacture traction inverters and on-board chargers for electric vehicles. However, "insufficient range for long-distance travel" and "inconvenient charging" are two major pain points for consumers of new energy vehicles. To extend the driving range, major manufacturers have adopted technologies that increase battery capacity and provide fast charging solutions to effectively address charging and range anxiety. This has led to the development of 800V high-voltage system technology for new energy vehicles. However, two-level 800V high-voltage systems face challenges such as high motor shaft voltage and current, and insufficient motor withstand voltage and corrosion resistance. Three-level converters offer several advantages, including (1) more output levels, halved power device withstand voltage requirements, lower harmonic content in the output waveform, and less motor oscillation; (2) reduced common-mode voltage peak value, lower motor shaft voltage, and lower insulation requirements; (3) reduced common-mode voltage variation amplitude, reduced shaft current, and reduced bearing corrosion; and (4) reduced dV / dt and di / dt, resulting in lower switching losses and electromagnetic interference. These advantages effectively address the problems faced by two-level converters. Currently, 650V planar GaN has reached a mature stage, and GaN power devices offer excellent performance at a lower price. Three-level converters based on 650V GaN devices have become an ideal choice for building 800V systems.

[0003] The industry has conducted extensive research and manufacturing on GaN-based three-level converters suitable for 800V systems. TI designed an all-GaN bidirectional three-phase inverter based on ANPC topology with a power output of 11kW and a peak efficiency of 98.5%. GaNsystems designed an all-GaN 800V on-board charger based on a three-level flying capacitor topology with a power output of 11kW and an efficiency greater than 98.5%. GaNsystems also designed a GaN / SiIGBT hybrid 800V inverter based on T-Type topology with a power output of 150kW and a peak efficiency of 99.2%. Visic used its self-developed 650V / 200A direct-drive GaN to build a three-phase three-level flying capacitor inverter with a power output of 100kW. However, currently, the industry only uses discrete components to build GaN-based three-level converters, resulting in lower integration, larger size, and greater parasitic inductance. Due to the presence of a two-dimensional electron gas, the turn-on and turn-off times of GaN power devices can be reduced to 10–20 ns. During the device switching process, the large inductance of the power circuit will lead to overvoltage. To prevent overvoltage and to take advantage of the high switching speed of GaN devices, thereby reducing switching losses, the inductance of the power circuit needs to be strictly limited. Therefore, modular design of GaN-based three-level converters for 800V systems is essential.

[0004] In 2023, Yue Sun, Hua Bai, and others from the University of Tennessee-Knoxville developed the first all-GaN three-level ANPC module. Based on DBC and bonded wire packaging, it reduced the parasitic inductance of the module's power loop to 5.21nH for the large loop and 1.92nH for the small loop. The analog junction-coolant thermal resistance for different switches was 0.37℃ / W and 0.53℃ / W, respectively. However, GaN-based three-level converter modules suitable for 800V systems have not yet been widely studied.

[0005] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0006] Currently, GaN-based three-level converter modules suitable for 800V systems have not been widely studied. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module.

[0008] This invention is implemented as follows: a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module includes:

[0009] The three-level ANPC module consists of six switching transistors S1-S6. The bus provides three levels: positive, zero, and negative. When unipolar modulation is used, a total of four zero levels are formed. Two zero levels can be switched with the positive level, and two zero levels can be switched with the negative level.

[0010] During state switching, there are two types of power circuits: small converter circuit and large converter circuit. Figure 1 (a) are two small commutation loops formed when switching between 0 level and DC+ or DC- level; Figure 1 (b) is the large commutation loop formed when switching between 0 level and DC+ level; Figure 1 (c) is the large commutation circuit formed when switching between 0 level and DC-level.

[0011] Furthermore, to reduce the parasitic inductance of the "small commutation circuit", S1 and S2 should form a vertical commutation structure, and S3 and S4 should form a vertical commutation structure; to reduce the parasitic inductance of the "large commutation circuit", S1, S5, S6, and S3 should form a vertical commutation structure, and S4, S6, S5, and S2 should form a vertical commutation structure.

[0012] Furthermore, the six planar GaN power switches S1 to S6 are arranged in a highly compact manner on the substrate: S1 and S2 are side by side on the left side of the module, adjacent to the positive bus; S3 and S4 are side by side on the right side, adjacent to the negative bus; S5 and S6 are placed in the middle and connected to the zero-level output node respectively. This positional relationship ensures that each switch in the small commutation loop (S1–S2 or S3–S4 in pairs) and the large commutation loop (S1–S5–S6–S3 and S4–S6–S5–S2) can complete the current loop through the shortest interconnection path, thereby significantly reducing space occupation and loop area.

[0013] Furthermore, taking advantage of the planar GaN lateral commutation and the insulation between the substrate and the chip source and drain, the commutation circuit is designed by using the DBC copper layer soldered to the chip substrate to form the commutation structure. In the ANPC topology, the S2 chip substrate is connected to the drain, while the remaining S1 and S3-S6 chip substrates are connected to the source.

[0014] Furthermore, the GaN chip substrate and the chip source or drain are connected by a pad with the same thickness as the chip.

[0015] Furthermore, taking the PCB-on-DBC package as an example, the electrical connection characteristics of the power circuit of the three-level ANPC module are as follows: Figure 2 As shown, S1-S6 are the S1-S6 switches in the ANPC topology, respectively. Orange represents copper, and green represents the organic dielectric layer FR4. Figure 2 (b) is Figure 1(a) The two small commutation loops formed when the corresponding 0 level switches to DC+ or DC- level; Figure 2 (c) is Figure 1 (b) is the large commutation loop formed when the corresponding 0 level and DC+ level switch are switched; Figure 2 (d) is Figure 1 (c) is the large commutation circuit formed when the corresponding 0 level and DC- level switch are switched.

[0016] Furthermore, based on the multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure, a three-dimensional stacked vertical commutation low-inductance packaging structure is combined to form a three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure, in which each switching transistor position is composed of symmetrically connected chips in parallel. Figure 1 Switches S1 to S6 are respectively composed of chips S1 symmetrical about the PCB substrate. 1-1 and S 1-2 ~S 6-1 and S 6-2 The parallel meters are mounted on the PCB surface, and the commutation circuit is formed by stacking symmetrical vertical commutation circuits.

[0017] Furthermore, the three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure, combined with "A Dynamic Current Sharing Layout Design Method and System for Multi-Chip Parallel Power Modules", S 1-1 S 1-2 ......S 6-1 and S 6-2 The switch positions are respectively adopted Figure 4 The design method of parallel driving four chips is shown. The four chips are arranged compactly. The right gate g1 of die1 and the left gate g2 of die2 are interconnected and led out. The right gate g3 of die3 and the left gate g4 of die4 are interconnected and led out, forming two mirror gate access points. Kelvin source (ks1-ks4) access points are led out from the source closest to each gate. The driver to gate and Kelvin source to ground lines are horizontally routed above the power loop, and are connected to the gate and Kelvin source access points in sequence. They are respectively laid on the upper and lower copper layers of two flexible PCBs to form a low-inductance vertical commutation structure. Figure 1 The three-level ANPC module will form a multi-loop vertical converter with 8 chips connected in parallel. Figure 1 The parasitic inductances of the four converter circuits shown are reduced to 0.322nH, 0.399nH, 0.614nH and 0.669nH respectively, all less than 1nH.

[0018] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0019] This invention studies GaN three-level ANPC modules and proposes a design scheme for a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module. It realizes vertical commutation in all commutation loops in the three-level ANPC module, including both large and small commutation loops, and achieves multi-loop low inductance integration of the three-level ANPC module.

[0020] This invention proposes a design scheme for a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module, which has the following advantages:

[0021] 1. Vertical commutation of four commutation circuits was achieved, with parasitic inductances of 0.322nH, 0.399nH, 0.614nH and 0.669nH respectively, all less than 1nH, effectively realizing low-inductance integration of all commutation circuits in the three-level module.

[0022] 2. Applicable to various packaging forms. Taking the PCB-on-DBC hybrid package as an example, this invention simultaneously achieves low thermal resistance integration, reducing the package thermal resistance to 0.155℃ / W.

[0023] The technical solution of this invention can be applied to 800V main drive inverter applications. Currently, the highest current is achieved with an Infineon 650V, 150A gallium nitride chip. Using the circuit vertical commutation type low parasitic parameter three-level power semiconductor module design method proposed in this invention, a three-level ANPC module with a rated voltage of 1300V and a rated current of 1200A can be designed. This will significantly improve the output power of the main drive inverter, and the low parasitic inductance throughout the module's circuit will greatly enhance the performance of high-power inverters.

[0024] This invention proposes a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module, which for the first time realizes the full-power loop vertical commutation design of a three-level ANPC GaN module. Attached Figure Description

[0025] Figure 1 The three-level ANPC topology and power circuit identifiers provided in this embodiment of the invention are: (a) two small converter circuits; (b) a large converter circuit switching between 0 level and DC+; and (c) a large converter circuit switching between 0 level and DC-.

[0026] Figure 2 The following is a description of the composition and commutation circuit of a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module with PCB-on-DBC packaging provided in this embodiment of the invention: (a) Composition of the power module with PCB-on-DBC packaging; (b) Schematic diagram of the small commutation circuit in the module; (c) Schematic diagram of the large commutation circuit in the module switching between zero level and positive level; (d) Schematic diagram of the large commutation circuit in the module switching between zero level and negative level.

[0027] Figure 3 This invention provides a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module with a three-dimensional stacked structure; (a) schematic diagram of the small commutation loop in the module; (b) schematic diagram of the large commutation loop switching between zero level and positive level in the module; (c) schematic diagram of the large commutation loop switching between zero level and negative level in the module.

[0028] Figure 4 This is the parallel structure diagram proposed in the "Dynamic Current Sharing Layout Design Method and System for Multi-Chip Parallel Power Modules" provided in the embodiments of the present invention.

[0029] Figure 5 This is a schematic diagram of a three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure provided in an embodiment of the present invention, which is a substrate welding / sintering package.

[0030] Figure 6 This is a schematic diagram of the embedded three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure provided in an embodiment of the present invention.

[0031] Figure 7 This is a PCB substrate design diagram for a PCB-on-DBC package provided in an embodiment of the present invention.

[0032] Figure 8 This is a design diagram of the DBC substrate in the PCB-on-DBC package provided in an embodiment of the present invention.

[0033] Figure 9 This is a heat dissipation base plate design diagram in the PCB-on-DBC package provided in an embodiment of the present invention.

[0034] Figure 10 This is a module assembly structure diagram provided in an embodiment of the present invention.

[0035] Figure 11 This is an overall effect diagram of the module provided in the embodiment of the present invention.

[0036] Figure 12 This is a heat dissipation path diagram provided in an embodiment of the present invention when using PCB-on-DBC packaging.

[0037] Figure 13 The PCB-on-DBC package module with a dual-side parallel structure provided in this embodiment of the invention has the following COMSOL thermal simulation results when the chip power is set to 100W and the heat transfer coefficient is infinite: (a) DBC surface temperature, (b) chip temperature. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] like Figure 1 As shown, an embodiment of the present invention provides a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module, comprising:

[0040] The three-level ANPC topology consists of six switching transistors S1-S6. The bus provides three voltage levels: positive, zero, and negative. When unipolar modulation is used, four zero-level voltages are formed. Two zero-level voltages can be switched with the positive voltage, and two zero-level voltages can be switched with the negative voltage. There are four commutation loops during state switching, including two types of power loops: small commutation loops and large commutation loops. Figure 1 (a) are two small commutation loops formed when switching between 0 level and DC+ or DC- level; Figure 1 (b) is the large commutation loop formed when switching between 0 level and DC+ level; Figure 1 (c) is the large commutation circuit formed when switching between 0 level and DC-level.

[0041] To reduce the parasitic inductance of the "small commutation loop," S1 and S2 should form a vertical commutation structure, and S3 and S4 should form a vertical commutation structure. To reduce the parasitic inductance of the "large commutation loop," S1, S5, S6, and S3 should form a vertical commutation structure, and S4, S6, S5, and S2 should form a vertical commutation structure. Therefore, this invention proposes a design method for a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module, combined with a planar GaN chip.

[0042] In the module shown, six planar GaN power switches S1 to S6 are arranged in a highly compact manner on the substrate: S1 and S2 are side by side on the left side of the module, adjacent to the positive bus; S3 and S4 are side by side on the right side, adjacent to the negative bus; S5 and S6 are placed in the middle and connected to the zero-level output node respectively. This positional relationship ensures that each switch in the small commutation loop (S1–S2 or S3–S4 in pairs) and the large commutation loop (S1–S5–S6–S3 and S4–S6–S5–S2) can complete the current loop through the shortest interconnection path, thereby significantly reducing space occupation and loop area.

[0043] like Figure 2 (a) shows a side cross-sectional view of the multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module proposed in this invention when packaged in a PCB-on-DBC package, wherein S1 is Figure 1 S1 corresponds to the switching transistor, and S1-S6 are the corresponding transistors of the chip. Figure 1In the ANPC topology, the S1-S6 switches are shown in orange (copper) and green (organic dielectric layer FR4). This is a schematic diagram after the module is soldered and assembled. Figure 2 (b) corresponds to Figure 1 (a) Two small converter loops; Figure 2 (c) corresponds to Figure 1 (b) The large converter circuit; Figure 2 (d) corresponds to Figure 1 (c) Large commutation loop. As can be seen from the figure, all four commutation loops form a vertical commutation structure, thus having extremely low loop parasitic inductance. Furthermore, each chip substrate is directly soldered to the DBC substrate, achieving a direct heat dissipation structure and low thermal resistance integration.

[0044] This invention fully utilizes the lateral commutation characteristics of planar GaN and the insulation between the substrate and the chip source and drain. The commutation circuit design leverages the DBC copper layer soldered to the chip substrate to form the commutation structure. In the ANPC topology, the drain of the S2 chip substrate is connected, while the remaining S1 and S3-S6 chip substrates are connected to the source. Figure 2 (a) uses pads of the same thickness as the chip to connect the PCB and DBC substrate. Chips S1-S6 are implemented according to... Figure 2 The circuit is positioned to form a vertical converter loop.

[0045] This invention is in Figure 2 Based on the proposed multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure, a three-dimensional stacked vertical commutation structure is further combined, such as S1 consisting of S1-1 and S1-2 connected in parallel to form... Figure 3 The diagram shows a three-dimensional stacked vertical multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure, in which each switch position is formed by symmetrically connected chips in parallel, and the commutation loop is formed by stacking symmetrical vertical commutation loops.

[0046] The positions S1-1~S6-1 and S1-2~S6-2 are respectively adopted using Figure 4 The four-chip parallel structure shown can achieve Figure 1 Eight chips are connected in parallel for dynamic current sharing at each switching transistor location. This achieves a three-level ANPC GaN power module with a rated voltage of 1300V and a rated current of 480A. The three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module structure is combined with the design method and system for dynamic current sharing layout of multi-chip parallel power modules. 1-1 S 1-2 ......S 6-1 and S 6-2 The switch positions are respectively adopted Figure 4The design method of parallel driving four chips is shown. The four chips are arranged compactly. The right gate g1 of die1 and the left gate g2 of die2 are interconnected and led out. The right gate g3 of die3 and the left gate g4 of die4 are interconnected and led out, forming two mirror gate access points. Kelvin source (ks1-ks4) access points are led out from the source closest to each gate. The driver to gate and Kelvin source to ground lines are horizontally routed above the power loop, and are connected to the gate and Kelvin source access points in sequence. They are respectively laid on the upper and lower copper layers of two flexible PCBs to form a low-inductance vertical commutation structure.

[0047] The multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module proposed in this invention can be packaged in various ways, such as... Figure 3 It is a PCB-on-DBC package. Figure 5 For DBC substrate soldering / sintering packaging, Figure 6 Embedded packaging.

[0048] The multi-loop vertical commutation three-level power semiconductor module of the present invention can flexibly select a variety of packaging schemes to adapt to different power levels, heat dissipation requirements and size constraints, so as to optimize parasitic parameters while meeting electrical performance requirements.

[0049] exist Figure 3 In the PCB-on-DBC package shown, the upper layer is an aluminum-based PCB substrate, and the lower layer is a ceramic-based DCC (Direct Copper Clad) insulating substrate. The power die is directly soldered to the PCB traces, while the diode and inductive components are connected to the DBC through vias. This package utilizes the precision routing of the PCB combined with the high thermal conductivity of the DBC to achieve a high degree of integration between the traces and the power chip, reducing parasitic inductance of the traces. Furthermore, it allows for rapid prototyping using PCB technology, meeting the needs of small-to-medium batch production and experimental verification.

[0050] Figure 5 The DBC substrate soldering / sintering package shown connects the power die directly to the DBC ceramic substrate via lead-free soldering or metal powder sintering, and then tightly attaches it to the heat sink at the bottom of the module. This solution eliminates the PCB layer, resulting in a more direct heat conduction path for the power device and lower thermal resistance. At the same time, the mechanical strength and cycle reliability of the sintered connection are superior to traditional soldering, making it particularly suitable for high-power, high-current, or long-life industrial drive scenarios.

[0051] Figure 6The embedded package shown embeds the power chip, drive circuit, and necessary passive components together within a substrate of high thermal conductivity material, surrounded by a metal heat dissipation frame or shell. This approach minimizes module thickness, significantly suppresses parasitic inductance and capacitance, and results in excellent overall electrical performance. Simultaneously, the thermal expansion between the device and the package is well-matched, exhibiting excellent thermal cycling durability, making it particularly suitable for new energy motor control and electric transportation applications where size and efficiency are extremely critical.

[0052] Implementation Case 1:

[0053] Taking a gallium nitride chip with a rated voltage of 650V, a rated current of 60A, and a model number of GS-065-060-2-D2 as an example, this invention demonstrates a three-level ANPC power module with a multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module combined with a dual-side parallel and dynamic current sharing layout structure. The design steps and design effects are demonstrated using a PCB-on-DBC packaging scheme.

[0054] Step 1: PCB substrate design. A four-layer PCB board with AD design is used. The PCB uses 4 ounces (0.15mm) copper thickness to increase the module's current carrying capacity. The chip placement is as follows: Figure 3 As shown in Figure 4, the circuit is soldered on both sides of the PCB. The first and second layers of copper form the upper commutation circuit, and the third and fourth layers of copper form the lower commutation circuit. The driver chip is integrated on the left side of the PCB, and the power input / output ports are on the right side. Figure 7 As shown.

[0055] Step 2: DBC substrate design, such as Figure 8 As shown in the left figure, the copper layer on one side where the substrate is soldered to the chip is designed according to the different potential distributions of the chip substrate in the first step. It passes through the insulating material ALN to the copper on the other side, as shown in the left figure. Figure 8 As shown in the right figure, it is used to weld with the heat dissipation base plate to form a direct water cooling structure;

[0056] Step 3: Design the heat dissipation base plate. Currently, a pin-fin base plate design is adopted, such as... Figure 9 As shown;

[0057] Step 4: Module assembly. On both sides of the PCB substrate, GaN chip pads and spacers are soldered using 227℃ Sn99Cu0.7Ag0.3 solder paste. The top surface of the chip heat sink is soldered to the DBC substrate using 183℃ Sn63Pb37 solder paste. The surface of the DBC substrate is then soldered to the heat sink base plate using 183℃ Sn63Pb37 solder paste. The module assembly structure is as follows: Figure 10 As shown, the overall effect of the module is as follows: Figure 11 As shown.

[0058] Parasitic inductance of the module: The parasitic inductance of the designed module was extracted using ANSYS Q3D Extractor. Figure 7 The three-level ANPC module adopts a three-dimensional stacked multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module design. The parasitic inductances of the four commutation loops extracted at 100MHz are 0.322nH, 0.399nH, 0.614nH and 0.669nH respectively, all less than 1nH, effectively realizing low inductance integration of all commutation loops of the three-level module.

[0059] Module thermal resistance: The heat dissipation path of the chip is as follows Figure 12 As shown, the designed module was imported into COMSOL for thermal resistance extraction. With the chip power set to 100W, the heat transfer coefficient set to infinity, and the DBC surface temperature set to 25℃, the simulation results are as follows: Figure 13 As shown, R th =ΔT / P Junction-shell thermal resistance R th_jc1 =0.155℃ / W, R th_jc2 =0.155℃ / W, and because the symmetrical chips are isolated by the PCB, there is no thermal coupling between the chips on both sides of the PCB.

[0060] The entire module has a rated voltage of 1300V, a rated current of 480A, and a size of 8cm*9cm*1.5cm, achieving high power density integration.

[0061] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-loop vertical commutation type low parasitic parameter three-level power semiconductor module, characterized in that, Suitable for three-level ANPC topology, including a three-level power module consisting of 6 switching transistors S1 to S6, the module having three bus levels: positive level, zero level, and negative level; The zero level is divided into two types, which can be switched with positive or negative levels to form four commutation circuits, including two small commutation circuits and two large commutation circuits. The module structure is designed to suppress parasitic inductance in the above commutation circuits.

2. The power semiconductor module as described in claim 1, characterized in that, In the small commutation circuit, the switching transistors S1 and S2, and S3 and S4 are arranged vertically to construct a vertical commutation path, and the parasitic inductance is reduced by decreasing the current path area.

3. The power semiconductor module as described in claim 1, characterized in that, In the large commutation circuit, switches S1, S5, S6, and S3 together form one large commutation path, and switches S4, S6, S5, and S2 form another large commutation path. All large commutation paths adopt a vertical commutation structure to optimize the inductance characteristics of the commutation circuit.

4. The power semiconductor module as described in any one of claims 2 or 3, characterized in that, Six planar GaN power switches S1 to S6 are arranged in a highly compact manner on the substrate: S1 and S2 are side by side on the left side of the module, adjacent to the positive bus; S3 and S4 are side by side on the right side, adjacent to the negative bus; S5 and S6 are placed in the middle and are connected to the zero-level output node respectively. This positional relationship ensures that the switches in both small and large commutation circuits can complete the current loop through the shortest interconnection path.

5. The power semiconductor module as described in claim 1, characterized in that, Each switching transistor uses a planar GaN device as the switching chip. The GaN device substrate is insulated from the source or drain. It can be connected to different electrodes by soldering copper onto the substrate to construct a vertical commutation structure.

6. The power semiconductor module as described in claim 4, characterized in that, In the ANPC topology, the substrate of the S2 switch chip is connected to its drain, and the substrates of the other switches S1 and S3 to S6 chips are connected to their sources, forming a multi-loop vertical commutation structure.

7. The power semiconductor module as described in claim 6, characterized in that, Each commutation circuit is formed by stacking two vertical commutation circuits, and each switching transistor is composed of two chips connected in parallel, which are symmetrically distributed about the substrate.

8. The power semiconductor module as described in claim 7, characterized in that, The chip positions symmetrically distributed on the substrate all adopt a parallel structure of 4 chips, so that the S1 to S6 switching transistors in the ANPC module are connected in parallel by 8 chips.

9. The power semiconductor module as described in claim 8, characterized in that, An 8-chip dual-side parallel multi-loop vertical converter structure is formed, with a rated voltage of 1300V and a rated current of 480A; and the parasitic inductance of the four converter loops is reduced to 0.322nH, 0.399nH, 0.614nH and 0.669nH, all less than 1nH, realizing high-power multi-loop low-inductance integration.

10. The power semiconductor module as described in claim 9, characterized in that, It is suitable for a variety of packaging solutions, including PCB-on-DBC packaging, DBC substrate soldering / sintering packaging, and embedded packaging.

Images