Surface-emitting laser and method for manufacturing surface-emitting laser

Abstract

The vertical cavity surface emitting laser includes a first distributed Bragg reflector (DBR) including first and second dielectric layers alternately arranged in a first axis direction, and a semiconductor portion including a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, wherein the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged in the first axis direction, and the Group III nitride region includes an n-type Group III nitride region, wherein the semiconductor portion includes a monolithic diffraction grating having a periodic one-dimensional pattern, and the monolithic diffraction grating, the Group III nitride active region, and the distributed Bragg reflector are arranged in the first axis direction to form an optical cavity, and the periodic one-dimensional pattern extends in a second axis direction intersecting the first axis direction.

Description

[Technical Field]

[0001] The present invention relates to a surface-emitting laser and a method for manufacturing a surface-emitting laser. [Background technology]

[0002] Surface-emitting lasers are known as vertical-cavity surface-emitting lasers (VCSELs). VCSELs consist of a semiconductor active region disposed between n-side and p-side semiconductor regions and two distributed Bragg reflectors (DBRs) that act as highly reflective mirrors. The semiconductor active region is disposed between the two DBRs to form an optical cavity. The n-side and p-side regions inject carriers, i.e., electrons and holes, into the active region, where they recombine to generate light. The light thus generated travels through the optical cavity, reflecting multiple times by the DBRs, resulting in laser oscillation. VCSELs provide one of the DBRs with a less reflective mirror, which is used to emit a laser beam. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Appl. Phys. Lett. 92, 141102 (2008) [Non-patent document 2] Apply. Phys. Express, 12, 036504 (2019) [Non-patent document 3] Appl. Phys. Lett. 105, 031111 (2014) [Non-patent document 4] J. Vac. Sci. Technol. B 33, 050603 (2015) [Non-patent document 5] Appl. Phys. Express 12, 044004 (2019) [Non-patent document 6] Sci. Rep. 8, 10350 (2018)

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Non-licensed literature 9

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[0004] Fabrication of the reflecting mirrors in VCSELs, or distributed Bragg reflectors, has been a considerable challenge for decades in the scientific community, particularly in the III-nitride material system. III-nitride VCSELs are provided with a top mirror and a bottom mirror. III-nitride device layers are deposited on a substrate to form a semiconductor stack consisting of an n-side region, an active region, and a p-side region. A top mirror, the so-called p-side mirror, can then be formed on the semiconductor stack and includes alternating layers of different dielectric materials disposed on the device layers. The bottom mirror must be positioned to form a cavity; the top and bottom mirrors are positioned close to each other to allow for the formation of an optical cavity, which leads to the removal of the substrate. Another approach, forming the bottom mirror without removing the substrate, is to use an epitaxial DBR (NPL1) or a nanoporous DBR (NPL2). Yet another approach to forming a bottom mirror is to use a dielectric DBR (NPL3) or a high-index-contrast grating (NPL4), which are formed by polishing the substrate all the way down to the device layer or by separating the substrate by laser lift-off. However, these approaches show that fabrication of the bottom mirror remains a bottleneck issue, and each approach has some technical difficulties rather than advantages.

[0005] For example, the formation of epitaxial DBRs requires complex, time-consuming semiconductor deposition and is prone to degraded crystal quality. The formation of dielectric DBRs requires substrate removal using complex chemical-mechanical polishing (CMP). The use of CMP in the removal process is again challenging, tedious, and difficult to control, and wastes expensive III-nitride substrates.

[0006] Alternatively, the curved mirror approach in Non-Patent Document 5 and Non-Patent Document 6 (NPL5 and NPL6) involves polishing and etching the semiconductor substrate to create an n-side DBR mirror, using a significant portion of the substrate. Because the curved DBR mirror is formed on the backside of the substrate, this VCSEL structure does not require removal of the substrate, which can cause some inconveniences. Using a curved mirror provides a VCSEL with a long optical cavity.

[0007] Specifically, with regard to the substrate, the thickness must first be reduced to reduce absorption losses within the cavity, and thinning the substrate can be a difficult process to control and may damage the wafer, as the substrate must be thinned from an initial thickness of 300-400 micrometers to a target thickness of 10-30 micrometers to provide the cavity for the VCSEL.

[0008] Yet another approach is to provide III-nitride-based VCSELs with monolithic high-index-contrast gratings as the reflective mirrors. Fabrication of gratings used at visible wavelengths involves complex etching of semiconductor materials. Long operating times can degrade device performance and shorten device lifetimes.

[0009] Additionally, existing methods for fabricating high index contrast gratings use electron beam (e-beam) lithography and etching, which can damage the device layers. Accordingly, this process requires additional protective layers to avoid damage to the active region and subsequent device layers.

[0010] Taking all of these drawbacks into consideration, it is an object of the present invention to provide a structure for a III-nitride VCSEL and a method for fabricating a III-nitride VCSEL. Another object is to provide a monolithic high-index contrast grating and a method for fabricating a monolithic high-index contrast grating using epitaxial lateral overgrowth (ELO). The ELO process and ELO structure enable the semiconductor device layers to have high crystalline quality and prevent the device layers from being directly exposed to an etching environment in the formation of the grating. [Means for solving the problem]

[0011] One aspect of the present disclosure is a VCSEL, the VCSEL comprising: a first distributed Bragg reflector (DBR) including first and second dielectric layers alternately arranged in a first axis direction; and a semiconductor portion including a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, wherein the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged in the first axis direction, and the Group III nitride region comprises an n-type Group III nitride region; wherein the semiconductor portion includes a monolithic diffraction grating having a periodic one-dimensional pattern, and the monolithic diffraction grating, the Group III nitride active region, and the distributed Bragg reflector are arranged in the first axis direction to form an optical cavity, and the periodic one-dimensional pattern extends in a second axis direction that intersects the first axis direction.

[0012] Another aspect of the present disclosure is a method for fabricating a vertical cavity surface emitting laser (VCSEL), the method comprising: forming a patterned epitaxial lateral overgrowth (ELO) mask on a surface of a substrate, the substrate comprising one of a III-nitride substrate, a silicon substrate, a sapphire substrate, a GaN-on-sapphire template, or a GaN-on-silicon template, the patterned ELO mask including a diffraction grating pattern and an opening to the surface of the substrate; growing III-nitride on the substrate using the patterned ELO mask to form the diffraction grating pattern. forming a III-nitride region overlying a turn, wherein the diffraction grating pattern is transferred to the III-nitride region; growing a semiconductor stack including an n-type III-nitride region, a III-nitride active region, and a p-type III-nitride region; growing a conductive layer after growing the semiconductor stack; forming a first distributed Bragg reflector (DBR) on the conductive layer to produce a product, wherein the DBR includes alternating first and second dielectric layers; and removing the substrate from the product to expose the patterned ELO mask, wherein the diffraction grating pattern includes a periodic one-dimensional pattern extending along the surface of the substrate. [Effects of the Invention]

[0013] The above aspects can provide a structure for a III-nitride based VCSEL and a method for fabricating a III-nitride based VCSEL. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic diagram showing a vertical-cavity surface-emitting laser (VCSEL) according to the present embodiment. [Figure 2] FIG. 2 is a flowchart showing the main steps of a method for manufacturing a VCSEL according to this embodiment. [Figure 3A] FIG. 3A is a diagram illustrating steps for fabricating a monolithic grating according to this embodiment. [Figure 3B] FIG. 3B is a diagram illustrating steps for fabricating a monolithic grating according to this embodiment. [Figure 3C] FIG. 3C shows steps for fabricating a monolithic grating according to this embodiment. [Figure 3D] FIG. 3D is a diagram illustrating steps for fabricating a monolithic grating according to this embodiment. [Figure 4] FIG. 4 is a plan view showing a patterned ELO mask formed by two patterning steps. [Figure 5A] FIG. 5A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 5B] FIG. 5B is a diagram illustrating the main steps for manufacturing a VCSEL according to this embodiment. [Figure 5C] FIG. 5C is a diagram illustrating the main steps for manufacturing a VCSEL according to this embodiment. [Figure 6A] FIG. 6A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 6B] FIG. 6B is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 6C] FIG. 6C is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 7A] FIG. 7A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 7B] FIG. 7B is a diagram illustrating the main steps for manufacturing a VCSEL according to this embodiment. [Figure 7C] FIG. 7C is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 8A] FIG. 8A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 8B] FIG. 8B is a diagram illustrating the main steps for manufacturing a VCSEL according to this embodiment. [Figure 8C] FIG. 8C is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 9A] FIG. 9A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 9B] FIG. 9B is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 10A] FIG. 10A is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 10B] FIG. 10B is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 10C] FIG. 10C is a diagram showing the main steps for manufacturing a VCSEL according to this embodiment. [Figure 11A] FIG. 11A is a plan view showing the VCSEL according to the present embodiment. [Figure 11B] FIG. 11B is a cross-sectional view taken along line II shown in FIG. 11A. [Figure 12A] FIG. 12A is a plan view showing the VCSEL according to the present embodiment. [Figure 12B] FIG. 12B is a cross-sectional view taken along line II-II shown in FIG. 12A. [Figure 13A] FIG. 13A is a plan view showing the VCSEL according to the present embodiment. [Figure 13B] FIG. 13B is a cross-sectional view taken along line III-III shown in FIG. 13A. [Figure 14A] FIG. 14A is a plan view showing the VCSEL according to the present embodiment. [Figure 14B] FIG. 14B is a cross-sectional view taken along line IV-IV shown in FIG. 14A. [Figure 15A] FIG. 15A is a plan view showing the VCSEL according to the present embodiment. [Figure 15B] FIG. 15B is a cross-sectional view taken along line VV shown in FIG. 15A. DETAILED DESCRIPTION OF THE INVENTION

[0015] The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, shown by way of example, in which: With reference to the accompanying drawings, schematic diagrams illustrating vertical cavity surface emitting lasers, methods of fabricating vertical cavity surface emitting lasers, and monolithic high index contrast gratings and methods of fabricating high index contrast gratings monolithically using epitaxial lateral overgrowth, in accordance with the present disclosure, are described below: For ease of understanding, the same reference numerals are used, where possible, to designate identical elements common to the drawings.

[0016] FIG. 1 is a schematic diagram illustrating a vertical-cavity surface-emitting laser (VCSEL) according to an embodiment of the present invention. The VCSEL 11 includes a distributed Bragg reflector (DBR) 13 and a semiconductor portion 15 including a monolithic diffraction grating 17. The DBR 13 includes first and second dielectric layers 19 and 21 alternately arranged in a first axis direction Ax1, where the material of the first dielectric layer 19 is different from the material of the second dielectric layer 21. The semiconductor portion 15 excludes the substrate used to grow the semiconductor portion 15. The VCSEL 11 can further include a dielectric layer 18 that can cover part or all of the monolithic diffraction grating 17. The dielectric layer 18 can extend along the surface structure of the monolithic diffraction grating 17 because it originates from a patterned ELO mask used in the growth process.

[0017] The semiconductor portion 15 includes a p-type III-nitride region 23, a III-nitride region 25 including an n-type III-nitride region, and a III-nitride active region 27 located between the p-type III-nitride region 23 and the n-type III-nitride region of the III-nitride region 25. The p-type III-nitride region 23, the III-nitride active region 27, and the n-type III-nitride region of the III-nitride region 25 are arranged in a first axis direction Ax1. The monolithic diffraction grating 17 has a periodic one-dimensional pattern 17a. The monolithic diffraction grating 17, the semiconductor portion 15, and the DBR 13 are arranged in the first axis direction Ax1 to form an optical cavity 29. The monolithic diffraction grating 17 is disposed along a surface of the III-nitride region 25, and the periodic one-dimensional pattern 17a extends in a second axis direction Ax2 that intersects with the first axis direction Ax1.

[0018] The VCSEL 11 further includes an anode electrode 31 and a conductive layer 35. The conductive layer 35 has an inner portion 35a and an outer portion 35b surrounding the inner portion 35a and is disposed on the p-type III-nitride region 23. The inner portion 35a is transparent to light from the III-nitride active region 27 and may be disposed between the semiconductor portion 15 and the DBR 13. The outer portion 35b is not covered by the DBR 13, allowing the anode electrode 31 to contact the outer portion 35b. The conductive layer 35 connects the anode electrode 31 to the p-type III-nitride region 23. The conductive layer 35 may include a III-nitride semiconductor such as p-type GaN, a conductive inorganic material such as indium tin oxide (ITO), or both. In one example, the DBR 13 may be disposed in contact with the conductive layer 35. If desired, the semiconductor portion 15 can be disposed between the p-type III-nitride region 23 and the conductive layer 35, which may further include a tunnel junction having n-type conductivity.

[0019] The VCSEL 11 includes a cathode electrode 33. The cathode electrode 33 is electrically connected to the n-type III-nitride region of the III-nitride region 25. As shown in FIG. 1 , the cathode electrodes 33 (33a and 33b) can be disposed in contact with either or both of the front and back surfaces of the n-type III-nitride region of the III-nitride region 25.

[0020] Specifically, the cathode electrodes 33 (33a and 33b) may be disposed in contact with either the front surface or the back surface of the n-type group III nitride region of the group III nitride region 25.

[0021] In the VCSEL 11 having a mesa 37 in the semiconductor portion 15, the mesa 37 includes the p-type Group III nitride region 23, the Group III nitride active region 27, and a portion of the n-type Group III nitride region of the Group III nitride region 25. The mesa 37 is located on the remaining portion of the n-type Group III nitride region of the Group III nitride region 25, and at the bottom of the mesa 37, the mesa 37 is surrounded by the n-type Group III nitride front surface 25a of the Group III nitride region 25. A cathode electrode 33a may be disposed on the n-type Group III nitride front surface 25a of the Group III nitride region 25.

[0022] In a VCSEL 11 that provides a monolithic diffraction grating 17 having a peripheral portion that is not covered by the dielectric layer 18 and exposes a portion of the n-type III-nitride back surface 25b of the III-nitride region 25, the cathode electrode 33b may be disposed on the n-type III-nitride back surface 25b, with the n-type III-nitride back surface 25b located outside the monolithic diffraction grating 17 and the dielectric layer 18.

[0023] The dielectric layer 18 may include an unpatterned portion 18b and a patterned portion 18c. The patterned portion 18c may cover the back surface 25b of the n-type III-nitride region 25, such that the patterned portion 18c is provided with a periodic one-dimensional pattern 18a corresponding to the periodic one-dimensional pattern 17a. The unpatterned portion 18b may be replaced with another dielectric DBR stack 18d, such that the monolithic diffraction grating 17 includes not only the periodic one-dimensional pattern 17a but also another dielectric DBR stack 18d, where the periodic one-dimensional pattern 17a extends in the second axis direction Ax2 and the another dielectric DBR stack 18d includes two types of dielectric layers alternately arranged in the first axis direction Ax1.

[0024] Cavity 29 has a total cavity length L CAV and the total cavity length L CAV can be defined as the spacing between the monolithic diffraction grating 17 and the DBR 13 in the present VCSEL 11, which is greater than 1 micrometer. CAV is less than 30 micrometers because VCSEL 11 does not include any portion of the substrate used to grow semiconductor portion 15.

[0025] The semiconductor portion 15 has a conductive aperture portion 39a and a smaller conductive portion 39b surrounding the conductive aperture portion 39a. The open conductive portion 39a provides an electrical path for the VCSEL 11 from the anode electrode 31 to the cathode electrode 33. Carriers such as electrons and holes flow through the electrical path and recombine in the III-nitride active region 27 to generate light, which is emitted from one of the DBR 13 or the monolithic diffraction grating 17.

[0026] FIG. 2 is a flowchart showing the main steps of a method for fabricating a VCSEL. Referring to FIG. 2, a general description of an exemplary fabrication process according to this embodiment is provided. First, in S101, a substrate is prepared. In S102, an epitaxial lateral overgrowth (ELO) mask is formed on the substrate, and a patterned surface for a periodic one-dimensional pattern 18a is provided to generate a patterned ELO mask from the ELO mask. In S103, III-nitride is deposited on the substrate and the patterned ELO mask. This deposition on the patterned ELO mask can transfer the patterned surface of the patterned ELO mask to the III-nitride thus deposited. In S104, the III-nitride thus deposited is polished to obtain a flat surface and to adjust the cavity length of the VCSEL. In S105, a III-nitride semiconductor stack is grown on the planarized surface, followed by front-end processing to form an aperture structure, a DBR, and electrodes, thereby fabricating a product. In S106, the product is bonded to a support, and then the substrate is separated from the product, for example, by either cryogenic processing or laser lift-off, to obtain a device stack bonded to the support. The thus separated substrate is recyclable. In S107, back-end processing is applied to the device stack, and then in S108, the device stack is separated into semiconductor device chips.

[0027] A detailed description is given below of the VCSEL according to the present embodiment, in which the group III nitride can be deposited by, for example, metalorganic chemical vapor deposition (MOCVD).

[0028] 3A, 3B, 3C, and 3D illustrate steps for fabricating a monolithic diffraction grating 17. Referring to FIGS. 3A and 3B, a substrate 101 is provided. The substrate 10 can include one of a group III-nitride substrate, a GaN-on-sapphire substrate, a GaN-on-Si substrate, a silicon substrate, a sapphire substrate, or other foreign substrates. The group III-nitride substrate may include a gallium nitride-based material such as gallium nitride (GaN). Prior to performing epitaxial lateral overgrowth (ELO), an ELO mask 103 is formed on the surface of the substrate 101 by photolithography and etching. The ELO mask 103 includes an inorganic dielectric material such as silicon oxide. Specifically, a layer of inorganic dielectric material is deposited on the substrate 101 and then patterned twice for ELO as well as the monolithic diffraction grating 17.

[0029] 3A to 3C, a photolithography mask 105, such as a resist, is first formed on an inorganic dielectric layer 103, and the inorganic dielectric layer 103 is etched using the resist mask 105 to form an ELO mask 107 having an ELO pattern, where the ELO pattern includes an opening 107a into the substrate 101. After removing the photolithography mask 105, another photolithography mask 109, such as a resist, is formed on the ELO mask 107, and then a dielectric layer 110 is deposited on the mask 109. To provide a one-dimensional pattern in the ELO mask 107, the dielectric layer 110 is etched without a mask to expose the top of the mask 109. Then, removing the resist mask 109 produces a patterned ELO mask 111, which has a pattern 18a for the monolithic diffraction grating 17.

[0030] In this embodiment, the first patterning is to form an ELO pattern, and the second patterning is to form a pattern 18a for the monolithic diffraction grating 17. If necessary, the second patterning may be performed first before the first patterning.

[0031] 4 is a plan view showing a patterned ELO mask formed by two patterning steps. Referring to FIG. 4, the patterned ELO mask 111 has multiple patterned regions 111a that are separated from one another. Each of the patterned regions 111a is prepared separately from the opening 107a for the monolithic diffraction grating 17 of the VCSEL 11.

[0032] As shown in FIG. 3C, III-nitride is grown or deposited on the substrate 101 by MOCVD using a patterned ELO mask 111 to form a thick III-nitride region 113. At least a portion of the III-nitride region 113 may be doped with an n-type dopant, such as silicon. In this embodiment, the III-nitride region 113 may completely cover the diffraction grating 17. The III-nitride region 113 may be provided with a thickness greater than that of the nitride region 25. The III-nitride ELO region may be formed by doping at least a portion of the n-type dopant, such as silicon, onto the substrate 101. 5 / cm 2 Below, 10 4 / cm or less or 10 3 / cm 2 The following defect densities may be included:

[0033] 3D, prior to subsequent semiconductor deposition, III-nitride region 113 can be processed to obtain the desired length of optical cavity 29. For example, III-nitride region 113 can be polished or etched to form planarized III-nitride region 115, and the polished or etched surface of III-nitride region 115 is planarized to prepare it for subsequent epitaxial growth.

[0034] 5A, 5B, and 5C illustrate steps for fabricating the VCSEL 11. After planarization of the III-nitride region 113, as shown in FIG. 5A, a stacked semiconductor layer 117 is grown, which includes a III-nitride region 25, a III-nitride active region 27, and a p-type III-nitride region 23. The nitride region 25 can include a GaN-based or AlN-based material doped with an n-type dopant to provide electrons to the III-nitride active region 27, and the p-type III-nitride region 23 can include a GaN-based or AlN-based material doped with a p-type dopant to provide holes to the III-nitride active region 27. The III-nitride active region 27 can include a GaN-based or AlN-based material such as GaN, InGaN, AlN, or AlGaN. The III-nitride active region 27 may be provided with a single layer or quantum well structure, such as a single quantum well (SQW) or multiple quantum well (MQW). If desired, a buried tunnel junction can be grown after depositing the p-type III-nitride region 23.

[0035] 5B , a mask 119, such as a resist, is formed on the semiconductor stack 117 to produce a semiconductor aperture region from the semiconductor stack 117 and the polished III-nitride region 115. An aperture structure 117a for the semiconductor portion 15 is created from the semiconductor stack 115 by implanting ions, such as hydrogen atoms, n-type dopant atoms, and / or p-type dopant atoms, into the semiconductor stack 117 using the mask 119. The aperture structure 117a comprises a semiconductor aperture region 121 and an isolation region 123 surrounding the semiconductor aperture region 121.

[0036] The first half of an exemplary method for fabricating a VCSEL has been described above. Next, a description of the second half of an exemplary method according to this embodiment will be given.

[0037] After removing the mask 119, a conductive layer 125 is deposited on the aperture structure 117a, which covers the semiconductor aperture region 121 and the isolation region 123, as shown in Figure 5C. The conductive layer 125 may include a heavily doped III-nitride semiconductor layer, such as GaN or AlGaN, and / or an inorganic layer, such as indium tin oxide (ITO), and is transparent to light from the III-nitride active region 27.

[0038] 6A, 6B, and 6C illustrate a process for fabricating the VCSEL 11. As shown in FIG. 6A, a distributed Bragg reflector (DBR) stack 127 is formed on the conductive layer 125, specifically, a first dielectric layer 127a and a second dielectric layer 127b are alternately deposited to form an arrangement of these dielectric layers.

[0039] As shown in Figure 6B, a resist-like mask 129 is formed on DBR stack 127. DBR stack 127 is etched with mask 129 to expose a portion of conductive layer 125, thereby forming patterned DBR stack 131, or DBR 131. DBR 131 is aligned with monolithic diffraction grating 17 associated with patterned ELO mask 111 (17), thereby providing a substantial portion of optical cavity 29 for VCSEL 11.

[0040] 6C, a first electrode 133, such as an anode metal electrode, is formed on DBR 127 to provide product 135. First electrode 133 is disposed in contact with the exposed surface of conductive layer 125.

[0041] 7A, 7B, and 7C show steps for fabricating the VCSEL 11. As shown in Fig. 7A, the product 135 is bonded to a support ST at the first electrode 133.

[0042] The substrate 101 is removed from the product 135 by either low temperature processing or laser lift-off to expose the patterned ELO mask 111 associated with the monolithic grating 17, thereby producing the VCSEL stack 137. The VCSEL stack 137 is provided with a first electrode 133 located on its front side.

[0043] As shown in FIG. 7B, to form a second electrode, such as a cathode metal electrode, on the VCSEL stack 137, the patterned ELO mask 111 is treated with a mask 139, such as a resist, to form an opening 111b therein by photolithography and etching.

[0044] 7C, after removing the mask 139, a second electrode 141 is formed on the backside of the VCSEL stack 137 to create a VCSEL having a first electrode 133 and a second electrode 141 on opposite sides of the VCSEL 11. The second electrode 141 is disposed in contact with the backside of the III-nitride region 115.

[0045] The above process completes the fabrication of the VCSEL 11 type.

[0046] A description is given below of an example of a VCSEL according to this embodiment: Figures 8A, 8B and 8C show steps for fabricating a VCSEL 11.

[0047] After forming the semiconductor stack 117 as shown in FIG. 5A , a semiconductor mesa 143 and an aperture structure 117a are fabricated from the semiconductor stack 117 to expose the n-type III-nitride region 115, as shown in FIGS. 8A and 8B . In this embodiment, as shown in FIG. 8A , the semiconductor mesa 143 is first formed by photolithography and etching using a mask 145 such as a resist, and then the aperture structure 117a is formed as shown in FIG. 5B . Referring to FIG. 8B , the aperture structure 117a includes a semiconductor aperture region 121 and an isolation region 123 surrounding the semiconductor aperture region 121. If necessary, the aperture structure 117a can be formed first, and then the semiconductor mesa 143 can be formed.

[0048] 8C , the conductive layer 125 is grown on the aperture structure 117a, covering the semiconductor aperture region 121 and the isolation region 123, but not on the n-type III-nitride region 115. The conductive layer 125 is transparent to light from the III-nitride active region 27. The conductive layer 125 may also include a heavily doped III-nitride semiconductor layer, such as GaN or AlGaN, and / or an inorganic layer, such as indium tin oxide (ITO). The III-nitride semiconductor conductive layer 125 may be formed on the semiconductor mesa 143 by, for example, selective growth using an inorganic or dielectric mask 147.

[0049] 9A and 9B illustrate steps for fabricating the VCSEL 11. As shown in FIG. 9A, a DBR stack 127 is formed on a conductive layer 125. A portion of the DBR stack 127 is removed by etching to expose a portion of the conductive layer 125, thereby forming a patterned DBR stack 131, i.e., DBR 131. The DBR 131 is aligned with a monolithic diffraction grating 17 associated with a patterned ELO mask 111 (17), thereby providing a substantial portion of the optical cavity 29 in the VCSEL 11.

[0050] 9B, a first electrode 133, such as an anode metal electrode, and a second electrode 141, such as a cathode metal electrode, are formed on the exposed conductive layer 125 and the exposed n-type III-nitride region 115, respectively, thereby producing a product 149. The first electrode 133 and the second electrode 141 are both located on the front side of the semiconductor regions (125 and 115). Specifically, the first electrode 133 is disposed on the conductive layer 125 on the mesa 143 in contact with the conductive region 125, and the second electrode 141 is disposed in contact with the n-type III-nitride region 115.

[0051] Figures 10A, 10B, and 10C show a process for fabricating a VCSEL 11. The product 149 is bonded to a support in the same manner as shown in Figure 6C, with the support omitted in Figures 9B to 10C for simplicity.

[0052] 10A, substrate 101 is removed from product 149 to expose patterned ELO mask 111 associated with monolithic grating 17, thereby creating VCSEL stack 151. VCSEL stack 151 is provided with first electrode 133 and second electrode 141, with first electrode 133 and second electrode 141 located on the same side thereof.

[0053] 10B, in a VCSEL having the first and second electrodes on the same side, the patterned ELO mask 111 is left on the backside of the III-nitride region 115. The above process completes the fabrication of one type of VCSEL 11.

[0054] 10C, the dielectric material of the patterned ELO mask 111 can be removed to expose the periodic one-dimensional pattern 17a, which is transferred from the patterned ELO mask 111 to the III-nitride region 115. Thus, a monolithic diffraction grating 17 is formed on the backside of the III-nitride region 115.

[0055] The above process completes the fabrication of the VCSEL 11 type.

[0056] A description is given below with reference to several VCSELs according to this embodiment using Figures 11 to 15. The DBR mirror 13 can also function as a passivation / isolation layer between the p and n electrodes.

[0057] FIG. 11A is a plan view showing a VCSEL 11a according to this embodiment, and FIG. 11B is a cross-sectional view taken along line II shown in FIG. 11A.

[0058] An example process includes the following steps: 1. Depositing an ELO dielectric mask layer on a host substrate such as a GaN substrate, a GaN-on-sapphire template, or a GaN-on-Si template. 2. Patterning a diffraction grating on an ELO mask 3. Forming growth-assist portions, i.e., openings, in the ELO mask layer to expose the surface of the host substrate 101, thereby forming a patterned ELO mask 111. 4. Growing a GaN layer on the mask by an epitaxial lateral overgrowth procedure, thus allowing the layer to at least cover the lattice pattern of the laterally patterned ELO mask, thereby forming an epitaxial lateral overgrowth (ELO) nitride layer. 5. Planarizing the overgrown nitride layer by polishing or etching to control the length of the optical cavity. 6. Forming a semiconductor stack by resuming growth of the following: an n-GaN layer (e.g., about 1000 nm thick) for the cladding layer and n-contact layer; an active region (e.g., InGaN / GaN quantum well); an AlGaN electron blocking layer (e.g., about 30 nm); a p-GaN layer (e.g., about 200 nm thick); and a p-GaN layer (e.g., about 10 nm thick). 7. Carrying out ion implantation to define electrical and optical openings in the semiconductor stack 8. Forming a transparent conductive layer for the p-contact 9. Depositing the dielectric DBR mirror stack 10. Depositing contact metal electrodes and flip-chip bonding to a support (not shown). 11. Removing the substrate using either low temperature processes as described in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20) or laser lift-off if a template substrate is used, thereby significantly reducing costs, and where removing the substrate allows the same substrate to be used repeatedly. 12. Finally, deposit a metal contact electrode on the n-side. 13. Removing the patterned ELO mask 111

[0059] The monolithic diffraction grating 17 is provided on the surface of III-nitride region 25, such as n-GaN or unintentionally doped (UID)-GaN, which is grown on patterned ELO mask 111 by epitaxial lateral overgrowth techniques. The III-nitride thus grown includes a GaN diffraction grating, which is transferred from patterned ELO mask 111. III-nitride region 23 and III-nitride region 27 can be grown by MOCVD after forming III-nitride region 25 by polishing, which can be used to adjust the cavity length and / or planarize the III-nitride region. III-nitride region 23 and III-nitride region 27 are restarted device layers and also include an undoped active region and a p-type layer, each of which includes an alloy of In, Ga, and / or Al and N.

[0060] FIG. 12A is a plan view showing a VCSEL 11b according to this embodiment, and FIG. 12B is a cross-sectional view taken along line II-II shown in FIG. 12B.

[0061] An example process includes the following steps: 1. Forming a DBR mirror stack (18d) of periodically arranged dielectric layers on a host substrate (101), such as a GaN substrate, a GaN-on-sapphire template, or a GaN-on-Si template. 2. Depositing a separate dielectric layer (18c) on the DBR mirror stack (18d) 3. Forming a grating pattern in a separate dielectric layer (18c) for a monolithic grating pattern. 4. Forming growth-assist portions, i.e., openings, in the separate dielectric layer (17c) and the DBR mirror stack (18d) to expose the surface of the host substrate 101, thereby forming a patterned ELO mask 111. 5. Growing a GaN layer on the mask by an epitaxial lateral overgrowth procedure, allowing the laterally grown layer to at least cover the grating pattern, thereby forming an ELO nitride layer. 6. Planarizing the ELO nitride layer (113) by polishing or etching to control the length of the cavity. 7. Forming a semiconductor stack by resuming growth of the following layers: growing an n-GaN layer (e.g., about 1000 nm thick) for the cladding layer and n-contact layer, an active region (e.g., InGaN / GaN quantum well), an AlGaN electron blocking layer (e.g., about 30 nm), a p-GaN layer (e.g., about 200 nm thick), and a p-GaN layer (e.g., about 10 nm thick). 8. Ion implantation to define electrical and optical apertures 9. Depositing a transparent conductive layer (35) for the p-contact 10. Depositing the dielectric DBR mirror stack (13) 11. Depositing contact metal electrodes (31) and flip-chip bonding to a support (not shown). 12. Either by low-temperature processing as in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20) or by laser lift-off if a template substrate is used, thereby significantly reducing costs, where removal of the substrate allows the same substrate to be used repeatedly. 13. Finally, deposit the metal contact electrode (33b) on the n-side.

[0062] The monolithic diffraction grating 17 is provided on the surface of III-nitride region 25, such as n-GaN or UID-GaN, which is grown over the patterned ELO mask 11 by epitaxial lateral overgrowth. The III-nitride thus grown includes a GaN diffraction grating, which is transferred from the patterned ELO mask 111. The patterned ELO mask 111 is provided with an additional DBR mirror 18d. The additional DBR mirror 18d is positioned adjacent to the GaN diffraction grating 17a above it and is bonded to the diffraction grating 17a, thereby forming a single mirror. III-nitride region 23 and III-nitride region 27 can be grown by MOCVD after forming III-nitride region 25 by polishing, which can adjust the cavity length and / or planarize the III-nitride region. III-nitride region 23 and III-nitride region 27 are restarted device layers comprising an undoped active region and a p-type layer, respectively, each of which comprises an alloy of N with In, Ga and / or Al.

[0063] The periodic one-dimensional pattern 17a and the additional DBR mirror (18d) are combined to increase reflectivity without complexity, and the additional DBR mirror (18d) is positioned in contact with the dielectric layer containing the periodic one-dimensional pattern 17a and the periodic one-dimensional pattern 18a.

[0064] FIG. 13A is a plan view showing a VCSEL 11c according to this embodiment, and FIG. 13B is a cross-sectional view taken along line III-III shown in FIG. 13A.

[0065] An example process includes the following steps: 1. Forming an ELO dielectric mask layer on a host substrate, such as a GaN substrate, a GaN-on-sapphire template, or a GaN-on-Si template. 2. Patterning the diffraction grating on the ELO mask layer 3. Forming growth-assist portions, i.e., openings, in the ELO mask layer to expose the surface of the host substrate 101, thereby forming a patterned ELO mask 111. 4. Growing a GaN layer on the ELO mask by an epitaxial lateral overgrowth procedure, thus allowing the laterally grown layer to cover at least the lattice pattern, thereby forming an ELO nitride layer. 5. Planarizing the ELO nitride layer by polishing or etching to control the length of the optical cavity. 6. Forming a semiconductor stack by resuming growth of the following: an n-GaN layer (e.g., about 1000 nm thick) for the cladding layer and n-contact layer; an active region (e.g., InGaN / GaN quantum well); an AlGaN electron blocking layer (e.g., about 30 nm); a p-GaN layer (e.g., about 200 nm thick); and a p-GaN layer (e.g., about 10 nm thick). 7. Creating a mesa from the semiconductor stack and forming an n-GaN contact region on the semiconductor stack. 8. Ion implantation to define electrical and optical apertures 9. Depositing a transparent conductive layer (35) for the p-contact 10. Depositing a dielectric DBR mirror (13) (this can be used as isolation between the p-side pad and the n-side pad) 11. Depositing contact metal electrodes (31 and 33a) and flip-chip bonding to a support (not shown). 12. Removal of the substrate either by low temperature processing in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20) or by laser lift-off if a template substrate is used. Removing the substrate 101 allows the same substrate to be reused, thereby significantly reducing costs. 13. Removing the patterned ELO mask 111 to expose the III-nitride region 25, the backside of which is provided with the periodic one-dimensional pattern 17a of the monolithic diffraction grating 17;

[0066] The dielectric DBR mirror 13 is located on a conductive layer 35, which is provided on top of the mesa 37 and extends from the anode electrode 31 to the cathode electrode 33a, covering the top and side surfaces of the mesa 37. Another dielectric material film 45 may be located on the dielectric DBR mirror 13 and may extend from the anode electrode 31 to the cathode electrode 33a above it. The dielectric DBR mirror 13, if any, and the other dielectric material film 45 serve as a passivation film. The mesa 37 allows the anode electrode 31 and cathode electrode 33a to be located on the same side of the VCSEL 11c, allowing the VCSEL 11c to be mounted by flip-chip bonding.

[0067] The monolithic diffraction grating 17 is provided on the surface of III-nitride region 25, such as n-GaN or UID-GaN, which is grown on a patterned ELO mask 111 by epitaxial lateral overgrowth. The III-nitride thus grown includes a GaN diffraction grating, which is transferred from the patterned ELO mask 111. III-nitride region 23 and III-nitride region 27 can be grown by MOCVD after forming III-nitride region 25 by polishing or etching, which can be used to adjust the cavity length and / or planarize the III-nitride region. III-nitride region 23 and III-nitride region 27 are restarted device layers, including an undoped active layer and a p-type layer, respectively, each of which includes an alloy of In, Ga, and / or Al with N.

[0068] FIG. 14A is a plan view showing a VCSEL 11d according to this embodiment, and FIG. 14B is a cross-sectional view taken along line IV-IV shown in FIG. 14A.

[0069] An example process includes the following steps: 1. Forming a DBR mirror stack (18d) of periodically arranged dielectric layers on a host substrate 101, such as a GaN substrate, a GaN-on-sapphire template, or a GaN-on-Si template. 2. Depositing a separate dielectric layer (18c) on the DBR mirror stack (18d) 3. Forming a monolithic grating pattern in a separate dielectric layer (18c) 4. Forming openings in the growth-assist portions, i.e., the separate dielectric layer (18c) and the DBR mirror stack (18d), to expose the surface of the host substrate 101, thereby forming a patterned ELO mask 111. 5. Growing a GaN layer on the mask by an epitaxial lateral overgrowth procedure to at least cover the laterally grown grating pattern, thereby forming an ELO nitride layer. 6. Planarizing the ELO nitride layer (113) by polishing or etching to control the cavity length. 7. Forming a semiconductor stack by resuming growth of the following layers: an n-GaN layer (e.g., about 1000 nm thick) for the cladding layer and n-contact layer, an active region (e.g., InGaN / GaN quantum well), an AlGaN electron blocking layer (e.g., about 30 nm), a p-GaN layer (e.g., about 200 nm thick), and a p-GaN layer (e.g., about 10 nm thick). 8. Fabricating a mesa from the semiconductor stack and forming a contact n-GaN region on the semiconductor stack. 9. Ion implantation to define electrical and optical apertures 10. Depositing a transparent conductive layer (35) for the p-contact 11. Depositing a dielectric DBR mirror (13) (this can be used as insulation between the p-side pad and the n-side pad) 12. Depositing contact metal electrodes (31 and 33a) and flip-chip bonding to a support (not shown) 13. Removing the substrate 101 by low-temperature processing as described in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20), or by laser lift-off if a template substrate is used. Removing the substrate allows the same substrate to be reused repeatedly, thereby significantly reducing costs.

[0070] The dielectric DBR mirror 13 is located on a conductive layer 35, which is provided on top of the mesa 37 and extends from the anode electrode 31 to the cathode electrode 33a, covering the top and side surfaces of the mesa 37. Another dielectric material film 45 may be located on the dielectric DBR mirror 13 and may extend from the anode electrode 31 to the cathode electrode 33a. The dielectric DBR mirror 13 and, if present, the other dielectric material film 45 serve as passivation films. The mesa 37 allows the anode electrode 31 and the cathode electrode 33a to be located on the same side of the VCSEL 11d, allowing the VCSEL 11d to be mounted by flip-chip bonding.

[0071] The monolithic diffraction grating 17 is formed on the surface of a III-nitride region 25, such as n-GaN or UID-GaN, and is grown over a patterned ELO mask 111 by epitaxial lateral overgrowth. The grown III-nitride includes a GaN diffraction grating, which is transferred from the patterned ELO mask 111. An additional DBR mirror 18d is formed on the patterned ELO mask 111. The additional DBR mirror 18d is positioned adjacent to the GaN diffraction grating 17a above it and combined with the diffraction grating 17a to form a single mirror. The periodic one-dimensional pattern 17a and the additional DBR mirror 18d can be combined to increase reflectivity without complexity, and the additional DBR mirror 18d is positioned in contact with the periodic one-dimensional pattern 17a and the dielectric layer containing the periodic one-dimensional pattern 18a. III-nitride regions 23 and 27 can be grown by MOCVD after forming III-nitride region 25 by polishing or etching, which can adjust the cavity length and / or planarize the III-nitride regions. III-nitride regions 23 and 27 are restarted device layers and also include an undoped active region and a p-type layer, respectively, each of which includes an alloy of In, Ga, and / or Al with N.

[0072] FIG. 15A is a plan view of a VCSEL 11e according to this embodiment, and FIG. 15B is a cross-sectional view taken along line VV shown in FIG. 15A.

[0073] An example process includes the following steps: 1. Forming an ELO mask on a host substrate, such as a GaN substrate, a GaN-on-Sapphire template, or a GaN-on-Si template. 2. Patterning a diffraction grating on the ELO mask 3. Forming a growth assisting portion on the host substrate 4. Growing a GaN layer on the mask by an epitaxial lateral overgrowth procedure, such that the laterally grown layer at least covers the lattice pattern, thereby forming an ELO nitride layer. 5. Planarizing the ELO nitride layer by polishing or etching to control the length of the optical cavity 6. Forming a semiconductor stack by resuming growth for the following layers: an n-GaN layer (e.g., about 1000 nm thick) for the cladding layer and n-contact layer; an active region (e.g., InGaN / GaN or InGaN / InGaN quantum well); an AlGaN electron blocking layer (e.g., about 30 nm); a p-GaN layer (e.g., about 200 nm thick), and a buried tunnel junction (51) including a p-GaN layer (e.g., about 10 nm thick) and an n-GaN layer (e.g., about 10 nm). 7. Creating a mesa from the semiconductor stack to form a contact n-GaN region 8. Ion implantation to define electrical and optical apertures 9. Depositing a transparent conductive layer (35) for the p-contact 10. Depositing the dielectric DBR mirror (13) and passivation film 45 11. Depositing contact metal electrodes (31) and flip-chip bonding to a support (not shown). 12. Removing the substrate (101) either by low-temperature processing or by laser lift-off if a template substrate is used, as in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20). Removing the substrate allows the same substrate to be used repeatedly, thereby significantly reducing costs.

[0074] The VCSEL 11e further includes a buried tunnel junction 51 disposed between the p-type III-nitride region 23 and the DBR 13. The buried tunnel junction 51 is a p ++ -GaN and other highly doped p-type III-nitrides, and n ++ and highly doped n-type III-nitrides such as GaN. ++ A -GaN layer is deposited on the p-type III-nitride region 23 and then n ++ -GaN layer is p ++ - is deposited on the GaN layer to form a tunnel junction. ++ The GaN layer is disposed in contact with an n-type conductive layer 35. At the tunnel junction, the conductivity type of the III-nitride changes to the other conductivity type. A reverse bias voltage is applied to the tunnel junction, causing carriers to tunnel through the junction.

[0075] The tunnel junction 51 in this embodiment can be applied to any one of the former exemplary VCSELs 11a to 11d. The inclusion of the tunnel junction improves the performance of the VCSEL and also mitigates ITO absorption.

[0076] The dielectric DBR mirror 13 is located on the conductive layer 35, which is disposed on top of the mesa 37. The dielectric material film 45 or the dielectric DBR mirror 13 extends from the anode electrode 31 to the cathode electrode 33a, covers the top and side surfaces of the mesa 37, and also serves as a passivation film. The mesa 37 allows the anode electrode 31 and the cathode electrode 33a to be located on the same side of the VCSEL 11e, allowing the VCSEL 11e to be mounted by flip-chip bonding.

[0077] The monolithic diffraction grating 17 is disposed on the surface of a III-nitride region 25, such as n-GaN or UID-GaN, which is grown by epitaxial lateral overgrowth on a patterned ELO mask 111. The III-nitride thus grown includes a GaN diffraction grating, which is transferred from the patterned ELO mask 111. The III-nitride regions 23 and 27 and the buried tunnel junction 51 (tunnel junction) may be grown by MOCVD after forming the III-nitride region 25 by polishing or etching, which can adjust the cavity length and / or planarize the III-nitride region. The III-nitride regions 23 and 27 are reopened device layers, including an undoped active layer and a p-type layer, respectively, each of which includes an alloy of In, Ga, and / or Al with N.

[0078] A technical explanation of some technical terms related to the VCSEL according to this embodiment will be given below.

[0079] Host substrate and ELO mask

[0080] In one embodiment, the GaN-based layer 113 is grown by ELO on the host substrate 101 using a patterned ELO mask 111 made of SiO, where the GaN-based layer 113 does not coalesce on the SiO. The patterned ELO mask 111 can be composed of stripe-shaped openings 107a, and the SiO stripes of the patterned ELO mask 111 define the spacing between the openings 107a to enable growth of high-quality III-nitride semiconductor layers and prevent bowing or bending of the substrate 101 during epitaxial growth by avoiding coalescence between adjacent semiconductor layers. This can provide a VCSEL with reduced defect densities, such as dislocations and stacking faults. Furthermore, these techniques can be used with heterosubstrates such as sapphire, SiC, LiAlO, and Si, as long as they allow for growth of ELO GaN-based layers.

[0081] Patterned grating on ELO mask

[0082] Diffraction gratings can be formed with patterned ELO masks, for example nanoimprinting, which is a commercially acceptable technique compared to other techniques such as E-beam lithography or holography.

[0083] Diffraction gratings can be formed by first depositing a photosensitive material on an ELO mask and then applying the desired grating pattern to the photosensitive material. Alternatively, nanoimprinting, E-beam, or holography can also be used to print the desired grating pattern. The desired grating pattern is then transferred to a photoresist material. For example, grating pattern parameters, such as height (H), period (P), and width (W), can be defined using the factors H / P and W / P, as shown in Figure 3D. The transverse electrical (TE) mode map of n-GaN grating reflectivity can exceed 99% at an incident light wavelength of 405 nm when H / P is approximately 0.27 and W / P is approximately 0.35 with a period P of approximately 375 nm. After transferring the grating pattern to the photoresist, a dielectric material, such as SiO2, is deposited to completely fill the photoresist. Etching, such as reactive ion etching, is performed to expose the underlying photoresist. Chemical lift-off of the photoresist then leaves the grating pattern on the ELO mask, thereby forming a patterned ELO mask.

[0084] Forming a grating on top of the ELO mask containing the DBR mirror structure

[0085] Diffraction gratings can be formed by first depositing a photosensitive material on an ELO mask (in this case, a DBR mirror used as an ELO mask) and then applying the desired diffraction grating pattern to the photosensitive material. Alternatively, nanoimprinting, electron beam, or holography can be used to print the desired grating pattern. The desired grating pattern is then transferred to a photoresist material. For example, grating pattern parameters such as height (H), period (P), and width (W) can be defined by the factors H / P and W / P.

[0086] Once the grating pattern is transferred onto the photoresist, a dielectric material, e.g., SiO2, is deposited over the pattern to completely fill it, and an etch, e.g., reactive ion etching, is performed to expose the underlying photoresist. Chemical lift-off of the photoresist then leaves the grating pattern in the SiO2 layer on top of the DBR structure.

[0087] Growth of III-nitride layers

[0088] Next, III-nitride region 113 is grown by MOCVD. The III-nitride region is provided with a grating shape at the bottom of the III-nitride thus grown, as shown in FIG. 3C. III-nitride region 113 is polished or etched to a desired thickness to form planarized III-nitride region 115. After adjusting the thickness of III-nitride layer 113 by polishing or etching, III-nitride stack 117 is grown thereon.

[0089] Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as III-element sources, and ammonia (NH3) is used as the source gas to supply nitrogen. Hydrogen (H2) and / or nitrogen (N2) are used as carrier gases. Silane (SiH4) and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants, respectively.

[0090] The pressure can usually be set to 50 to 760 Torr. III-nitride based semiconductor layers are generally grown at a temperature range of 700 to 1250°C.

[0091] Exemplary growth parameters include: TMG may be 12 sccm; NH3 may be 8 slm; carrier gas may be 3 slm; SiH4 may be 1.0 sccm; and V / III ratio may be about 7700.

[0092] In one embodiment, the growth pressure is in the range of 50 to 760 Torr, preferably 100 to 300 Torr, to obtain large widths of the island-shaped III-nitride semiconductor regions; the growth temperature can be in the range of 900 to 1200°C; the V / III ratio can be in the range of 50 to 30,000, more preferably 3,000 to 10,000; the TMG flow rate can be in the range of 2 to 20 sccm; the NH3 gas can be in the range of 3 to 10 slm; and the carrier gas can be hydrogen gas alone or both hydrogen gas and nitrogen gas. After about 2 to 8 hours of growth, the ELO GaN-based layer had a thickness of about 8 to 50 micrometers and a width of about 20 to 150 micrometers. The ELO GaN-based layer thus grown also extends laterally along the ELO mask, providing fewer defective crystalline regions (wings) of epitaxial lateral overgrowth.

[0093] ion implantation

[0094] Ion implantation is used to create electrical and optical apertures in GaN-based layers by damaging the GaN-based layer outside the aperture, so that the damaged GaN-based material is no longer conductive. This method keeps the surface planar and can provide very little refractive index waveguiding between the aperture and damaged regions. However, the damaged regions have the potential to increase optical losses within the cavity and tend to have higher absorption values ​​than the unimplanted material in the aperture region. Heavy ions, such as aluminum (Al) and boron (B), can be used for the ion implantation procedure.

[0095] transparent conductor

[0096] ITO can be used as a commonly used transparent current spreading layer. The inclusion of ITO in a VCSEL can cause additional absorption; however, this can be reduced by lowering the electromagnetic wave intensity around the ITO layer. Other approaches, such as tunnel junctions, can also be used to spread the current and reduce optical absorption.

[0097] tunnel junction

[0098] Tunnel junctions are an alternative to the use of ITO. Tunnel junctions allow for the injection of holes through an n-type semiconductor into the p-side of the device. This is achieved by using a junction between a highly doped n-type region and a highly doped p-type region under reverse bias, allowing electrons to tunnel from the valence band of the p-type region to the conduction band of the n-type region.

[0099] Dielectric Bragg Reflector (DBR)

[0100] Traditionally, VCSELs utilize epitaxial DBRs, consisting of either bilayer AlN / GaN or bilayer AlInN / GaN, or a dielectric DBR mirror. Primary considerations in selecting a DBR design include ease of fabrication, where the DBR mirror includes alternating dielectric layers that are bonded together to form a reflective mirror above the VCSEL's resonant cavity. For example, a combination of SiO2 / Ta2O5 dielectric layers can be used as a dielectric DBR mirror.

[0101] Monolithic epitaxial GaN lattice

[0102] A key part of a VCSEL is the reflector. Typically, a dielectric DBR is used as the mirror. However, due to issues with electrical injection or thermal management, at least one side of the mirror for the VCSEL's resonant cavity should be replaced with a better alternative. In the present VCSEL, a monolithic diffraction grating is used, formed on the wings of an epitaxial lateral overgrown GaN, as a good alternative to the DBR mirror.

[0103] Monolithic epitaxial GaN diffraction gratings have periodic structures such as GaN recesses or protrusions arranged on the surface of GaN, where the height (H), width (W), and period (P) of the arrangement are comparable to the wavelength of the VCSEL. When light strikes the grating perpendicularly, it is diffracted in various directions depending on the wavelength and period of the grating. By appropriately choosing the grating period and filling factors such as W / P and H / P, all the light energy can be reflected back.

[0104] While there are several alternatives for demonstrating gratings, the present disclosure provides a unique method for demonstrating sub-wavelength gratings on devices, thus preventing the device layers from being exposed to any etching environment during the fabrication process.

[0105] Metal Pad

[0106] Metals such as gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), and titanium (Ti) are used as the material for the metal pads. The metal layer can be formed by sputtering, evaporation, or plating.

[0107] This disclosure relates to an improved fabrication method demonstrating a monolithic grating for III-nitride VCSELs. Specifically, this disclosure provides a VCSEL operating at visible or ultraviolet wavelengths, with a monolithic GaN grating as one of its reflective mirrors. A novel and inventive feature of the disclosure is the integration of the grating via epitaxial lateral overgrowth. This approach avoids exposing device layers to physical etching during the fabrication process, in which semiconductor device layers are bombarded with heavy ions, such as aluminum or boron, to form the desired grating shape. This process can ultimately increase layer resistance due to ion bombardment and introduce current leakage paths. Additionally, such practicalities can damage the device's active region or adjacent epitaxial layers. The process detailed in this disclosure is expected to provide significant improvements in device performance and reduced manufacturing costs by eliminating complex procedures. This disclosure simplifies the fabrication of gratings operating at VCSEL wavelengths. This disclosure is of interest for applications in non-patent literature 7 (NPL7) to 15 (NPL15) for visible light emitting lasers for data communications, LiDAR, biochemical and environmental sensing, scientific instrumentation, holographic data storage, augmented / virtual (AR / VR) displays, and illumination. Because cleaved or etched facets are not required for laser operation, this disclosure will be useful in hybrid integration with other optoelectronic components, such as silicon photonics.

[0108] The use of a monolithic epitaxial lattice has the following advantages:

[0109] A sufficiently long cavity is used without excessive diffraction losses, with two reflective mirrors defining the VCSEL cavity, where this disclosure proposes using n-GaN for the lattice arrangement, and designing the lattice pattern near the active region, i.e., on the p-side, is complicated and may damage the device layers.

[0110] Better thermal management through sufficiently long cavities and / or contact placement on nitride layer

[0111] Gratings are commonly placed on the p-GaN side of the device to facilitate easy fabrication at the expense of damage, whereas formation of the n-side grating requires removal of the substrate, which is complex and tedious and not available for all crystal planes of III-nitrides.

[0112] The n-side grating is typically formed after removing the device layers from the substrate, whereas in this disclosure the grating is formed before forming the device layers.

[0113] In this disclosure, the grating is designed to be formed either on the host substrate or on a material disposed on the substrate, thus preventing damage to the device layers during laser lift-off.

[0114] A dielectric DBR can be formed over the top planar surface to improve its reflectivity.

[0115] Template substrates such as GaN / sapphire or GaN / Si, called foreign substrates, can be used to demonstrate diffraction gratings.

[0116] When a template substrate is used, laser lift-off is adopted. In a conventional scenario, the use of a template substrate may damage the device layer, but the present disclosure using the ELO method may cause less damage because the ELO mask may act as a protection layer for the device layer.

[0117] In this disclosure, the n-side grating is realized with the aid of ELO mask design. Furthermore, substrate removal has been demonstrated for almost all crystal orientations of GaN substrates in Non-Patent Document 16 (NPL16) to Non-Patent Document 20 (NPL20). The application of laser lift-off to foreign substrates is readily available. High-quality, large-sized GaN substrates are very expensive, and current ELO technology can unlock the use of foreign substrates in VCSEL fabrication.

[0118] Designing diffraction gratings that operate at visible wavelengths is laborious, complex, and sophisticated. Electron beam lithography and holography are generally preferred over nanoimprinting. In nanoimprinting, applying excessive force to imprint a pattern on a device layer can damage or destroy the device layer. In this disclosure, however, nanoimprinting to form the diffraction grating pattern is performed on either a thick host substrate or an ELO mask, allowing the grating to be printed using any existing technology.

[0119] Grating formation

[0120] The n-side grating surface can be formed in several ways, including, but not limited to, forming a grating pattern on a host substrate with an ELO mask. The host substrate can include a GaN substrate, a GaN / sapphire template, or a GaN / Si template. The procedure for obtaining the grating is described in detail below.

[0121] Disposing a dielectric thin film, for example, about 100 nm, on the host substrate. Coating a photoresist (PR) material or nanoimprint assist material onto a dielectric thin film Transferring a diffraction grating pattern into the material Filling the pattern with a dielectric material Exposing nanoimprint-assist materials or PR materials by etching Leaving the desired grating pattern on the ELO mask by removing the PR material or nanoimprint-assist material

[0122] A procedure for obtaining an ELO mask with a grating pattern is presented with reference to the drawings.

[0123] To aid in lateral semiconductor growth, the III-nitride material underlying the ELO mask is exposed, either in the form of stripes or openings of any other shape.

[0124] The procedure begins with providing a host substrate, preferably a GaN substrate, which has a low dislocation density (1 cm -2 10 per 5 ~10 6 The ELO method has low defect density (defects of GaN-on-silicon and GaN-on-sapphire). Alternatively, template substrates such as GaN-on-silicon and GaN-on-sapphire may be used. A host substrate, such as a GaN substrate, GaN-on-sapphire, or GaN-on-silicon template, is used as an ELO seed layer. Using these template substrates can improve the yield of III-nitride devices and thus reduce production costs. Non-Patent Document 15 (NPL15) to Non-Patent Document 20 (NPL20) propose using the ELO method to form low-defect epitaxial layers for optical devices such as edge-emitting lasers, micro-LEDs, and VCSELs.

[0125] A first aspect of the above embodiment is a vertical cavity surface emitting laser (VCSEL) comprising: a first distributed Bragg reflector (DBR) including first and second dielectric layers alternately arranged in a first axis direction; and a semiconductor portion including a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, wherein the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged in the first axis direction, and the Group III nitride region comprises an n-type Group III nitride region, wherein the semiconductor portion includes a monolithic diffraction grating having a periodic one-dimensional pattern, and the monolithic diffraction grating, the Group III nitride active region, and the distributed Bragg reflector are arranged in the first axis direction to form an optical cavity, and the periodic one-dimensional pattern extends in a second axis direction that intersects the first axis direction.

[0126] In a second aspect of this embodiment, the VCSEL according to the first aspect further comprises a dielectric layer disposed on the semiconductor portion, the dielectric layer extending over the monolithic diffraction grating and covering the periodic one-dimensional pattern.

[0127] In a third aspect of this embodiment, the VCSEL according to the second aspect further comprises a second distributed Bragg reflector (DBR), wherein the dielectric layer is disposed between the second DBR and the semiconductor portion, the second DBR including a third dielectric layer and a fourth dielectric layer alternately arranged in the first axis direction, and the second DBR and the periodic one-dimensional pattern are combined together to form a single reflector.

[0128] In a fourth aspect of this embodiment, a VCSEL according to any one of the first to third aspects may further comprise a conductive layer disposed on the semiconductor portion, a portion of the conductive layer being disposed between the first DBR and the semiconductor portion, and a first electrode disposed on the conductive layer outside the DBR, the first electrode being disposed in contact with the conductive layer.

[0129] In a fifth aspect of this embodiment, the VCSEL according to the fourth aspect further comprises a second electrode, the III-nitride region having a first surface and a second surface opposite the first surface, the monolithic diffraction grating being formed on the first surface, and the second electrode being disposed on the second surface.

[0130] In a sixth aspect of this embodiment, the VCSEL according to the fourth aspect further comprises a second electrode, the III-nitride region having a first surface and a second surface opposite the first surface, the monolithic diffraction grating being formed on the first surface, and the second electrode being disposed on the first surface.

[0131] In a seventh aspect of this embodiment, in a VCSEL according to any of the first to sixth aspects, the total cavity length of the optical cavity may be greater than 1 micrometer.

[0132] In an eighth aspect of this embodiment, in the VCSEL according to any one of the first to seventh aspects, the distance between the monolithic diffraction grating and the DBR can be 30 micrometers or less.

[0133] A ninth aspect of the present embodiments is a method for fabricating a vertical cavity surface emitting laser (VCSEL): forming a patterned epitaxial lateral overgrowth (ELO) mask on a surface of a substrate, the substrate comprising one of a III-nitride substrate, a silicon substrate, a sapphire substrate, a GaN-on-sapphire template, or a GaN-on-silicon template, the patterned ELO mask including a diffraction grating pattern and an opening to the surface of the substrate; growing III-nitride on the substrate using the patterned ELO mask, so that the III-nitride covering the diffraction grating pattern is deposited on the surface of the substrate. forming a III-nitride region, wherein the diffraction grating pattern is transferred to the III-nitride region; growing a semiconductor stack including an n-type III-nitride region, a III-nitride active region, and a p-type III-nitride region; growing a conductive layer after growing the semiconductor stack; forming a first distributed Bragg reflector (DBR) on the conductive layer to produce a product, the DBR including alternating first and second dielectric layers; and removing the substrate from the product to expose the patterned ELO mask, wherein the diffraction grating pattern includes a periodic one-dimensional pattern extending along the surface of the substrate.

[0134] In a tenth aspect of this embodiment, the method according to the ninth aspect may further comprise forming a first metal electrode at the conductive layer after forming the first DBR and before removing the substrate.

[0135] In an eleventh aspect of this embodiment, the method according to the ninth or tenth aspect may further comprise planarizing the III-nitride region by at least one of polishing or etching before growing the semiconductor stack.

[0136] In a twelfth aspect of this embodiment, the method according to any one of the ninth to eleventh aspects may further comprise: before growing the conductive layer, generating a mesa from the semiconductor layer stack by etching to form an etched surface of the semiconductor layer stack, the mesa forming the etched surface of the semiconductor layer stack that includes the III-nitride active region; and forming a second electrode on the etched surface of the semiconductor layer stack.

[0137] In a thirteenth aspect of this embodiment, the method according to any one of the ninth to eleventh aspects can further include, after removing the substrate, removing a portion of the patterned ELO mask to expose the III-nitride region; and forming a second metal electrode on the exposed surface of the III-nitride region.

[0138] In a fourteenth aspect of this embodiment, the method according to any one of the ninth to twelfth aspects may further comprise removing the patterned ELO mask after removing the substrate.

[0139] In a fifteenth aspect of this embodiment, in the method according to any one of the ninth to thirteenth aspects, the patterned ELO mask can further comprise a second distributed Bragg reflector comprising third and fourth dielectric layers alternately arranged on the surface of the substrate.

[0140] While the principles of this invention have been explained and illustrated in preferred embodiments, it will be understood by those skilled in the art that the invention can be changed in arrangement and detail without departing from such principles. We therefore claim all modifications and variations that are within the spirit and scope of the following claims. [Explanation of symbols]

[0141] 11,11a, 11b, 11c, 11d, 11e VCSEL 13 Distributed Bragg Reflector (DBR) 15 Semiconductor Department 17 Monolithic diffraction grating 17a, 18 Periodic one-dimensional patterns 17b Non-patterned section 17c Pattern section 23 p-type Group III nitride region 25 n-type III-nitride region 27 III nitride active region 29 Optical Cavity 31 Anode electrode 33, 33a, 33b cathode electrodes 35 Conductive layer 37 Mesa L CAV Total cavity length Ax1, Ax2 Axial direction

Claims

1. A vertical cavity surface emitting laser (VCSEL) comprising: a first distributed Bragg reflector (DBR) including first and second dielectric layers alternately arranged in a first axial direction; a semiconductor portion including a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, wherein the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged in the first axis direction, and the Group III nitride region includes an n-type Group III nitride region; Including, the semiconductor portion includes a monolithic diffraction grating having a periodic one-dimensional pattern, the monolithic diffraction grating, the III-nitride active region, and the first distributed Bragg reflector are arranged in the first axis direction to form an optical cavity, and the periodic one-dimensional pattern extends in a second axis direction that intersects the first axis direction; Vertical-cavity surface-emitting laser.

2. a dielectric layer disposed on the semiconductor portion, the dielectric layer extending over the monolithic diffraction grating and covering the periodic one-dimensional pattern; 2. The vertical cavity surface emitting laser according to claim 1.

3. further comprising a second distributed Bragg reflector (DBR); the dielectric layer is disposed between the second DBR and the semiconductor portion, the second DBR includes third and fourth dielectric layers alternately arranged in the first axis direction; the second DBR and the periodic one-dimensional pattern are combined together to form a single reflecting mirror; 3. The vertical cavity surface emitting laser according to claim 2.

4. a conductive layer disposed on the semiconductor portion, a portion of the conductive layer being disposed between the first DBR and the semiconductor portion; a first electrode disposed on the conductive layer outside the first DBR, the first electrode being in contact with the conductive layer; Further provided with 4. The vertical cavity surface emitting laser according to claim 1.

5. Further comprising a second electrode; the III-nitride region has a first surface and a second surface opposite the first surface; the monolithic diffraction grating is formed on the first surface, and the second electrode is disposed on the second surface.

5. The vertical cavity surface emitting laser according to claim 4.

6. Further comprising a second electrode; the III-nitride region has a first surface and a second surface opposite the first surface; the monolithic diffraction grating is formed on the first surface, and the second electrode is disposed on the first surface.

5. The vertical cavity surface emitting laser according to claim 4.

7. the total cavity length of the optical cavity is greater than 1 micrometer; 7. The vertical cavity surface emitting laser according to claim 1.

8. the distance between the monolithic diffraction grating and the first DBR is 30 micrometers or less; 8. The vertical cavity surface emitting laser according to claim 1.

9. 1. A method for fabricating a vertical cavity surface emitting laser (VCSEL), comprising: forming a patterned epitaxial lateral overgrowth (ELO) mask over a surface of a substrate, the substrate comprising one of a III-nitride substrate, a silicon substrate, a sapphire substrate, a GaN-on-sapphire template, or a GaN-on-silicon template, the patterned ELO mask comprising a diffraction grating pattern and an opening to the surface of the substrate; growing a III-nitride layer on the substrate using the patterned ELO mask to form a III-nitride region overlying the grating pattern, wherein the grating pattern is transferred to the III-nitride region; growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region, and a p-type Group III nitride region; growing a conductive layer after growing the semiconductor stack; forming a first distributed Bragg reflector (DBR) on the conductive layer to produce a product, the first DBR including alternating first and second dielectric layers; removing the substrate from the product to expose the patterned ELO mask; Equipped with the diffraction grating pattern comprises a periodic one-dimensional pattern extending along the surface of the substrate; method.

10. and forming a first metal electrode at the conductive layer after forming the first DBR and before removing the substrate.

10. The method of claim 9.

11. and planarizing the III-nitride region by at least one of polishing or etching before growing the semiconductor stack. The method according to claim 9 or claim 10.

12. creating a mesa from the semiconductor stack by etching to form an etched surface of the semiconductor stack before growing the conductive layer, the mesa forming the etched surface of the semiconductor stack that includes the III-nitride active region; forming a second electrode on the etched surface of the semiconductor stack; Further preparations 12. The method according to any one of claims 9 to 11.

13. removing portions of the patterned ELO mask after removing the substrate to expose the Group III nitride regions; forming a second metal electrode on the exposed surface of the Group III nitride region; Further preparations 12. The method according to any one of claims 9 to 11.

14. further comprising removing the patterned ELO mask after removing the substrate.

13. The method according to any one of claims 9 to 12.

15. the patterned ELO mask further includes a second distributed Bragg reflector including third and fourth dielectric layers alternately disposed on the surface of the substrate; 14. The method according to any one of claims 9 to 13.

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