Semiconductor photodetector and its manufacturing method

Abstract

To provide a semiconductor photodetector with high light-receiving sensitivity and high ESD withstand voltage.SOLUTION: A semiconductor photodetector includes an n-type InP substrate 110, an n-type InGaAs light absorption layer 130, and an InP window layer 140, and in the InP window layer 140, in a semiconductor light receiving element 100 in which a p-type impurity diffusion region 150 reaching the top of the n-type InGaAs light absorption layer 130 is formed, the n-type InGaAs light absorption layer 130 has a thickness of 2.2 μm or more, and a carrier density due to n-type impurities of 2.5×1015 / cm3 or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-receiving element and a method for manufacturing the same, and more particularly to a semiconductor light-receiving element that receives light in the infrared region as a wavelength, and a method for manufacturing the same. [Background technology]

[0002] Semiconductor light receiving elements are widely used, and photodiodes for optical fibers and infrared sensors are typical examples of semiconductor light receiving elements that detect light wavelengths in the infrared region.

[0003] For example, Patent Document 1 discloses a semiconductor photodetector having an n-type InP substrate, an n-type InP buffer layer stacked on the n-type InP substrate, an i-type (n-type) InGaAs light absorption layer stacked on the n-type InP buffer layer, an n-type InP cap layer stacked on the i-type (n-type) InGaAs light absorption layer, and a p-type impurity region formed by ion-implanting p-type impurities from the n-type InP cap layer and forming a p-n junction with the i-type (n-type) InGaAs light absorption layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-259936 Summary of the Invention [Problem to be solved by the invention]

[0005] The invention disclosed in Patent Document 1 is for use in optical communication systems, and its challenge was to improve high-speed response. Light-receiving elements used in infrared sensors, which are applications other than optical communication systems, are required to have high ESD resistance (also known as electrostatic discharge resistance) and high light-receiving sensitivity.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor light-receiving element that has high ESD resistance while maintaining light-receiving sensitivity, and a method for manufacturing the same. [Means for solving the problem]

[0007] To achieve the above object, the inventors focused on the carrier density and thickness of the light absorption layer in a semiconductor light receiving element and completed the present invention. Specifically, when the thickness of the InGaAs light absorption layer of a semiconductor light receiving element is reduced, the resulting ESD resistance voltage increases, but the light receiving sensitivity is significantly reduced. In contrast, the inventors discovered that doping an InGaAs light absorption layer of a specific thickness or greater with n-type impurities to a specific carrier density or greater can significantly improve the ESD resistance voltage to 1500 V or more, while limiting the reduction in light receiving sensitivity. Thus, the inventors discovered that the ESD resistance voltage can be significantly improved without significantly reducing the light receiving sensitivity. Specifically, the gist of the present invention is as follows:

[0008] <1> an n-type InP substrate; an n-type InGaAs light absorption layer on the n-type InP substrate; an InP window layer on the n-type InGaAs light absorption layer; a semiconductor light-receiving element in which a p-type impurity diffusion region is formed in the InP window layer, the p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorption layer, The n-type InGaAs light absorption layer has a thickness of 2.2 μm or more and a carrier density due to n-type impurities of 2.5×10 15 / cm 3 A semiconductor light-receiving element characterized by the above.

[0009] <2> The carrier density due to the n-type impurity of the n-type InGaAs light absorption layer is 6.0×10 15 / cm 3 That's all, <1> The semiconductor light receiving element according to claim 1.

[0010] <3> The p-type impurity contained in the p-type impurity diffusion region is Zn. <1> or <2> The semiconductor light receiving element according to claim 1.

[0011] <4> The n-type impurity contained in the n-type InGaAs light absorption layer is Si. <1> ~ <3> 10. The semiconductor light-receiving element according to claim 9, wherein

[0012] <5> the thickness of the n-type InGaAs light absorption layer is 2.7 μm or more and 3.5 μm or less; <1> ~ <4> 10. The semiconductor light-receiving element according to claim 9, wherein

[0013] <6> a light absorption layer forming step of forming an n-type InGaAs light absorption layer on an n-type InP substrate; a window layer forming step of forming an InP window layer on the n-type InGaAs light absorption layer; a diffusion region forming step of forming a p-type impurity diffusion region in the InP window layer, the p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorption layer, The n-type InGaAs light absorption layer formed in the light absorption layer forming step has a thickness of 2.2 μm or more and a carrier density due to n-type impurities of 2.5×10 15 / cm 3 A method for manufacturing a semiconductor light-receiving element, characterized by the above.

[0014] <7> the diffusion region forming step comprises diffusing a p-type impurity from a surface side of the InP window layer in an MOCVD furnace after the InP window layer is formed in the window layer forming step; <6> 10. A method for manufacturing the semiconductor light receiving element according to claim 9. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a semiconductor light-receiving element having high light-receiving sensitivity and high ESD resistance, and a method for manufacturing the same. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor light-receiving element according to one embodiment of the present invention. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor light-receiving element according to a specific embodiment of the present invention. [Figure 3] 1A to 1C are schematic cross-sectional views of a semiconductor light-receiving element for explaining an embodiment of a manufacturing method according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Prior to describing the embodiments of the present invention, the following points will be explained in advance.

[0018] <Semiconductor composition> First, in this specification, when the term "InGaAs" is used without specifying the elemental composition ratio, it refers to any compound in which the composition ratio of the group III elements In (indium) and Ga (gallium) to the group V element As (arsenic) is 1:1, and the ratio of the group III elements In to Ga is not fixed. However, "InGaAs" may contain up to 5% (molar concentration, the same applies hereinafter) of Al relative to the total of In and Ga, or up to 5% of P (phosphorus) and Sb (antimony) relative to As. Furthermore, even when the term "InP" is used, it may contain up to 5% of group III and V elements other than In and P. The composition ratio of the III-V elements can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.

[0019] <Conductivity type> In this specification, a layer that functions electrically as p-type is referred to as a p-type semiconductor layer (sometimes abbreviated as "p-type layer"), and a layer that functions electrically as n-type is referred to as an n-type semiconductor layer (sometimes abbreviated as "n-type layer"). On the other hand, when specific impurities such as Si, Zn, S, Sn, and Mg are not intentionally added, the layer is called "i-type" or "undoped." Undoped III-V compound semiconductor layers may contain unavoidable impurities that are present during the manufacturing process. Specifically, when the dopant concentrations of both p-type and n-type impurities are low, and the carrier density is, for example, 2.5 × 10 15 / cm 3 In this specification, a material having a concentration of less than 1000 ppm is considered to be “undoped.” The concentration values ​​of impurities such as Si, Sn, S, Te, Mg, and Zn are determined by SIMS analysis.

[0020] <Thickness of semiconductor layer> The thickness of each semiconductor layer provided in the semiconductor light-receiving element can be calculated from the cross-sectional observation of the growth layer by a scanning electron microscope and a transmission electron microscope.

[0021] <Carrier density> To obtain the carrier density, the carrier density of each layer is obtained by an etching CV (ECV) measurement device. For example, ECV Pro manufactured by Nanometrics can be used as the ECV measurement device. By sequentially removing each layer of the contact layer and the window layer by wet etching, with the surfaces of each layer of the contact layer, window layer, and light absorption layer exposed, a voltage is applied using the electrolytic solution specified by the device manufacturer of the ECV measurement device to perform CV measurement. The carrier density was calculated from the CV measurement results. Note that the carrier density due to n-type impurities in this specification is the measured value before p-type impurity diffusion (before the diffusion region formation process), and in the semiconductor light-receiving element after p-type impurity diffusion, it is the carrier density in the region other than the p-type impurity diffusion region that is not affected by diffusion. In the n-type InGaAs light absorption layer, when the n-type impurity is any one or more of Si, S, Se, and Te, the activation rate of the n-type impurity is close to 100%, and the difference between the n-type impurity concentration and the carrier density due to the n-type impurity is less than 10%. In the present invention, the n-type impurity concentration averaged in the thickness direction of the n-type InGaAs light absorption layer by SIMS may be used as the carrier density due to the n-type impurity. In the diffusion of p-type impurities, since it becomes a codoped state of p-type impurities and n-type impurities, when the n-type impurity concentration of each layer by SIMS is regarded as the carrier density due to n-type impurities, the SIMS measurement may be performed on either the inside or the outside of the p-type impurity diffusion region. In the present invention, the entire InGaAs light absorption layer in which n-type impurities are intentionally added, including the portion where p-type impurities are diffused, is expressed as the n-type InGaAs light absorption layer.

[0022] <p-type impurity concentration in the p-type impurity diffusion region> Regarding the p-type impurity concentration in the p-type impurity diffusion region, the case where the p-type impurity is Zn will be described below as an example. The Zn concentration in the Zn diffusion region is determined by SIMS (Secondary Ion Mass Spectrometry) in the depth direction with respect to the center of the Zn diffusion region, and the average Zn concentration in each layer is obtained based on the Zn concentration profile in the depth direction in each layer. When Zn is used as the p-type impurity, in SIMS analysis, there is a difference in the detection rate (ionization rate) of Zn between the cases where the base material is InP and InGaAs. Therefore, for Zn, in order to correct the absolute value of the element concentration, the Zn concentration in the InP layer uses the analysis results for InP with a known Zn concentration, and the Zn concentration in the InGaAs layer uses the analysis results for InGaAs with a known Zn concentration to correct the concentration respectively.

[0023] Hereinafter, referring to FIG. 1, a semiconductor light receiving element according to an embodiment of the present invention will be described. A semiconductor light receiving element 100 according to an embodiment of the present invention includes at least an n-type InP substrate 110, an n-type InGaAs light absorption layer 130 on the n-type InP substrate 110, and an InP window layer 140 on the n-type InGaAs light absorption layer 130. And a p-type impurity diffusion region 150 reaching above the n-type InGaAs light absorption layer 130 is formed in the InP window layer 140. Here, the n-type InGaAs light absorption layer 130 in the semiconductor light receiving element 100 has a thickness of 2.2 μm or more and a carrier density of 2.5×10 15 / cm 3 or more. Hereinafter, the details of each component will be described sequentially.

[0024] <n-type InP substrate> A generally available n-type InP substrate 110 can be used. Representative examples of the n-type impurity in the n-type InP substrate 110 are S (sulfur) and Sn (tin). The carrier density of the n-type InP substrate 110 is not particularly limited. For example, it is 1.0×10 18 / cm 3 or more and 9.0×10 18 / cm 3It is only necessary to adopt the one. The thickness, diameter, and surface orientation of the substrate are not particularly limited.

[0025] <n-type InGaAs light absorption layer> An n-type InGaAs light absorption layer 130 is provided on an n-type InP substrate 110. The n-type InGaAs light absorption layer 130 has a thickness of 2.2 μm or more, and a carrier density due to n-type impurities of 2.5×10 15 / cm 3 or more. If the thickness of the n-type InGaAs light absorption layer 130 is made thinner than 2.2 μm, even if the ESD withstand voltage can be slightly improved, the light reception sensitivity will decrease because the quantum efficiency decreases. Therefore, in the semiconductor light receiving element 100 according to the present invention, while making the thickness of the n-type InGaAs light absorption layer 130 2.2 μm or more, which is larger than the normal thickness, the carrier density due to n-type impurities in the n-type InGaAs light absorption layer 130 is increased to 2.5×10 15 / cm 3 or more, so that it is possible to obtain excellent ESD withstand voltage while increasing the light reception sensitivity. Here, the carrier density due to n-type impurities in the n-type InGaAs light absorption layer 130 means the carrier density of the n-type InGaAs light absorption layer 130 before the Zn diffusion process, and after the Zn diffusion process, it means the carrier density in the region where Zn has not diffused (the region other than the p-type impurity diffusion region 150). As described above, the thickness-averaged Si concentration by SIMS of the n-type InGaAs light absorption layer 130 may be regarded as the carrier density due to n-type impurities. As the n-type impurity to dope the InGaAs light absorption layer 130, Si, Ge, Sn, Pb, S, Se, Te can be used. Desirably, Si, S, Se, Te, which are easy to obtain raw material gases and do not diffuse during the growth of the n-type InGaAs light absorption layer 130 by MOCVD, can be used. Most preferably, it is Si.

[0026] -Composition ratio- Here, the composition ratio of the n-type InGaAs light absorption layer 130 is In x1 Ga (1-x1)In this case, the In composition ratio x1 is expressed as As. While the In composition ratio x1 is not particularly limited as long as epitaxial growth is possible on the n-type InP substrate 110, it is preferable to set it to 52.18≦x1≦54.47, and more preferably 52.75≦x1≦53.89. This is because the lattice constant of the InP substrate and the InGaAs layer can be approximately matched, reducing stress near the film interface and reducing the likelihood of defects such as slip and crosshatch in the InGaAs layer. The n-type impurity in the n-type InGaAs light absorption layer 130 may be, for example, Si. Alternatively, the lattice mismatch of the InGaAs layer with the InP substrate may be used instead of the composition ratio of the n-type InGaAs light absorption layer 130. The lattice mismatch can be obtained from a graph of 2θ (horizontal axis) and diffracted X-ray intensity (vertical axis) by measuring a 2θ-ω scan (diffractometer curve) using X-rays on the (400) plane of the InP substrate 110 and the InGaAs light absorption layer 130 thereon. Diffraction peak position 2θ of InP substrate InP and the diffraction peak position 2θ of the InGaAs layer InGaAs From the Bragg diffraction equation, the lattice constants a InP , a InGaAs Calculate the lattice constant difference Δa = a InP -a InGaAs Then, Δa / a InP The degree of lattice mismatch can be evaluated by the following equation: More simply, in the 2θ-ω scan measurement results, the diffraction angle difference Δ2θ=2θ between the diffraction peak position of the InP substrate and the diffraction peak position of InGaAs is calculated. InP -2θ InGaAs The lattice mismatch can be evaluated using the above method. A Δ2θ of ±200 arcsec or less is preferable, and ±100 arcsec or less is even more preferable. The smaller the lattice mismatch, the less likely defects such as slip and crosshatch will occur in the InGaAs layer on the InP substrate. This also reduces the warping of the epitaxial substrate, making it easier to handle during subsequent processing and preventing cracking of the epitaxial substrate after deposition of films such as SiN.

[0027] -Thickness- The thickness of the n-type InGaAs light absorption layer 130 refers to the thickness without considering the diffusion of p-type impurities, and is the thickness of the n-type InGaAs light absorption layer 130 before the diffusion of p-type impurities. As described above, the thickness of the n-type InGaAs light absorption layer 130 is 2.2 μm or more, preferably 2.7 μm or more, and more preferably 2.75 μm or more. On the other hand, in order to ensure the ESD breakdown voltage of the semiconductor light receiving element 100, it is preferable to set the thickness of the n-type InGaAs light absorption layer 130 to 3.5 μm or less, and more preferably 3.45 μm or less. If the thickness of the n-type InGaAs light absorption layer 130 is too thin, there is a drawback that the light reception sensitivity decreases. Also, if the thickness is too thick, slips and cross-hatching are likely to occur in the InGaAs layer 130 and the InP window layer 140 thereon. Furthermore, the growth time during the film formation of the InGaAs layer on the InP substrate becomes long, resulting in a decrease in manufacturing throughput and an increase in manufacturing cost.

[0028] - Carrier density - The carrier density due to the n-type impurities in the n-type InGaAs light absorption layer 130 is 2.5×10 15 / cm 3 or more as described above, and preferably 3.0×10 15 / cm 3 or more. In order to increase the ESD breakdown voltage, it is more preferable to set the carrier density to 6.0×10 15 / cm 3 or more. If the carrier density due to the n-type impurities is 1.0×10 16 / cm 3 or less, the ESD breakdown voltage can be increased while maintaining the light reception sensitivity. If the carrier density due to the n-type impurities in the n-type InGaAs light absorption layer 130 is too low, the effect of increasing the ESD breakdown voltage is weak. Conversely, if the carrier density due to the n-type impurities is too high, the light reception sensitivity decreases.

[0029] <InP window layer> An InP window layer 140 is provided on the n-type InGaAs photoabsorption layer 130. The InP window layer 140 may be undoped, but it is preferably doped with an n-type impurity such as Si, and the carrier density due to the n-type impurity is 5.0×10 15 / cm 3 or more and 1.1×10 16 / cm 3 or less. Here, the carrier density due to the n-type impurity in the InP window layer 140 refers to the carrier density before the Zn diffusion process, similar to the n-type InGaAs photoabsorption layer 130. The thickness of the InP window layer 140 is not particularly limited, but it can be, for example, 0.5 μm to 2 μm. The InP window layer 140 is preferably made of InP, but other group III or V elements may be mixed in the InP by a few percent as long as it has a sufficient bandgap to transmit the wavelength absorbed by the n-type InGaAs photoabsorption layer 130.

[0030] <p-type impurity diffusion region> A p-type impurity diffusion region 150 is formed in the InP window layer 140 of the semiconductor light-receiving element 100, and the p-type impurity diffusion region 150 reaches above the n-type InGaAs photoabsorption layer 130. More specifically, as shown in FIG. 1, the p-type impurity diffusion region 150 is provided from the outermost surface of the InP window layer 140 to the surface layer portion of the n-type InGaAs photoabsorption layer 130 in a part of the in-plane direction of the InP window layer 140. For convenience, here, the portion of the p-type impurity diffusion region 150 formed in the InP window layer 140 is referred to as the in-window layer diffusion region 152, and the portion formed in the n-type InGaAs photoabsorption layer 130 is referred to as the in-photoabsorption layer diffusion region 151.

[0031] Here, the fact that the p-type impurity diffusion region 150 "reaches" above the n-type InGaAs photoabsorption layer 130 means that the p-type impurity of the p-type impurity diffusion region 150 diffuses to a position deeper than 0.30 μm into the n-type InGaAs photoabsorption layer from at least the interface between the InP window layer 140 and the n-type InGaAs photoabsorption layer toward the n-type InP substrate 110 side. And the concentration of the p-type impurity is 1.0×10 18 / cm 3If the above conditions are met, it is assumed that p-type impurities have diffused. The n-type InGaAs light absorption layer 130 is doped with n-type impurities, and the InP window layer 140 is also doped with n-type impurities. Therefore, the diffusion region 151 in the light absorption layer and the diffusion region 152 in the window layer of the p-type impurity diffusion region 150 are co-doped with p-type impurities and n-type impurities. Note that the p-type impurity in the p-type impurity diffusion region is preferably Zn.

[0032] The size of the p-type impurity diffusion region 150 in the in-plane direction is not particularly limited, but when it is formed in a circular shape when viewed from above, it can be, for example, 10 μmφ or more and 450 μmφ or less. The shape of the p-type impurity diffusion region 150 is not limited to a circle, and it may be a polygonal shape such as a triangle, a rectangle, or a pentagon. The smaller the area of ​​the p-type impurity diffusion region 150, the easier it is to obtain the effects of the present invention. For this reason, the area of ​​the p-type impurity diffusion region 150 is set to 159050 μm 2 Preferably less than 129600 μm 2 Less than 62500 μm is more preferable. 2 The lower limit of the area is more preferably 100 μm for practical use and mass production. 2 The above is preferable.

[0033] The semiconductor photodetector 100 described above has an optimized thickness of the n-type InGaAs light absorption layer and an optimized carrier density due to n-type impurities in the n-type InGaAs light absorption layer, and therefore can achieve both excellent photosensitivity and ESD resistance.

[0034] Next, a specific embodiment applicable to the semiconductor light receiving element according to the present invention will be described with reference to Fig. 2. Below, configurations with the same last two digits of the reference numerals are the same as those described in the above-described embodiments, and therefore, redundant explanations will be omitted. Similarly, when referring to Fig. 3, redundant explanations of common configurations will be omitted.

[0035] <Buffer layer> The semiconductor light-receiving element 200 may have a buffer layer 220 between the n-type InP substrate 210 and the n-type InGaAs light absorption layer 230. The buffer layer 220 is preferably made of InP and is preferably undoped. The thickness of the buffer layer 220 can be set to 0.3 μm or more and 1.0 μm or less.

[0036] <Cap Layer> It is preferable to provide a cap layer 260 that also serves as a contact layer on a part of the upper surface of the p-type impurity diffusion region 250, for example, at the edge. The carrier density of the cap layer 260 is preferably less than 5.0×10 15 / cm 3 before the Zn diffusion process, and it is more preferable to use undoped InGaAs with a carrier density less than 2.5×10 15 / cm 3 The thickness of the cap layer 260 can be set to 50 nm or more and 0.2 μm or less. When the composition ratio of the cap layer 260 is expressed as In x2 Ga (1-x2) As, although the In composition ratio x2 of the cap layer is not particularly limited, it is preferably 52.18≦x2≦54.47, and more preferably 52.75≦x2≦53.89. This is because the lattice constants of the InP substrate and the InGaAs layer can be made substantially consistent, the stress near the film interface becomes small, and defects such as slips and cross-hatching are less likely to occur in the InGaAs layer. Also, by diffusing p-type impurities into the cap layer 260 in the diffusion region formation process described later to make it p-type and using the cap layer 260 as a p-type contact layer, the contact resistance with the p-type electrode 280 can be reduced.

[0037] <AR Coating Layer> An AR coating layer 270 for antireflection can be provided on the portion of the InP window layer 240 other than the cap layer 260. It is preferable to use SiN for the AR coating layer 270, and the thickness can be set to 0.1 μm or more and 0.5 μm or less.

[0038] A p-type electrode 280 can be provided in contact with the cap layer 260, and an n-type electrode 290 can be provided on the back surface of the n-type InP substrate 210. The thickness of each can be 0.5 μm or more and 4.0 μm or less. The p-type electrode 280 can be made of, in order from the cap layer side, titanium (Ti), platinum (Pt), and gold (Au), while the n-type electrode can be made of an AuGe alloy or the like. The shape of the electrode can be designed appropriately depending on the application, and can be, for example, a polygonal shape such as a circle, triangle, square, or pentagon. The example shown in FIG. 2 is merely an example. The p-type electrode 280 can also be provided with a bonding pad for connecting a wire to pass current.

[0039] Considering that the semiconductor light receiving element 200 will be used for a sensor, the overall thickness of the semiconductor light receiving element 200 is preferably 100 μm or more and 300 μm or less, and the width and depth are preferably about 500 μm, and when the light receiving portion is formed to be circular in top view, the diameter of the light receiving portion can be, for example, 10 μmφ or more and 450 μmφ or less. Furthermore, since the light receiving portion is provided inside the p-type impurity diffusion region, the shape of the light receiving portion may be similar to the shape of the p-type impurity diffusion region 150 and is not limited to a circle, but may also be a polygonal shape such as a triangle, a rectangle, or a pentagon.

[0040] See steps A to D schematically shown in Fig. 3. A method for manufacturing a semiconductor photodetector 300 according to one embodiment of the present invention includes a light absorption layer forming step of forming an n-type InGaAs light absorption layer 330 on an n-type InP substrate 310, a window layer forming step of forming an InP window layer 340 on the n-type InGaAs light absorption layer 330, and a diffusion region forming step of forming a p-type impurity diffusion region 350 in the InP window layer 340, the p-type impurity diffusion region 350 reaching the top of the n-type InGaAs light absorption layer 330. The thickness of the n-type InGaAs light absorption layer 330 formed in the light absorption layer forming step is set to 2.2 µm or more, and the carrier density due to the n-type impurity is set to 2.5 × 10 15 / cm 3 That's all.

[0041] Each layer of the semiconductor layer is preferably formed using an MOCVD method. The diffusion region formation step (Step D) preferably involves forming an InP window layer 340 in the window layer formation step, and then diffusing p-type impurities from the surface side of the InP window layer 340 using an MOCVD furnace. The diffusion region formation step (Step D) may include a step of forming a cap layer 360 and a step of partially removing the cap layer to expose a portion of the InP window layer 340, and the diffusion region formation step (Step D) may also diffuse p-type impurities into the cap layer 360.

[0042] A preferred embodiment of the diffusion region formation step will be described specifically using Zn as a p-type impurity. After epitaxial growth of all semiconductor layers, Zn is diffused from the top surface of the epitaxial layer only into the desired region by MOCVD. That is, if the InP window layer 340 is the top layer of the semiconductor layer, Zn is diffused from the surface of the InP window layer 340. If a cap layer (not shown) is the top layer of the semiconductor layer, Zn is diffused from the surface of the cap layer. To diffuse Zn only into the desired region, a dielectric thin film (e.g., SiO, SiON, SiN film) is first formed by CVD, and then the dielectric thin film is patterned into a predetermined shape by photolithography using a resist. The patterned dielectric thin film can be used as a mask 370 for Zn diffusion. Zn is then diffused from the top surface of the epitaxial layer, through the cap layer (if present), into the InP window layer 340 and the n-type InGaAs light absorption layer 330. The cap layer 360 can be made p-type by diffusing Zn, and can be suitably used as a p-type contact layer.

[0043] In this case, the Zn concentration in the n-type InGaAs light absorption layer 330 peaks near the interface between the InP window layer 340 and the n-type InGaAs light absorption layer 330, and gradually decreases from the interface toward the n-type InP substrate 310. The Zn peak concentration in the InGaAs light absorption layer 330 was 1.0×10 when measured by SIMS. 19 / cm 3 Over 5.0 x 10 19 / cm3 The average Zn concentration in the diffusion region 351 in the n-type InGaAs light absorption layer 330 can be set to 8.0×10 or less. 18 / cm 3 Over 4.0 x 10 19 / cm 3 and preferably 9.0×10 18 / cm 3 Over 3.0 x 10 19 / cm 3 The average Zn concentration in the diffusion region 351 in the light absorption layer is 1.0×10 Zn concentration from the interface between the InP window layer 340 and the n-type InGaAs light absorption layer 330 in the n-type InGaAs light absorption layer 330. 18 / cm 3 As described above, Zn is diffused into a part of the region where each semiconductor layer is doped with an n-type impurity such as Si, so that diffusion region 352 in the window layer where Zn is diffused into InP window layer 340 and diffusion region 351 in the light absorption layer where Zn is diffused into n-type InGaAs light absorption layer 330 are co-doped with Zn and the n-type impurity (for example, Si).

[0044] In the diffusion region forming step, the p-type impurity diffusion region 350 can be formed by using a quartz tube sealing method instead of the MOCVD method, or the p-type impurity diffusion region 350 can be formed by an ion implantation method.

[0045] 3 can be formed by sputtering, electron beam evaporation, resistance heating, etc. The AR coating layer, not shown in FIG. 3, can be formed by CVD, coating, etc.

[0046] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way. [Example]

[0047] Example 1 See Figure 2 above. An n-type InP substrate (thickness: 625 μm, carrier density: 3.0 × 10 18 / cm3 An undoped InP buffer layer, an n-type InGaAs light absorption layer, an n-type InP window layer, and an undoped InGaAs cap layer were sequentially formed on the substrate by MOCVD. The composition, dopant, carrier density, and thickness of each layer are shown in Table 1 below. The carrier density of each layer was measured using an ECV measurement device (ECV Pro manufactured by Nanometrics) before Zn diffusion. Next, a mask was formed on the cap layer and etched, after which a SiN film (thickness: 0.2 μm) was formed by CVD. A pattern was formed by photolithography using a resist, and Zn was diffused from the cap layer into the n-type InP window layer and the n-type InGaAs light absorption layer by MOCVD. DEZn (diethyl zinc) was used as the Zn source. Finally, a p-type electrode and an n-type electrode were formed, respectively, to complete the semiconductor photodetector according to Example 1.

[0048] [Table 1]

[0049] The average Zn concentration in the thickness direction measured by SIMS at the center of the Zn diffusion region in the InGaAs cap layer was 5.0 × 10 19 / cm 3 The average Zn concentration in the thickness direction at the center of the Zn diffusion region in the InP window layer is 5.0 × 10 18 / cm 3 In addition, the Zn concentration in the depth direction at the center of the Zn diffusion region was 1.0 × 10 18 / cm 3 The depth position up to which the thickness reaches or below this value is 0.33 μm from the interface between the InP window layer and the InGaAs light absorption layer.

[0050] <Example 2> In Example 1, the carrier density of the InGaAs light absorption layer before Zn diffusion was 3.0 × 10 15 / cm 3 This was 1.0×10 16 / cm 3 A semiconductor light-receiving element according to Example 2 was fabricated in the same manner as in Example 1, except for changing the above.

[0051] <Comparative Example 1> In Example 1, the carrier density of the InGaAs light absorption layer before Zn diffusion was 3.0 × 10 15 / cm 3 This was 3.0×10 14 / cm 3 A semiconductor light-receiving element according to Comparative Example 1 was fabricated in the same manner as in Example 1, except for changing the above.

[0052] <Comparative Example 2> A semiconductor light-receiving element according to Comparative Example 2 was fabricated in the same manner as Comparative Example 1, except that the thickness of the InGaAs light absorption layer, which was 2.8 μm in Comparative Example 1, was changed to 2.55 μm.

[0053] <Comparative Example 3> A semiconductor light-receiving element according to Comparative Example 3 was fabricated in the same manner as Comparative Example 1, except that the thickness of the InGaAs light absorption layer was changed from 2.8 μm in Comparative Example 1 to 3.45 μm.

[0054] (Evaluation 1: Light receiving sensitivity) For each of Examples 1 and 2 and Comparative Examples 1 to 3, the light-receiving sensitivity at wavelengths of 1060 nm, 1460 nm, and 1550 nm was measured as follows.

[0055] The fabricated semiconductor photodetector is placed on a prober installed in a darkroom, and the probe needle is placed against the p-type electrode pad. The n-type electrode is electrically connected to the prober stage. First, with no light source present, a predetermined reverse voltage is applied to the p-type and n-type electrodes, and the current (reverse current) flowing between the p-type and n-type electrodes is measured. This yields the dark current. Next, with a predetermined reverse voltage applied to the p-type and n-type electrodes, laser light sources with wavelengths of 1060 nm, 1460 nm, and 1550 nm are used, focused with a lens, and directed into the photosensitive area of ​​the semiconductor photodetector. The reverse current under light irradiation is measured. This yields the photocurrent. The laser light irradiation power is also measured separately using a photodetector with known photosensitivity. The photosensitivity can be calculated from the measurements obtained above using the following equation: [Photosensitivity] (A / W) = ([Photocurrent] - [Dark current]) / [Illumination power] By performing the above measurement while changing the wavelength of the light source, the light receiving sensitivity at each wavelength can be obtained. The photosensitivity ([wavelength] / 1240nm) values ​​for 100% quantum efficiency at wavelengths of 1060nm, 1460nm, and 1550nm are 0.855, 1.178, and 1.25, respectively, and these values ​​are the maximum photosensitivity values ​​at each wavelength. The photosensitivity values ​​in Table 1 are within the quantum efficiency ranges of 77-82%, 80-86%, and 78-85% at each wavelength, which can be said to be sufficiently high.

[0056] (Rating 2: ESD resistance) The ESD withstand voltage was measured for each of Examples 1 and 2 and Comparative Examples 1 to 3. Nine samples were obtained by selecting one chip from each of nine locations on the wafer surface for Examples 1 and 2 and Comparative Examples 1 to 3, and each chip was attached to a TO stem with silver paste and an Au wire to establish electrical continuity with the TO stem, creating a test sample for measuring the ESD withstand voltage. The average value was used as the ESD withstand voltage value. The ESD withstand voltage was measured in accordance with the test method for the human body model electrostatic breakdown test of JEITA ED-4701 / 304A. The ESD withstand voltage was measured using an automatic electrostatic breakdown measurement device (HED-S5000 manufactured by Hanwa Electronics Industries, Ltd.) A calibration sample was set and the device was calibrated. Next, the test sample was set, and the conditions were as follows: starting voltage 100 V, ending voltage 4000 V, voltage step 100 V, voltage application number 3, interval time 0.5 seconds, and application mode positive voltage application → negative voltage application. The ambient temperature during measurement was 25°C. After applying the test voltage three times, the current was measured when a voltage of -5V was applied. The pass / fail criterion was set to 1μA, and if the value was less than 1μA, the applied voltage was increased by 100V and the test voltage was applied again. The voltage applied when the current when a voltage of -5V was applied exceeded 1μA was taken as the ESD withstand voltage value. Specifically, a test voltage of +100V was first applied to the test sample three times, every 0.5 seconds. After each test voltage was applied, the test sample was discharged by a discharge circuit. The current was then measured when -5V was applied. If it was less than 1 μA, it was judged to have passed. If it passed, a test voltage of -100V was then applied three times, every 0.5 seconds, and the current was measured when -5V was applied. If it was less than 1 μA, it was judged to have passed. If it passed, a test voltage of +200V was applied three times in the same way and the current at -5V was measured. If it passed, the test voltage was then changed to -200V and the same procedure was repeated. The absolute value of the test voltage was increased by 100V in increments of 100V until the current when -5V was applied exceeded 1 μA.

[0057] Table 2 shows the manufacturing conditions and measurement results for Examples 1 and 2 and Comparative Examples 1 to 3.

[0058] [Table 2]

[0059] From Table 2 above, it can be seen that by forming a light absorption layer that satisfies the conditions of the present invention, excellent ESD resistance was obtained without substantially reducing the light receiving sensitivity. [Industrial Applicability]

[0060] The semiconductor light-receiving element according to the present invention is useful because it can achieve both excellent light-receiving sensitivity and ESD resistance. [Explanation of symbols]

[0061] 100, 200, 300 Semiconductor photodetector 110, 210, 310 n-type InP substrate 220 buffer layer 130, 230, 330 n-type InGaAs light absorption layer 140, 240, 340 InP window layer 150, 250, 350 p-type impurity diffusion region 151, 251, 351 Diffusion region in light absorption layer 152, 252, 352 Diffusion region in window layer 260, 360 cap layer 270 AR coating layers 280 p type electrode 290 n-type electrode 370 Mask

Claims

1. an n-type InP substrate; an n-type InGaAs light absorption layer on the n-type InP substrate; an InP window layer on the n-type InGaAs light absorption layer; a p-type impurity diffusion region is formed in the InP window layer, the p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorption layer, The n-type InGaAs light absorption layer has a thickness of 2.2 μm or more and 3.5 μm or less, and a carrier density due to n-type impurities of 2.5×10 １５ / cm ３ That's all, a p-type impurity diffusion region having a p-type impurity concentration of 1×10 18 / cm 3 or more, and a depth position at which the p-type impurity concentration becomes 1×10 18 / cm 3 or less, the depth position being 0.30 μm or more and 0.33 μm or less from the interface between the InP window layer and the n-type InGaAs light absorption layer toward the n-type InP substrate.

2. The carrier density due to the n-type impurity of the n-type InGaAs light absorption layer is 6.0×10 １５ / cm ３ The semiconductor light-receiving element according to claim 1, wherein the concentration is not less than 1.0×10 16 / cm 3 .

3. 2. The semiconductor light-receiving element according to claim 1, wherein the p-type impurity contained in said p-type impurity diffusion region is Zn.

4. 2. The semiconductor light-receiving element according to claim 1, wherein the n-type impurity contained in said n-type InGaAs light absorption layer is Si.

5. 5. The semiconductor light-receiving element according to claim 1, wherein the thickness of said n-type InGaAs light absorption layer is 2.7 μm or more and 3.5 μm or less.

6. a light absorption layer forming step of forming an n-type InGaAs light absorption layer on an n-type InP substrate; a window layer forming step of forming an InP window layer on the n-type InGaAs light absorption layer; a diffusion region forming step of forming a p-type impurity diffusion region in the InP window layer, the p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorption layer, The n-type InGaAs light absorption layer formed in the light absorption layer forming step has a thickness of 2.2 μm or more and 3.5 μm or less, and a carrier density due to n-type impurities of 2.5×10 １５ / cm ３ That is all, a p-type impurity diffusion region formed in the diffusion region formation step, the p-type impurity diffusion region having a p-type impurity concentration of 1×10 18 / cm 3 or more, and a depth position at which the p-type impurity concentration becomes 1×10 18 / cm 3 or less, the depth position from the interface between the InP window layer and the n-type InGaAs light absorption layer to the n-type InP substrate side being 0.30 μm or more and 0.33 μm or less.

7. 7. The method for manufacturing a semiconductor light-receiving element according to claim 6, wherein the diffusion region forming step comprises diffusing p-type impurities from a surface side of the InP window layer in an MOCVD furnace after the InP window layer is formed in the window layer forming step.

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