Digital-to-Analog Converter

Abstract

The digital-to-analog converter 100A includes a plurality of conversion current units 110, compensation current units 120, and a first amplifier 131. Each conversion current unit includes a first differential switch pair 111, a first stacked transistor M3, and a first current source transistor M4. The first differential switch pair is controlled by a first control signal Qj and a first inverse control signal QJ-. The first stacked transistor M3 and the first current source transistor M4 are connected in series with each other and connected to the first differential switch pair. The compensation current unit includes a second stacked transistor M7. The first amplifier has an input terminal connected to the source of the second stacked transistor M7 and an output terminal connected to the gates of the second and first stacked transistors M7, respectively. The output impedance of the digital-to-analog converter can be increased at a lower cost, and the linearity of the digital-to-analog converter can be improved.

Description

[Technical Field]

[0001] The present disclosure relates to digital-to-analog converters, and more particularly to digital-to-analog converters having compensation current units. [Background technology]

[0002] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals so that they can be recognized externally. In this digital age, DACs are an essential component of various electronic devices. However, DACs are susceptible to the fluctuating equivalent output impedance of their output terminals, which can lead to poor linearity. Summary of the Invention

[0003] An embodiment of the present disclosure is a digital-to-analog converter. The digital-to-analog converter includes a plurality of conversion current units, a compensation current unit, a first amplifier circuit, and a current source circuit. Each of the conversion current units includes a first differential switch pair, a first stacked transistor, and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverse control signal. The first stacked transistor and the first current source transistor are connected in series with each other and connected to the first differential switch pair. The compensation current unit includes a second differential switch pair, a second stacked transistor, and a second current source transistor. The second differential switch pair is controlled by a second control signal. The second stacked transistor and the second current source transistor are connected in series with each other and connected to the second differential switch pair, with the gate of the second current source transistor being connected to the gate electrode of the first current source transistor. The input terminal of the first amplifier circuit is connected to the source of the second stacked transistor, and the output terminal of the first amplifier circuit is connected to the gate of the second stacked transistor and the gate of the first stacked transistor. The current source circuit is connected to the second current source transistor to form a current mirror, and is also connected to the first current source transistor to form a current mirror. [Brief explanation of the drawings]

[0004] The present disclosure can be more fully understood by reading the following detailed description of the embodiments in conjunction with the following drawings. [Figure 1A] FIG. 1 is a circuit schematic diagram of a digital-to-analog converter according to some embodiments of the present disclosure. [Figure 1B] FIG. 1 is a circuit schematic diagram of a digital-to-analog converter according to some embodiments of the present disclosure. [Figure 1C] FIG. 1 is a circuit schematic diagram of a portion of a digital-to-analog converter in a single-sided output configuration according to some embodiments of the present disclosure. [Figure 2A] FIG. 1 is a circuit schematic diagram of a digital-to-analog converter according to some embodiments of the present disclosure. [Figure 2B] FIG. 1 is a circuit schematic diagram of a digital-to-analog converter according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] The following detailed description is provided in combination with examples and drawings, but the specific examples described are used only to interpret the present invention and do not limit the present invention, and the descriptions of structures and operations do not limit the order of their execution. Any devices having equivalent effects resulting from a structure in which any elements are rearranged are all within the scope of the present disclosure.

[0006] Terms used throughout the specification and claims generally have their ordinary meaning as used within the art, the subject matter disclosed herein, and the specific context, unless otherwise specified.

[0007] As used herein, "connected" or "coupled" can refer to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and can also refer to two or more elements operating or moving with each other.

[0008] 1A, which is a circuit schematic diagram of a digital-to-analog converter 100A according to some embodiments of the present disclosure. As shown in FIG. 1A, the digital-to-analog converter 100A includes a plurality of conversion current units 110, a compensation current unit 120, an amplifier circuit 131, a front-end processor 130, a digital controller 150, and a current source circuit 140.

[0009] In some embodiments, the digital controller 150 is used to generate the digital signal DS. The front-end processor 130 converts the digital signal DS into a plurality of control signals.

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[0010] 1A, each of the multiple conversion current units 110 includes a differential switch pair 111, a stacked transistor M3, and a current source transistor M4. For simplicity, FIG. 1A only shows the detailed layout of a single conversion current unit 110. In the following text, unless otherwise specified, it should be understood that the described layout of a single conversion current unit 110 applies to each of the multiple conversion current units 110. Among them, the differential switch pair 111 includes a switch M1 and a switch M2, and the switches M1 and M2 are controlled by a control signal (Qj) and an inverse control signal (Qj-), respectively. In detail, the switch M1 is controlled by one of the control signal (Qj) and the inverse control signal (Qj-), and the switch M2 is controlled by the other of the control signal (Qj) and the inverse control signal (Qj-).

[0011] Furthermore, the control signal (Qj) and the inverse control signal (Qj-) are related to the digital signal DS. In other words, the digital signal DS is converted into the control signal (Qj) and the inverse control signal (Qj-) through the front-end processor 130, and the digital-to-analog converter 100A then generates an analog signal based on the control signal (Qj) and the inverse control signal (Qj-). Since the control signal (Qj) and the inverse control signal (Qj-) are opposite to each other, when one of the switches M1 and M2 is turned on, the other of the switches M1 and M2 is turned off.

[0012] In some embodiments, j in the control signal (Qj) and the inverse control signal (Qj-) can represent multiple positive integers, and multiple conversion current units 110 receive corresponding control signals (Qj) and inverse control signals (Qj-), respectively. For example, the switches M1 and M2 in the first conversion current unit 110 receive the control signals

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[0013] As shown in FIG. 1A , in the current conversion unit 110, switch M1 is connected between output terminal n1 and node n3, and switch M2 is connected between output terminal n2 and node n3. Stacked transistor M3 and current source transistor M4 are connected in series between nodes n3 and n4. NMOS transistors are used as examples of switch M1, switch M2, stacked transistor M3, and current source transistor M4. Specifically, the source of switch M1 and the source of switch M2 are connected to node n3, the drain of switch M1 is connected to output terminal n1, and the drain of switch M2 is connected to output terminal n2. The source of stacked transistor M3 is connected to the drain of current source transistor M4. The drain of stacked transistor M3 is connected to node n3, and the source of current source transistor M4 is connected to node n4. In some embodiments, node n4 is a ground terminal.

[0014] 1A, similar to the conversion current unit 110, the compensation current unit 120 includes a differential switch pair 121, a stacked transistor M7, and a current source transistor M8. The differential switch pair 121 is connected to a control signal

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[0015] Specifically, differential switch pair 121 includes switches M5 and M6. Switch M5 is controlled by a control signal (B). In some embodiments, switch M6 is controlled by an inverse control signal (C).

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[0016] In some embodiments, the control signal (B) and the inverse control signal (B-) are a fixed differential signal pair, and compared with the control signal (Qj) and the inverse control signal (Qj-) received by the conversion current unit 110, the control signal (B) and the inverse control signal (B-) remain unchanged, and the control signal (Qj) and the inverse control signal (Qj-) change corresponding to the digital signal DS.

[0017] In other words, in some embodiments, switch M5 is held on and switch M6 is held off. In some variations, switch M5 is controlled by the inverse control signal (B-) and switch M6 is controlled by the control signal (B). In other words, switch M5 is held off and switch M6 is held on.

[0018] As shown in FIG. 1A , in the compensation current unit 120, switch M5 is connected between output terminal n1 and node n5, and switch M6 is connected between output terminal n2 and node n5. Stacked transistor M7 and current source transistor M8 are connected in series between node n5 and node n4. NMOS transistors are used as examples of switch M5, switch M6, stacked transistor M7, and current source transistor M8. Specifically, the source of switch M5 and the source of switch M6 are connected at node n5, the drain of switch M5 is connected to output terminal n1, and the drain of switch M6 is connected to output terminal n2. The source of stacked transistor M7 is connected to the drain of current source transistor M8. The drain of stacked transistor M7 is connected to node n5, and the source of current source transistor M8 is connected to node n4.

[0019] Referring again to FIG. 1A, the amplifier circuit 131 is connected between the gate and source of the stacked transistor M7. Specifically, the amplifier circuit 131 may include an operational amplifier OPA, in which the inverting input terminal of the operational amplifier OPA is connected to the source of the stacked transistor M7, the non-inverting input terminal of the operational amplifier OPA is connected to the bias signal Vb, and the output terminal of the operational amplifier OPA is connected to the gate of the stacked transistor M7. In FIG. 1A, the inverting input terminal is represented by the symbol - and the non-inverting input terminal is represented by the symbol +. In this configuration, a regulated loop L1 is formed between the gate and source of the stacked transistor M7.

[0020] The gate of the stacked transistor M7 is also connected to the gate of each stacked transistor M3 in the plurality of conversion current units 110. Correspondingly, the amplifier circuit 131 can provide a voltage signal Vsh to the gate of the stacked transistor M3 and the gate of the stacked transistor M7. For simplicity, FIG. 1A only shows the connection between the stacked transistor M7 and a single conversion current unit 110, but it should be understood that the other conversion current units 110 are also connected to the stacked transistor M7 in the same manner. In the above arrangement, the output terminal of the amplifier circuit 131 is connected to the gate of the stacked transistor M7, and further connected to the gate of each stacked transistor M3 in the plurality of conversion current units 110 via the gate of the stacked transistor M7. In this way, the amplifier circuit 131 provides gain, thereby increasing the total impedance of the stacked transistor M3 and the current source transistor M4 and the total impedance of the stacked transistor M7 and the current source transistor M8, respectively, and correspondingly increasing the output impedance of the conversion current unit 110 and the compensation current unit 120.

[0021] 1A, in some embodiments, the gate of current source transistor M8 is further connected to the gate of each current source transistor M4 in the plurality of conversion current units 110. For simplicity, FIG. 1A only shows the connection scheme between current source transistor M8 and a single conversion current unit 110, but it should be understood that the other conversion current units 110 are also connected to current source transistor M8 in the same manner.

[0022] 1A, the current source circuit 140 is connected to the current source transistor M8 to form a current mirror. In this way, the current source transistor M8 can generate a mirror current by turning on the current source circuit 140. At the same time, the current source circuit 140 can also be connected to each current source transistor M4 in the multiple conversion current units 110 to form a current mirror. In this way, each current source transistor M4 can generate a mirror current by turning on the current source circuit 140.

[0023] In some embodiments, the current source circuit 140 may include a current source 141 and a gate bias circuit 142. One end of the current source 141 is used to receive the power supply voltage VDD, and the other end of the current source 141 is connected to the gate bias circuit 142. The gate bias circuit 142 is connected to a ground terminal and is used to provide gate bias to the gates of the current source transistors M4 and M8.

[0024] In some embodiments, the gate bias circuit 142 may be implemented by a transistor (not shown). The gate of this transistor is connected to the gates of the current source transistors M4 and M8. The drain of this transistor is connected to the gate of this transistor and to the current source 141. The source of this transistor is connected to the ground terminal.

[0025] In various embodiments, the digital-to-analog converter 100A can output analog signals from the output terminal n1 and the output terminal n2 in various ways. For example, the digital-to-analog converter 100A can be implemented with a single-sided output architecture. FIG. 1C is a circuit schematic diagram of a portion of a digital-to-analog converter according to some embodiments of the present disclosure in a single-sided output architecture. As shown in FIG. 1C, in the single-sided output architecture, the digital-to-analog converter 100A further includes an operational amplifier 131C and an output resistor RF. The inverting input terminal of the operational amplifier 131C is connected to the output terminal n1. The non-inverting input terminal of the operational amplifier 131C is connected to a ground terminal. The output resistor RF is connected between the output terminal n1 and the output terminal of the operational amplifier 131C.

[0026] In the above example, the multiple current conversion units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of switches M1 that are turned on and switch M5 that is kept on. The sum of the currents I2 is determined by the number of switches M2 that are turned on and switch M6. In this way, the digital-to-analog converter 100A can generate an output voltage, where the output voltage is equal to the sum of the output currents I1 multiplied by the output resistance RF.

[0027] As another example, the digital-to-analog converter 100A can be implemented with a double-sided output structure. In the double-sided output structure, the digital-to-analog converter 100A can further include a load resistor (not shown). The load resistor can include a resistor R1 and a resistor R2 (not shown). Specifically, the resistor R1 is connected to the plurality of conversion current units 110 at the output terminal n1, and the resistor R2 is connected to the plurality of conversion current units 110 at the output terminal n2. In some embodiments, the resistors R1 and R2 have the same resistance value. Furthermore, in another embodiment, the load resistor can include only the resistor R1, in which case the resistor R1 is connected to the output terminal n1, and the output terminal n2 is changed to a ground terminal.

[0028] In the above example, the multiple current conversion units 110 are used to generate multiple output currents I1 flowing through switch M1 and multiple currents I2 flowing through switch M2. The sum of the output currents I1 is determined by the number of switches M1 that are turned on and switch M5 that is kept on. The sum of the output currents I2 is determined by the number of switches M2 that are turned on and switch M6. The sum of the output currents I1 and the sum of the output currents I2 flow through resistors R1 and R2, respectively, generating an output voltage difference between output terminals n1 and n2.

[0029] Please refer to FIG. 1B. FIG. 1B is a circuit schematic diagram of a digital-to-analog converter 100B according to some embodiments of the present disclosure. Compared with the digital-to-analog converter 100A in FIG. 1A, the main difference is that the amplifier circuit 131 of the digital-to-analog converter 100B includes a transistor M13 and a current source IS. Among them, the transistor M13, switches M1-M2, switches M5-M6, stacked transistor M3, stacked transistor M7, current source transistor M4, and current source transistor M8 are described as NMOS transistors. Specifically, the drain of transistor M13 is connected to the current source IS and the gate of stacked transistor M7. The gate of transistor M13 is connected to the source of stacked transistor M7. In this way, the amplifier circuit 131 provides gain, thereby increasing the total impedance of stacked transistor M3 and current source transistor M4 and the total impedance of stacked transistor M7 and current source transistor M8, respectively, and correspondingly increasing the output impedance of the conversion current unit 110 and the compensation current unit 120.

[0030] Please refer to FIG. 2A. FIG. 2A is a circuit schematic diagram of a digital-to-analog converter 200A according to some embodiments of the present disclosure. Referring to FIGS. 1A and 2A, the digital-to-analog converter 200A is a variation of the digital-to-analog converter 100A. The elements of the digital-to-analog converter 200A follow the coding scheme of the digital-to-analog converter 100A. For brevity, the discussion will focus on the differences between the digital-to-analog converter 200A and the digital-to-analog converter 100A, rather than the differences between the digital-to-analog converter 200A and the digital-to-analog converter 100A.

[0031] In the embodiment corresponding to FIG. 2A, the sources of the current source transistors M4 and M8 are connected to the power supply voltage VDD at node n6. The drains of the switches M2 and M6 are connected to the ground terminal at output terminal n2. Among them, the switches M1-M2, switches M5-M6, stacked transistor M3, stacked transistor M7, current source transistor M4, and current source transistor M8 will be described using PMOS transistors as an example.

[0032] Please refer to FIG. 2B. FIG. 2B is a circuit schematic diagram of a digital-to-analog converter 200B according to some embodiments of the present disclosure. Compared with the digital-to-analog converter 200A in FIG. 2A, the main difference is that the amplifier circuit 131 of the digital-to-analog converter 200B includes a transistor M13 and a current source IS. Among them, the transistor M13, switches M1-M2, switches M5-M6, stacked transistor M3, stacked transistor M7, current source transistor M4, and current source transistor M8 are described as PMOS transistors. Specifically, the drain of the transistor M13 is connected to the current source IS and the gate of the stacked transistor M7. The gate of the transistor M13 is connected to the source of the stacked transistor M7. In this way, the amplifier circuit 131 provides gain, thereby increasing the total impedance of the stacked transistor M3 and the current source transistor M4 and the total impedance of the stacked transistor M7 and the current source transistor M8, respectively, and correspondingly increasing the output impedance of the conversion current unit 110 and the compensation current unit 120.

[0033] 2B, one end of the current source 141 is connected to the ground terminal, and the other end of the current source 141 is connected to the gate bias circuit 142. The gate bias circuit 142 is used to receive the power supply voltage VDD and provide a gate bias voltage to the gates of the current source transistors M4 and M8.

[0034] As described above, the technique of the present disclosure can increase the output impedance of a digital-to-analog converter at lower cost and can help improve the linearity of the digital-to-analog converter.

[0035] Although the present disclosure has been disclosed by the above-described embodiments, it is not intended to limit the present disclosure, and therefore, a person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and the scope of protection of the present disclosure shall be considered as defined by the appended claims. [Explanation of symbols]

[0036] 100A~100B Digital-to-Analog Converter 110 conversion current unit 111, 121 differential switch pair 120 Compensation Current Unit 130 Front-End Processor 140 Current source circuit 150 Digital Controller (Qj), (B) Control signal (Qj-), (B-) Inverse control signals M3, M7 stacked transistors M4, M8 Current source transistors M1, M2, M5, M6 switches M13 transistor Vb Bias signal 131 Amplifier circuit 131C operational amplifier Vsh voltage signal DS Digital Signal 141, IS current source 142 Gate bias circuit 200A~200B Digital-to-Analog Converter n1, n2 output terminals n3~n6 nodes L1 regulatory loop VDD power supply voltage RF Output Resistance

Claims

1. A plurality of conversion current units, each of the conversion current units comprising: a first differential switch pair controlled by a first control signal and a first inverse control signal; a plurality of conversion current units including a first stacked transistor and a first current source transistor connected in series with each other and connected to the first differential switch pair; A current unit, a second differential switch pair controlled by a second control signal; a current unit including a second stacked transistor and a second current source transistor connected in series with each other and connected to the second differential switch pair, wherein a gate of the second current source transistor is connected to a gate of the first current source transistor; a first amplifier circuit, an input terminal of the first amplifier circuit being connected to the source of the second stacked transistor and an output terminal of the first amplifier circuit being connected to each of the gate of the second stacked transistor and the gate of the first stacked transistor; a current source circuit connected with the second current source transistor to form a current mirror and connected with the first current source transistor to form a current mirror; the first differential switch pair: a first switch, wherein a first terminal of the first switch is connected to a first output terminal and a second terminal of the first switch is connected to the first stacked transistor at a first node; a second switch, a first terminal of which is connected to the second output terminal and a second terminal of which is connected to the first node; the second differential switch pair: a third switch controlled by the second control signal, the third switch having a first terminal connected to the first output terminal and a second terminal connected to the second stacked transistor at a second node; a fourth switch, the fourth switch being controlled by a second inverse control signal and connected to the second node; wherein the second control signal and the second inverse control signal remain unchanged; Digital-to-analog converter.

2. The first amplifier circuit an operational amplifier, wherein an inverting input terminal of the operational amplifier is connected to the source of the second stacked transistor, a non-inverting input terminal of the operational amplifier is connected to a bias signal, and an output terminal of the operational amplifier is connected to each of the gate of the second stacked transistor and the gate of the first stacked transistor; 2. The digital-to-analog converter according to claim 1.

3. The first amplifier circuit a first transistor, the drain of which is connected to the gate of the second stacked transistor and the gate of the first stacked transistor, and the gate of which is connected to the source of the second stacked transistor; a first current source connected to the drain of the first transistor; 2. The digital-to-analog converter according to claim 1.

4. an operational amplifier; an output resistor; and wherein the inverting input terminal of the operational amplifier is connected to the first output terminal, and the non-inverting input terminal of the operational amplifier is connected to a ground terminal; the output resistor is connected between the first output terminal and the output terminal of the operational amplifier; 2. The digital-to-analog converter according to claim 1.

5. Further comprising a load resistor, the load resistor comprising: a first resistor connected to the first output terminal; 2. The digital-to-analog converter according to claim 1.

6. The load resistor further comprises: a second resistor connected to the second output terminal; 6. The digital-to-analog converter according to claim 5.

7. 2. The digital-to-analog converter according to claim 1, wherein the first current source transistor is connected to a ground terminal.

8. 2. The digital-to-analog converter of claim 1, wherein the first current source transistor is adapted to receive a power supply voltage.

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