Semiconductor device and manufacturing method thereof

Abstract

To suppress a deterioration of a yield by improving reliability of a semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate SUB; an insulation film IF1 that is formed on an upper surface of the semiconductor substrate SUB of an outer peripheral region OR so as to surround a cell region CR in a flat surface view; and a resistance element SR that is formed onto the insulation film IF1 so as to surround the cell region CR in the flat surface view. On the upper surface of the semiconductor substrate SUB of the outer peripheral region OR, an insulation film IF2 having a thickness that is thinner than that of the insulation film IF1 is formed. A dummy pattern DP1 is formed over the insulation film IF1 from the insulation film IF2 so as to cover a step generated between the insulation film IF2 and the insulation film IF1.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a resistor element on the periphery of a cell region and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device having a cell region in which a high-voltage metal oxide semiconductor field effect transistor (MOSFET) is formed, a resistive element may be provided in the peripheral region surrounding the cell region in order to improve the breakdown voltage of the peripheral region.

[0003] For example, Patent Document 1 discloses a semiconductor device that includes a resistive field plate as a resistive element around a central region where a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) is formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-102705 Summary of the Invention [Problem to be solved by the invention]

[0005] The peripheral region requires a high-voltage structure, e.g., 1000 V or higher, and therefore the resistive element is formed on an insulating film, e.g., 1 μm or thick. Therefore, a high step occurs between the semiconductor substrate and the insulating film. The resistive element is formed by depositing a conductive film, e.g., a polycrystalline silicon film, and then patterning the conductive film. During this patterning, an anisotropic etching process is performed on the conductive film, which tends to leave a portion of the conductive film in the form of a sidewall at the step. If the remaining conductive film peels off during a subsequent manufacturing process, the conductive film remains as a foreign substance and may cause defects. This results in problems of reduced reliability and yield of the semiconductor device.

[0006] The main object of the present application is to provide a technology that can suppress the generation of the above-mentioned foreign matter, thereby improving the reliability of semiconductor devices and suppressing a decrease in yield. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] According to one embodiment, a semiconductor device includes a cell region in which a MOSFET is formed and a peripheral region surrounding the cell region in a plan view. The semiconductor device includes a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, a first insulating film formed on the upper surface of the semiconductor substrate in the peripheral region so as to surround the cell region in a plan view, and a resistive element formed on the first insulating film so as to surround the cell region in a plan view. A second insulating film having a thickness thinner than the first insulating film is formed on the upper surface of the semiconductor substrate in the peripheral region, and a first dummy pattern is formed on the second insulating film and over the first insulating film to cover a step occurring between the second insulating film and the first insulating film.

[0009] A method for manufacturing a semiconductor device according to one embodiment is a method for manufacturing a semiconductor device having a cell region where a MOSFET is formed and a peripheral region surrounding the cell region in a plan view, the method comprising the steps of: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after step (a), forming a first insulating film on the upper surface of the semiconductor substrate in the peripheral region so as to surround the cell region in a plan view; (c) after step (b), forming a second insulating film having a thickness thinner than that of the first insulating film on the upper surface of the semiconductor substrate in the peripheral region; (d) after step (c), forming a first conductive film on the first insulating film and the second insulating film so as to cover a step occurring between the second insulating film and the first insulating film; and (e) after step (d), forming a first conductive film on the first insulating film covering the step. (f) after step (e), forming a third insulating film on the first insulating film and the first conductive film, (g) after step (f), forming a second conductive film on the third insulating film, (h) after step (g), patterning the second conductive film to form a resistor element located on the first insulating film so as to surround the cell region in a plan view, and (i) after step (h), selectively removing a portion of the third insulating film, a portion of the first conductive film, and a portion of the second insulating film on the upper surface of the semiconductor substrate, wherein the first conductive film left in the peripheral region after step (i) forms a first dummy pattern, and the first dummy pattern is formed from above the second insulating film to above the first insulating film so as to cover the step. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved and a decrease in yield can be suppressed. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2]1 is a plan view showing an overview of a resistance element according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 8 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 7. [Figure 9] 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 10] 10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 11] 11A to 11C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 12] 12 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] 13 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 14] 14 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 13. [Figure 15] 15 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 14. [Figure 16] 16 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 15. [Figure 17] 1 is an enlarged cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 18] FIG. 1 is an enlarged cross-sectional view of a main part of a semiconductor device in a study example. [Figure 19] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of semiconductor device> A semiconductor device 100 according to a first embodiment will be described below with reference to FIGS. 1 to 4. FIG. 1 is a plan view of a semiconductor chip that is the semiconductor device 100. FIG. 2 is a plan view showing an outline of a resistor element SR. FIG. 3 is a cross-sectional view taken along line AA shown in FIG. 1. FIG. 4 is a cross-sectional view showing an enlarged region 1A of a portion of the cell region CR and an enlarged region 2A of a portion of the outer peripheral region OR.

[0015] 1 shows mainly a wiring pattern formed above a semiconductor substrate SUB. The semiconductor device 100 has a cell region CR in which a MOSFET is formed, and an outer periphery region OR that surrounds the cell region CR in a plan view.

[0016] As shown in FIG. 1, the cell region CR is covered with a source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE, the source wiring SW surrounds the gate wiring GW, and the drain wiring DW surrounds the source wiring SW. The source wiring SW is electrically connected to the source electrode SE. Here, the gate wiring GW does not completely surround the source electrode SE, and the source electrode SE and the source wiring SW are connected integrally at the location where a portion of the gate wiring GW is separated.

[0017] Although not shown here, the source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW are covered with a protective film such as a polyimide film. Openings are provided in parts of the protective film, and the source electrode SE and gate wiring GW exposed through the openings become the source pad and gate pad. External connection members such as wires or clips (copper plates) are connected to the source pad and gate pad, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or wiring board.

[0018] Between the source wiring SW and the drain wiring DW, an insulating film IF1 and a resistor SR are formed so as to surround the cell region CR in plan view. The resistor SR is formed on the insulating film IF1.

[0019] As shown in FIG. 2, the resistor element SR includes a spiral-shaped resistor portion SRa, a first contact portion SRb located on the inner periphery of the resistor portion SRa, and a second contact portion SRc located on the outer periphery of the resistor portion SRa. The resistor portion SRa, the first contact portion SRb, and the second contact portion SRc are integrated and made of the same conductive film. The resistor portion SRa has a shape in which a single conductive film is wound around the cell region CR multiple times. The number of turns of the resistor portion SRa is not limited to the example shown in FIG. 2 and can be set as appropriate. The first contact portion SRb and the second contact portion SRc are annular.

[0020] As will be described later, the first contact portion SRb is electrically connected to the source wiring SW through the hole CH, and the second contact portion SRc is electrically connected to the drain wiring DW through the hole CH. One end of the resistor portion SRa is connected to the first contact portion SRb, and the other end of the resistor portion SRa is connected to the second contact portion SRc. Therefore, a current flows through the resistor element SR.

[0021] In terms of an equivalent circuit, a resistive element SR is connected between the source and drain of the MOSFET 1Q. The longer the length of the resistive portion SRa and the more turns the resistive portion SRa makes, the more the voltage between the source and drain is divided, and therefore the electric field is relaxed from the drain wiring DW toward the source wiring SW. Therefore, the breakdown voltage of the semiconductor device 100 can be improved in the peripheral region OR.

[0022] 3 and 4, a plurality of MOSFETs 1Q are formed in the cell region CR, and a resistor SR is formed in the peripheral region OR. First, the structure of the MOSFET 1Q in the cell region CR (region 1A) will be described, and then the structure of the resistor SR in the peripheral region OR (region 2A) and the structure around it will be described.

[0023] The semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In this case, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked body consisting of an n-type silicon substrate and an n-type semiconductor layer will also be described as the semiconductor substrate SUB.

[0024] A gate insulating film GI is formed on the upper surface of the semiconductor substrate SUB in the cell region CR. A gate electrode GE is formed on the gate insulating film GI. An insulating film IF3 is formed on the gate electrode GE. The gate insulating film GI is, for example, a silicon oxide film and has a thickness of, for example, 80 nm or more and 120 nm or less. The gate electrode GE is, for example, a polycrystalline silicon film doped with n-type impurities and has a thickness of, for example, 400 nm or more and 500 nm or less. The insulating film IF3 is, for example, a silicon oxide film and has a thickness of, for example, 80 nm or more and 120 nm or less.

[0025] On the upper surface side of the semiconductor substrate SUB, a p-type body region PB is formed in the semiconductor substrate SUB in the cell region CR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV. Furthermore, a p-type high-concentration diffusion region PA is formed in the body region PB. The high-concentration diffusion region PA has a higher impurity concentration than the body region PB.

[0026] The gate electrode GE is formed across the two body regions PB with a gate insulating film GI interposed therebetween. An n-type well region NW is formed in the semiconductor substrate SUB between the two body regions PB. The well region NW has a higher impurity concentration than the drift region NV. The body region PB, which is located between the source region NS and the well region NW and below the gate electrode GE, functions as a channel region of the MOSFET 1Q.

[0027] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. A drain voltage is supplied from the drain electrode DE to the semiconductor substrate SUB (drain region ND, drift region NV). The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated.

[0028] The path from the source region NS to the drain region ND via the channel region (body region PB), well region NW, and drift region NV forms the current path of the MOSFET 1Q.

[0029] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the MOSFET 1Q in the cell region CR. The interlayer insulating film IL is made of, for example, a stacked film of a silicon nitride film and a silicon oxide film formed on the silicon nitride film. The silicon oxide film may include a thick silicon oxide film containing phosphorus (PSG: Phospho Silicate Glass film) and a thick silicon oxide film containing boron and phosphorus (BPSG: Boro Phospho Silicate Glass film). The thickness of the interlayer insulating film IL is, for example, 900 nm or more and 1200 nm or less.

[0030] A hole CH reaching the source region NS is formed in the interlayer insulating film IL. Although not shown here, the source region NS is divided in the depth direction (Y direction) of the drawing, and a heavily doped diffusion region PA is formed in the surface of the body region PB. The hole CH also extends in the Y direction. That is, a portion of the hole CH reaches the heavily doped diffusion region PA.

[0031] In the cell region CR, a source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is embedded in the hole CH. The source electrode SE is electrically connected to the source region NS, the heavily doped diffusion region PA, and the body region PB, and supplies a source voltage to these regions.

[0032] Although not shown here, a hole reaching the gate electrode GE is also formed in the interlayer insulating film IL. The gate wiring GW is formed on the interlayer insulating film IL and embedded in the hole CH. Therefore, the gate wiring GW is electrically connected to the gate electrode GE and supplies a gate voltage to the gate electrode GE.

[0033] Next, the structure of the resistor element SR in the outer peripheral region OR (region 2A) and the structure around it will be described.

[0034] An insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB in the peripheral region OR. The insulating film IF1 is, for example, a silicon oxide film, and has a thickness of, for example, 900 nm or more and 1200 nm or less.

[0035] A resistor element SR is formed on the insulating film IF1 via an insulating film IF3. As described above, the resistor element SR includes a resistor portion SRa, a first contact portion SRb, and a second contact portion SRc. The resistor element SR is, for example, a polycrystalline silicon film doped with p-type impurities and has a thickness of, for example, 500 nm to 700 nm.

[0036] An insulating film IF2 is formed on the upper surface of the semiconductor substrate SUB in the peripheral region OR. The insulating film IF2 is made of the same insulating film as the gate insulating film GI and has a thickness thinner than that of the insulating film IF1, for example, a thickness of 80 nm or more and 120 nm or less.

[0037] A step occurs between the insulating film IF2 and the insulating film IF1. A dummy pattern DP1 is formed from the top of the insulating film IF2 to the top of the insulating film IF1 so as to cover the step. The dummy pattern DP1 is made of the same conductive film as the gate electrode GE, but is made of a conductive film different from that of the resistor element SR.

[0038] A dummy pattern DP2 is formed on the side surface of the dummy pattern DP1, which is formed at a position higher than the insulating film IF1, via an insulating film IF3. The dummy pattern DP2 is made of the same conductive film as the resistor element SR.

[0039] The dummy patterns DP1 and DP2 are in a floating state and are not electrically connected to semiconductor elements such as the MOSFET 1Q and the resistor SR.

[0040] On the upper surface side of the semiconductor substrate SUB, a p-type resurf region PRS is formed in the semiconductor substrate SUB in the peripheral region OR. The resurf region PRS is formed directly below the resistor element SR via an insulating film IF1. A p-type well region PW is formed in the resurf region PRS. A high-concentration diffusion region PA is formed in the well region PW. The well region PW is electrically connected to the body region PB of the cell region CR. The well region PW has a higher impurity concentration than the resurf region PRS and a lower impurity concentration than the high-concentration diffusion region PA.

[0041] An n-type heavily doped diffusion region NA is formed in the semiconductor substrate SUB in the peripheral region OR on the upper surface side of the semiconductor substrate SUB. The heavily doped diffusion region NA has a higher impurity concentration than the drift region NV. A heavily doped diffusion region PA is formed in the heavily doped diffusion region NA.

[0042] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the resistor element SR, the dummy pattern DP1, and the insulating film IF1 in the peripheral region OR. A plurality of holes CH are formed in the interlayer insulating film IL, reaching the first contact portion SRb, the second contact portion SRc, the heavily doped diffusion region NA, and the heavily doped diffusion region PA. As shown in FIG. 2, the first contact portion SRb and the second contact portion SRc are annular in plan view, and the holes CH reaching them also have annular shapes in plan view, following the shapes of the first contact portion SRb and the second contact portion SRc.

[0043] In the peripheral region OR, a source wiring SW and a drain wiring DW are formed on the interlayer insulating film IL, and the source wiring SW and the drain wiring DW are buried in the plurality of holes CH, respectively.

[0044] The source wiring SW is electrically connected to the heavily doped diffusion region PA, the well region PW, the resurf region PRS, and the body region PB, and supplies a source voltage to these. The source wiring SW is also connected to the first contact portion SRb, and supplies a source voltage to the first contact portion SRb.

[0045] The drain wiring DW is electrically connected to the drain electrode DE via an n-type semiconductor substrate SUB (high-concentration diffusion region NA, drift region NV, and drain region ND). The drain wiring DW is also connected to the second contact portion SRc. Therefore, the drain voltage supplied from the drain electrode DE to the drain wiring DW is also supplied to the second contact portion SRc.

[0046] The source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW are each made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film or a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0047] The source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW may be composed of a plug layer filling the hole CH and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is composed of the barrier metal film and the conductive film. The plug layer is composed of a stacked film of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0048] <Method of manufacturing a semiconductor device> 5 to 16, the manufacturing steps included in the manufacturing method of the semiconductor device 100 will be described below. In the following description, the region 1A (cell region CR) and the region 2A (periphery region OR) in FIG.

[0049] Furthermore, the main features of the semiconductor device 100 and its manufacturing method in embodiment 1 are the structures of the resistor element SR, dummy pattern DP1 and dummy pattern DP2 and the manufacturing method thereof, and these features will be explained in detail later in comparison with the study example.

[0050] 5, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. As described above, the n-type semiconductor substrate SUB itself constitutes the drift region NV here, but the drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). Next, an insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB by thermal oxidation.

[0051] As shown in FIG. 6, first, a resist pattern RP1 having a pattern covering a part of the peripheral region OR is formed on the insulating film IF1. Next, the insulating film IF1 is patterned by performing an anisotropic etching process using the resist pattern RP1 as a mask. As a result, the insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB in the peripheral region OR so as to surround the cell region CR in a plan view. Thereafter, the resist pattern RP1 is removed by ashing.

[0052] 7, an n-type well region NW is formed in the semiconductor substrate SUB in the cell region CR by photolithography and ion implantation, and a p-type resurf region PRS and a p-type well region PW are formed in the semiconductor substrate SUB in the peripheral region OR. Then, impurities contained in the well region NW, resurf region PRS, and well region PW are diffused by performing a heat treatment at, for example, 1200°C.

[0053] 8, first, an insulating film IF2 having a thickness thinner than that of the insulating film IF1 is formed by thermal oxidation on the upper surface of the semiconductor substrate SUB in the cell region CR and the peripheral region OR. Next, a conductive film CF1 is formed on the insulating films IF1 and IF2 by, for example, CVD. The conductive film CF1 is a polycrystalline silicon film doped with n-type impurities, and is formed so as to cover the step occurring between the insulating films IF2 and IF1.

[0054] As shown in FIG. 9, a resist pattern RP2 having a pattern that opens near the center of the insulating film IF1 is formed on the conductive film CF1. Next, an anisotropic etching process is performed using the resist pattern RP2 as a mask to pattern the conductive film CF1. This patterning selectively removes a portion of the conductive film CF1 on the insulating film IF1 so that the conductive film CF1 that covers the step remains. Note that the conductive film CF1 in the cell region CR also remains. Thereafter, the resist pattern RP2 is removed by ashing.

[0055] As shown in FIG. 10, first, an insulating film IF3 is formed on the insulating film IF1 and the conductive film CF1 by, for example, a CVD method. Next, a conductive film CF2 is formed on the insulating film IF3 by, for example, a CVD method. The conductive film CF2 is a non-doped polycrystalline silicon film. Next, a p-type impurity such as boron (B) or boron difluoride (BF2) is introduced into the conductive film CF2 by an ion implantation method.

[0056] As shown in FIG. 11, first, a resist pattern RP3 is formed on the conductive film CF2, selectively covering the conductive film CF2 located on the insulating film IF1. Next, an anisotropic etching process is performed on the conductive film CF2 using the resist pattern RP3 as a mask. By patterning the conductive film CF2 in this manner, a resistor element SR located on the insulating film IF1 is formed so as to surround the cell region CR in a plan view. Thereafter, the resist pattern RP3 is removed by ashing.

[0057] Furthermore, by the anisotropic etching process, the conductive film CF2 is left as a dummy pattern DP2 on the side surface of the conductive film CF1 formed at a position higher than the insulating film IF1 via the insulating film IF3. Note that the conductive film CF2 in the cell region CR is completely removed.

[0058] 12, first, a resist pattern RP4 is formed to cover the resistor element SR and the conductive film CF1 near the step in the peripheral region OR and to selectively cover the conductive film CF1 in the cell region CR. Next, using the resist pattern RP4 as a mask, an anisotropic etching process is performed on the conductive film CF2, thereby selectively removing part of the insulating film IF3, part of the conductive film CF1, and part of the insulating film IF2 on the upper surface of the semiconductor substrate SUB. Thereafter, the resist pattern RP4 is removed by ashing.

[0059] Here, the conductive film CF1 left in the peripheral region OR forms a dummy pattern DP1. The dummy pattern DP1 is formed from the top of the insulating film IF2 to the top of the insulating film IF1 so as to cover a step occurring between the insulating films IF2 and IF1. Furthermore, the conductive film CF1 left in the cell region CR forms the gate electrode GE of the MOSFET 1Q, and the insulating film IF2 left in the cell region CR forms the gate insulating film GI of the MOSFET 1Q.

[0060] 13, first, a p-type body region PB is formed in the semiconductor substrate SUB in the cell region CR on the upper surface side of the semiconductor substrate SUB by photolithography and ion implantation. Then, impurities contained in the body region PB are diffused by performing a heat treatment at, for example, 1100°C.

[0061] Next, photolithography and ion implantation are used to form an n-type source region NS in the body region PB, and an n-type heavily doped diffusion region NA in the semiconductor substrate SUB in the peripheral region OR. Then, a heat treatment at, for example, 950° C. is performed to diffuse the impurities contained in the source region NS and the heavily doped diffusion region NA.

[0062] Although not shown here, before these ion implantations, a through film such as a silicon oxide film is formed on the semiconductor substrate SUB. This through film may be removed after the ion implantation, but may also be left as part of an interlayer insulating film IL, which will be described later.

[0063] 14, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the MOSFET 1Q in the cell region CR and to cover the resistor SR, the dummy patterns DP1 and DP2, and the insulating film IF1 in the peripheral region OR. The interlayer insulating film IL is a laminated film including, for example, a silicon nitride film formed by a CVD method, a silicon oxide film formed by a CVD method, a PSG film formed by a coating method, and a BPSG film formed by a coating method.

[0064] 15, first, a plurality of holes CH are formed in the interlayer insulating film IL by photolithography and anisotropic etching. The plurality of holes CH include a hole reaching the first contact portion SRb, a hole reaching the second contact portion SRc, a hole reaching the semiconductor substrate SUB (high-concentration diffusion region NA, well region PW) in the peripheral region OR, a hole reaching the source region NS, and a hole reaching the gate electrode GE.

[0065] Next, by photolithography and ion implantation, a heavily doped diffusion region PA is formed in the heavily doped diffusion region NA located at the bottom of the hole CH, the well region PW, and the body region PB. Although not shown here, a heavily doped diffusion region PA is also formed in the first contact portion SRb and the second contact portion SRc.

[0066] As shown in FIG. 16, a source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW are formed on an interlayer insulating film IL. To form these, a laminated film is first formed on the interlayer insulating film IL by sputtering or CVD. The laminated film is made of a barrier metal film, such as a titanium tungsten film or a titanium nitride film, and a conductive film, such as an aluminum film. Next, the source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW are formed by patterning the laminated film. The source electrode SE, gate wiring GW, source wiring SW, and drain wiring DW are each buried in a hole CH.

[0067] Thereafter, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE, the gate wiring GW, the source wiring SW, and the drain wiring DW by, for example, a coating method. Parts of the protective film are opened to expose the regions of the source electrode SE and the gate wiring GW that will become the source pad and the gate pad.

[0068] Thereafter, the semiconductor device 100 shown in FIG. 4 is manufactured through the following manufacturing steps. First, the lower surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface of the semiconductor substrate SUB by sputtering.

[0069] <Study example and main features of the first embodiment> Fig. 17 is a cross-sectional view showing a structure in the vicinity of the dummy pattern DP1. Fig. 18 is a cross-sectional view of a semiconductor device in an example study conducted by the present inventors based on Patent Document 1 and the like. As shown in Fig. 18, in the example study, unlike the first embodiment, the resistance element SR is formed of a conductive film CF1. Note that in the example study, the gate electrode GE is also formed of a conductive film CF1.

[0070] Because a high voltage is applied to the resistance element SR, the thickness of the insulating film IF1 is set to be sufficiently thick so that a tunnel current does not flow in the semiconductor substrate SUB, and therefore the height of the step generated between the insulating films IF2 and IF1 is also very high.

[0071] As shown in FIG. 18, when a resistor element SR is formed using a conductive film CF1, the conductive film CF1 is processed into a sidewall shape by an anisotropic etching process during patterning, and a dummy pattern DP3 is left in the step. In the subsequent manufacturing process, various cleaning steps are performed before film formation or after removing the resist pattern. If the insulating films IF1 and IF2 in contact with the dummy pattern DP3 are retracted by these cleaning steps, the dummy pattern DP3 becomes more likely to peel off. If this happens, the dummy pattern DP3 will remain on the semiconductor substrate SUB in a wafer state as a foreign object, causing defects.

[0072] To completely remove such dummy pattern DP3, it is possible to further extend the anisotropic etching process performed during patterning of the conductive film CF1. However, in this case, the semiconductor substrate SUB located between the gate electrodes GE in the cell region CR is also exposed to the etching, resulting in the removal of the semiconductor substrate SUB. This can easily cause problems such as a change in the threshold voltage of the MOSFET 1Q.

[0073] Furthermore, the portion spanning the step is covered with a resist pattern many times in subsequent manufacturing processes, and if the step is very high, there is a problem that the resist pattern is likely to be interrupted at the step when it is formed.

[0074] Furthermore, in the example under consideration, both the gate electrode GE and the resistor element SR are formed from a single layer of conductive film CF1, so if the characteristics of the gate electrode GE are prioritized, there is a problem in that it is difficult to appropriately set the resistivity required for the resistor element SR.

[0075] As shown in FIG. 17, in the first embodiment, the gate electrode GE is formed by the conductive film CF1, and the resistance element SR is formed by the conductive film CF2. Therefore, the characteristics of the gate electrode GE and the resistance element SR can be set separately. The resistance element SR is formed to have high resistance in order to reduce the current flowing through the resistance element SR, and p-type impurities are introduced into it. For example, boron (B) is introduced into the conductive film CF2, and the impurity concentration is 4.9×10 -17 cm ―3 For example, phosphorus (P) is introduced into the conductive film CF1, and the impurity concentration is about 5.5×10 -19 cm ―3 That's about it.

[0076] Furthermore, in the first embodiment, a dummy pattern DP1 is formed from the insulating film IF2 to the insulating film IF1 so as to cover a step occurring between the insulating film IF2 and the insulating film IF1. Compared to the case where the dummy pattern DP1 is left in a sidewall shape, as in the dummy pattern DP3 of the study example, the area where the dummy pattern DP1 contacts the insulating films IF2 and IF1 is increased. Therefore, in the first embodiment, the dummy pattern DP1 is less likely to peel off even when subjected to various cleaning processes. Therefore, the generation of foreign matter can be suppressed, thereby improving the reliability of the semiconductor device 100 and suppressing a decrease in yield.

[0077] Note that, when the conductive film CF2 is patterned, a sidewall-like dummy pattern DP2 is formed on the side surface of the dummy pattern DP1, which is formed at a position higher than the insulating film IF1. If this dummy pattern DP2 peels off, the dummy pattern DP2 may also become a source of foreign matter, but in the subsequent manufacturing process, the dummy pattern DP2 is covered with the interlayer insulating film IL. During this time, the dummy pattern DP2 is exposed to several cleaning processes, but the number of these processes is relatively small, so the dummy pattern DP2 is unlikely to peel off.

[0078] Furthermore, at the location spanning the step, the conductive film CF1 is likely to have a shape with a slope toward the insulating film IF1 during deposition of the conductive film CF1. The dummy pattern DP2 further reduces the slope. Therefore, when a resist pattern is formed on the dummy pattern DP1 and the dummy pattern DP2, the resist pattern is more easily applied and less likely to be interrupted.

[0079] 17, the height H1 of the first step occurring between the semiconductor substrate SUB and the dummy pattern DP1 on the semiconductor substrate SUB and the height H2 of the second step occurring between the insulating film IF1 and the dummy pattern DP1 on the insulating film IF1 are lower than the height H3 of the third step occurring between the insulating films IF2 and IF1 (height H1, height H2<height H3).

[0080] The height H3 is gradually reduced by the dummy pattern DP1. That is, in the studied example, the height H3 made the resist pattern more likely to be interrupted, but in the first embodiment, the resist pattern covers the portions of height H1 and height H2, which are lower than height H3. Since the height H3, which was previously determined by the insulating film IF1, is reduced, the coatability of the resist pattern is further improved, and the resist pattern is less likely to be interrupted.

[0081] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Fig. 19. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0082] 19 shows a manufacturing process following FIG. 11 of the first embodiment. In FIG. 11, an anisotropic etching process is performed on the conductive film CF2 to form the resistor element SR and the dummy pattern DP2. In the second embodiment, the anisotropic etching process is further continued. As a result, the dummy pattern DP2 is removed.

[0083] Although a plurality of dummy patterns DP2 are formed, at least the dummy patterns DP2 that are relatively small in size are removed. That is, as shown in Fig. 19, of the conductive film CF1 formed at a position higher than the insulating film IF1, at least the dummy patterns DP2 remaining on the side surfaces of the conductive film CF1 located on the insulating film IF1 are removed. The anisotropic etching process may be continued until all the dummy patterns DP2 are removed.

[0084] As described above, the dummy patterns DP2 are subjected to several cleaning steps before they are covered with the interlayer insulating film IL. Since the number of cleaning steps is relatively small, the possibility of the dummy patterns DP2 peeling off is also small. However, in order to reduce this possibility as much as possible, in the second embodiment, at least some of the multiple dummy patterns DP2 are removed in advance.

[0085] 1, the insulating film IF1 has a relatively large thickness and is formed so as to surround the cell region CR, occupying a relatively large area of ​​the semiconductor substrate SUB in a wafer state. Therefore, the semiconductor substrate SUB in a wafer state is likely to warp due to stress from the insulating film IF1, and various processing accuracies may be reduced.

[0086] The anisotropic etching process is performed under conditions that allow the polycrystalline silicon films (conductive films CF1 and CF2) to be easily etched and the silicon oxide films (insulating films IF1 and IF3) to be difficult to etch, but while the polycrystalline silicon films are being etched, the silicon oxide films are also gradually etched. In other words, by extending the anisotropic etching process, the insulating film IF3 exposed from the resist pattern RP3 is etched.

[0087] In particular, when the anisotropic etching process is performed until all of the dummy patterns DP2 are removed, the insulating film IF3 is removed and the insulating film IF1 located below the insulating film IF3 is also etched. This reduces the stress from the insulating film IF1, and reduces warpage of the semiconductor substrate SUB in a wafer state.

[0088] On the other hand, after the insulating film IF3 is removed, the upper surface of the conductive film CF1 is exposed. If the anisotropic etching process is further continued, the conductive film CF1 begins to be etched, and the height of the conductive film CF1 decreases. Since the conductive film CF1 in the cell region CR becomes the gate electrode GE, fluctuations in the height of the conductive film CF1 may cause the characteristics of the MOSFET 1Q to deviate from the desired design values.

[0089] Therefore, if there is a concern that the characteristics of the MOSFET 1Q may fluctuate, it is desirable to remove as much of the dummy pattern DP2 as possible without completely removing the insulating film IF3. On the other hand, if there appears to be no problem with the characteristics of the MOSFET 1Q, it is desirable to perform an anisotropic etching process so that not only the insulating film IF3 but also the insulating film IF1 is etched, prioritizing the removal of all of the dummy patterns DP2 and the reduction of warpage of the semiconductor substrate SUB in the wafer state.

[0090] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0091] 100 Semiconductor device 1A Area (Cell Area) 2A area (outer area) 1Q MOSFET CH hole CR Cell Area DE drain electrode DP1~DP3 dummy patterns DW Drain wiring GE gate electrode GI gate insulating film GW Gate wiring IF1~IF3 insulating film IL Interlayer insulating film NA high concentration diffusion region ND drain region NS Source Region NV drift region NW well region OR outer area PA High concentration diffusion region PB body region PRS Resurf Range PW well region RP1~RP4 resist patterns SE source electrode SR resistor element SRa resistance section SRb 1st contact part SRc 2nd contact part SUB Semiconductor substrate SW source wiring

Claims

1. A semiconductor device having a cell region in which a MOSFET is formed and a peripheral region surrounding the cell region in a plan view, a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a first insulating film formed on the upper surface of the semiconductor substrate in the peripheral region so as to surround the cell region in a plan view; a resistor element formed on the first insulating film so as to surround the cell region in a plan view; Equipped with a second insulating film having a thickness thinner than that of the first insulating film is formed on the upper surface of the semiconductor substrate in the peripheral region; a first dummy pattern is formed from on the second insulating film to on the first insulating film so as to cover a step occurring between the second insulating film and the first insulating film.

2. 2. The semiconductor device according to claim 1, The first dummy pattern is not electrically connected to the MOSFET and the resistor element.

3. 2. The semiconductor device according to claim 1, a second dummy pattern formed on a side surface of the first dummy pattern, the second dummy pattern being formed at a position higher than the first insulating film, with a third insulating film interposed therebetween;

4. 4. The semiconductor device according to claim 3, the first dummy pattern and the second dummy pattern are not electrically connected to the MOSFET and the resistor element.

5. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the thickness of the first dummy pattern is thinner than the thickness of the first insulating film.

6. 2. The semiconductor device according to claim 1, The resistive element is a spiral resistance portion; a first contact portion that is integrated with the resistor portion and is located on the inner circumferential side of the resistor portion; a second contact portion that is integrated with the resistor portion and is located on the outer periphery of the resistor portion; 10. A semiconductor device comprising:

7. 7. The semiconductor device according to claim 6, The MOSFET is a gate insulating film formed on the upper surface of the semiconductor substrate in the cell region; a gate electrode formed on the gate insulating film; a body region formed in the semiconductor substrate in the cell region on the upper surface side of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; a source region of the first conductivity type formed in the body region; and the gate insulating film is made of the same insulating film as the second insulating film, the gate electrode is made of the same conductive film as the first dummy pattern, but is made of a conductive film different from that of the resistor element.

8. 8. The semiconductor device according to claim 7, an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the MOSFET in the cell region and to cover the resistance element, the first dummy pattern, and the first insulating film in the peripheral region; a first hole formed in the interlayer insulating film and reaching the first contact portion; a second hole formed in the interlayer insulating film and reaching the second contact portion; a third hole formed in the interlayer insulating film and reaching the semiconductor substrate in the peripheral region; a fourth hole formed in the interlayer insulating film and reaching the source region; a fifth hole formed in the interlayer insulating film and reaching the gate electrode; a source electrode formed on the interlayer insulating film; a gate wiring formed on the interlayer insulating film and surrounding the source electrode in a plan view; a source wiring formed on the interlayer insulating film, surrounding the gate wiring in a plan view, and electrically connected to the source electrode; a drain wiring formed on the interlayer insulating film and surrounding the source wiring in a plan view; a drain electrode formed below the lower surface of the semiconductor substrate; Further provided with the source wiring is embedded in the first hole and is electrically connected to the first contact portion; the drain wiring is embedded in the second hole and the third hole, and is electrically connected to the second contact portion and the semiconductor substrate; the source electrode is embedded in the fourth hole and is electrically connected to the source region; the gate wiring is buried in the fifth hole and is electrically connected to the gate electrode.

9. 2. The semiconductor device according to claim 1, the first dummy pattern is doped with impurities of the first conductivity type; The semiconductor device, wherein the resistor element is doped with an impurity of a second conductivity type opposite to the first conductivity type.

10. 1. A method for manufacturing a semiconductor device having a cell region in which a MOSFET is formed and a peripheral region surrounding the cell region in a plan view, the method comprising: (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film on the upper surface of the semiconductor substrate in the peripheral region so as to surround the cell region in a plan view; (c) after the step (b), forming a second insulating film having a thickness thinner than that of the first insulating film on the upper surface of the semiconductor substrate in the peripheral region; (d) after the step (c), forming a first conductive film on the first insulating film and the second insulating film so as to cover a step occurring between the second insulating film and the first insulating film; (e) after the step (d), selectively removing a portion of the first conductive film on the first insulating film so that the first conductive film covering the step remains; (f) after the step (e), forming a third insulating film on the first insulating film and the first conductive film; (g) after the step (f), forming a second conductive film on the third insulating film; (h) after the step (g), patterning the second conductive film to form a resistor element located on the first insulating film so as to surround the cell region in a plan view; (i) after the step (h), selectively removing a portion of the third insulating film, a portion of the first conductive film, and a portion of the second insulating film on the upper surface of the semiconductor substrate; Equipped with the first conductive film remaining in the outer peripheral region after the step (i) forms a first dummy pattern; The method for manufacturing a semiconductor device, wherein the first dummy pattern is formed from above the second insulating film to above the first insulating film so as to cover the step.

11. 11. The method for manufacturing a semiconductor device according to claim 10, The first dummy pattern is not electrically connected to the MOSFET and the resistor element.

12. 11. The method for manufacturing a semiconductor device according to claim 10, In the patterning of the step (h), an anisotropic etching process is performed on the second conductive film using a resist pattern that selectively covers the second conductive film as a mask; a second dummy pattern formed on a side surface of the first conductive film, the second dummy pattern being left via the third insulating film by the anisotropic etching process, the second conductive film being left as a second dummy pattern on a side surface of the first conductive film, the side surface being formed at a position higher than the first insulating film.

13. 13. The method for manufacturing a semiconductor device according to claim 12, a second dummy pattern formed on the first insulating film and remaining on at least a side surface of the first conductive film positioned above the first insulating film by further continuing the anisotropic etching process after the second dummy pattern is formed, the second dummy pattern being removed from the first conductive film formed at a position higher than the first insulating film.

14. 13. The method for manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the first dummy pattern and the second dummy pattern are not electrically connected to the MOSFET and the resistor element.

15. 11. The method for manufacturing a semiconductor device according to claim 10, A method for manufacturing a semiconductor device, wherein the thickness of the first conductive film is thinner than the thickness of the first insulating film.

16. 11. The method for manufacturing a semiconductor device according to claim 10, The resistive element is a spiral resistance portion; a first contact portion that is integrated with the resistor portion and is located on the inner circumferential side of the resistor portion; a second contact portion that is integrated with the resistor portion and is located on the outer periphery of the resistor portion; A method for manufacturing a semiconductor device, comprising:

17. 17. The method for manufacturing a semiconductor device according to claim 16, In the step (c), the second insulating film is also formed on the upper surface of the semiconductor substrate in the cell region; In the step (d), the first conductive film is also formed on the second insulating film in the cell region; In the step (e), the first conductive film in the cell region is left, In the step (f), the third insulating film is also formed on the first conductive film in the cell region; In the step (g), the second conductive film is also formed on the third insulating film in the cell region; In the step (h), the second conductive film in the cell region is removed; the first conductive film remaining in the cell region after the step (i) forms a gate electrode of the MOSFET; the second insulating film remaining in the cell region after the step (i) forms a gate insulating film of the MOSFET.

18. 18. The method for manufacturing a semiconductor device according to claim 17, (j) after the step (i), forming a body region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate in the cell region on the upper surface side of the semiconductor substrate; (k) after the step (j), forming a source region of the first conductivity type in the body region; (l) after the step (k), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the MOSFET in the cell region and to cover the resistance element, the first dummy pattern, and the first insulating film in the peripheral region; (m) after the step (l), forming in the interlayer insulating film a first hole reaching the first contact portion, a second hole reaching the second contact portion, a third hole reaching the semiconductor substrate in the outer periphery region, a fourth hole reaching the source region, and a fifth hole reaching the gate electrode; (n) after the step (m), forming, on the interlayer insulating film, a source electrode, a gate wiring surrounding the source electrode in a plan view, a source wiring surrounding the gate wiring in a plan view and electrically connected to the source electrode, and a drain wiring surrounding the source wiring in a plan view; (o) after the step (n), forming a drain electrode below the lower surface of the semiconductor substrate; Further provided with the source wiring is embedded in the first hole and is electrically connected to the first contact portion; the drain wiring is embedded in the second hole and the third hole, and is electrically connected to the second contact portion and the semiconductor substrate; the source electrode is embedded in the fourth hole and is electrically connected to the source region; the gate wiring is embedded in the fifth hole and is electrically connected to the gate electrode.

19. 20. The method of manufacturing a semiconductor device according to claim 18, The first conductive film is doped with impurities of the first conductivity type, The method for manufacturing a semiconductor device, wherein the second conductive film is doped with an impurity of the second conductivity type.

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