Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of improving the bonding reliability between bonding pads and bonding wires.SOLUTION: A semiconductor device has a first metal film that constitutes the topmost layer of wiring with bonding pads. The concentration of impurities at the grain boundaries of the first metal film is higher than the concentration of impurities within the crystal grains in the first metal film. The maximum grain size of the crystal grains in the first metal film is less than 5 μm.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Japanese Patent Laid-Open Publication No. 2014-187073 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has wiring and an OPM (Over Pad Metallurgy) film. The wiring is the top layer wiring. The wiring has a bonding pad. The wiring is made of an aluminum alloy. The OPM film is disposed on the bonding pad. A bonding wire is bonded to the bonding pad via the OPM film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-187073 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is room for improvement in the reliability of the bonding between the bonding pad and the bonding wire in the semiconductor device described in Patent Document 1. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a first metal film constituting an uppermost wiring layer having a bonding pad. The concentration of impurities at the grain boundaries of the first metal film is higher than the concentration of impurities within the crystal grains in the first metal film. The maximum grain size of the crystal grains contained in the first metal film is less than 5 μm. [Effects of the Invention]

[0006] The reliability of the bond between the bonding pad and the bonding wire can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2] 10A to 10C are process diagrams showing a manufacturing method of the semiconductor device DEV1. [Figure 3] FIG. 2 is a cross-sectional view illustrating the sputtering step S1. [Figure 4] FIG. 10 is a cross-sectional view illustrating a wiring patterning step S2. [Figure 5] FIG. 10 is a cross-sectional view illustrating a protective film forming step S3. [Figure 6] FIG. 10 is a cross-sectional view illustrating an OPM film forming step S4. [Figure 7] FIG. 2 is a cross-sectional view of the semiconductor device DEV2. [Figure 8] FIG. 2 is a cross-sectional view of the semiconductor device DEV3. [Figure 9] FIG. 10 is a cross-sectional view of the semiconductor device DEV4. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) A semiconductor device according to the first embodiment will be described below. The semiconductor device according to the first embodiment is referred to as semiconductor device DEV1.

[0010] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0011] FIG. 1 is a cross-sectional view of a semiconductor device DEV1. As shown in FIG. 1, the semiconductor device DEV1 has an interlayer insulating film ILD, wiring WL (first metal film), a protective film PV, an OPM film OPM1 (second metal film), and an OPM film OPM2. Note that FIG. 1 does not show structures below the interlayer insulating film ILD. The semiconductor device DEV1 is a power device. A specific example of a power device is an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor device DEV1 is not limited to an IGBT.

[0012] The interlayer insulating film ILD is the uppermost interlayer insulating film. The interlayer insulating film ILD is formed of, for example, silicon oxide (SiO2). The wiring WL is disposed on the interlayer insulating film ILD. The wiring WL is the uppermost wiring. The wiring WL has a bonding pad BP1 and a bonding pad BP2. If the semiconductor device DEV1 is an IGBT, the bonding pad BP1 and the bonding pad BP2 are a gate electrode and an emitter electrode, respectively.

[0013] The wiring WL contains a first metal element as a main component. That is, the content of the first metal element in the wiring WL is 99 percent or more. The first metal element is, for example, aluminum (Al). The second metal element may be copper (Cu). The wiring WL2 may contain the second metal element. When the first metal element is aluminum, the second metal element is, for example, at least one of silicon (Si), copper (Cu), and palladium (Pd).

[0014] The wiring WL contains an impurity. The impurity is, for example, oxygen (O). The impurity may be nitrogen (N) or carbon (O). That is, the wiring WL only needs to contain at least one of oxygen, nitrogen, and carbon as an impurity.

[0015] The wiring WL is polycrystalline. The impurity concentration at the grain boundaries of the wiring WL is higher than the impurity concentration within the crystal grains of the wiring WL. When the impurity contained in the wiring WL is oxygen, the oxygen concentration within the crystal grains of the wiring WL is preferably 0.6 atomic percent or more and 0.8 atomic percent or less, and the oxygen concentration at the grain boundaries of the wiring WL is preferably 0.9 atomic percent or more and 1.5 atomic percent or less.

[0016] The impurity concentration at the grain boundaries of the wiring WL and the impurity concentration within the crystal grains of the wiring WL are measured using an EPMA (Electron Probe Micro Analyzer). The spot diameter of the electron beam used for this measurement is 1 μm or less. The impurity concentration at the grain boundaries of the wiring WL and the impurity concentration within the crystal grains of the wiring WL are measured at three measurement points, and the average value is calculated.

[0017] The maximum grain size of the crystal grains contained in the wiring WL is less than 5 μm. The maximum grain size of the crystal grains contained in the wiring WL is preferably less than 4 μm. The maximum value of the crystal grains contained in the wiring WL is measured by EBSD (Electron Back Scattered Electron) method. More specifically, first, an EBSD image is acquired on the cross section of the wiring WL. This EBSD image has a magnification of 1500 times and a size of 50 μm × 50 μm. Second, the crystal grain with the largest grain size in the EBSD image is identified, and the square root of the value obtained by dividing the area of ​​the crystal grain by π / 4 is calculated. This square root is regarded as the maximum grain size of the crystal grains contained in the wiring WL.

[0018] The hardness of the wiring WL is preferably 0.8 GPa or more. The hardness of the wiring WL is measured by a nanoindentation hardness test specified in ISO14577. The test conditions for this nanoindentation hardness test are room temperature and an indenter penetration depth of approximately 10 percent of the thickness of the wiring WL. The hardness of the wiring WL is measured at 10 measurement points, and the average value is calculated.

[0019] The protective film PV is disposed on the interlayer insulating film ILD so as to cover the wiring WL. The protective film PV is formed of, for example, polyimide. An opening OP1 and an opening OP2 are formed in the protective film PV. The opening OP1 penetrates the protective film PV in the thickness direction. A bonding pad BP1 is exposed from the opening OP1. The opening OP2 penetrates the protective film PV in the thickness direction. A bonding pad BP2 is exposed from the opening OP2.

[0020] The opening width of the opening OP1 is defined as width W1. The opening width of the opening OP2 is defined as width W2. Width W1 is smaller than width W2. Width W1 is preferably 300 μm or less. Width W1 is, for example, 90 μm or more. Width W2 is preferably 1000 μm or more. Width W2 is, for example, 10000 μm or less.

[0021] The OPM film OPM1 is disposed on the bonding pad BP1 exposed from the opening OP1. The OPM film OPM1 has, for example, an electroless nickel-plated film OPM1a, an electroless palladium-plated film OPM1b, and an electroless gold-plated film OPM1c.

[0022] The electroless nickel plating film OPM1a is an electroless plating film (a film formed by electroless plating) containing nickel (Ni). The electroless nickel plating film OPM1a is disposed on the bonding pad BP1 exposed from the opening OP1.

[0023] The electroless palladium plating film OPM1b is an electroless plating film containing palladium. The electroless palladium plating film OPM1b is disposed on the electroless nickel plating film OPM1a. The electroless gold plating film OPM1c is an electroless plating film containing gold (Au). The electroless gold plating film OPM1c is disposed on the electroless palladium plating film OPM1b. The OPM film OPM1 does not necessarily have the electroless palladium plating film OPM1b. In this case, the electroless gold plating film OPM1c is disposed on the electroless nickel plating film OPM1a.

[0024] The OPM film OPM2 is disposed on the bonding pad BP2 exposed from the opening OP2. The OPM film OPM2 has the same film configuration as the OPM film OPM1. That is, the OPM film OPM2 has, for example, an electroless nickel-plated film OPM2a, an electroless palladium-plated film OPM2b, and an electroless gold-plated film OPM2c. The electroless nickel-plated film OPM2a is an electroless plated film containing nickel.

[0025] The electroless nickel plating film OPM2a is disposed on the bonding pad BP2 exposed from the opening OP2. The electroless palladium plating film OPM2b is an electroless plating film containing palladium. The electroless palladium plating film OPM2b is disposed on the electroless nickel plating film OPM2a. The electroless gold plating film OPM2c is an electroless plating film containing gold. The electroless gold plating film OPM2c is disposed on the electroless palladium plating film OPM2b. The OPM film OPM2 does not necessarily have the electroless palladium plating film OPM2b. In this case, the electroless gold plating film OPM2c is disposed on the electroless nickel plating film OPM2a.

[0026] The thicknesses of the electroless nickel plating films OPM1a and OPM2a are defined as T1 and T2, respectively. Thicknesses T1 and T2 are, for example, 0.5 times or more the maximum grain size of the crystal grains contained in the wiring WL.

[0027] The semiconductor device DEV1 may further include a bonding wire BW, a clip CL, and a bonding layer JL.

[0028] The bonding wire BW contains a third metal element as a main component. That is, the content of the third metal element in the bonding wire BW is 99 mass percent or more. The third metal element is any one of aluminum, copper, silver (Ag), and gold. One end of the bonding wire BW forms a ball portion. The bonding wire BW is bonded to the OPM film OPM1 at the ball portion. That is, the bonding wire BW is bonded to the bonding pad BP1 via the OPM film OPM1.

[0029] The clip CL is made of, for example, copper or a copper alloy. The clip CL is joined to the bonding pad BP2 by a joining layer JL. The joining layer JL is made of, for example, a solder alloy such as a tin (Sn) alloy. Although not shown, the bonding pad BP1 is electrically connected to a lead frame or the like via a bonding wire BW, and the bonding pad BP2 is electrically connected to a lead frame or the like via the clip CL and the joining layer JL.

[0030] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0031] Fig. 2 is a process diagram showing a method for manufacturing the semiconductor device DEV1. As shown in Fig. 2, the method for manufacturing the semiconductor device DEV1 includes a sputtering step S1, a wiring patterning step S2, a protective film forming step S3, an OPM film forming step S4, and a packaging step S5.

[0032] Prior to the sputtering step S1, the interlayer insulating film ILD and the underlying structure are formed. The interlayer insulating film ILD and the underlying structure are formed by a conventionally known method, and therefore, a description thereof will be omitted here.

[0033] 3 is a cross-sectional view illustrating the sputtering step S1. As shown in FIG. 3, in the sputtering step S1, a material for forming the wiring WL is deposited on the interlayer insulating film ILD. The sputtering gas used in this sputtering contains, for example, argon (Ar) gas and oxygen gas (O2). When nitrogen is introduced as an impurity into the wiring WL, nitrogen gas (N2) is used instead of oxygen gas, and when carbon is introduced as an impurity into the wiring WL, a gas containing carbon (carbon monoxide (CO), methane (CH4), etc.) is used instead of oxygen gas. The content of oxygen gas in the sputtering gas is preferably 0.025 volume percent or more and 0.25 volume percent or less.

[0034] FIG. 4 is a cross-sectional view illustrating the wiring patterning step S2. In the wiring patterning step S2, as shown in FIG. 4, the constituent material of the wiring WL formed in the sputtering step S1 is patterned. In the wiring patterning step S2, first, a resist pattern is formed on the constituent material of the wiring WL formed in the film. This resist pattern is formed by exposing and developing a photoresist. Second, using this resist pattern as a mask, the constituent material of the wiring WL formed in the film is dry-etched. This results in the formation of the wiring WL having bonding pads BP1 and BP2.

[0035] 5 is a cross-sectional view illustrating the protective film forming step S3. As shown in FIG. 5, in the protective film forming step S3, a constituent material of the protective film PV is applied onto the interlayer insulating film ILD so as to cover the wiring WL. Second, the applied constituent material of the protective film PV is exposed and developed to form openings OP1 and OP2. Third, the applied constituent material of the protective film PV is hardened by heating, thereby forming the protective film PV.

[0036] 6 is a cross-sectional view illustrating the OPM film forming step S4. As shown in FIG. 6, in the OPM film forming step S4, OPM films OPM1 and OPM2 are formed on the bonding pads BP1 exposed from the openings OP1 and on the bonding pads BP2 exposed from the openings OP2. The OPM films OPM1 and OPM2 are formed by, for example, electroless plating.

[0037] In the packaging process S5, the lead frame or the like is connected to the OPM film OPM1 by bonding wires BW, and the lead frame or the like is connected to the OPM film OPM2 by clips CL, thereby forming the semiconductor device DEV1 having the structure shown in FIG.

[0038] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below in comparison with a semiconductor device according to a comparative example, which will be referred to as a semiconductor device DEV2.

[0039] 7 is a cross-sectional view of the semiconductor device DEV2. As shown in FIG. 7, the semiconductor device DEV2 has an interlayer insulating film ILD, a wiring WL, a protective film PV, and OPM films OPM1 and OPM2. In the semiconductor device DEV2, the wiring WL has bonding pads BP1 and BP2. In the semiconductor device DEV2, the oxygen concentration at the grain boundaries of the wiring WL is approximately the same as the oxygen concentration within the crystal grains of the wiring WL. Furthermore, in the semiconductor device DEV2, the maximum grain size of the crystal grains contained in the wiring WL is 5 μm or more (approximately 17 μm).

[0040] Electroless nickel plating films are difficult to grow on certain crystal planes of aluminum. Because the wiring WL is polycrystalline, such specific crystal planes may exist on the surfaces of bonding pads BP1 and BP2. Even if such specific crystal planes exist on the surfaces of bonding pads BP1 and BP2, if thicknesses T1 and T2 are set to 0.5 times or more the maximum grain size of the crystal grains contained in the wiring WL, the electroless nickel plating films OPM1a and OPM2a will grow laterally, thereby covering the specific crystal planes.

[0041] In the semiconductor device DEV2, for example, heating performed in the protective film forming step S3 coarsens the crystal grains contained in the wiring WL, and the maximum grain size of the crystal grains contained in the wiring WL is approximately 17 μm. Therefore, unless thicknesses T1 and T2 are made considerably thicker, chips will occur in the electroless nickel plating films OPM1a and OPM2a, and these chips will cause chips in the OPM films OPM1 and OPM2. A bonding wire BW is bonded to the bonding pad BP1 via the OPM film OPM1, but a chip in the OPM film OPM1 may cause the bonding wire BW to peel off from the OPM film OPM1. Thus, in the semiconductor device DEV2, there is room for improvement in the reliability of the bond between the bonding wire BW and the bonding pad BP1.

[0042] In the semiconductor device DEV2, by increasing thicknesses T1 and T2, it is possible to cover specific crystal planes on which the electroless nickel-plated films OPM1a and OPM2a are difficult to grow with the electroless nickel-plated films OPM1a and OPM2a. However, in this case, stress associated with the formation of the electroless nickel-plated films OPM1a and OPM2a increases, which may cause warping of the semiconductor device DEV2. Furthermore, in this case, the manufacturing costs associated with the formation of the electroless nickel-plated films OPM1a and OPM2a increase.

[0043] In the semiconductor device DEV1, a small amount of oxygen gas is added to the sputtering gas in the sputtering process S1. As a result, the grain boundaries of the wiring WL are slightly oxidized, and the oxygen concentration at the grain boundaries of the wiring WL is higher than the oxygen concentration within the crystal grains of the wiring WL. As a result, even when the semiconductor device DEV1 is heated in the protective film formation process S3, the oxidized grain boundaries suppress interdiffusion, so that the crystal grains contained in the wiring WL are less likely to coarsen, and the maximum grain size of the crystal grains contained in the wiring WL is less than 5 μm.

[0044] Samples 1 and 2 were prepared to confirm that the coarsening of the grains in the wiring WL can be suppressed by increasing the oxygen concentration at the grain boundaries of the wiring WL compared to the oxygen concentration within the grains of the wiring WL. In Samples 1 and 2, aluminum was sputtered to form the wiring WL. As shown in Table 1, the oxygen gas content in the sputtering gas in Sample 1 was 0.05 volume percent. On the other hand, in Sample 2, the sputtering gas contained only argon and no oxygen gas. After aluminum sputtering, Samples 1 and 2 were annealed at 400°C for 30 minutes.

[0045] [Table 1]

[0046] In Sample 1, the oxygen concentration at the grain boundaries of the sputtered aluminum was higher than the oxygen concentration within the grains of the sputtered aluminum, whereas in Sample 2, the oxygen concentration at the grain boundaries of the sputtered aluminum was lower than the oxygen concentration within the grains of the sputtered aluminum.

[0047] In Sample 1, the maximum grain size of the crystal grains contained in the aluminum film formed by sputtering was 3.56 μm. On the other hand, in Sample 2, the maximum grain size of the crystal grains contained in the aluminum film formed by sputtering was 16.84 μm. This comparison confirms that the oxygen concentration at the grain boundaries of the wiring WL is higher than the oxygen concentration within the crystal grains of the wiring WL, thereby suppressing the coarsening of the crystal grains contained in the wiring WL. In addition, as a result of suppressing the coarsening of the crystal grains in Sample 1, the hardness of the aluminum film formed by sputtering is higher than that of Sample 2.

[0048] In the semiconductor device DEV1, the maximum grain size of the crystal grains contained in the wiring WL is less than 5 μm, so that it is possible to prevent chipping from occurring in the electroless nickel plating film OPM1a (OPM film OPM1) and the electroless nickel plating film OPM2a (OPM film OPM2) without increasing the thicknesses T1 and T2, and thus improve the reliability of the bond between the bonding wire BW and the bonding pad BP1. Note that even when the impurities contained in the wiring WL are nitrogen or carbon, the nitrogen or carbon present in the grain boundaries of the wiring WL suppresses coarsening of the crystal grains contained in the wiring WL, and thus it is possible to similarly improve the reliability of the bond between the bonding wire BW and the bonding pad BP1.

[0049] When the width W1 is small (more specifically, when the width W1 is 300 μm or less), the bonding area between the bonding wire BW and the OPM film OPM1 is small, and chips in the OPM film OPM1 are more likely to affect the bonding reliability. With the semiconductor device DEV1, even when the width W1 is 300 μm or less, it is possible to improve the bonding reliability between the bonding wire BW and the bonding pad BP1.

[0050] (Second embodiment) A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is referred to as semiconductor device DEV3. Here, differences from semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0051] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0052] 8 is a cross-sectional view of the semiconductor device DEV3. As shown in FIG. 8, the semiconductor device DEV3 has an interlayer insulating film ILD, a wiring WL, a protective film PV, and a bonding wire BW. In the semiconductor device DEV3, the wiring WL has a bonding pad BP1. In the semiconductor device DEV3, an opening OP1 is formed in the protective film PV. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV1.

[0053] In the semiconductor device DEV3, the OPM film OPM1 is not formed on the bonding pad BP1 exposed from the opening OP1. In the semiconductor device DEV3, the bonding wire BW is directly bonded to the bonding pad BP1. In these respects, the configuration of the semiconductor device DEV3 differs from the configuration of the semiconductor device DEV1. The semiconductor device DEV3 is, for example, an LSI (Large Scale Integrated circuit).

[0054] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below in comparison with a semiconductor device according to a comparative example, which will be referred to as a semiconductor device DEV4.

[0055] 9 is a cross-sectional view of the semiconductor device DEV4. As shown in FIG. 9, the semiconductor device DEV4 has an interlayer insulating film ILD, a wiring WL, a protective film PV, and a bonding wire BW. In the semiconductor device DEV4, the wiring WL has a bonding pad BP1. In the semiconductor device DEV4, an opening OP1 is formed in the protective film PV. In the semiconductor device DEV4, the OPM film OPM1 is not formed on the bonding pad BP1 exposed from the opening OP1. In the semiconductor device DEV4, the bonding wire BW is directly bonded to the bonding pad BP1.

[0056] However, in the semiconductor device DEV4, the impurity concentration at the grain boundaries of the wiring WL is not higher than the impurity concentration within the crystal grains of the wiring WL. As a result, in the semiconductor device DEV4, the maximum grain size of the crystal grains contained in the wiring WL is 5 μm or more, and the hardness of the wiring WL is low. Therefore, in the semiconductor device DEV4, the wiring WL deforms during wire bonding, reducing the thickness of the bonding pad BP1 directly below the bonding wire BW, making it prone to cracks in the bonding pad BP1. Such cracks can reduce the reliability of the bond between the bonding pad BP1 and the bonding wire BW.

[0057] On the other hand, in the semiconductor device DEV3, the maximum grain size of the crystal grains contained in the wiring WL is less than 5 μm, and the wiring WL is hard. Therefore, in the semiconductor device DEV3, by suppressing deformation of the wiring WL due to wire bonding, it is possible to suppress a reduction in the thickness of the bonding pad BP1 directly below the bonding wire BW, and ultimately to suppress the occurrence of cracks in the bonding pad BP1. Therefore, the semiconductor device DEV3 can improve the bonding reliability between the bonding wire BW and the bonding pad BP1.

[0058] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0059] BP1, BP2 bonding pads, BW bonding wire, CL clip, DEV1, DEV2, DEV3, DEV4 semiconductor device, ILD interlayer insulating film, JL bonding layer, OP1, OP2 opening, OPM1 OPM film, OPM1a electroless nickel plating film, OPM1b electroless palladium plating film, OPM1c electroless gold plating film, OPM2 OPM film, OPM2a electroless nickel plating film, OPM2b electroless palladium plating film, OPM2c electroless gold plating film, PV protective film, S1 sputtering process, S2 wiring patterning process, S3 protective film formation process, S4 formation process, S5 packaging process, T1, T2 thickness, W1, W2 width, WL, WL2 wiring.

Claims

1. a first metal film constituting a top layer wiring having a bonding pad; a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; The first metal film is Aluminum and At least one of copper, silicon, and palladium; Including, The semiconductor device, wherein the content of aluminum in the first metal film is 99 mass percent or more.

2. A semiconductor device comprising a first metal film constituting a top layer wiring having a bonding pad, a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; The impurity is at least one of oxygen, nitrogen, and carbon.

3. A semiconductor device comprising a first metal film constituting a top layer wiring having a bonding pad, a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; the impurity is oxygen, the concentration of oxygen in the crystal grains of the first metal film is 0.6 atomic percent or more and 0.8 atomic percent or less; The semiconductor device, wherein the concentration of oxygen at the grain boundaries of the first metal film is 0.9 atomic percent or more and 1.5 atomic percent or less.

4. A semiconductor device comprising a first metal film constituting a top layer wiring having a bonding pad, a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; The semiconductor device further comprises a second metal film disposed on the bonding pad.

5. The semiconductor device according to claim 4 , wherein the second metal film is an electroless plated film.

6. the second metal film has a first film disposed on the bonding pad; 6. The semiconductor device according to claim 5, wherein the first film is an electroless nickel plating film.

7. the second metal film further includes a second film disposed on the first film; 7. The semiconductor device according to claim 6, wherein the second film is an electroless gold plating film.

8. the second metal film further includes a second film disposed on the first film and a third film disposed on the second film; the second film is an electroless palladium plating film, 7. The semiconductor device according to claim 6, wherein the third film is an electroless gold plating film.

9. Further comprising a bonding wire; 7. The semiconductor device according to claim 6, wherein said bonding wire is bonded to said second metal film.

10. the bonding wire contains a third metal element; The content of the third metal element in the bonding wire is 99 mass percent or more, 10. The semiconductor device according to claim 9, wherein the third metal element is any one of aluminum, copper, silver, and gold.

11. Further comprising a bonding wire; 2. The semiconductor device according to claim 1, wherein said bonding wire is bonded to said bonding pad.

12. A semiconductor device comprising a first metal film constituting a top layer wiring having a bonding pad, a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; The hardness of the first metal film is 0.8 GPa or more.

13. A semiconductor device comprising a first metal film constituting a top layer wiring having a bonding pad, a concentration of impurities at the grain boundaries of the first metal film is higher than a concentration of the impurities within the grains of the first metal film; the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm; a protective film covering the first metal film; an opening for exposing the bonding pad is formed in the protective film; The semiconductor device, wherein the width of the opening is 300 μm or less.

14. forming a first metal film by sputtering; and forming a top layer wiring having a bonding pad by patterning the first metal film, A method for manufacturing a semiconductor device, wherein, when the sputtering is performed, oxygen gas is added to the sputtering gas so that the impurity concentration at the grain boundaries of the first metal film is higher than the impurity concentration within the crystal grains in the first metal film, and the maximum grain size of the crystal grains contained in the first metal film is less than 5 μm.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the content of said oxygen gas in said sputtering gas is not less than 0.025 volume percent and not more than 0.25 volume percent.

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