Semiconductor package assembly and manufacturing method

Abstract

In an embodiment of the present disclosure, a semiconductor package assembly and manufacturing method are disclosed, the semiconductor package assembly including: a substrate having a first surface; a first chip structure located on the substrate and electrically connected to the first surface of the substrate; an intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, a first solder ball formed on the first interconnect region and a first pad formed on the second interconnect region, the intermediate layer being electrically connected to the first surface of the substrate via the first pad; and a molding material for encapsulating the first chip structure, the intermediate layer, and the first surface of the substrate, the first solder ball having a surface exposed to the molding material and a predetermined height between the exposed surface of the first solder ball and the first interconnect surface of the intermediate layer.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on July 8, 2022, bearing application number 202210806540.3 and entitled "Semiconductor Package Assembly and Manufacturing Method," the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to the field of semiconductor technology, and more particularly to semiconductor package assemblies and manufacturing methods. [Background technology]

[0003] Across all sectors, industries, and regions, the electronics industry is continually demanding lighter, faster, smaller, more feature-rich, more reliable, and more cost-effective products. To meet these increasing demands from many different consumers, more circuitry must be integrated to provide the required functionality. In almost every application, there is an increasing need for smaller size, higher performance, and increased functionality of integrated circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, embodiments of the present disclosure provide a semiconductor package assembly and manufacturing method. [Means for solving the problem]

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor package assembly, the semiconductor package assembly comprising: a substrate having a first surface; a first chip structure located on the substrate and electrically connected to a first side of the substrate; an intermediate layer having a first interconnection surface, the first interconnection surface having a first interconnection region and a second interconnection region, a first solder ball formed on the first interconnection region, and a first pad formed on the second interconnection region, the intermediate layer being electrically connected to a first surface of the substrate via the first pad; and a molding material for encapsulating the first chip structure, the intermediate layer, and the first surface of the substrate, wherein the first solder ball has a surface exposed to the molding material and has a predetermined height between the exposed surface of the first solder ball and the first interconnection surface of the intermediate layer.

[0006] In some embodiments, the first chip structure includes a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the substrate; The intermediate layer is located on the first chip structure.

[0007] In some embodiments, the semiconductor package assembly further comprises: a first conductive line, wherein each of the first semiconductor chips is electrically connected to the substrate via the first conductive line; a second conductive line, the second interconnect region electrically connected to the substrate through the second conductive line.

[0008] In some embodiments, a plurality of second pads are formed on the first interconnect region, wherein the number of the first pads is greater than the number of the second pads and the area of ​​the first pads is smaller than the area of ​​the second pads.

[0009] In some embodiments, the first chip structure includes a plurality of first semiconductor chips arranged sequentially along a direction parallel to the substrate; The first chip structure is located on the intermediate layer.

[0010] In some embodiments, the semiconductor package assembly further comprises: a first conductive block located between the first semiconductor chips and the intermediate layer, wherein each of the first semiconductor chips is electrically connected to the substrate via the first conductive block; and a second conductive block located between the intermediate layer and the substrate, the intermediate layer being electrically connected to the substrate via the second conductive block.

[0011] In some embodiments, the semiconductor package assembly further comprises: A second package structure including second solder balls is included, and the second package structure is electrically connected to the first solder balls via the second solder balls.

[0012] In some embodiments, the volume of the first solder ball is greater than the volume of the second solder ball.

[0013] In some embodiments, the molding material has a first thickness in a direction perpendicular to the substrate; The second package structure includes a second molding material, and in a direction perpendicular to the substrate, the second molding material has a second thickness, where the first thickness is equal to or greater than the second thickness.

[0014] According to a second aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor package assembly, the method comprising: providing a substrate having a first surface; forming a first chip structure on the substrate, the first chip structure electrically connected to a first side of the substrate; forming an intermediate layer having a first interconnection surface, the first interconnection surface having a first interconnection region and a second interconnection region, a first solder ball formed on the first interconnection region, and a first pad formed on the second interconnection region, the intermediate layer being electrically connected to a first surface of the substrate via the first pad; forming a molding material to encapsulate the first chip structure, the intermediate layer, and the first surface of the substrate, wherein the first solder ball has a surface exposed to the molding material and has a predetermined height between the exposed surface of the first solder ball and the first interconnection surface of the intermediate layer.

[0015] In some embodiments, forming the molding material comprises: forming a first package mold, a surface of the first package mold being parallel to a surface of the substrate, the first package mold being positioned above the first chip structure and the intermediate layer and being spaced a certain distance from the first chip structure and the intermediate layer; forming a molding material pre-layer using the first package mold as a mask; and removing a portion of the molding material pre-layer to form a molding material and expose a surface of the first solder ball.

[0016] In some embodiments, forming the first chip structure includes forming a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the substrate; forming an intermediate layer on the first chip structure.

[0017] In some embodiments, the method for manufacturing the semiconductor package assembly includes: After forming the intermediate layer, forming first conductive lines, wherein each of the first semiconductor chips is electrically connected to the substrate via the first conductive lines; Further comprising forming a second conductive line, the second interconnect region being electrically connected to the substrate via the second conductive line.

[0018] In some embodiments, the method for manufacturing the semiconductor package assembly includes: The method further includes forming a plurality of second pads on the first interconnect region, wherein the number of the first pads is greater than the number of the second pads, and the area of ​​the first pads is smaller than the area of ​​the second pads.

[0019] In some embodiments, the first chip structure is formed on the intermediate layer; Forming the first chip structure includes forming a plurality of first semiconductor chips arranged sequentially along a direction parallel to the substrate.

[0020] In some embodiments, the method for manufacturing the semiconductor package assembly includes: forming a substrate, then forming a second conductive block on the substrate, and forming an intermediate layer on the second conductive block, wherein the intermediate layer is electrically connected to the substrate via the second conductive block; The method further includes, after forming the intermediate layer, forming a first conductive block on the intermediate layer and forming a first chip structure on the first conductive block, wherein each of the first semiconductor chips is electrically connected to the substrate via the first conductive block.

[0021] In some embodiments, the method for manufacturing the semiconductor package assembly includes: The method further includes forming a second package structure including second solder balls, the second package structure being electrically connected to the first solder balls via the second solder balls.

[0022] In some embodiments, the volume of the first solder ball is greater than the volume of the second solder ball.

[0023] In some embodiments, the molding material has a first thickness in a direction perpendicular to the substrate; The second package structure includes a second molding material, and in a direction perpendicular to the substrate, the second molding material has a second thickness, where the first thickness is equal to or greater than the second thickness.

[0024] In the embodiment of the present disclosure, by providing an intermediate layer, the subsequent second package structure can be connected to the first chip structure and the substrate through the first solder balls on the intermediate layer, thereby realizing interconnections between structures of different types or specifications, thereby increasing the flexibility of combinations between different structures. At the same time, since the first chip structure and the second package structure are packaged independently, testing and failure analysis are also easier. In addition, since there is a predetermined height between the top surface of the first solder balls and the first interconnection surface, the entire package structure can have a relatively thin overall thickness, thereby achieving good bonding strength with the subsequent second package structure. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic structural diagram of a semiconductor package assembly according to an embodiment of the present disclosure; [Figure 2] 1 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure; [Figure 3] FIG. 2 is a schematic structural diagram of a semiconductor package assembly according to another embodiment of the present disclosure. [Figure 4] 1 is a flowchart of a method for manufacturing a semiconductor package assembly according to an embodiment of the present disclosure. [Figure 5a] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5b] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5c] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5d] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5e] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5f]1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5g] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 5h] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to an embodiment of the present disclosure. [Figure 6a] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. [Figure 6b] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. [Figure 6c] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. [Figure 6d] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. [Figure 6e] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. [Figure 6f] 1A-1C are schematic diagrams of device structures of a semiconductor package assembly during manufacturing according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] In order to more clearly describe the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

[0027]

[0023] Exemplary embodiments disclosed by the present disclosure will now be described in more detail with reference to the drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments described herein. Rather, these embodiments are provided so that the present disclosure may be more fully understood and the scope of the present disclosure may be fully conveyed to those skilled in the art.

[0028] In the following description, many specific details are set forth to provide a more complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features that are well known in the art are not described, that is, not all features of the actual embodiments are described herein, and well-known functions and configurations are not described in detail.

[0029] In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

[0030] When an element or layer is referred to as being "on," "adjacent to," or "connected to" or "coupled to" another element or layer, it is understood that it may be directly on, adjacent to, or directly connected to or coupled to the other element or layer, or that intervening elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on," "directly adjacent to," or "directly connected to," or "directly coupled to," there are no intervening elements or layers. While terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or sections, it is understood that these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the present disclosure. However, the description of a second element, component, region, layer, or section does not imply that the first element, component, region, layer, or section is necessarily present in the present disclosure.

[0031] Spatial relationship terms such as "below," "bottom of," "below," "under," "above," "above," and the like may be used herein for convenience of description to describe one element or feature in relation to other elements or features shown in the figures. It should be understood that the spatial relationship terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown. For example, if the device in the figures is turned over, then an orientation of an element or feature described as "below" or "beneath" or "below" other elements or features would now be "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise), and the spatial descriptions used herein interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "one," and "said" are intended to include the plural forms unless the context clearly dictates otherwise. Also, the terms "comprising" and / or "comprising," when used herein, determine the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] In order to fully understand the present disclosure, detailed steps and detailed structures are presented in the following description to describe the technical solutions of the present disclosure. Although the preferred embodiments of the present disclosure are described in detail below, the present disclosure can have other embodiments in addition to these detailed descriptions.

[0034] On this basis, an embodiment of the present disclosure provides a semiconductor package assembly. Figure 1 is a schematic structural diagram of a semiconductor package assembly according to an embodiment of the present disclosure.

[0035] Referring to FIG. 1, the semiconductor package assembly includes: a substrate 10 having a first surface 101; a first chip structure 20 located on the substrate 10 and electrically connected to a first surface 101 of the substrate 10; an intermediate layer (30) having a first interconnection surface (301), the first interconnection surface (301) having a first interconnection region (31) and a second interconnection region (32), first solder balls (312) formed on the first interconnection region (31) and first pads (321) formed on the second interconnection region (32), the intermediate layer (30) being electrically connected to a first surface (101) of the substrate via the first pads (321); and a molding material 40 for encapsulating the first chip structure 20, the intermediate layer 30, and the first surface 101 of the substrate 10, wherein the first solder ball 312 has a surface exposed to the molding material 40 and has a predetermined height h between the exposed surface of the first solder ball 312 and the first interconnection surface 301 of the intermediate layer 30.

[0036] In an embodiment of the present disclosure, the intermediate layer can be provided to allow the subsequent second package structure to be connected to the first chip structure and the substrate via the first solder balls on the intermediate layer. In an embodiment of the present disclosure, the intermediate layer can be a non-organic material such as a silicon intermediate layer, or a structure containing any one or more organic materials. The intermediate layer can realize interconnections between structures of different types or specifications, thereby providing greater flexibility in combining different structures. At the same time, the first chip structure and the second package structure are packaged independently, making testing and failure analysis easier.

[0037] In one embodiment of the present disclosure, there is a predetermined height h between the top surface of the first solder ball and the first interconnection surface, and the predetermined height h is at least 1 / 5 to 1 / 2 of the thickness of the intermediate layer. In some embodiments, when the thickness of the intermediate layer is 100 to 200 μm, the predetermined height h is 50 to 120 μm. This setting can effectively suppress stress problems caused by mismatches in thermal expansion coefficients between the molding material and the intermediate layer, and can also have good bonding strength with the subsequent second package structure by ensuring that the entire package structure has a relatively thin overall thickness.

[0038] FIG. 2 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure.

[0039] In some embodiments, the substrate 10 may be a printed circuit board (PCB) or a redistribution board.

[0040] Referring to FIG. 2, the substrate 10 includes a substrate base 11, and an upper substrate insulating dielectric layer 12 and a lower substrate insulating dielectric layer 13 disposed on the upper and lower surfaces of the substrate base 11, respectively.

[0041] The substrate base 11 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other element semiconductors or compound semiconductors such as a glass base or a III-V compound base (such as a gallium nitride base or a gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be another epitaxial structure such as a SiGe on insulator (SGOI).

[0042] The upper and lower insulating dielectric layers 12 and 13 can be solder masks, for example, the material of the upper and lower insulating dielectric layers 12 and 13 can be green paint.

[0043] In the embodiment of the present disclosure, the first surface 101 of the substrate 10 is the upper surface of the substrate upper insulating dielectric layer 12. The substrate 10 further includes a second surface 102 spaced apart from the first surface 101, and the second surface 102 is the lower surface of the substrate lower insulating dielectric layer 13.

[0044] The substrate 10 further includes upper substrate connection pads 14 located within the upper substrate insulating dielectric layer 12, lower substrate connection pads 15 located within the lower substrate insulating dielectric layer 13, and substrate connection vias 16 that penetrate the substrate base 11 and interconnect the upper substrate connection pads 14 and the lower substrate connection pads 15.

[0045] The material of the substrate upper connection pads 14 and the substrate lower connection pads 15 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold. The substrate connection vias 16 may be through-silicon vias (TSVs).

[0046] The substrate 10 further includes substrate connection bumps 17, which are located on a second surface 102 of the substrate 10. The substrate connection bumps 17 can electrically connect the semiconductor package assembly to an external device, and can receive at least one of a control signal, a power signal, and a ground signal for operating the first chip structure from the external device, or a data signal stored in the first chip structure from the external device, and can also provide data in the first chip structure to the external device.

[0047] The substrate connection bumps 17 include a conductive material. In the embodiment of the present disclosure, the substrate connection bumps 17 are solder balls. The shapes of the substrate connection bumps provided in the embodiment of the present disclosure are merely specific embodiments that can be implemented at a low level in the embodiment of the present disclosure and are not intended to limit the present disclosure. It is understood that the substrate connection bumps can have other shapes and structures. The number, spacing, and positions of the substrate connection bumps are not limited to a specific arrangement and can be variously modified.

[0048] 2, the substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the substrate 10. The first signal transmission region 110 is electrically connected to the first chip structure 20, and the second signal transmission region 120 is electrically connected to the intermediate layer 30.

[0049] The substrate 10 further includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and the first chip structure 20 is located on the third signal transmission region 130.

[0050] In the embodiment of the present disclosure, there are two situations regarding the positional relationship between the first chip structure and the intermediate layer: one is when the intermediate layer 30 is located above the first chip structure 20, as shown in FIG. 1; and the other is when the first chip structure 20 is located above the intermediate layer 30, as shown in FIG. 3.

[0051] In the embodiment shown in FIG. 1, the first chip structure 20 includes a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the substrate 10, and the intermediate layer 30 is located on the first chip structure 20.

[0052] In this embodiment, by stacking a plurality of first semiconductor chips one above the other, the horizontal area of ​​the semiconductor package assembly can be saved.

[0053] The first semiconductor chip may be a DRAM chip or other type of semiconductor chip.

[0054] With continued reference to FIG. 1 , the semiconductor package assembly further comprises: a first conductive line 51, each of the first semiconductor chips 21 being electrically connected to the substrate 10 via the first conductive line 51; and a second conductive line 52, wherein the second interconnect region 32 is electrically connected to the substrate 10 via the second conductive line 52.

[0055] Specifically, the first semiconductor chip 21 has a first connection end 211, which is located on the same side as the first signal transmission region 110, and a first conductive line 51 is drawn from the first connection end 211 to the first transmission region 110 to realize an electrical connection between the first semiconductor chip 21 and the substrate 10.

[0056] A first pad 321 is formed on the second interconnection region 32, and a second conductive line 52 is drawn from the first pad 321 to the second transmission region 120 to realize an electrical connection between the intermediate layer 30 and the substrate 10.

[0057] In the embodiment of the present disclosure, the electrical connection between the first chip structure and the substrate by wire bonding includes an overhang method and a film on wire (FOW) method.

[0058] 1, wire bonding is performed using an overhang method. Two adjacent first semiconductor chips 21 are connected by an adhesive film 60, and the adhesive film 60 does not cover the first connecting end 211 and the first conductive line 51 on the first semiconductor chip 21 below it, and the adhesive film 60 is arranged in a staggered manner with respect to the first semiconductor chip 21 below it.

[0059] In some other embodiments, wire bonding (not shown) is performed using a film-on-wire method, where a plurality of the first semiconductor chips are aligned along a direction perpendicular to the substrate, and an adhesive film between two adjacent first semiconductor chips covers the first connection ends and the first conductive lines on the underlying first semiconductor chip.

[0060] It will be appreciated that performing electrical connection using lead wires in the embodiments of the present disclosure is merely a specific embodiment that can be performed at a low level in the embodiments of the present disclosure and is not intended to limit the present disclosure, and that other electrical connection methods, such as hybrid bonding or bump interconnection, can also be used.

[0061] Continuing to refer to FIG. 1, the intermediate layer 30 includes an intermediate base 33, an intermediate upper insulating dielectric layer 34, and an intermediate lower insulating dielectric layer 35 disposed on the upper and lower surfaces of the intermediate base 33, respectively.

[0062] The intermediate base 33 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other element semiconductors or compound semiconductors such as a glass base or a III-V compound base (such as a gallium nitride base or a gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as a SiGe on insulator (SGOI).

[0063] The intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be solder mask, for example, the material of the intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be green paint.

[0064] A plurality of second pads 311 are formed on the first interconnection region 31 of the intermediate layer 30, wherein the number of the first pads 321 is greater than the number of the second pads 311, and the area of ​​the first pads 321 is smaller than the area of ​​the second pads 311.

[0065] The second pads need to be matched to the second package structure and interconnected later, so the layout design is relatively fixed. The first pads carry the interconnection between the second package structure and the substrate, so the layout design is more flexible. By increasing the number of first pads and designing them to have a smaller area, the signal transmission efficiency can be improved.

[0066] The material of the first pad 321 and the second pad 311 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

[0067] In the embodiment shown in Figure 3, the first chip structure 20 includes a plurality of first semiconductor chips 21 arranged sequentially along a direction parallel to the substrate 10, and the first chip structure 20 is located on the intermediate layer 30.

[0068] In this embodiment, the package height of the semiconductor package assembly can be reduced by sequentially arranging a plurality of first semiconductor chips in the horizontal direction.

[0069] Continuing to refer to Figure 3, the semiconductor package assembly further includes a first conductive block 201 located between the first semiconductor chip 21 and the intermediate layer 30, where each of the first semiconductor chips 21 is electrically connected to the substrate 10 via the first conductive block 201, and a second conductive block 322 located between the intermediate layer 30 and the substrate 10, where the intermediate layer 30 is electrically connected to the substrate 10 via the second conductive block 322.

[0070] In this embodiment, the first semiconductor chip is interconnected with the intermediate layer via the first conductive block, and the intermediate layer is interconnected with the substrate, so that the first semiconductor chip is connected to the substrate via the first conductive block and the intermediate layer.

[0071] In one embodiment, the area of ​​the first pad 321 is greater than the area of ​​the second pad 311 .

[0072] In the embodiment shown in FIG. 3, since the intermediate layer is directly interconnected with the substrate, the second interconnection region does not primarily communicate between other package structures and the substrate, and therefore the first pad can use a large area of ​​metal to increase the heat dissipation area and improve heat dissipation efficiency.

[0073] In one embodiment, referring to FIG. 1 , the semiconductor package assembly further includes a second package structure 70, which includes second solder balls 71, and the second package structure 70 is electrically connected to the first solder balls 312 via the second solder balls 71.

[0074] In one embodiment, the volume of the first solder ball 312 is larger than the volume of the second solder ball 71. With this configuration, the first solder ball 312 and the second solder ball 71 prevent lateral flow of solder during a subsequent reflow soldering process, reducing the risk of short circuits between adjacent solder balls and improving the bonding strength between the first solder ball and the second solder ball.

[0075] The molding material 40 has a first thickness in a direction perpendicular to the substrate 10, and the second package structure 70 includes a second molding material 73, which has a second thickness in a direction perpendicular to the substrate 10, where the first thickness is equal to or greater than the second thickness. The relatively large thickness of the molding material 40 can fully support the second package structure and prevent the first package structure from warping toward the second package structure.

[0076] The second package structure 70 further includes a second substrate 72, the structure of which may be the same as or different from that of the substrate 10, and will not be described again here.

[0077] The second package structure includes a second chip structure (not shown), which may be a universal flash memory chip (UFS: Universal File Store).

[0078] The semiconductor package assembly provided by the embodiments of the present disclosure can be applied to a multi-chip package (UFS Multi Chip Package: UMCP) with a package-on-package (PoP) structure.

[0079] In the embodiment of the present disclosure, the upper surface of the molding material is flush with the upper surface of the first solder ball, so when forming the molding material, there is no need to use a specially shaped package mold, and a normal package mold can be used for packaging. The specially shaped package mold has high manufacturing costs and more complicated processes. Therefore, the semiconductor package assembly provided by the embodiment of the present disclosure can reduce costs and at the same time simplify the forming process.

[0080] An embodiment of the present disclosure provides a method for manufacturing a semiconductor package assembly, and details can be seen in FIG. 4. As shown in the figure, the method includes the following steps:

[0081] In step 401, a substrate having a first side is provided.

[0082] In step 402, a first chip structure is formed on the substrate, and the first chip structure is electrically connected to a first side of the substrate.

[0083] In step 403, an intermediate layer having a first interconnection surface is formed, the first interconnection surface having a first interconnection region and a second interconnection region, a first solder ball is formed on the first interconnection region, and a first pad is formed on the second interconnection region, and the intermediate layer is electrically connected to a first surface of the substrate via the first pad.

[0084] In step 404, a molding material is formed to encapsulate the first chip structure, the intermediate layer, and the first surface of the substrate, wherein the first solder ball has a surface exposed to the molding material and has a predetermined height between the exposed surface of the first solder ball and the first interconnection surface of the intermediate layer.

[0085] The manufacturing method of a semiconductor package assembly provided by the embodiments of the present disclosure will be described in more detail below with reference to specific embodiments.

[0086] 5a to 5h are schematic diagrams of a device structure of a semiconductor package assembly in a manufacturing process according to an embodiment of the present disclosure, and FIGS. 6a to 6e are schematic diagrams of a device structure of a semiconductor package assembly in a manufacturing process according to another embodiment of the present disclosure. It should be noted that in the manufacturing method of a semiconductor package assembly shown in FIGS. 5a to 5h, a first chip structure is formed first and then an intermediate layer is formed, whereas in the manufacturing method of a semiconductor package assembly shown in FIGS. 6a to 6e, an intermediate layer is formed first and then the first chip structure is formed.

[0087] First, one embodiment of the method for manufacturing the semiconductor package assembly will be described in detail with reference to FIGS. 5a to 5h.

[0088] First, referring to FIG. 5a, step 401 is carried out, specifically, a substrate 10 having a first surface 101 is provided.

[0089] In some embodiments, the substrate 10 may be a printed circuit board (PCB) or a redistribution board.

[0090] The substrate 10 includes a substrate base 11, and an upper substrate insulating dielectric layer 12 and a lower substrate insulating dielectric layer 13 disposed on the upper and lower surfaces of the substrate base 11, respectively.

[0091] The substrate base 11 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other element semiconductors or compound semiconductors such as a glass base or a III-V compound base (such as a gallium nitride base or a gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be another epitaxial structure such as a SiGe on insulator (SGOI).

[0092] The upper and lower insulating dielectric layers 12 and 13 can be solder masks, for example, the material of the upper and lower insulating dielectric layers 12 and 13 can be green paint.

[0093] In the embodiment of the present disclosure, the first surface 101 of the substrate 10 is the upper surface of the substrate upper insulating dielectric layer 12. The substrate 10 further includes a second surface 102 spaced apart from the first surface 101, and the second surface 102 is the lower surface of the substrate lower insulating dielectric layer 13.

[0094] The substrate 10 further includes upper substrate connection pads 14 located within the upper substrate insulating dielectric layer 12, lower substrate connection pads 15 located within the lower substrate insulating dielectric layer 13, and substrate connection vias 16 that penetrate the substrate base 11 and interconnect the upper substrate connection pads 14 and the lower substrate connection pads 15.

[0095] The material of the substrate upper connection pads 14 and the substrate lower connection pads 15 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold. The substrate connection vias 16 may be through silicon vias (TSVs).

[0096] The substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the substrate 10. The first signal transmission region 110 is electrically connected to a first chip structure to be formed later, and the second signal transmission region 120 is electrically connected to an intermediate layer 30 to be formed later.

[0097] In some embodiments, first signal transmission region 110 and second signal transmission region 120 are not interconnected.

[0098] The substrate 10 further includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and the first chip structure is located on the third signal transmission region 130.

[0099] In some embodiments, the first signal transmission region 110 and the third signal transmission region 130 are interconnected, and the third signal transmission region 130 and the second signal transmission region 120 are not interconnected.

[0100] Next, referring to FIG. 5b, step 402 is performed, specifically, a first chip structure 20 is formed on the substrate 10, and the first chip structure 20 is electrically connected to the first surface 101 of the substrate 10.

[0101] In one embodiment, forming the first chip structure 20 includes forming a plurality of first semiconductor chips 21 stacked in sequence along a direction perpendicular to the substrate 10. In this embodiment, by stacking the plurality of first semiconductor chips in sequence upward, horizontal area of ​​the semiconductor package assembly can be saved.

[0102] Specifically, first, an adhesive film 60 is formed on the substrate 10, and then the first chip structure 20 is formed on the adhesive film 60. Two adjacent first semiconductor chips 21 are connected by the adhesive film 60.

[0103] Next, referring to Figures 5c to 5d, step 403 is performed, specifically, forming an intermediate layer 30 having a first interconnection surface 301, the first interconnection surface 301 having a first interconnection region 31 and a second interconnection region 32, a first solder ball 312 is formed on the first interconnection region 31, and a first pad 321 is formed on the second interconnection region 32, and the intermediate layer 30 is electrically connected to the first surface 101 of the substrate 10 via the first pad 321.

[0104] Specifically, first, referring to FIG. 5c, a carrier tape 2 is adhered onto a ring 1, then an adhesive film 60 is adhered onto the carrier tape 2, and then an intermediate layer is adhered onto the adhesive film 60, where the intermediate layer is in the shape of a strip, and the intermediate layer is cut to form individual units as shown in FIG. 5c.

[0105] Next, referring to FIG. 5 d , an intermediate layer 30 is formed on the chip stack structure 20 .

[0106] Specifically, the single intermediate layer 30 formed in FIG. 5c is adhered onto the first chip structure 20.

[0107] In one embodiment of the present disclosure, as shown in Fig. 5d, an initial first solder ball 312' is first formed on the first interconnection region 31 of the intermediate layer 30, and then formed as the first solder ball 312 after etching or grinding. The initial first solder ball 312' has an initial height in a direction perpendicular to the intermediate layer 30.

[0108] The intermediate layer 30 includes an intermediate base 33, an intermediate upper insulating dielectric layer 34 and an intermediate lower insulating dielectric layer 35 disposed on the upper and lower surfaces of the intermediate base 33, respectively.

[0109] The intermediate base 33 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other element semiconductors or compound semiconductors such as a glass base or a III-V compound base (such as a gallium nitride base or a gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as a SiGe on insulator (SGOI).

[0110] The intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be solder mask, for example, the material of the intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be green paint.

[0111] Continuing to refer to FIG. 5d, the manufacturing method of the semiconductor package assembly further includes forming a plurality of second pads 311 on the first interconnection region 31, wherein the number of the first pads 321 is greater than the number of the second pads 311, and the area of ​​the first pads 321 is smaller than the area of ​​the second pads 311.

[0112] The second pads need to be matched to the second package structure and interconnected later, so the layout design is relatively fixed. The first pads carry the interconnection between the second package structure and the substrate, so the layout design is more flexible. By increasing the number of first pads and designing them to have a smaller area, the signal transmission efficiency can be improved.

[0113] The material of the first pad 321 and the second pad 311 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

[0114] Continuing to refer to FIG. 5d, the manufacturing method of the semiconductor package assembly further includes forming a first conductive line 51 after forming the intermediate layer 30, wherein each of the first semiconductor chips 21 is electrically connected to the substrate 10 via the first conductive line 51, and forming a second conductive line 52, wherein the second interconnection region 32 is electrically connected to the substrate 10 via the second conductive line 52.

[0115] Specifically, a first connection end 211 is formed on the first semiconductor chip 21, the first connection end 211 is located on the same side as the first signal transmission region 110, and a first conductive line 51 is drawn from the first connection end 211 to the first transmission region 110 to realize an electrical connection between the first semiconductor chip 21 and the substrate 10.

[0116] A first pad 321 is formed on the second interconnection region 32, and a second conductive line 52 is drawn from the first pad 321 to the second transmission region 120 to realize an electrical connection between the intermediate layer 30 and the substrate 10.

[0117] Next, referring to Figures 5e to 5g, step 404 is performed, including molding material 40 for encapsulating the first chip structure 20, the intermediate layer 30, and the first surface 101 of the substrate 10, wherein the first solder ball 312 has a surface exposed to the molding material 40 and has a predetermined height h between the exposed surface of the first solder ball 312 and the first interconnection surface 301 of the intermediate layer 30.

[0118] Forming the molding material 40 includes: forming a first package mold 91, a surface of the first package mold 91 being parallel to a surface of the substrate 10, the first package mold 91 being positioned above the first chip structure 20 and the intermediate layer 30, and being spaced a certain distance from the first chip structure 20 and the intermediate layer 30; forming a molding material pre-layer 400 using the first package mold 91 as a mask; Etching and removing a portion of the molding material pre-layer 400 to form a molding material 40 and expose the surface of the first solder ball 312.

[0119] Specifically, referring first to FIG. 5e, a first package mold 91 is formed on the first chip structure 20 and the intermediate layer 30, and a second package mold 92 is formed below the substrate 10, where the second package mold 92 is parallel to the surface of the substrate 10.

[0120] Next, referring to FIG. 5f, a molding material pre-layer 400 is formed between the first package mold 91 and the second package mold 92 using the first package mold 91 and the second package mold 92 as a mask.

[0121] The molding material pre-layer 400 completely covers the first surface of the substrate 10 , the first chip structure 20 , the intermediate layer 30 , and the initial first solder balls 312 ′ on the intermediate layer 30 .

[0122] The method for manufacturing the semiconductor package assembly further includes removing the first package mold 91 and the second package mold 92 after forming the molding material pre-layer 400 .

[0123] Next, referring to FIG. 5g, a portion of the molding material pre-layer 400 is removed to form the molding material 40, and the surface of the first solder ball 312 is exposed.

[0124] Specifically, by using a grinding wheel to grind the surface of the molding material, a portion of the molding material pre-layer 400 can be removed, and a portion of the initial first solder ball 312' can be removed to form a first solder ball 312 having a predetermined height h.

[0125] In the embodiment of the present disclosure, since the first solder ball is formed on the first interconnection region, there is no need to expose the first interconnection region, and there is no need to use a package mold with a special shape; only a normal first package mold can be used, and since the first package mold has a simple shape, the manufacturing process is simple and the cost is low.

[0126] Still referring to FIG. 5g, after forming the molding material 40, substrate connection bumps 17 are formed on the second surface 102 of the substrate 10, and the substrate connection bumps 17 include a conductive material.

[0127] Next, referring to FIG. 5h, a second package structure 70 is formed, the second package structure 70 including second solder balls 71, and the second package structure 70 is electrically connected to the first solder balls 312 via the second solder balls 71.

[0128] In one embodiment, the volume of the first solder ball 312 is larger than the volume of the second solder ball 71. With this configuration, the first solder ball 312 and the second solder ball 71 prevent lateral flow of solder during a subsequent reflow soldering process, reducing the risk of short circuits between adjacent solder balls and improving the bonding strength between the first solder ball and the second solder ball.

[0129] The molding material 40 has a first thickness in a direction perpendicular to the substrate 10, and the second package structure 70 includes a second molding material 73, which has a second thickness in a direction perpendicular to the substrate 10, where the first thickness is equal to or greater than the second thickness. The relatively large thickness of the molding material 40 can fully support the second package structure and prevent the first package structure from warping toward the second package structure.

[0130] The second package structure 70 further includes a second substrate 72, the structure of which may be the same as or different from that of the substrate 10, and will not be described again here.

[0131] Next, another embodiment of the method for manufacturing the semiconductor package assembly will be described in detail with reference to FIGS. 6a to 6f.

[0132] It should be noted that the substrates in Figures 6a-6f are similar to those in Figures 5a-5h and will not be described again here.

[0133] First, referring to FIG. 6a, after forming a substrate 10, a second conductive block 322 is formed on the substrate 10, and an intermediate layer 30 is formed on the second conductive block 322, and the intermediate layer 30 is electrically connected to the substrate 10 via the second conductive block 322.

[0134] In one embodiment, the area of ​​the first pad 321 is greater than the area of ​​the second pad 311 .

[0135] In the embodiment shown in FIG. 3, since the intermediate layer is directly interconnected with the substrate, the second interconnection region does not primarily communicate between other package structures and the substrate, and therefore the first pad can use a large area of ​​metal to increase the heat dissipation area and improve heat dissipation efficiency.

[0136] Next, referring to FIG. 6b, a first chip structure 20 is formed on the intermediate layer 30, and forming the first chip structure 20 includes forming a plurality of first semiconductor chips 21 arranged sequentially along a direction parallel to the substrate 10.

[0137] Specifically, after forming an intermediate layer 30, a first conductive block 201 is formed on the intermediate layer 30, and a first chip structure 20 is formed on the first conductive block 201, and each of the first semiconductor chips 21 is electrically connected to the substrate 10 via the first conductive block 201.

[0138] Next, referring to Fig. 6c, a first package mold 91 and a second package mold 92 are formed. The first package mold and the second package mold in this embodiment are similar to the first package mold and the second package mold in Figs. 5a to 5h, and will not be described again here.

[0139] 6d, the first package mold 91 and the second package mold 92 are used as a mask to form a molding material pre-layer 400. The molding material pre-layer 400 completely covers the first surface of the substrate 10, the first chip structure 20, the intermediate layer 30, and the initial first solder balls 312′ on the intermediate layer 30.

[0140] After the molding material pre-layer 400 is formed, the first package mold 91 and the second package mold 92 are removed.

[0141] Next, referring to FIG. 6e, a portion of the molding material pre-layer 400 is removed to form the molding material 40, and a portion of the initial first solder ball 312' is removed to form the first solder ball 312 having a predetermined height h.

[0142] Still referring to FIG. 6e, after forming the molding material 40, substrate connection bumps 17 are formed on the second surface 102 of the substrate 10, and the substrate connection bumps 17 include a conductive material.

[0143] Next, referring to FIG. 6f, a second package structure 70 is formed, the second package structure 70 including second solder balls 71, and the second package structure 70 is electrically connected to the first solder balls 312 via the second solder balls 71.

[0144] The second package structure in this embodiment is similar to the second package structure in FIGS. 5a to 5h, and will not be described again here.

[0145] The above are merely preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure should all be included in the scope of protection of the present disclosure. [Industrial Applicability]

[0146] In the embodiment of the present disclosure, by providing an intermediate layer, the subsequent second package structure can be connected to the first chip structure and the substrate through the first solder balls on the intermediate layer, thereby realizing interconnections between structures of different types or specifications, thereby increasing the flexibility of combinations between different structures. At the same time, since the first chip structure and the second package structure are packaged independently, testing and failure analysis are also easier. In addition, since there is a predetermined height between the top surface of the first solder balls and the first interconnection surface, the entire package structure can have a relatively thin overall thickness, thereby achieving good bonding strength with the subsequent second package structure. [Explanation of symbols]

[0147] 1 ring 2 Carrier tape 10 Substrate 101 Page 1 102 2nd page 11 PCB base 12. Top insulating dielectric layer of substrate 13 Bottom insulating dielectric layer 14 Top board connection pads 15 Bottom board connection pad 16 Substrate connection vias 17 Substrate connection bumps 20 First chip structure 21 First semiconductor chip 211 first connection end 201 First Conductive Block 30 Middle Class 301 First interconnection surface 31 First Interconnection Area 32 Second Interconnection Area 311 Second Pad 312 First solder ball 312' Initial first solder ball 321 First Pad 33 Intermediate Base 34 Middle upper insulating dielectric layer 35 Middle bottom insulating dielectric layer 322 Second Conductive Block 40 Molding materials 51 First conductive wire 52 Second conductive wire 60 Adhesive film 70 Second package structure 71 Second solder ball 72 Second board 73 Second molding material 91 First package mold 92 Second package mold

Claims

1. 1. A semiconductor package assembly, comprising: a substrate having a first surface, the first surface including a first signal transmission region and a second signal transmission region located on opposite sides of the substrate, the first signal transmission region and the second signal transmission region not being interconnected; a first chip structure located on the substrate, the first chip structure including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the substrate, each of the first semiconductor chips being electrically connected only to the first signal transmission region via a first conductive line; an intermediate layer located on the first chip structure and having a first interconnection surface, the first interconnection surface having a first interconnection region and a second interconnection region, a first solder ball and a second pad formed on the first interconnection region, the first solder ball formed on the second pad, the second interconnection region electrically connected only to the second signal transmission region via a second conductive line, a first pad formed on the second interconnection region, the first pad electrically connected to the second conductive line; a molding material for encapsulating the first chip structure, the intermediate layer, and the first surface of the substrate, the first solder balls having surfaces exposed to the molding material, the exposed surfaces of the first solder balls being no higher than the surface of the molding material, and a predetermined height being between the exposed surfaces of the first solder balls and the first interconnection surface of the intermediate layer, the predetermined height being 1 / 5 to 1 / 2 or more of the thickness of the intermediate layer; a second package structure including second solder balls, the second package structure being electrically connected to the first solder balls via the second solder balls, and the volume of the first solder balls being larger than the volume of the second solder balls.

2. The number of the first pads is greater than the number of the second pads, and the area of ​​the first pads is smaller than the area of ​​the second pads. The semiconductor package assembly of claim 1 .

3. In a direction perpendicular to the substrate, the molding material has a first thickness; the second package structure includes a second molding material, and in a direction perpendicular to the substrate, the second molding material has a second thickness, and the first thickness is equal to or greater than the second thickness; The semiconductor package assembly of claim 1 .

4. 1. A method for manufacturing a semiconductor package assembly, comprising: providing a substrate having a first surface, the first surface including a first signal transmission region and a second signal transmission region located on opposite sides of the substrate, the first signal transmission region and the second signal transmission region not being interconnected; forming a first chip structure on the substrate, the first chip structure including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the substrate, each of the first semiconductor chips being electrically connected only to the first signal transmission region via a first conductive line; forming an intermediate layer located on the first chip structure and having a first interconnection surface, the first interconnection surface having a first interconnection region and a second interconnection region, a first solder ball and a second pad formed on the first interconnection region, the first solder ball formed on the second pad, the second interconnection region electrically connected only to the second signal transmission region via a second conductive line, a first pad formed on the second interconnection region, the first pad electrically connected to the second conductive line; forming a molding material for encapsulating the first chip structure, the intermediate layer, and the first surface of the substrate, wherein the first solder balls have surfaces exposed to the molding material, the exposed surfaces of the first solder balls are not higher than the surface of the molding material, and a predetermined height is provided between the exposed surfaces of the first solder balls and a first interconnection surface of the intermediate layer, the predetermined height being equal to or greater than 1 / 5 to 1 / 2 of a thickness of the intermediate layer; forming a second package structure including second solder balls, the second package structure being electrically connected to the first solder balls via the second solder balls, and a volume of the first solder balls being greater than a volume of the second solder balls.

5. Forming the molding material includes: forming a first package mold, a surface of the first package mold being parallel to a surface of the substrate, the first package mold being positioned above the first chip structure and the intermediate layer and being spaced a certain distance from the first chip structure and the intermediate layer; forming a molding material pre-layer using the first package mold as a mask; removing a portion of the molding material pre-layer to form a molding material and expose a surface of the first solder ball; The method for manufacturing a semiconductor package assembly according to claim 4 .

6. The number of the first pads is greater than the number of the second pads, and the area of ​​the first pads is smaller than the area of ​​the second pads. The method for manufacturing a semiconductor package assembly according to claim 4 .

7. In a direction perpendicular to the substrate, the molding material has a first thickness; the second package structure includes a second molding material, and in a direction perpendicular to the substrate, the second molding material has a second thickness, and the first thickness is equal to or greater than the second thickness; The method for manufacturing a semiconductor package assembly according to claim 5 .

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