Image sensor, control method, control device, electronic device and storage medium

Abstract

The present application discloses an image sensor, a control method, a control device, an electronic device and a storage medium, which belong to the technical field of electronic devices. The image sensor is a pixel circuit array, the pixel circuit array includes a plurality of pixel group circuits, each pixel group circuit includes a white pixel circuit and at least two color pixel circuits, the at least two color pixel circuits are arranged surrounding the white pixel circuit, the pixel circuit array includes at least two pixel circuit rows and at least two pixel circuit columns, the at least two pixel circuit rows share a control signal line, and the at least two pixel circuit columns share an output signal line, where the pixel circuit row includes a white pixel circuit or a color pixel circuit, and the pixel circuit column includes a pixel circuit array including the white pixel circuit or the color pixel circuit, and a pixel signal processing module connected to the output signal line.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application filed on August 25, 2021, bearing application number 202110984568.1 and entitled "Image sensor, control method, control device, electronic device and storage medium," the entire contents of which are incorporated herein by reference.

[0002] The present application belongs to the technical field of electronic equipment, and specifically relates to an image sensor, a control method, a control device, an electronic equipment, and a storage medium. [Background technology]

[0003] Currently, the five-pixel color filter array (CFA) inspired by light-emitting diode (LED) display technology, i.e., RGBW3.0, has solved many of the drawbacks (such as reduced color resolution) of traditional CFA architectures such as Kodak RGBW CFA and Bayer RGB CFA. However, the structure of RGBW3.0 is significantly different from traditional CFA architectures, and there is currently no corresponding pixel signal processing circuit design for the pixel array, making it impossible to accurately control RGBW3.0. Summary of the Invention [Problem to be solved by the invention]

[0004] The purpose of the embodiments of the present application is to provide an image sensor, a control method, a control device, an electronic device, and a storage medium that can solve the problem that the color filter array cannot be accurately controlled due to the lack of a corresponding pixel signal processing circuit scheme for the pixel array in the related art. [Means for solving the problem]

[0005] According to a first aspect, an embodiment of the present application provides an image sensor, the image sensor comprising: a pixel circuit array including a plurality of pixel group circuits, each pixel group circuit including one white pixel circuit and at least two color pixel circuits, the at least two color pixel circuits being arranged surrounding the white pixel circuit, the pixel circuit array including at least two pixel circuit rows and at least two pixel circuit columns, the at least two pixel circuit rows sharing one control signal line and the at least two pixel circuit columns sharing one output signal line, wherein the pixel circuit rows include white pixel circuits or color pixel circuits, and the pixel circuit columns include white pixel circuits or color pixel circuits; and a pixel signal processing module connected to the output signal line.

[0006] According to a second aspect, an embodiment of the present application provides an electronic device, the electronic device including the image sensor according to the first aspect.

[0007] According to a third aspect, an embodiment of the present application provides a control method for an image sensor, the image sensor including: a pixel circuit array and a pixel signal processing module; the pixel circuit array includes a plurality of pixel group circuits, each pixel group circuit including one white pixel circuit and a plurality of color pixel circuits, the plurality of color pixel circuits being arranged surrounding the white pixel circuit; each pixel circuit row of the pixel circuit array sharing one control signal line; each pixel circuit column of the pixel circuit array sharing one output signal line; the pixel signal processing module being connected to the output signal line; when the pixel circuit row includes a white pixel circuit or a color pixel circuit and the pixel circuit column includes a white pixel circuit or a color pixel circuit, the pixel signal processing module includes a selection module, a first sub-processing module, a second sub-processing module and a first processing buffer module; the control method includes: Controlling the selection module to transmit the first target signal to the first sub-processing module; Controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on the third output signal of the third output signal line, and analog-to-digital conversion processing on the third output signal after the amplification processing; and controlling a first processing buffer module to store the first target signal and the third output signal and to perform image processing on the first target signal and the third output signal; Here, the first target signal includes a first output signal of a first output signal line or a second output signal of a second output signal line, the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column is a pixel circuit column including white pixel circuits, and the color pixel circuit column is a pixel circuit column including color pixel circuits.

[0008] According to a fourth aspect, an embodiment of the present application provides a control device for an image sensor, the image sensor including a pixel circuit array and a pixel signal processing module, the pixel circuit array including a plurality of pixel group circuits, each pixel group circuit including one white pixel circuit and a plurality of color pixel circuits, the plurality of color pixel circuits being arranged surrounding the white pixel circuit, each pixel circuit row of the pixel circuit array sharing one control signal line, each pixel circuit column of the pixel circuit array sharing one output signal line, the pixel signal processing module being connected to the output signal line, when the pixel circuit row includes a white pixel circuit or a color pixel circuit and when the pixel circuit column includes a white pixel circuit or a color pixel circuit, the pixel signal processing module includes a selection module, a first sub-processing module, a second sub-processing module and a first processing buffer module, and the control device Controlling the selection module to transmit the first target signal to the first sub-processing module; Controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on the third output signal of the third output signal line, and analog-to-digital conversion processing on the third output signal after the amplification processing; and controlling a first processing buffer module to store the first target signal and the third output signal and to perform image processing on the first target signal and the third output signal; Here, the first target signal includes a first output signal of a first output signal line or a second output signal of a second output signal line, the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column is a pixel circuit column including white pixel circuits, and the color pixel circuit column is a pixel circuit column including color pixel circuits.

[0009] According to a fifth aspect, an embodiment of the present application provides an electronic device, the electronic device including a processor, a memory, and a program or instructions stored in the memory and operable to run on the processor, the program or instructions implementing the steps of the method according to the second aspect when executed by the processor.

[0010] According to a sixth aspect, an embodiment of the present application provides a readable storage medium having a program or instructions stored thereon, the program or instructions implementing the steps of the method of the second aspect when executed by a processor.

[0011] According to a seventh aspect, an embodiment of the present application provides a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor running a program or instruction and used to implement the method of the second aspect.

[0012] In an embodiment of the present application, the pixel circuit array is composed of a plurality of pixel group circuits. Each pixel circuit row of the pixel circuit array shares one control signal line, and each pixel circuit column of the pixel circuit array shares one output signal line, specifically, the color pixel circuits of each row share one control signal line, the white pixel circuits of each row share one pixel control signal, and the color pixel circuits of each column share one output signal line, and the white pixel circuits of each column share one output signal line. The pixel control signal shared by the white pixel circuits of each row and the pixel control signal shared by the color pixel circuits of each row are independent of each other, and the output signal lines of the color pixel circuits and the output signal lines of the white pixel circuits are independent of each other. [Effects of the Invention]

[0013] The embodiments of the present application provide an RGBW pixel circuit array architecture, which realizes a pixel circuit array rearrangement compared to conventional pixel circuit arrays. On the one hand, this pixel circuit array architecture is applied to a CFA type (e.g., an RGBW3.0 CFA), which solves the problem that CFA cannot be used with conventional pixel circuit arrays, and provides a basis for the widespread application of CFA in complementary metal-oxide semiconductor image sensors (CIS). On the other hand, it realizes independent signal processing between color pixels and white pixels, and while adaptively using the CFA pixel structure, effectively avoids signal crosstalk between color pixels and white pixels, thereby improving the sensitivity of the image sensor. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic diagram of a pixel array layout and a pixel group layout of a complementary metal oxide semiconductor image sensor according to an embodiment of the present application. [Figure 2] 1 is a schematic diagram showing the structure of a pixel of a complementary metal oxide semiconductor image sensor according to an embodiment of the present application; [Figure 3] 2 is a second schematic diagram of the pixel structure of a complementary metal oxide semiconductor image sensor according to an embodiment of the present application. [Figure 4] 1 is a schematic diagram of a pixel circuit array architecture of a complementary metal oxide semiconductor image sensor according to an embodiment of the present application; [Figure 5] 1 is a schematic structural diagram of a pixel circuit array according to an embodiment of the present application; [Figure 6] 1 is a structural schematic diagram of a pixel signal processing module according to an embodiment of the present application; [Figure 7] FIG. 1 is a structural schematic diagram of an analog data multiplexer according to an embodiment of the present application; [Figure 8] 1 is a structural schematic diagram of a digital data demultiplexing device according to an embodiment of the present application; [Figure 9] 2 is a second schematic structural diagram of a pixel circuit array according to an embodiment of the present application; [Figure 10] 2 is a second structural schematic diagram of a pixel signal processing module according to an embodiment of the present application; [Figure 11] 1 is a schematic structural diagram of an adder according to an embodiment of the present application; [Figure 12] 2 is a second schematic diagram of the structure of an adder according to an embodiment of the present application; [Figure 13] FIG. 2 is a flow chart schematic diagram of a control method for an image sensor in an embodiment of the present application; [Figure 14] FIG. 2 is a schematic block diagram of a control device for an image sensor according to an embodiment of the present application. [Figure 15] 1 is a schematic block diagram of an electronic device according to an embodiment of the present application. [Figure 16] FIG. 2 is a second schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0015] The following clearly describes the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application fall within the scope of protection of the present application.

[0016] The terms "first," "second," etc. in the specification and claims of this application are intended to distinguish between similar objects and are not intended to describe a particular order or sequence. It is to be understood that terms so used are interchangeable where appropriate, so that embodiments of this application may be performed in orders other than those illustrated or described herein. Note that "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the related objects.

[0017] A pixel array of a CIS using RGBW3.0 is composed of pixel groups. As shown in Figure 1, each pixel group 100 has five pixels, including four colored pixels (i.e., color pixels), including a red pixel 102, a blue pixel 104, and two green pixels 106, all of which are "L" shaped. The colorless and transparent white pixel 108 is still square. The white pixel 108 is located in the middle of the pixel group 100 and is surrounded by the four "L" shaped colored pixels. Under the color filter of each colored pixel is a photosensitive element, such as a photodiode, whose role is to convert light filtered by the color filter into an electrical signal, such as current, voltage, or potential energy, which is used for back-end processing.

[0018] In modern CIS manufacturing processes, irregular-shaped pixels (i.e., "L"-shaped) are still not widely applicable to consumer CIS products due to process and yield issues. To achieve successful implementation, "L"-shaped color pixels in RGBW3.0 are divided into multiple rectangular pixels. There are two approaches, as shown in Figures 2 and 3. As shown in Figure 2, in Approach 1, the red region 202, blue region 204, and green region 206 each consist of three pixels. The middle white region 208 consists of four pixels, all of the same size. As shown in Figure 3, in Approach 2, each color region consists of five pixels, and the central white region 208 consists of 16 pixels. In both approaches, the ratio of green, red, and blue pixels remains constant—always 2:1:1. However, the occupancy rate of the white region in the pixel group region changes due to the change in the number of white pixels, and the ratio of white pixels to colored pixels in method 1 is 1:3, while the ratio of white pixels to colored pixels in method 2 is 4:5.

[0019] In the CIS pixel circuit array architecture using RGBW3.0, as shown in Figure 4, the pixels in each row share a set of pixel control signals, which include a pixel reset signal (φrst) for controlling the reset time of the pixel, a charge transfer switch signal (φtran) for controlling the exposure time of the pixel, and a pixel signal read switch signal (φsel) for controlling the read time of the pixel, and the pixel control signals are generated by a pixel control signal generation module 402. The pixels in each column share one pixel output signal (Vout) transmission line, and the pixels in each row take turns using this shared transmission line to transmit Vout to the back-end signal processing circuit.

[0020] Each pixel includes a pixel circuit. As shown in Figure 4, the pixel circuit 404 includes a four-transistor active pixel sensor (APS) circuit, in which a light-sensitive photodiode (PD) converts light into electrons, which are then transferred to a floating diffusion (FD) region by a charge transfer transistor (switched by φtran). When the pixel is selected and read (φsel is pulled up), the charge in FD is read as a voltage signal by a source follower consisting of Msf and Msel, and output as Vout.

[0021] The RGBW3.0 CFA has a significantly different structure than conventional CFA formats such as Bayer RGB and Kodak RGBW, making it impossible to apply pixel signal processing circuits corresponding to conventional pixel arrays. The image sensor and electronic device according to the present application can solve this problem.

[0022] Hereinafter, the image sensor, the control method, the control device, the electronic device, and the storage medium according to the embodiments of the present application will be described in detail with reference to specific embodiments and application scenarios thereof in conjunction with the drawings.

[0023] An embodiment of the present application provides an image sensor, the image sensor comprising: a pixel circuit array including a plurality of pixel group circuits, each pixel group circuit including one white pixel circuit and at least two color pixel circuits, the at least two color pixel circuits being arranged surrounding the white pixel circuit, the pixel circuit array including at least two pixel circuit rows and at least two pixel circuit columns, the at least two pixel circuit rows sharing one control signal line and the at least two pixel circuit columns sharing one output signal line, wherein the pixel circuit rows include white pixel circuits or color pixel circuits, and the pixel circuit columns include white pixel circuits or color pixel circuits; and a pixel signal processing module connected to the output signal line.

[0024] In this embodiment, for the "L"-shaped pixel structure scheme, the CFA of the pixel layer uses the layout shown in Figure 1, and each pixel group includes four color pixels and one white pixel, where the four color pixels include a red pixel (R), a blue pixel (B), and two green pixels (G), all of which are "L" shaped. The colorless and transparent white pixel (W) is square, and is located in the middle of the pixel group and is surrounded by the four "L"-shaped color pixels.

[0025] As shown in FIG. 5 , the circuit structure of the pixel array 600 and the pixel circuit array 700 corresponding to the pixel array 600 is such that the pixel circuit array 700 is composed of a plurality of pixel group circuits 702, and one pixel group circuit 702 is composed of a plurality of pixel circuits 704 (one pixel group 602 in the pixel array 600 corresponds to one pixel group circuit 702, and one pixel in the pixel array 600 corresponds to one pixel circuit 704), and the pixel circuits in each row are all controlled by a pixel control signal generation module 800.

[0026] A pixel circuit row includes white pixel circuits or color pixel circuits, and a pixel circuit column includes white pixel circuits or color pixel circuits, which corresponds to each pixel circuit row of the pixel circuit array sharing one control signal line and each pixel circuit column of the pixel circuit array sharing one output signal line, specifically, the color pixel circuits of each row share one pixel control signal (i.e., control signal line) and the white pixel circuits of each row share one pixel control signal, and the color pixel circuits of each column share one output signal line and the white pixel circuits of each column share one output signal line. The pixel control signal shared by the white pixel circuits of each row and the pixel control signal shared by the color pixel circuits of each row are independent of each other, and the output signal line of the color pixel circuits and the output signal line of the white pixel circuits are independent of each other. The output voltage signal of the color pixel circuit of each column is Vout, and the voltage signal output from the white pixel circuit of each column is Vout_w. The signal transmission line transmits the output signals (Vout and Vout_w) of each column to the pixel signal processing module 900 and is processed by the pixel signal processing module 900.

[0027] The embodiments of the present application provide an RGBW pixel circuit array architecture, which realizes a pixel circuit array rearrangement compared to a conventional pixel circuit array. On the one hand, this pixel circuit array architecture is applied to a CFA type (e.g., RGBW3.0 CFA), which solves the problem that a CFA cannot be used with a conventional pixel circuit array, and provides a basis for the widespread application of CFA in CIS. On the other hand, it realizes independent signal processing between color pixels and white pixels, and while adaptively using the CFA pixel structure, effectively avoids signal crosstalk between color pixels and white pixels, thereby improving the sensitivity of the image sensor.

[0028] Furthermore, in one embodiment of the present application, the pixel signal processing module includes: a plurality of selection modules connected to a first output signal line and a second output signal line, where the first output signal line is an output signal line corresponding to a white pixel circuit column and the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column being a pixel circuit column including white pixel circuits, and the color pixel circuit column being a pixel circuit column including color pixel circuits; a first processing module including a plurality of first sub-processing modules, where the first sub-processing modules are connected to the selection module; and a plurality of second sub-processing modules, where the second sub-processing modules are connected to a third output signal line, where the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column; and a first processing buffer module connected to the first processing module.

[0029] The selection module transmits the first output signal on the first output signal line or the second output signal on the second output signal line to the first sub-processing module, the first sub-processing module amplifies the first output signal or the second output signal and performs analog-to-digital conversion on the amplified first output signal or the second output signal, the second sub-processing module amplifies the third output signal on the third output signal line and performs analog-to-digital conversion on the amplified third output signal. The first processing buffer module stores the first output signal, the second output signal, and the third output signal, and performs image processing on the stored first output signal, the second output signal, and the third output signal to improve the signal quality of the first output signal, the second output signal, and the third output signal, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, and automatic exposure control.

[0030] In this embodiment, the pixel signal processing module includes a plurality of selection modules, a first processing module, and a first processing buffer module, and the first processing module includes a plurality of first sub-processing modules and a plurality of second sub-processing modules. An output signal from an output signal line corresponding to a white pixel circuit column (i.e., the first output signal line) and an output signal from an output signal line corresponding to one adjacent color pixel circuit column (i.e., the second output signal line) are multiplexed to the same first sub-processing module by one selection module. An output signal from an output signal line corresponding to another color pixel circuit column adjacent to the first output signal line (i.e., the third output signal line) uses the second sub-processing module.

[0031] The first processing buffer module is connected to all of the first sub-processing modules and all of the second sub-processing modules, and is used to sequentially store and perform image processing on the first output signal, the second output signal, and the third output signal after amplification processing and analog-to-digital conversion processing.

[0032] 6 , the pixel signal processing module 900 includes an analog data multiplexer (MUX) 902, a first sub-processing module 904, a second sub-processing module 906, and a first processing buffer module 908. The output signal of the color pixel circuit 7042 of each column is Vout, and the output signal of the white pixel circuit 7044 of each column is Vout_w. One output signal Vout and one output signal Vout_w pass through one MUX 902 and then multiplexed into one first sub-processing module 904, where MUX is the selection module. The first sub-processing module 904 includes one programmable gain amplifier (PGA) circuit 9042 and one analog-to-digital converter (ADC) circuit 9044, and the second sub-processing module 906 includes one PGA circuit 9062 and one ADC circuit 9064. The PGA circuit is used to amplify the signal, and the output signal VPGA is further input to the ADC circuit, which is used to perform analog-to-digital conversion on the signal VPGA. The first processing buffer module 908 is an ISP and image buffer, which is used to store and perform image processing on the signal.

[0033] It should be noted that, as shown in FIG. 6, the two input signals of MUX 902 are respectively the output signal Vout_w of one white pixel circuit column in one column of pixel group circuits and the output signal Vout of any one color pixel circuit column in the pixel group circuits of this column.

[0034] When reading pixel circuit signals using the row-by-row scanning method, the pixels in the first row are read first, for example, the signals of the color pixels R and G are read, and the signal of the color pixel R is transmitted to MUX 902 and then to the PGA circuit and ADC circuit for processing, while the signal of the color pixel G is transmitted directly to the PGA circuit and ADC circuit for processing. Next, the pixels in the second row are read, for example, the signal of the white pixel W is read, and the signal of the white pixel W is transmitted to MUX 902 and then to the PGA circuit and ADC circuit, sharing the same PGA circuit and ADC circuit as the signal of the color pixel R. Because the pixels in the first row and the pixels in the second row are not read simultaneously, there is no conflict between the processing of the PGA circuit and the ADC circuit.

[0035] In the embodiment of the present application, since the number of white pixels and color pixels are different and in different rows, some sub-modules of the white pixel signal processing link and the color pixel processing link can be multiplexed, thereby saving space and energy consumption.

[0036] Furthermore, in one embodiment of the present application, the first processing buffer module includes a plurality of first demultiplexing modules, where the first demultiplexing modules are connected to the first sub-processing modules; a plurality of first buffer modules, where the first buffer modules are connected to the first demultiplexing modules; a plurality of second buffer modules, where the second buffer modules are connected to the first demultiplexing modules or the second buffer modules are connected to the second sub-processing modules; and a first image processing module connected to the first buffer module and the second buffer module.

[0037] Here, the first buffer module is used to store the first output signal, the second buffer module is used to store the second output signal when connected to the first demultiplexing module, the second buffer module is used to store the third output signal when connected to the second sub-processing module, and the first image processing module is used to perform image processing on the first output signal, the second output signal and the third output signal.

[0038] In this embodiment, the first processing buffer module includes a plurality of first demultiplexing modules, a plurality of first buffer modules, a plurality of second buffer modules, and a first image processing module. The first demultiplexing module is used to transmit the first output signal and the second output signal output from the first sub-processing module to different buffer modules. Specifically, the first output signal is transmitted to the first buffer module, the second output signal is transmitted to the second buffer module, and the third output signal is transmitted to the second buffer module. That is, the output signal of the white pixel circuit array is stored in the first buffer module, and the output signal of the color pixel circuit array is stored in the second buffer module.

[0039] The first image processing module further performs image processing on the signals stored in the first buffer module and the second buffer module.

[0040] It should be noted that the number of the plurality of first demultiplexing modules is equal to the number of selection modules.

[0041] 6, after entering the first processing buffer module 908, the first output signal and the second output signal are stored in different buffer modules (Buffer and Buffer_W) by a digital data demultiplexer (DEMUX) 9082 of the first processing buffer module 908, where DEMUX is the first demultiplexing module. Specifically, the second output signal and the third output signal (i.e., the output signal of the color pixel string) are buffered in Buffer, and the first output signal (i.e., the output signal of the white pixel string) is buffered in Buffer_W. The buffered signals then enter an ISP 9084 for digital image processing.

[0042] The above method performs independent buffering for the output signals of the color pixel rows and the output signals of the white pixel rows, and the first image processing module can select the output signals of the color pixel rows or the output signals of the white pixel rows at any location for post-processing, greatly expanding the variety of image signal processing options.

[0043] It should be noted that the circuit structure of the DEMUX 9082 is as shown in FIG. 8, and the DEMUX 9082 is controlled by a φSel2 signal, and inputs the output signal of the ADC to Buffer and Buffer_W, respectively.

[0044] Common buffer modules include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0045] In FIG. 6, the data demultiplexer may be arranged before the ADC, and at this time, the data demultiplexer must use an analog data demultiplexer instead of a digital data demultiplexer.

[0046] Furthermore, in one embodiment of the present application, the pixel signal processing module further includes a plurality of first sampling modules, and the first sampling modules are connected to the output ends of the output signal lines.

[0047] The first sampling module is used to perform noise removal processing on the output signal of the output signal line.

[0048] In this embodiment, the pixel signal processing module further includes a plurality of first sampling modules, one end of which is connected to the output end of the output signal line, and the other end of which is connected to the selection module or the second sub-processing module, and the first sampling modules are used to perform noise removal processing on the output signal of the output signal line.

[0049] 6, the output signal of each column's color pixel circuit is Vout, and the output signal of each column's white pixel circuit is Vout_w. The output signals Vout and Vout_w are both subjected to noise reduction processing by an independent correlated double sampling (CDS) circuit 910 (i.e., a first sampling module). Specifically, after two samplings (the sampled signals are stored in capacitors C1 and C2), an operational amplifier ACDS is used to perform signal subtraction to obtain the difference between the two sampled signals, i.e., a VCDS signal. The VCDS signal output from the CDS circuit 910 is input to a PGA circuit for adjustable signal amplification.

[0050] As shown in FIG. 7, the MUX includes a switch S1, a switch S2, and an operational amplifier. The MUX is controlled by a φSel1 signal, and the VCDS and VCDS_W signals output from the CDS enter the MUX for signal synthesis.

[0051] The above method performs noise removal processing on the output signals of the color pixel circuit arrays and the output signals of the white pixel circuit arrays, thereby improving the accuracy of the signals.

[0052] 6, each sub-module on each pixel signal processing link in the pixel signal processing module 900 needs to be provided with timing and control signals by the signal processing & control signal module 912. After the pixel signal has scanned all the sub-modules on the link and been buffered in Buffer or Buffer_W, the signal enters the ISP 9084 for digital image processing. After the processing is completed, the final image signal is output from the CIS chip by the I / O 914.

[0053] Furthermore, in one embodiment of the present application, when a white pixel circuit includes a plurality of sub-white pixel circuits and a color pixel circuit includes a plurality of sub-color pixel circuits, a pixel circuit row may include sub-color pixel circuits, or may include sub-white pixel circuits and sub-color pixel circuits, and a pixel circuit column may include sub-color pixel circuits, or may include sub-white pixel circuits and sub-color pixel circuits.

[0054] In this embodiment, for the composite pixel scheme (shown in FIGS. 2 and 3) in which a white pixel is divided into a plurality of rectangular white sub-pixels and a color pixel is divided into a plurality of rectangular color sub-pixels, taking the structure shown in FIG. 2 as an example, each pixel group 602 in the pixel array 600 includes 16 sub-pixels, and therefore, as shown in FIG. 9, each pixel group circuit 702 in the pixel circuit array 700 includes 16 sub-pixel circuits 706, specifically 4 white sub-pixel circuits and 12 color sub-pixel circuits. The sub-pixel circuits in each row are all controlled by a pixel control signal generation module 800, and the output signals of the sub-pixel circuits in each column are transmitted to a pixel signal processing module 900 for processing.

[0055] In the pixel circuit array, the sub-pixel circuits in each row include two situations: one is that each row includes only sub-color pixel circuits, and the other is that each row includes sub-white pixel circuits and sub-color pixel circuits; and the sub-pixel circuits in each column include two situations: one is that each column includes only sub-color pixel circuits, and the other is that each column includes sub-white pixel circuits and sub-color pixel circuits.

[0056] All the sub-pixel circuits (whether sub-color pixel circuits or sub-white pixel circuits) in each row are controlled by the pixel control signal generating module, that is, all the sub-pixel circuits in each row share one pixel control signal (i.e., control signal line), and the signals output from all the sub-pixel circuits (whether sub-color pixel circuits or sub-white pixel circuits) in each column share one signal transmission line (i.e., output signal line) to the pixel signal processing module.

[0057] The embodiments of the present application provide an RGBW pixel circuit array architecture. On the one hand, this pixel circuit array architecture is applied to a CFA-type (e.g., RGBW3.0 CFA) composite pixel scheme, solving the problem that the CFA composite pixel scheme cannot use traditional pixel circuit arrays, and laying the foundation for the widespread application of CFA in CIS. On the other hand, each pixel circuit in the pixel circuit array can perform signal processing and readout, adaptively using the CFA pixel structure while effectively avoiding signal crosstalk between pixels.

[0058] Furthermore, in one embodiment of the present application, the pixel signal processing module includes a plurality of second processing modules, each connected to an output signal line; a second processing buffer module, the second processing buffer module including a plurality of second demultiplexing modules, the second demultiplexing module connected to a first target processing module, wherein the first target processing module is a second processing module connected to an output signal line corresponding to the first target pixel circuit column, the first target pixel circuit column being a pixel circuit column including a sub-white pixel circuit and a sub-color pixel circuit; a plurality of third buffer modules connected to the second demultiplexing module; and a plurality of fourth buffer modules, the fourth buffer module connected to the second demultiplexing module or the fourth buffer module connected to the second target processing module, wherein the second target processing module is a second processing module connected to an output signal line corresponding to the second target pixel circuit column, the second target pixel circuit column being a pixel circuit column including a sub-color pixel circuit; and a second image processing module connected to the third buffer module and the fourth buffer module.

[0059] Here, the second processing module is used to amplify the output signal of the output signal line and perform analog-to-digital conversion on the amplified output signal; the third buffer module is used to store the fourth output signal, which is a signal of the sub-white pixel circuit output from the output signal line corresponding to the first target pixel circuit column; the fourth buffer module, when connected to the second demultiplexing module, is used to store the fifth output signal, which is a signal of the sub-color pixel circuit output from the output signal line corresponding to the first target pixel circuit column; and the fourth buffer module, when connected to the second target processing module, is used to store the sixth output signal of the second target processing module; the second image processing module is used to perform image processing on the fourth, fifth, and sixth output signals, thereby improving the signal quality of the fourth, fifth, and sixth output signals, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, and automatic exposure control.

[0060] In this embodiment, for the composite pixel scheme, the pixel signal processing module includes a plurality of second processing modules and a second processing buffer module, and the second processing buffer module includes a plurality of second demultiplexing modules, a plurality of third buffer modules, a plurality of fourth buffer modules, and a second image processing module. The second processing modules are used to amplify and perform analog-to-digital conversion on the output signals of the output signal lines, and the second demultiplexing module transmits the output signals of the first target pixel circuit column after amplification and analog-to-digital conversion to different buffer modules (i.e., the third buffer module and the fourth buffer module) for storage. Specifically, the output signals of the first target pixel circuit column include signals of the sub-white pixel circuits (i.e., the fourth output signal) and the sub-color pixel circuits (i.e., the fifth output signal), and the fourth output signal is transmitted to the third buffer module for storage using the second demultiplexing module, and the fifth output signal is transmitted to the fourth buffer module for storage using the second demultiplexing module.

[0061] In addition, the output signal of the second target pixel circuit column only includes the signal of the sub-color pixel circuit (i.e., the sixth output signal), and the output signal of the second target pixel circuit column is subjected to amplification processing and analog-to-digital conversion processing using the second target processing module, and then directly transmitted to the fourth buffer module for storage.

[0062] The second image processing module further performs image processing on the signals stored in the third buffer module and the fourth buffer module.

[0063] Here, the first target processing module and the second target processing module each include one PGA circuit and one ADC circuit. The PGA circuit is used to amplify a signal, and the output signal VPGA or VPGA / W is further input to the ADC circuit, which is used to perform analog-to-digital conversion of the signal VPGA or VPGA / W.

[0064] 10 , the pixel signal processing module 900 includes a first target processing module 916, a second target processing module 918, and a second processing buffer module 920. The output signal of each sub-color pixel circuit column is Vout, and the output signal of each pixel circuit column including a sub-white pixel circuit and a sub-color pixel circuit is Vout / w. The output signal Vout passes through the second target processing module 918, and the output signal Vout / w passes through the first target processing module 916 and enters the ISP and image buffer (i.e., the second processing buffer module 920). The first target processing module 916 includes one PGA circuit 9162 and one ADC circuit 9164, and the second target processing module 918 includes one PGA circuit 9182 and one ADC circuit 9184.

[0065] In one pixel group, sub-white pixels are present only in the two middle columns, so one DEMUX 9202 is installed in the column link where the sub-white pixels are present. After the output signal Vout / w passes through the DEMUX 9202, the sub-color pixel information (i.e., the fifth output signal) and the sub-white pixel information (i.e., the fourth output signal) are buffered in different buffer modules (Buffer or Buffer_W). Specifically, the fifth output signal is buffered in Buffer, and the fourth output signal is buffered in Buffer_W. In addition, the output signal Vout (i.e., the sixth output signal) of the pixel circuit column including only sub-color pixel circuits is buffered in Buffer.

[0066] When reading pixel circuit signals using the row-by-row scanning method, the pixels in the first row are read first, for example, the signals of the sub-color pixels R1, R2, G1, and G2 are read. The signals of the sub-color pixels R1 and G2 are transmitted to the corresponding PGA circuits and ADC circuits and stored in the corresponding buffers. The signals of the sub-color pixels R2 and G1 are transmitted to the corresponding PGA circuits and ADC circuits and stored in the corresponding buffers by the DEMUX. Next, the pixels in the second row are read, for example, the signals of the sub-color pixels R3 and G3 and the signals of the sub-white pixels W1 and W2 are read. The signals of the sub-color pixels R3 and G3 are transmitted to the corresponding PGA circuits and ADC circuits and stored in the corresponding buffers. The signals of the sub-white pixels W1 and W2 are transmitted to the corresponding PGA circuits and ADC circuits and stored in the corresponding buffers by the DEMUX.

[0067] In the above method, the pixel signal processing module adapts to the pixel array of the composite pixel scheme, and uses different buffer modules to buffer the signals of the sub-color pixel circuits and the sub-white pixel circuits independently, thereby avoiding confusion and congestion between signals and providing convenience for the ISP to perform post-processing.

[0068] It should be noted that common buffer modules include DRAM, SRAM, etc. The circuit structure of the DEMUX is shown in Figure 8. In Figure 10, a data demultiplexer may be placed before the ADC, and in this case, the data demultiplexer should use an analog data demultiplexer rather than a digital data demultiplexer.

[0069] Furthermore, in one embodiment of the present application, the second processing buffer module further includes a plurality of signal combining modules, which are connected to the second image processing module, the first target buffer module and the second target buffer module, and the first target buffer module and the second target buffer module are third buffer modules that respectively store signals of two sub-white pixel circuits of adjacent rows in the target pixel group circuit.

[0070] Here, the signal synthesis module is used to fuse the output signal of the first target buffer module with the output signal of the second target buffer module, i.e., enhance the output signal of the first target buffer module and the output signal of the second target buffer module.

[0071] In this embodiment, the composite pixel scheme may require signal merging of same-color pixels, so same-color pixel composite of sub-color pixels generally occurs in pixel arrays, and signal composite of sub-white pixels is relatively difficult to achieve in pixel arrays.

[0072] In contrast, an embodiment of the present application provides a sub-white pixel signal fusion scheme, and when sub-color pixel signal fusion is used, a signal combining module is used to combine corresponding sub-white pixel signals. Specifically, the second processing buffer module includes a plurality of signal combining modules, and the signal combining modules are used for signals of two sub-white pixel circuits in adjacent rows in a target pixel group circuit, the signals of the two sub-white pixel circuits in adjacent rows being signals stored in the first target buffer module and the second target buffer module respectively, and the target pixel group circuit is any one of the pixel group circuits in the pixel circuit array.

[0073] For example, as shown in Figure 10, by installing one adder 9206 (i.e., the above-mentioned signal synthesis module) at the output ends of two adjacent Buffer_W, it is possible to easily realize signal fusion of sub-white pixels (for example, sub-white pixel W1 and sub-white pixel W2, or sub-white pixel W3 and sub-white pixel W4). It should be noted that, as shown in Figure 10, the adder 9206 is located after the ADC, and therefore performs digital signal synthesis.

[0074] The circuit structure of an adder is shown in Figure 11, and is composed of multiple full adders. The circuit structure of a full adder is shown in Figure 12. N-bit binary digital signals A1, A2, ..., AN and N-bit binary digital signals B1, B2, ..., BN pass through the adders to generate N-bit binary digital signals S1, S2, ..., SN, respectively. C1, C2, ..., CN are carries in the addition.

[0075] The above method realizes the fusion of two adjacent sub-white pixel signals, which provides convenience for post-processing of the ISP.

[0076] Furthermore, in one embodiment of the present application, the pixel signal processing module further includes a plurality of second sampling modules, which are connected between the second processing module and the output signal line, and the second sampling modules are used to perform noise reduction processing on the output signal of the output signal line.

[0077] In this embodiment, the pixel signal processing module further includes a plurality of second sampling modules, one end of which is connected to the output end of the output signal line, and the other end of which is connected to the second processing module, and the second sampling modules are used to perform noise removal processing on the output signal of the output signal line.

[0078] For example, as shown in FIG. 10, the output signal of each pixel circuit column including only sub-color pixel circuits is Vout, and the output signal of each pixel circuit column including sub-color pixel circuits and sub-white pixel circuits is Vout / w, and both the output signal Vout and the output signal Vout / w are subjected to noise removal processing by an independent CDS 922 (i.e., a second sampling module).

[0079] The above method performs noise removal processing on the output signal from the output signal line, thereby improving the accuracy of the signal.

[0080] 10, each sub-module on each pixel signal processing link in the pixel signal processing module needs to be provided with timing and control signals by the signal processing & control signal module 912. After the pixel signal has scanned all the sub-modules on the link and been buffered in Buffer or Buffer_W, the signal enters the ISP 9204 for digital image processing. After the processing is completed, the final image signal is output from the CIS chip by the I / O 914.

[0081] An embodiment of the present application provides an electronic device, which includes the image sensor of the above embodiment.

[0082] In this embodiment, the pixel circuit array of the image sensor is composed of a plurality of pixel group circuits. Each pixel circuit row of the pixel circuit array shares one control signal line, and each pixel circuit column of the pixel circuit array shares one output signal line, specifically, the color pixel circuits of each row share one control signal line, the white pixel circuits of each row share one pixel control signal, the color pixel circuits of each column share one output signal line, and the white pixel circuits of each column share one output signal line. The pixel control signal shared by the white pixel circuits of each row and the pixel control signal shared by the color pixel circuits of each row are independent of each other, and the output signal lines of the color pixel circuits and the output signal lines of the white pixel circuits are independent of each other.

[0083] The embodiments of the present application provide an RGBW pixel circuit array architecture, which realizes a pixel circuit array rearrangement compared to a conventional pixel circuit array. On the one hand, this pixel circuit array architecture is applied to a CFA type (e.g., RGBW3.0 CFA), which solves the problem that a CFA cannot be used with a conventional pixel circuit array, and provides a basis for the widespread application of CFA in CIS. On the other hand, it realizes independent signal processing between color pixels and white pixels, and while adaptively using the CFA pixel structure, effectively avoids signal crosstalk between color pixels and white pixels, thereby improving the sensitivity of the image sensor.

[0084] The electronic device may be a mobile electronic device or a non-mobile electronic device. Illustratively, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the non-mobile electronic device may be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, and the embodiments of the present application are not specifically limited.

[0085] The electronic device in the embodiment of the present application may be a device having an operating system, which may be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiment of the present application is not specifically limited.

[0086] An embodiment of the present application provides a control method for an image sensor, the image sensor comprising: a pixel circuit array and a pixel signal processing module; the pixel circuit array comprises a plurality of pixel group circuits, each pixel group circuit comprising one white pixel circuit and a plurality of color pixel circuits, the plurality of color pixel circuits being arranged surrounding the white pixel circuit; each pixel circuit row of the pixel circuit array shares a control signal line; each pixel circuit column of the pixel circuit array shares an output signal line; the pixel signal processing module is connected to the output signal line; when the pixel circuit row comprises a white pixel circuit or a color pixel circuit, and when the pixel circuit column comprises a white pixel circuit or a color pixel circuit, the pixel signal processing module comprises a selection module, a first sub-processing module, a second sub-processing module and a first processing buffer module; as shown in FIG. 13 , the control method comprises: In step 1302, controlling the selection module to transmit a first target signal to a first sub-processing module; In step 1304, controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on the third output signal of the third output signal line, and to perform analog-to-digital conversion processing on the third output signal after the amplification processing; Step 1306 includes controlling a first processing buffer module to store the first target signal and the third output signal, and to perform image processing on the first target signal and the third output signal.

[0087] Here, the first target signal includes a first output signal of a first output signal line or a second output signal of a second output signal line, the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column is a pixel circuit column including white pixel circuits, and the color pixel circuit column is a pixel circuit column including color pixel circuits.

[0088] In this embodiment, the pixel signal processing module includes a plurality of selection modules, a first processing module, and a first processing buffer module, and the first processing module includes a plurality of first sub-processing modules and a plurality of second sub-processing modules. An output signal from an output signal line corresponding to a white pixel circuit column (i.e., the first output signal line) and an output signal from an output signal line corresponding to one adjacent color pixel circuit column (i.e., the second output signal line) are multiplexed to the same first sub-processing module by one selection module. An output signal from an output signal line corresponding to another color pixel circuit column adjacent to the first output signal line (i.e., the third output signal line) uses the second sub-processing module.

[0089] The first processing buffer module is connected to all the first sub-processing modules and all the second sub-processing modules, and is used to sequentially store and perform image processing on the first output signals, second output signals and third output signals after amplification processing and analog-to-digital conversion processing, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, automatic exposure control and the like.

[0090] In the embodiment of the present application, since the number of white pixels and color pixels are different and in different rows, some sub-modules of the white pixel signal processing link and the color pixel processing link can be multiplexed, thereby saving space and energy consumption.

[0091] Furthermore, in one embodiment of the present application, the first processing buffer module includes a first demultiplexing module, a first buffer module, a second buffer module, and a first image processing module, and controlling the first processing buffer module to sequentially perform storage processing and image processing on the first target signal and the third output signal includes controlling the first demultiplexing module to store the first output signal in the first buffer module and the second output signal in the second buffer module, and controlling the second buffer module to store the third output signal, and controlling the first image processing module to perform image processing on the first output signal stored in the first buffer module to improve signal quality of the first output signal, and to perform image processing on the second output signal and the third output signal stored in the second buffer module to improve signal quality of the second output signal and the third output signal.

[0092] In this embodiment, the first processing buffer module includes a plurality of first demultiplexing modules, a plurality of first buffer modules, a plurality of second buffer modules, and a first image processing module. The first demultiplexing module is used to transmit the first output signal and the second output signal output from the first sub-processing module to different buffer modules. Specifically, the first output signal is transmitted to the first buffer module, the second output signal is transmitted to the second buffer module, and the third output signal is transmitted to the second buffer module. That is, the output signal of the white pixel circuit array is stored in the first buffer module, and the output signal of the color pixel circuit array is stored in the second buffer module.

[0093] The first image processing module further performs image processing on the signals stored in the first buffer module and the second buffer module, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, automatic exposure control, etc.

[0094] The above method performs independent buffering for the output signals of the color pixel rows and the output signals of the white pixel rows, and the first image processing module can select the output signals of the color pixel rows or the output signals of the white pixel rows at any location for post-processing, greatly expanding the variety of image signal processing options.

[0095] Furthermore, in one embodiment of the present application, when the white pixel circuit includes a plurality of sub-white pixel circuits and the color pixel circuit includes a plurality of sub-color pixel circuits, the pixel circuit row includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel circuit column includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel signal processing module includes a second processing module and a second processing buffer module, the second processing buffer module includes a second demultiplexing module, a third buffer module, a fourth buffer module and a second image processing module, and the control method includes controlling the second processing module to amplify the output signal of the output signal line and to perform analog-to-digital conversion on the output signal of the output signal line after the amplification process, controlling the second demultiplexing module to store the fourth output signal in the third buffer module and the fifth output signal in the fourth buffer module, and and controlling the second image processing module to perform image processing on the fourth output signal stored in the third buffer module to improve signal quality of the fourth output signal, and to perform image processing on the fifth and sixth output signals stored in the fourth buffer module to improve signal quality of the fifth and sixth output signals, wherein the fourth output signal is a signal of the sub-white pixel circuit output from an output signal line corresponding to the first target pixel circuit column, the first target pixel circuit column being a pixel circuit column including a sub-white pixel circuit and a sub-color pixel circuit, the fifth output signal is a signal of the sub-color pixel circuit output from an output signal line corresponding to the first target pixel circuit column, the second target processing module is a second processing module connected to the output signal line corresponding to the second target pixel circuit column, and the second target pixel circuit column being a pixel circuit column including a sub-color pixel circuit.

[0096] In this embodiment, for the composite pixel scheme, the pixel signal processing module includes a plurality of second processing modules and a second processing buffer module, and the second processing buffer module includes a plurality of second demultiplexing modules, a plurality of third buffer modules, a plurality of fourth buffer modules, and a second image processing module. The second processing modules are used to amplify and perform analog-to-digital conversion on the output signals of the output signal lines, and the second demultiplexing module transmits the output signals of the first target pixel circuit column after amplification and analog-to-digital conversion to different buffer modules (i.e., the third buffer module and the fourth buffer module) for storage. Specifically, the output signals of the first target pixel circuit column include signals of the sub-white pixel circuits (i.e., the fourth output signal) and the sub-color pixel circuits (i.e., the fifth output signal), and the fourth output signal is transmitted to the third buffer module for storage using the second demultiplexing module, and the fifth output signal is transmitted to the fourth buffer module for storage using the second demultiplexing module.

[0097] In addition, the output signal of the second target pixel circuit column only includes the signal of the sub-color pixel circuit (i.e., the sixth output signal), and the output signal of the second target pixel circuit column is subjected to amplification processing and analog-to-digital conversion processing using the second target processing module, and then directly transmitted to the fourth buffer module for storage.

[0098] The second image processing module further performs image processing on the signals stored in the third buffer module and the fourth buffer module, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, and automatic exposure control.

[0099] In the above method, the pixel signal processing module adapts to the pixel array of the composite pixel scheme, and uses different buffer modules to buffer the signals of the sub-color pixel circuits and the sub-white pixel circuits independently, thereby avoiding confusion and congestion between signals and providing convenience for the ISP to perform post-processing.

[0100] Furthermore, in one embodiment of the present application, the second processing buffer module further includes a signal combining module, and the control method further includes controlling the signal combining module to combine the output signal of the first target buffer module with the output signal of the second target buffer module, and the first target buffer module and the second target buffer module are third buffer modules that respectively store signals of two sub-white pixel circuits in adjacent rows in the target pixel group circuit.

[0101] In this embodiment, the pixel synthesis scheme may require signal fusion of same-color pixels, so same-color pixel synthesis of sub-color pixels generally occurs in pixel arrays, and signal synthesis of sub-white pixels is relatively difficult to achieve in pixel arrays.

[0102] In contrast, an embodiment of the present application provides a sub-white pixel signal fusion scheme, and when sub-color pixel signal fusion is used, a signal combining module is used to combine corresponding sub-white pixel signals. Specifically, the second processing buffer module includes a plurality of signal combining modules, and the signal combining modules are used for signals of two sub-white pixel circuits in adjacent rows in a target pixel group circuit, the signals of the two sub-white pixel circuits in adjacent rows being signals stored in the first target buffer module and the second target buffer module respectively, and the target pixel group circuit is any one of the pixel group circuits in the pixel circuit array.

[0103] The above method realizes the fusion of two adjacent sub-white pixel signals, which provides convenience for post-processing of the ISP.

[0104] Furthermore, in one embodiment of the present application, the control method further includes controlling the second image processing module to enhance the second target signal by fusing the output signal of the signal synthesis module with a second target signal, where the second target signal is a signal of a sub-color pixel circuit in the target pixel group circuit.

[0105] In this embodiment, when the sub-color pixel signals undergo signal fusion with each other and the sub-white pixel signals also undergo signal matching with each other, the sub-white pixel signal after fusion is completed and the sub-color pixel signal after fusion are paired in the same pixel group, that is, the second image processing module is used to realize the signal fusion between the sub-white pixel signal and the sub-color pixel signal in the same pixel group, thereby enhancing the photosensitivity of the sub-color pixels.

[0106] The above method provides convenience for post-processing of ISP and at the same time greatly enriches the types of image signal processing.

[0107] It should be noted that, in the image sensor control method according to the embodiment of the present application, the execution body may be an image sensor control device or a control module for executing the image sensor control method in the image sensor control device. In the embodiment of the present application, the image sensor control device according to the embodiment of the present application will be described by taking the image sensor control device executing the image sensor control method as an example.

[0108] An embodiment of the present application provides a control device for an image sensor, the image sensor comprising: a pixel circuit array and a pixel signal processing module; the pixel circuit array comprises a plurality of pixel group circuits, each pixel group circuit comprising one white pixel circuit and a plurality of color pixel circuits, the plurality of color pixel circuits being arranged surrounding the white pixel circuit; each pixel circuit row of the pixel circuit array shares a control signal line; each pixel circuit column of the pixel circuit array shares an output signal line; the pixel signal processing module is connected to the output signal line; when the pixel circuit row comprises a white pixel circuit or a color pixel circuit, and when the pixel circuit column comprises a white pixel circuit or a color pixel circuit, the pixel signal processing module comprises a selection module, a first sub-processing module, a second sub-processing module, and a first processing buffer module; as shown in FIG. 14 , the control device comprises a control module 1402, which: Controlling the selection module to transmit the first target signal to the first sub-processing module; Controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on the third output signal of the third output signal line, and analog-to-digital conversion processing on the third output signal after the amplification processing; a first processing buffer module for storing the first target signal and the third output signal and for controlling image processing on the first target signal and the third output signal; Here, the first target signal includes a first output signal of a first output signal line or a second output signal of a second output signal line, the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column is a pixel circuit column including white pixel circuits, and the color pixel circuit column is a pixel circuit column including color pixel circuits.

[0109] In this embodiment, the pixel signal processing module includes a plurality of selection modules, a first processing module, and a first processing buffer module, and the first processing module includes a plurality of first sub-processing modules and a plurality of second sub-processing modules. An output signal from an output signal line corresponding to a white pixel circuit column (i.e., the first output signal line) and an output signal from an output signal line corresponding to one adjacent color pixel circuit column (i.e., the second output signal line) are multiplexed to the same first sub-processing module by one selection module. An output signal from an output signal line corresponding to another color pixel circuit column adjacent to the first output signal line (i.e., the third output signal line) uses the second sub-processing module.

[0110] The first processing buffer module is connected to all the first sub-processing modules and all the second sub-processing modules, and is used to sequentially store and perform image processing on the first output signals, second output signals and third output signals after amplification processing and analog-to-digital conversion processing, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, automatic exposure control and the like.

[0111] In the embodiment of the present application, since the number of white pixels and color pixels are different and in different rows, some sub-modules of the white pixel signal processing link and the color pixel processing link can be multiplexed, thereby saving space and energy consumption.

[0112] Furthermore, in one embodiment of the present application, the first processing buffer module includes a first demultiplexing module, a first buffer module, a second buffer module, and a first image processing module, and the control module 1402 is further used to control the first demultiplexing module to store the first output signal in the first buffer module and the second output signal in the second buffer module, control the second buffer module to store the third output signal, and control the first image processing module to perform image processing on the first output signal stored in the first buffer module to improve signal quality of the first output signal, and to perform image processing on the second output signal and the third output signal stored in the second buffer module to improve signal quality of the second output signal and the third output signal.

[0113] Furthermore, in one embodiment of the present application, when the white pixel circuit includes a plurality of sub-white pixel circuits and the color pixel circuit includes a plurality of sub-color pixel circuits, the pixel circuit row includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel circuit column includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel signal processing module includes a second processing module and a second processing buffer module, the second processing buffer module includes a second demultiplexing module, a third buffer module, a fourth buffer module and a second image processing module, the control module 1402 further controls the second processing module to perform an amplification process on the output signal of the output signal line and to perform an analog-to-digital conversion process on the output signal of the output signal line after the amplification process, controls the second demultiplexing module to store the fourth output signal in the third buffer module and the fifth output signal in the fourth buffer module, and controls the fourth buffer module to store the second output signal in the fourth buffer module. and controlling the second image processing module to perform image processing on the fourth output signal stored in the third buffer module to improve the signal quality of the fourth output signal, and to perform image processing on the fifth and sixth output signals stored in the fourth buffer module to improve the signal quality of the fifth and sixth output signals, wherein the fourth output signal is a signal of a sub-white pixel circuit output from an output signal line corresponding to a first target pixel circuit column, the first target pixel circuit column is a pixel circuit column including a sub-white pixel circuit and a sub-color pixel circuit, the fifth output signal is a signal of a sub-color pixel circuit output from an output signal line corresponding to the first target pixel circuit column, the second target processing module is a second processing module connected to the output signal line corresponding to the second target pixel circuit column, and the second target pixel circuit column is a pixel circuit column including a sub-color pixel circuit.

[0114] Furthermore, in one embodiment of the present application, the second processing buffer module further includes a signal combining module, and the control module 1402 is further used to control the signal combining module to combine the output signal of the first target buffer module with the output signal of the second target buffer module, and the first target buffer module and the second target buffer module are third buffer modules that respectively store signals of two sub-white pixel circuits in adjacent rows in the target pixel group circuit.

[0115] Furthermore, in one embodiment of the present application, the control module 1402 is further used to control the second image processing module to blend the output signal of the signal synthesis module with a second target signal to enhance the second target signal, where the second target signal is a signal of a sub-color pixel circuit in the target pixel group circuit.

[0116] The image sensor control device 1400 in the embodiment of the present application may be a device, or may be a component, integrated circuit, or chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the non-mobile electronic device may be a server, a network-attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, and the embodiment of the present application is not specifically limited.

[0117] The image sensor control device 1400 in the embodiment of the present application may be a device having an operating system, which may be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiment of the present application is not specifically limited.

[0118] The image sensor control device 1400 according to the embodiment of the present application can implement each process implemented in the method embodiment of FIG. 13, and will not be further described here to avoid repetition of description.

[0119] Optionally, as shown in FIG. 15 , an embodiment of the present application further provides an electronic device 1500, which includes a processor 1502, a memory 1504, and a program or instruction stored in the memory 1504 and operable on the processor 1502, which, when executed by the processor 1502, can realize each process of the embodiment of the pixel array control method and achieve the same technical effect, and will not be further described here to avoid repetition.

[0120] It should be noted that the electronic devices in the embodiments of the present application include the above mobile electronic devices and non-mobile electronic devices.

[0121] FIG. 16 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application.

[0122] The electronic device 1600 includes components such as, but not limited to, a radio frequency unit 1602, a network module 1604, an audio output unit 1606, an input unit 1608, a sensor 1610, a display unit 1612, a user input unit 1614, an interface unit 1616, a memory 1618, and a processor 1620.

[0123] As will be understood by those skilled in the art, the electronic device 1600 may further include a power source (e.g., a battery) for powering each component, and the power source may be logically connected to the processor 1620 by a power management system, thereby enabling the power management system to realize functions such as charge / discharge management and power consumption management. The electronic device structure shown in Figure 16 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than those shown, or a combination of some components, or a different arrangement of components, which will not be further described here.

[0124] Here, the sensor 1610 of the electronic device 1600 includes an image sensor, which includes a pixel circuit array and a pixel signal processing module, which includes a plurality of pixel group circuits, each pixel group circuit including one white pixel circuit and a plurality of color pixel circuits, which are arranged surrounding the white pixel circuit, each pixel circuit row of the pixel circuit array sharing one control signal line, each pixel circuit column of the pixel circuit array sharing one output signal line, and the pixel signal processing module connected to the output signal line, and when the pixel circuit row includes a white pixel circuit or a color pixel circuit and when the pixel circuit column includes a white pixel circuit or a color pixel circuit, the pixel signal processing module includes a selection module, a first sub-processing module, a second sub-processing module, and a first processing buffer module. The processor 1620 Controlling the selection module to transmit the first target signal to the first sub-processing module; Controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on the third output signal of the third output signal line, and analog-to-digital conversion processing on the third output signal after the amplification processing; a first processing buffer module for storing the first target signal and the third output signal and for controlling image processing on the first target signal and the third output signal; Here, the first target signal includes a first output signal of a first output signal line or a second output signal of a second output signal line, the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line is an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column is a pixel circuit column including white pixel circuits, and the color pixel circuit column is a pixel circuit column including color pixel circuits.

[0125] In this embodiment, the pixel signal processing module includes a plurality of selection modules, a first processing module, and a first processing buffer module, and the first processing module includes a plurality of first sub-processing modules and a plurality of second sub-processing modules. An output signal from an output signal line corresponding to a white pixel circuit column (i.e., the first output signal line) and an output signal from an output signal line corresponding to one adjacent color pixel circuit column (i.e., the second output signal line) are multiplexed to the same first sub-processing module by one selection module. An output signal from an output signal line corresponding to another color pixel circuit column adjacent to the first output signal line (i.e., the third output signal line) uses the second sub-processing module.

[0126] The first processing buffer module is connected to all the first sub-processing modules and all the second sub-processing modules, and is used to sequentially store and perform image processing on the first output signals, second output signals and third output signals after amplification processing and analog-to-digital conversion processing, where the image processing specifically includes post-processing such as linear correction, defect removal, interpolation, white balance, automatic exposure control and the like.

[0127] In the embodiment of the present application, since the number of white pixels and color pixels are different and in different rows, some sub-modules of the white pixel signal processing link and the color pixel processing link can be multiplexed, thereby saving space and energy consumption.

[0128] Furthermore, in one embodiment of the present application, the first processing buffer module includes a first demultiplexing module, a first buffer module, a second buffer module, and a first image processing module, and the processor 1620 is further used to control the first demultiplexing module to store the first output signal in the first buffer module and the second output signal in the second buffer module, to control the second buffer module to store the third output signal, and to control the first image processing module to perform image processing on the first output signal stored in the first buffer module to improve the signal quality of the first output signal, and to perform image processing on the second output signal and the third output signal stored in the second buffer module to improve the signal quality of the second output signal and the third output signal.

[0129] Furthermore, in one embodiment of the present application, when the white pixel circuit includes a plurality of sub-white pixel circuits and the color pixel circuit includes a plurality of sub-color pixel circuits, the pixel circuit row includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel circuit column includes the sub-color pixel circuits, or includes the sub-white pixel circuits and the sub-color pixel circuits, the pixel signal processing module includes a second processing module and a second processing buffer module, the second processing buffer module includes a second demultiplexing module, a third buffer module, a fourth buffer module and a second image processing module, the processor 1620 further controls the second processing module to perform amplification processing on the output signal of the output signal line and to perform analog-to-digital conversion processing on the output signal of the output signal line after the amplification processing, the second demultiplexing module to store the fourth output signal in the third buffer module and the fifth output signal in the fourth buffer module, and the fourth buffer module to store the second tag. and controlling the second image processing module to perform image processing on the fourth output signal stored in the third buffer module to improve the signal quality of the fourth output signal, and controlling the second image processing module to perform image processing on the fifth and sixth output signals stored in the fourth buffer module to improve the signal quality of the fifth and sixth output signals, wherein the fourth output signal is a signal of a sub-white pixel circuit output from an output signal line corresponding to a first target pixel circuit column, the first target pixel circuit column being a pixel circuit column including a sub-white pixel circuit and a sub-color pixel circuit, the fifth output signal is a signal of a sub-color pixel circuit output from an output signal line corresponding to the first target pixel circuit column, the second target processing module is a second processing module connected to the output signal line corresponding to the second target pixel circuit column, and the second target pixel circuit column being a pixel circuit column including a sub-color pixel circuit.

[0130] Furthermore, in one embodiment of the present application, the second processing buffer module further includes a signal combining module, and the processor 1620 is further used to control the signal combining module to combine the output signal of the first target buffer module with the output signal of the second target buffer module, and the first target buffer module and the second target buffer module are third buffer modules that respectively store signals of two sub-white pixel circuits of adjacent rows in the target pixel group circuit.

[0131] Furthermore, in one embodiment of the present application, the processor 1620 is further used to control the second image processing module to enhance the second target signal by blending the output signal of the signal synthesis module with the second target signal, where the second target signal is a signal of a sub-color pixel circuit in the target pixel group circuit.

[0132] It should be understood that in the embodiment of the present application, the radio frequency unit 1602 may be used to transmit and receive information or transmit and receive signals during a call, specifically, to receive downlink data from a base station or transmit uplink data to a base station, and the radio frequency unit 1602 may include, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, etc.

[0133] The network module 1604 provides users with wireless broadband Internet access, allowing them to, for example, send and receive email, browse web pages, and access streaming media.

[0134] The audio output unit 1606 can convert audio data received by the radio frequency unit 1602 or the network module 1604 or stored in the memory 1618 into an audio signal and output it as voice. The audio output unit 1606 can also provide audio output related to a specific function performed by the electronic device 1600 (e.g., ring tone, message tone, etc.). The audio output unit 1606 can include a speaker, a buzzer, a handset, etc.

[0135] The input unit 1608 is used to receive audio or video signals. The input unit 1608 may include a graphics processing unit (GPU) 16082 and a microphone 16084. The graphics processor 16082 processes image data of still or video images captured by an image capture device (e.g., a camera) in a video capture mode or an image capture mode. The processed image frames may be displayed on the display unit 1612, stored in the memory 1618 (or other storage medium), or transmitted via the radio frequency unit 1602 or the network module 1604. The microphone 16084 may receive voice and process the voice as audio data. In a telephone call mode, the processed audio data may be converted into a format that can be transmitted to a mobile communication base station via the radio frequency unit 1602 and output.

[0136] The electronic device 1600 further includes at least one sensor 1610, such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, a light sensor, a motion sensor, and other sensors.

[0137] The display unit 1612 is used to display information input by a user or information provided to a user, and may include a display panel 16122, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.

[0138] The user input unit 1614 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. Specifically, the user input unit 1614 includes a touch panel 16142 and other input devices 16144. The touch panel 16142, also known as a touch screen, can collect user touch operations on or near the touch panel 16142. The touch panel 16142 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch direction and detects signals generated by the touch operation and transmits the signals to the touch controller. The touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and transmits them to the processor 1620, and receives and executes commands sent from the processor 1620. The other input devices 16144 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control buttons, switch buttons, etc.), a trackball, a mouse, and a control lever, which will not be described further herein.

[0139] Furthermore, the touch panel 16142 may be overlaid on the display panel 16122, and when the touch panel 16142 detects a touch operation on or near it, it transmits the detected touch operation to the processor 1620 to determine the type of the touch event, and the processor 1620 then provides a corresponding visual output to the display panel 16122 based on the type of touch event. The touch panel 16142 and the display panel 16122 may be two independent components or may be integrated into one component.

[0140] The interface unit 1616 is an interface that connects an external device to the electronic device 1600. For example, the external device may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, an earphone port, etc. The interface unit 1616 may be used to receive input (e.g., data information, power, etc.) from the external device and transmit the received input to one or more elements within the electronic device 1600, or may be used to transmit data between the electronic device 1600 and the external device.

[0141] The memory 1618 may be used to store software programs and various data. The memory 1618 may mainly include a program storage area and a data storage area. Here, the program storage area may store an operating system, an application program required for at least one function (e.g., audio playback function, image playback function, etc.), etc., and the data storage area may store data generated by use of the mobile terminal (e.g., audio data, phone book, etc.). The memory 1618 may include high-speed random access memory, or may include non-volatile memory, such as at least one magnetic disk memory device, flash memory device, or other volatile solid-state memory device.

[0142] Processor 1620 runs or executes software programs and / or modules stored in memory 1618, accesses data stored in memory 1618, performs various functions of electronic device 1600, and processes data to monitor the overall operation of electronic device 1600. Processor 1620 may include one or more processing units, and preferably, processor 1620 may integrate an application processor and a modem processor. Here, the application processor is primarily for processing the operating system, user interface, and application programs, and the modem processor is primarily for processing wireless communications.

[0143] It should be noted that, in this specification, the terms "comprise," "include," "includes," or any other variant thereof are intended to cover the non-exclusive "comprise," whereby a process, method, article, or apparatus comprising a set of elements not only includes those elements, but also other elements not expressly listed or inherent in such process, method, article, or apparatus. Absent further limitations, an element defined by the phrase "comprises one of" does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising that element. It should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may include performing functions in an essentially simultaneous manner or in the reverse order based on the functionality involved. For example, the described method can be performed in a different order than described, and various steps can be added, omitted, or combined. Furthermore, features described with reference to some examples can be combined in other examples.

[0144] As will be apparent to those skilled in the art from the above description of the embodiments, the methods of the above embodiments can be realized in the form of software and a necessary general-purpose hardware platform. Of course, they can also be realized in hardware, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of the present application, in substance or in part contributing to the prior art, may be embodied in the form of a computer software product. This computer software product is stored in a storage medium (e.g., ROM / RAM, magnetic disk, optical disk) and includes some instructions for causing a terminal (which may be a mobile phone, computer, server, network device, etc.) to execute the methods described in each embodiment of the present application.

[0145] Although the above describes the embodiments of the present application in conjunction with the drawings, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not limiting. Those skilled in the art can implement many forms under the guidance of the present application without departing from the spirit and scope of protection of the claims, and all forms fall within the scope of protection of the present application.

Claims

1. An image sensor, a pixel circuit array including a plurality of pixel group circuits, each of the pixel group circuits including one white pixel circuit and at least two color pixel circuits, the at least two color pixel circuits being arranged surrounding the white pixel circuit, the pixel circuit array including at least two pixel circuit rows and at least two pixel circuit columns, each pixel circuit row of the pixel circuit array sharing one control signal line, and each pixel circuit column of the pixel circuit array sharing one output signal line, wherein the pixel circuit row includes the white pixel circuit or the color pixel circuit, and the pixel circuit column includes the white pixel circuit or the color pixel circuit; a pixel signal processing module connected to the output signal line; The pixel signal processing module includes: a plurality of selection modules, each of which is connected to a first output signal line and a second output signal line, wherein the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column being a pixel circuit column including the white pixel circuits, and the color pixel circuit column being a pixel circuit column including the color pixel circuits; A first processing module, the first processing module comprising: a plurality of first sub-processing modules, the first sub-processing modules being connected to the selection module; a first processing module including a plurality of second sub-processing modules, each second sub-processing module being connected to a third output signal line, the third output signal line being an output signal line corresponding to another of the color pixel circuit columns adjacent to the white pixel circuit column; a first processing buffer module connected to the first processing module.

2. The first processing buffer module a plurality of first demultiplexing modules, said first demultiplexing modules being connected to said first sub-processing module; a plurality of first buffer modules, the first buffer modules being connected to the first demultiplexing module; a plurality of second buffer modules, wherein the second buffer modules are connected to the first demultiplexing module or the second buffer modules are connected to the second sub-processing module; The image sensor of claim 1 , further comprising: a first image processing module connected to the first buffer module and the second buffer module.

3. The pixel signal processing module includes: The image sensor according to claim 1 , further comprising a plurality of first sampling modules, the first sampling modules being connected to output ends of the output signal lines.

4. When the white pixel circuit includes a plurality of sub-white pixel circuits and the color pixel circuit includes a plurality of sub-color pixel circuits, the pixel circuit row includes the sub-color pixel circuit, or includes the sub-white pixel circuit and the sub-color pixel circuit; The image sensor according to claim 1 , wherein the pixel circuit column includes the sub-color pixel circuit or includes the sub-white pixel circuit and the sub-color pixel circuit.

5. The pixel signal processing module includes: a plurality of second processing modules, the second processing modules being connected to the output signal line; a second processing buffer module, the second processing buffer module comprising: a second processing buffer module including a plurality of second demultiplexing modules, the second demultiplexing modules connected to a first target processing module, the first target processing module being a second processing module connected to an output signal line corresponding to a first target pixel circuit column, the first target pixel circuit column being a pixel circuit column including the sub-white pixel circuit and the sub-color pixel circuit; a plurality of third buffer modules, the third buffer modules being connected to the second demultiplexing module; a plurality of fourth buffer modules, the fourth buffer modules being connected to the second demultiplexing module or the fourth buffer modules being connected to a second target processing module, the second target processing module being a second processing module connected to an output signal line corresponding to a second target pixel circuit column, the second target pixel circuit column being a pixel circuit column including the sub-color pixel circuits; The image sensor of claim 4 , further comprising a second image processing module, the second image processing module being connected to the third buffer module and the fourth buffer module.

6. The second processing buffer module 6. The image sensor of claim 5, further comprising a plurality of signal combining modules, the signal combining modules being connected to the second image processing module, the first target buffer module, and the second target buffer module, the first target buffer module and the second target buffer module being third buffer modules each storing signals of two sub-white pixel circuits in adjacent rows in a target pixel group circuit.

7. The pixel signal processing module includes: The image sensor of claim 5 , further comprising a plurality of second sampling modules, the second sampling modules being connected between the second processing module and the output signal line.

8. An electronic device comprising the image sensor according to any one of claims 1 to 7.

9. A method for controlling an image sensor, the image sensor comprising: a pixel circuit array and a pixel signal processing module; the pixel circuit array comprises a plurality of pixel group circuits, each of the pixel group circuits comprising one white pixel circuit and a plurality of color pixel circuits, the plurality of color pixel circuits being arranged surrounding the white pixel circuit; each pixel circuit row of the pixel circuit array shares a control signal line; each pixel circuit column of the pixel circuit array shares a control signal line; and the pixel signal processing module is connected to the output signal line; When the pixel circuit row includes the white pixel circuit or the color pixel circuit, and the pixel circuit column includes the white pixel circuit or the color pixel circuit, the pixel signal processing module: a plurality of selection modules, each of which is connected to a first output signal line and a second output signal line, wherein the first output signal line is an output signal line corresponding to a white pixel circuit column, the second output signal line is an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column being a pixel circuit column including the white pixel circuits, and the color pixel circuit column being a pixel circuit column including the color pixel circuits; A first processing module, the first processing module comprising: a plurality of first sub-processing modules, the first sub-processing modules being connected to the selection module; a first processing module including a plurality of second sub-processing modules, each second sub-processing module being connected to a third output signal line, the third output signal line being an output signal line corresponding to another of the color pixel circuit columns adjacent to the white pixel circuit column; a first processing buffer module connected to the first processing module; The control method includes: controlling the selection module to transmit a first target signal to the first sub-processing module; Controlling the first sub-processing module to perform amplification and analog-to-digital conversion processing on the first target signal, and controlling the second sub-processing module to perform amplification processing on a third output signal from a third output signal line, and analog-to-digital conversion processing on the third output signal after amplification processing; and controlling the first processing buffer module to store the first target signal and the third output signal, and to perform image processing on the first target signal and the third output signal; the first target signal includes a first output signal on a first output signal line or a second output signal on a second output signal line, the first output signal line being an output signal line corresponding to a white pixel circuit column, the second output signal line being an output signal line corresponding to one color pixel circuit column adjacent to the white pixel circuit column, the third output signal line being an output signal line corresponding to another color pixel circuit column adjacent to the white pixel circuit column, the white pixel circuit column being a pixel circuit column including the white pixel circuits, and the color pixel circuit column being a pixel circuit column including the color pixel circuits; The method for controlling an image sensor, wherein the selection module selects the first output signal or the second output signal as the first target signal.

10. the first processing buffer module includes a first demultiplexing module, a first buffer module, a second buffer module and a first image processing module; The control of the first processing buffer module to sequentially perform storage processing and image processing on the first target signal and the third output signal includes: controlling the first demultiplexing module to store the first output signal in the first buffer module and the second output signal in the second buffer module; controlling the second buffer module to store the third output signal; 10. The control method of claim 9, further comprising controlling the first image processing module to perform image processing on the first output signal stored in the first buffer module to improve signal quality of the first output signal, and to perform image processing on the second output signal and the third output signal stored in the second buffer module to improve signal quality of the second output signal and the third output signal.

11. when the white pixel circuit includes a plurality of sub-white pixel circuits and the color pixel circuit includes a plurality of sub-color pixel circuits, the pixel circuit row includes the sub-color pixel circuits, or the sub-white pixel circuits and the sub-color pixel circuits, the pixel circuit column includes the sub-color pixel circuits, or the sub-white pixel circuits and the sub-color pixel circuits, the pixel signal processing module includes a second processing module and a second processing buffer module, the second processing buffer module includes a second demultiplexing module, a third buffer module, a fourth buffer module and a second image processing module; The control method includes: controlling the second processing module to amplify the output signal from the output signal line and to perform analog-to-digital conversion on the output signal from the output signal line after the amplification; controlling the second demultiplexing module to store a fourth output signal in the third buffer module and a fifth output signal in the fourth buffer module; controlling the fourth buffer module to store a sixth output signal of the second target processing module; and controlling the second image processing module to perform image processing on the fourth output signal stored in the third buffer module to improve signal quality of the fourth output signal, and to perform image processing on the fifth output signal and the sixth output signal stored in the fourth buffer module to improve signal quality of the fifth output signal and the sixth output signal, 10. The control method of claim 9, wherein the fourth output signal is a signal of a sub-white pixel circuit output from an output signal line corresponding to a first target pixel circuit column, the first target pixel circuit column being a pixel circuit column including the sub-white pixel circuit and the sub-color pixel circuit, the fifth output signal is a signal of a sub-color pixel circuit output from an output signal line corresponding to the first target pixel circuit column, the second target processing module being a second processing module connected to an output signal line corresponding to a second target pixel circuit column, and the second target pixel circuit column being a pixel circuit column including the sub-color pixel circuit.

12. the second processing buffer module further includes a signal synthesis module; The control method includes:

12. The control method of claim 11, further comprising: controlling the signal combining module to combine the output signal of a first target buffer module with the output signal of a second target buffer module, wherein the first target buffer module and the second target buffer module are third buffer modules each storing signals of two sub-white pixel circuits in adjacent rows in a target pixel group circuit.

13. 13. The control method of claim 12, further comprising: controlling the second image processing module to enhance the second target signal by fusing the output signal of the signal synthesis module with a second target signal, wherein the second target signal is a signal of a sub-color pixel circuit in the target pixel group circuit.

14. An electronic device comprising a processor, a memory, and a program or instructions stored in the memory and operable on the processor, the program or instructions implementing the steps of the image sensor control method of any one of claims 9 to 13 when executed by the processor.

Images