Generation and selection of commonly routable via mesh specifications in integrated circuits

Abstract

An aspect of the invention includes generating a set of via mesh specifications for cells in an integrated circuit. Each via mesh specification defines one or more straps for each layer above a first layer including one or more pins forming pin terminals, up to a top layer connecting the cell to a net for interconnecting the cell to one or more other cells, and defines one or more vias interconnecting adjacent ones of the layers. An aspect also includes verifying whether each via mesh specification is a commonly routable via mesh specification that ensures that the cell will interconnect with other cells through a net while satisfying all design rules, and including only the commonly routable via mesh specifications from the set of via mesh specifications in a library of via mesh specifications. The library is used to define and fabricate the integrated circuit.

Description

[Technical Field]

[0001] The present invention relates generally to integrated circuit development, and more particularly to the generation and selection of universally routable via mesh specifications in integrated circuits. [Background technology]

[0002] The development of an integrated circuit (i.e., a chip) involves several stages from design to fabrication. Some aspects of development are done iteratively to ensure that the final manufactured chip meets all design requirements. Also, some aspects of design may be done hierarchically. An example of an organization of a chip is as a set of interconnected cells. Each cell contains a number of interconnected components that allow the cell to perform a specific function (e.g., OR gate, NAND gate). The cells may be standard cells selected from a library to perform a specific function.

[0003] Cell interconnections are made through wires routed across multiple levels (i.e., metal layers) with vias (i.e., vertical interconnects) facilitating connections between stacked metal layers. Chip timing can be improved by using higher-level metal layers, which can accommodate thicker metal wires. However, this timing improvement must be balanced against the increased density that results from routing too many interconnects in the upper metal layers, because increased density increases interference and negatively impacts chip performance. Each cell may have a different pin layout and different placement options relative to the power grid of a particular chip. Placement refers to the specific location within the chip and affects routability. Routing refers to the path (e.g., wire width, metal layer) used for interconnection. A cell is not routable if it cannot interconnect with other cells to meet timing, power, and other requirements based on its specific placement. Summary of the Invention

[0004]

[0006] Embodiments of the present invention are directed to systems and methods for generating and selecting commonly routable via mesh specifications during integrated circuit development. As a non-limiting example, a computer-implemented method includes generating a set of via mesh specifications for cells within an integrated circuit. Each via mesh specification defines one or more straps in each layer above the first layer, including one or more pins forming pin terminals, up to the top layer, connecting the cell to a net for interconnecting the cell to one or more other cells. Each via mesh specification also includes one or more vias interconnecting adjacent ones of the layers. The computer-implemented method also includes verifying whether each via mesh specification in the set of via mesh specifications is a commonly routable via mesh specification, where a commonly routable via mesh specification ensures that cells interconnect with other cells through nets while satisfying all design rules, and including only those via mesh specifications from the set of via mesh specifications that are commonly routable in a via mesh specification library. A library of via mesh specifications is used to define and fabricate integrated circuits.

[0005] Other embodiments of the present invention implement the functionality of the above methods in computer systems and computer program products.

[0006] Further technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings.

[0007] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. These and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram of a system for generating and selecting commonly routable via mesh specifications during integrated circuit development, according to one or more embodiments. [Figure 2A] 1 is a three-dimensional representation of a via mesh generated in accordance with one or more embodiments of the present invention. [Figure 2B] 2B is a representation of a via mesh specification generated for the exemplary via mesh shown in FIG. 2A in accordance with one or more embodiments of the present invention. [Figure 3] 1 is a process flow of a method for generating a via mesh specification according to an embodiment of the present invention. [Figure 4] FIG. 1 illustrates aspects of a wiring analysis for an exemplary cell, in accordance with one or more embodiments of the present invention. [Figure 5] FIG. 1 illustrates aspects of a wiring analysis for an exemplary cell, in accordance with one or more embodiments of the present invention. [Figure 6] 3 illustrates an exemplary net forming a logical connection between an input pin of one cell and an output pin of another cell, according to an exemplary embodiment of the present invention. [Figure 7] 1 is a process flow for a method of assigning pin constraints that facilitates selection among commonly routable via mesh specifications, in accordance with one or more embodiments of the present invention. [Figure 8] 1 is a process flow for a method of selecting a via mesh as part of an optimization process, according to one or more embodiments of the present invention. [Figure 9] 1 is a process flow for a method of fabricating an integrated circuit according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The diagrams shown herein are exemplary. There may be many variations to the diagrams or the operations described therein without departing from the scope of the present invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" and variations thereof refer to having a communication path between two elements and do not imply a direct connection between the elements without an intervening element / connection between them. All of these variations are considered part of this specification.

[0010] As mentioned earlier, the cells that make up a chip are interconnected to perform the chip's overall function. Each cell involves the interconnection of components that together perform the cell's function (e.g., multiplication, AND gate). A via mesh provides multiple conductive paths from one or more points on one layer to one or more points on another layer. At the first level, the via mesh contains interconnected shapes (i.e., wires and vias) that connect to pin terminals, which may consist of a single pin or a set of separate pins that are logically treated as one pin. At each subsequent layer, one or more straps, which are conductive strips, form conductive paths that connect to straps on the adjacent layer through one or more vias. Straps within one layer are oriented parallel to each other, while straps on adjacent layers may be oriented differently (e.g., orthogonal) or parallel to each other. Routers that connect one or more pins of a cell to pins of other cells, which may or may not include a via mesh, connect only to straps on the highest level of the via mesh. The number of layers from one or more pins to the highest level defines the height of the via mesh. The redundancy provided by straps and vias results in a reduced resistance connection from one or more pins to the upper layer. The number of straps and vias determines the resistance. The reduced resistance is called an increased strength of the via mesh.

[0011] Embodiments of the present invention relate to the generation and selection of commonly routable via mesh specifications for integrated circuits. The via mesh specification provides a via mesh router with the required number of straps and vias for each metal layer of a cell. That is, the via mesh specification defines the via mesh structure and indicates the via mesh height. A given cell may have two or more via mesh specifications associated with it, and each via mesh specification may provide a different resistance and corresponding strength.

[0012] Conventional techniques for generating one or more via mesh specifications for cells do not consider common routability. A commonly routable via mesh specification is one that has a feasible route regardless of the placement of the cell within the integrated circuit. Thus, using conventional techniques, a via mesh specification selected from a library may not have a feasible route based on the placement of the cell and the design rules established for the chip. As detailed herein, cells with similar characteristics are grouped together, and the via mesh specification for that group is guaranteed to be routable regardless of placement. Thus, a specific via mesh with a specific height and strength can be selected from the via mesh specifications in the library based on the corresponding mesh specification and timing and other requirements, without any potential routing issues associated with the selected via mesh specification.

[0013] As will also be described in detail, the selection of one of the via mesh specifications may be based on the timing needs of the interconnect wires (i.e., nets) external to the via mesh, in addition to the resistance-capacitance (RC) tables associated with each via mesh specification. Specifically, the naming convention for pin constraints already used in conventional routing tools is modified to indicate via mesh strength in addition to net characteristics. Thus, the assignment of pin constraints by the routing tool corresponds to the selection of a via mesh specification from the commonly routable via mesh specifications available in the library for that cell type.

[0014] FIG. 1 is a block diagram of a system 100 for generating and selecting commonly routable via mesh specifications during the development of an integrated circuit 120, according to one or more embodiments. The various metal layers 205 (FIG. 2) that comprise the integrated circuit 120 are not shown in FIG. 1 . An exemplary cell 125 that comprises the integrated circuit 120 is shown. The system 100 includes a processing system 110 that is used to generate the design that is ultimately fabricated into the integrated circuit 120. The steps required to fabricate the integrated circuit 120 are well known and are briefly described herein. Once the physical layout is determined based in part on the selection of a via mesh specification from among the commonly routable via mesh specifications developed according to embodiments of the present invention, the determined physical layout is provided to an IC foundry. Based on the determined physical layout, masks are generated for each layer of the integrated circuit. The wafer is then processed in a mask sequence. This processing includes photolithography and etching, as further described with reference to FIG. 9 .

[0015] The processing system 110 includes one or more central processing units (processors) 21 a, 21 b, 21 c, etc. (collectively or generally referred to as processors 21 and / or processing devices). According to one or more embodiments of the present invention, each processor 21 may include a reduced instruction set computer (RISC) microprocessor. The processors 21 are coupled to system memory (e.g., random access memory (RAM) 24) and various other components via a system bus 33. A read-only memory (ROM) 22 is coupled to the system bus 33 and may include a basic input / output system (BIOS) that controls certain basic functions of the processing system 110.

[0016] Also shown are an input / output (I / O) adapter 27 and a communications adapter 26 coupled to the system bus 33. The I / O adapter 27 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 23 and / or a tape storage drive 25, or any other similar component. The I / O adapter 27, the hard disk 23, and the tape storage device 25 are collectively referred to herein as mass storage 34. An operating system 40 for execution on the processing system 110 may be stored in the mass storage 34. The RAM 22, the ROM 24, and the mass storage 34 are examples of memory 19 of the processing system 110. A network adapter 26 interconnects the system bus 33 with an external network 36, enabling the processing system 110 to communicate with other similar systems.

[0017] A display (e.g., a display monitor) 35 is connected to the system bus 33 by a display adapter 32, which may include a graphics adapter and video controller to improve performance for graphics-intensive applications. According to one or more embodiments of the present invention, adapters 26, 27, and / or 32 may be connected to one or more I / O buses that are connected to the system bus 33 through an intermediate bus bridge (not shown). Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Additional input / output devices are shown connected to the system bus 33 via a user interface adapter 28 and a display adapter 32. A keyboard 29, a mouse 30, and speakers 31 may be interconnected to the system bus 33 through a user interface adapter 28, which may include, for example, a super I / O chip that combines multiple device adapters into a single integrated circuit.

[0018] According to one or more embodiments of the present invention, processing system 110 includes a graphics processing unit 37. Graphics processing unit 37 is specialized electronic circuitry designed to manipulate and modify memory to speed up the creation of images in a frame buffer for output to a display. Generally, graphics processing unit 37 has a highly parallel architecture that makes it very efficient for manipulating computer graphics and image processing, making it more effective than a general-purpose CPU for algorithms in which the processing of large blocks of data is performed in parallel.

[0019] Thus, as configured herein, processing system 110 has processing capabilities in the form of processor 21, storage capabilities including system memory (e.g., RAM 24), and mass storage 34, input means such as keyboard 29 and mouse 30, and output capabilities including speaker 31 and display 35. According to one or more embodiments of the present invention, a portion of the system memory (e.g., RAM 24) and mass storage 34 collectively store an operating system, such as IBM® Corporation's AIX® operating system, for coordinating the functionality of the various components illustrated in processing system 110.

[0020] 2A and 2B illustrate an example via mesh 200 of an example cell 125 and a corresponding representation associated with a via mesh specification 250 generated in accordance with one or more embodiments of the present invention. FIG. 2A illustrates a three-dimensional representation of via mesh 200. Pins 210a, 210b (broadly referred to as 210) are shown on a first layer 205a (broadly referred to as 205). Straps 220a, 220b (broadly referred to as 220) are shown on a second layer 205b. As FIG. 2A illustrates, pins 210 and straps 220 are parallel, with vias 230 connecting each pin 210 to a corresponding strap 220. As previously mentioned, pins 210 and straps 220 on adjacent layers may alternatively be oriented differently (e.g., orthogonal). Another strap 220c is shown in the third layer 205c, which is the top layer of the exemplary via mesh structure 200. The straps 220c in the third layer 205c are orthogonal to the straps 220a, 220b in the second layer 205b. The number of layers 205 determines the height of the via mesh 200.

[0021] Vias 230 facilitate connections between pins 210 on the first layer 205a and straps 220a and 220b on the second layer 205b, and additional vias facilitate connections between each of straps 220a and 220b on the second layer 205b and strap 220c on the third layer 205c. The straps 220 and vias 230 form a via mesh 200. A routing tool called a router connects pins 210 of cells 125 through nets 600 (FIG. 6) and through the via mesh 200 of cells 125 to one or more other cells 125. Specifically, the router connects cells 125 to nets 600 at accesses 225 only at the top level 205 (i.e., the third layer 205c in the illustrated example). As previously mentioned, via mesh 200 (e.g., straps 220 and vias 230) provide redundancy in the connections from nets 600 to pins 210. The increased redundancy is proportional to the increased strength and decreased resistance of via mesh 200.

[0022] FIG. 2B illustrates a representation of a via mesh specification 250 generated for the exemplary via mesh 200 shown in FIG. 2A in accordance with one or more embodiments of the present invention. The via mesh specification 250 defines the structure of the via mesh 200 and provides the router with the number of wires and vias in each layer 205. The exemplary via mesh specification 250 depicted in FIG. 2B indicates that there are two pins 210 in the first layer 205a (i.e., metal layer 1 (M1)) connected by respective vias 230 to two straps 220 in the second layer 205b (i.e., metal layer 2 (M2)). An additional via 230 allows a strap 220c in the third layer 205c (i.e., metal layer 3 (M3)) to connect to both straps 220 in the second layer 205b, and thereby to both pins 210 in the first layer 205a. Using the number of straps 220 in M2 (2) and the number of straps 220 in M3 (1), the via mesh specification 250 can be expressed as {2,1}. This means that the number of metal layers, and therefore the height of the via mesh 200, is three, and also specifies the number of straps 220 in the second and all subsequent layers 205. As previously mentioned, exemplary embodiments of the present invention relate to generating a library of via mesh specifications 250, each guaranteed to be routable regardless of the placement of the cells 200. Routability is further discussed with reference to FIGS. 3-5.

[0023] FIG. 3 illustrates a process flow for a method 300 for generating a commonly routable via mesh specification 250 according to an embodiment of the present invention. At block 310, performing cell analysis refers to collecting statistics for each cell 200, including the number of input terminals, the number of input pins 210, the number of output terminals, the number of output pins 210, the cell width, and the cell height. A pin terminal refers to a logical representation of one or more pins 210. That is, a pin terminal may refer to a single pin 210 or a disjoint set of pins 210 logically treated as one. At block 320, grouping of cells 125 may be based on various cell statistics. For example, cells 125 may be grouped according to the number of output pins 210 versus the cell height, the number of input pins 210 versus the cell height, or the number of output terminals versus the number of input terminals. At block 330, it is determined whether a via mesh specification 250 has been defined for the group considering all cells 125 in the group. If so, the method 300 ends at block 360 with a completed library of via mesh specifications 250 that are compatible with any of the group's cells 200. If not, the processing of blocks 340 and 350 occurs iteratively, as shown.

[0024] At block 340, defining the via mesh specification 250 includes obtaining a resistance estimate for each via mesh specification 250 to be generated. A maximum strength via mesh 200 may be created for each group of cells 125, and then less-strength options for the via mesh 200 may be derived. At block 350, as a result of verifying routability, only commonly routable (i.e., routable regardless of placement) via mesh specifications 250 are retained in the library. Routability refers to the ability of cells 125 to interconnect with other cells 125 through nets 600 while satisfying all design rules. Generally, individual and packed placement scenarios are considered for each cell 125, as further described with reference to FIGS. 4 and 5. Any via meshes 200 that are not deemed commonly routable are removed from the via mesh specification library entry for that group of cells 125.

[0025] 3 shows, the definition of via mesh specifications (block 340) and verification of routability (block 350) are performed iteratively until all via mesh options for all cells 125 in a group have been considered. The determination of routability does not require the actual layout of a given via mesh 200. Thus, numerous via mesh options of various strengths and heights may be examined for routability in accordance with one or more embodiments of the present invention. Only via mesh specifications 250 that are routable regardless of placement are maintained in the library (block 360).

[0026] FIG. 4 illustrates aspects of the routing analysis that is part of the processing of block 350 for an exemplary cell 125, in accordance with one or more embodiments of the present invention. The statistics for the exemplary cell 125 include a number of input terminals of 2, two input pins 210 of shape A, two input pins 210 of shape B, a number of output terminals of 1, and one output pin 210 of shape Y. For example, the cell width may be 480 nanometers (nm) and the cell height may be 324 nm. As a result of these statistics, the exemplary cell 125 may be grouped with certain other cells 125. As shown, test cases are created for every placement of the cell 125 relative to the M2 (i.e., metal layer 2) grid of power staples 410. That is, as shown, a given via mesh option for a given cell 125 is repeated for each possible placement. Routing tracks and design rules are analyzed to determine free tracks on each layer 205. Multiple via meshes 200 can be constructed for each cell 125, so that the available resources are divided among the total number of cell via mesh straps.

[0027] The process of checking for routability at different placements is repeated for each cell 125 and for each possible via mesh 200 of the cells 125 in the group. The number of locations to check is calculated as the pitch of the power staple grid 410 divided by the placement pitch (i.e., the pitch of the placement grid). The result of the calculation, and therefore the number of placements each via mesh 200 must be checked for, may vary based on the specific chip technology. As previously mentioned, this process does not require that any of the via meshes 200 be actually pre-constructed. Instead, different placement options manifest themselves as different allocations of routing resources to the power grid. Based on this process, placement constraints are found for each cell 125 in the group. That is, if a given cell 125 with a given via mesh 200 cannot be placed at all of the locations shown in FIG. 4 according to the design rules, the via mesh specification 250 for that via mesh 200 is not added to the library for that group (block 360). In this way, any via mesh 200 placement constraints of any cell 125 are passed on to all cells 125 in that group.

[0028] FIG. 5 illustrates aspects of the routing analysis that is part of the processing of block 350 for an example cell 125, in accordance with one or more embodiments of the present invention. While FIG. 4 illustrates various placements for the power staple grid 410 of M2, FIG. 5 illustrates a pack placement scenario. Via meshes 200 found to be routable according to the placement illustrated in FIG. 4 are further explored in this pack placement scenario, which involves the cell 125 being replicated as shown. In the pack placement scenario, the cell 125 with the examined via mesh 200 is constrained not only by the power staples 410 but also by adjacent via meshes 200. A via mesh 200 is not routable if the router cannot insert the required number of wires or vias. If the reason for the routing failure is fundamental to the design of the via mesh 200, the corresponding via mesh specification 250 cannot be included in the library at block 360. As a result of the routing analysis of block 350, any via mesh specifications 250 included in the library (block 360) for a group of cells 125 will be commonly routable (i.e., routable regardless of placement).

[0029] FIG. 6 illustrates an exemplary net 600 forming a logical connection between an input pin 210 of one cell 125a and an output pin 210 of another cell 125b, according to an exemplary embodiment of the present invention. Both exemplary cells 125a and 125b are shown with a representation of a via mesh specification 250. However, according to an alternative embodiment of the present invention, only one of the cells 125a and 125b may have a via mesh 200. The wire code (WC) indicates constraints imposed on the net 600. The WC may indicate, for example, a minimum wire width and spacing. The width is based on timing criticality, with more critical nets having larger minimum wire widths. The used layer (UL) is a constraint on the net 600 indicating the longest wire and the wire that interconnects two portions of the net 600, each of which connects to one of the cells 125a and 125b, as shown. The UL may be a range of layers 205 or, as shown in this exemplary case, a single layer 205. The UL is generally located on a higher tier 205 based on the increased timing criticality of the net 600 .

[0030] As shown in FIG. 6 , connecting the input pin 210 of one cell 125 a with the output pin 210 of another cell 125 b requires not only a net 600 but also a via mesh 200 for one or both of the cells 125. The via mesh 200 for a cell 125 is selected from among available commonly routable via mesh specifications 250 generated in accordance with one or more embodiments of the present invention and stored in a library for the group to which the cell 125 belongs. The selected via mesh 200 must be compatible with the net 600, taking into account both timing and routing congestion considerations. As further explained with reference to FIGS. 7 and 8 , pin terminal constraints, referred to as pin constraints 760 ( FIG. 7 ), which are created to indicate net specifications, may be modified to also indicate the via mesh specification 250 to be selected from the library in accordance with one or more embodiments of the present invention. That is, each pin constraint 760 includes information about the corresponding via mesh specification 250. The corresponding via mesh specification 250 may or may not be among the commonly routable via mesh specifications 250 in the library populated by block 360, as further described with reference to FIG.

[0031] FIG. 7 illustrates a process flow for a method 700 for assigning pin constraints 760 that facilitate selection among commonly routable via mesh specifications 250, according to one or more embodiments of the present invention. The process illustrated in FIG. 7 may occur any time after the structure of the nets 600 has been defined. At block 710, reading optional design properties refers to design properties that may limit the strength of the via mesh 200 that can be used. At block 720, a check is made to see if any nets 600 interconnecting cells 125 remain that have not already been processed for assigning pin constraints 760. If not, the process flow is completed as shown. If the check at block 720 indicates that there is at least one net 600 that has not yet been processed, a check is made at block 730. At block 730, it is determined whether any pin terminals (i.e., a pin 210 or set of pins 210) remain that cannot be assigned pin constraints 760. If not, the check at block 720 is repeated. If there is at least one pin terminal that does not have a pin constraint 760 assigned, processing in block 740 is performed.

[0032] At block 740, the process includes obtaining properties of the net 600, the pin terminal, and the cell 125. Assigning pin constraints 760 to the pin terminal at block 750 refers to selecting from an existing lookup table of pin constraints 760. The table of pin constraints 760 is predefined with a corresponding table of resistance and capacitance (RC) entries.

[0033] An exemplary pin constraint 760 is shown. As shown, the pin constraint 760 modifies the traditional pin constraint naming convention so that cell properties are encoded in the name along with the net 600, more specifically, the UL properties. The cell 125 properties that are part of the pin constraint 760 include the pin terminal type (i.e., input or output), the pin 210 layer (e.g., the first metal layer, M1), the pin 210 width (e.g., in micrometers (microns)), and the number of pins 210 (i.e., the number of pins that must be connected). The UL properties that are part of the pin constraint 760 include the layer 205 identification, the minimum width according to the wire code in the UL, and a constraint subgroup property according to the wire code (e.g., 0, 1, 2) that indicates the strength of the via mesh 200 for the cell 125.

[0034] As previously mentioned, the process illustrated in FIG. 7 may occur at any time. The pin constraints 760 assigned in block 750 may not match the via mesh specifications 250 that are part of the library of commonly routable via meshes 200. For example, none of the via meshes 200 may match the width of the pin 210, which is 0.020 microns. FIG. 8 illustrates the process involved in optimizing the design of the integrated circuit 120. If the pin constraints 760 that match the selected net 600 have corresponding commonly routable via meshes 200 based on the library entries, the optimization process can benefit from improved accuracy of the timing analysis, as described.

[0035] 8 is a process flow for a method 800 for selecting a commonly routable via mesh 200 as part of an optimization process according to one or more embodiments of the present invention. The optimization process refers to a process of iteratively adjusting the design of an integrated circuit 120 to ensure timing requirements are met. At block 810, the process includes selecting or modifying properties of nets 600 or source or sink cells 125 (i.e., cells 125 with input or output terminals), or a combination thereof. These selections define properties that make up pin constraints 760, as shown in FIG. 7.

[0036] In block 820, searching for a pin constraint 760 that matches the properties selected in block 810 includes determining whether the pin constraint 760 matches a commonly routable via mesh specification 250 in the library. The search for the pin constraint 760 is based on matching the specification defined in block 810 based on the nomenclature of the pin constraint 760, as described with reference to FIG. 7. This same nomenclature also enables determining whether there is a match with a commonly routable via mesh specification 250 stored in the library, as also described with reference to FIG. 7. If the pin constraint 760 searched for in block 820 does not have a corresponding commonly routable via mesh specification 250, the pin terminal of the cell 125 is connected to the top layer without redundancy and the corresponding reduction in resistance caused by the via mesh 200. Consider an example embodiment in which the pin constraint 760 searched for in block 820 has a corresponding via mesh specification 250 in the library. In this case, the timing analysis of block 830 is improved as will be explained.

[0037] At block 830, performing timing analysis differs from conventional optimization processes by considering the via mesh 200. This is because specific via meshes 200 and corresponding resistance and capacitance (RC) entries may be used in the timing analysis, rather than the global route. At block 840, a check is made to see if any paths have negative slack (i.e., timing that does not meet requirements). If so, at block 850, a check is made to see if further optimization iterations can be added. If so, the process beginning at block 810 is repeated. If the check at block 840 indicates that no paths have negative slack (i.e., all paths meet timing requirements) or if further optimization is not possible according to the check at block 850, the process ends.

[0038] The via mesh 200 generation and selection approach according to one or more embodiments of the present invention has several advantages over conventional approaches. As discussed with reference to FIGS. 3-5 , the generation considers routability without requiring actual pre-construction of the via mesh options being considered. As a result, any via mesh specification 250 derived from a library of cells 125 within a given group is guaranteed to be routable regardless of the placement of the cells 125. In addition, modifying pin constraints 760 facilitates the selection of a particular via mesh specification 250 (if available) from the library according to the assigned pin constraints 760. This ensures that the via mesh 200 and nets 600 meet all design requirements. Furthermore, the optimization process that results in the final assignment of pin constraints takes into account the timing of the via mesh 200, thereby providing additional granularity in the analysis.

[0039] FIG. 9 is a process flow for a method of fabricating an integrated circuit according to an exemplary embodiment of the present invention. Once physical design data is obtained based in part on the processes described with reference to FIGS. 3, 7, and 8, integrated circuit 120 can be fabricated according to known processes outlined with reference to FIG. 6. Typically, a wafer having multiple copies of the final design is fabricated and cut (i.e., diced) so that each die is one copy of integrated circuit 120. At block 910, the process includes fabricating a mask for lithography based on the determined physical layout. At block 920, fabricating the wafer includes performing photolithography and etching using the mask. Once the wafer is diced, at block 930, each die is inspected and sorted to reject any defective die.

[0040] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments of the present invention may be devised without departing from the scope of the present invention. Various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and drawings. Such connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this regard. Thus, coupling of entities may refer to either direct or indirect coupling, and relationships between entities may be direct or indirect. Furthermore, various tasks and process steps described herein may be combined into a more integrated procedure or process having additional steps or functions not described in detail herein.

[0041] One or more of the methods described herein may be implemented using any or a combination of the following technologies, each of which is well known in the art: discrete logic circuits having logic gates for performing logical functions on data signals, application specific integrated circuits (ASICs) having appropriate combinatorial logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0042] For the sake of brevity, prior art related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are mentioned only briefly herein or omitted entirely, without providing details of well-known systems and / or processes.

[0043] In some embodiments, various functions or operations may occur at a given location, or in conjunction with the operation of one or more devices or systems, or both. In some embodiments, a portion of a given function or operation may be performed at a first device or location, and the remainder of the function or operation may be performed at one or more additional devices or locations.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to encompass the plural forms unless the context clearly dictates otherwise. Furthermore, it will be understood that the words "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0045] Corresponding structures, materials, acts, and equivalents of all means- or step-function-added elements in the following claims are intended to encompass any structure, material, or act for performing that function in combination with other claimed elements as specifically claimed. This disclosure has been presented for purposes of illustration and description and is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the disclosure. The embodiments were chosen and described to best explain the principles and practical application of the disclosure and to enable those skilled in the art to understand the disclosure in terms of various embodiments, with various modifications suited to the particular uses contemplated.

[0046] The diagrams depicted herein are exemplary. There may be many variations in the diagrams or steps (or operations) described herein without departing from the scope of this disclosure. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" refers to having a signal path between two elements, and does not imply a direct connection between elements without an intervening element / connection. All of these variations are considered part of this disclosure.

[0047] The following definitions and abbreviations shall be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," or "contains or containing," or variations thereof, are intended to cover a non-exclusive inclusion. For example, a formulation, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or that are inherently associated with such formulation, mixture, process, method, article, or device.

[0048] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include both an indirect "connected" and a direct "connected."

[0049] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of filing this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0050] The present invention may be a system, method, or computer program product, or a combination thereof, at any possible level of integration of technical detail. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0051] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, punch cards, or mechanically encoded devices such as ridge structures in grooves in which instructions are recorded, or any suitable combination of the above. The computer-readable storage medium used in this invention should not be construed as a transitory signal itself, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0052] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage within the computer-readable storage medium within the respective computing / processing device.

[0053] Computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and the like, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server, as a standalone software package. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to implement aspects of the present invention.

[0054] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or blocks, can be implemented by computer-readable program instructions.

[0055] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine whose instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored constitutes an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0056] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0057] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of an instruction, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or that operate or implement a combination of special-purpose hardware and computer instructions.

[0058] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements to the art found in the marketplace of the embodiments, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. using a processor to generate a set of via mesh specifications for cells in an integrated circuit, each via mesh specification defining one or more straps in each layer above a first layer including one or more pins forming pin terminals, up to a top-most layer connecting the cell to a net for interconnecting the cell to one or more other cells, each via mesh specification also including one or more vias interconnecting adjacent ones of the layers; using the processor to verify whether each via mesh specification in the set of via mesh specifications is a commonly routable via mesh specification, the commonly routable via mesh specification ensuring that the cells interconnect with other cells through the nets while satisfying all design rules; including, by the processor, only those via mesh specifications from the set of via mesh specifications that are commonly routable via mesh specifications into a library of via mesh specifications, the library of via mesh specifications being used to define and fabricate the integrated circuit; 20. A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , further comprising grouping the cell with one or more other cells into a cell group based on statistics of the cell.

3. 3. The computer-implemented method of claim 2, further comprising adding the commonly routable via mesh specifications obtained for the other cells of the cell group to the library of via mesh specifications.

4. 2. The computer-implemented method of claim 1, wherein verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of the via mesh complies with design requirements at each location within the cell.

5. 5. The computer-implemented method of claim 4, wherein said verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of adjacent copies of the via mesh complies with the design requirements at each location.

6. 2. The computer-implemented method of claim 1, further comprising assigning a pin constraint to each pin terminal, wherein the nomenclature of the pin constraint indicates a cell property and a net property.

7. 7. The computer-implemented method of claim 6, further comprising optimizing timing by selecting net properties, source cells, and sink cells, obtaining pin constraints that match the net properties and the source cells or the sink cells, obtaining corresponding commonly routable via mesh specifications from the via mesh specification library based on the nomenclature of the pin constraints, and performing timing analysis, wherein the timing analysis includes timing of the commonly routable via mesh specifications.

8. a memory having computer readable instructions; one or more processors that execute the computer-readable instructions; 10. A system comprising: generating a set of via mesh specifications for cells in an integrated circuit, each via mesh specification defining one or more straps in each layer above a first layer including one or more pins forming pin terminals, up to a top-most layer connecting the cell to a net for interconnecting the cell to one or more other cells, each via mesh specification also including one or more vias interconnecting adjacent ones of the layers; verifying whether each via mesh specification in the set of via mesh specifications is a commonly routable via mesh specification, wherein the commonly routable via mesh specification ensures that the cells interconnect with other cells through the nets while satisfying all design rules; including only those via mesh specifications from the set of via mesh specifications that are commonly routable via mesh specifications in a library of via mesh specifications, the library of via mesh specifications being used to define and fabricate the integrated circuit; and controlling the one or more processors to perform operations including:

9. 10. The system of claim 8, wherein the operations further comprise grouping the cell with one or more other cells into a cell group based on statistics of the cell.

10. 10. The system of claim 9, wherein said operations further comprise adding said commonly routable via mesh specifications obtained for said other cells of said cell group to said library of via mesh specifications.

11. 9. The system of claim 8, wherein said verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of the via mesh complies with design requirements at each location within the cell.

12. 12. The system of claim 11, wherein said verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of adjacent copies of the via mesh complies with the design requirements at each location.

13. 9. The system of claim 8, wherein the operations further comprise assigning a pin constraint to each pin terminal, the nomenclature of the pin constraint indicating a cell property and a net property.

14. 14. The system of claim 13, wherein the operations further include optimizing timing by selecting net properties, source cells, and sink cells, obtaining pin constraints that match the net properties and the source cells or the sink cells, obtaining corresponding commonly routable via mesh specifications from the via mesh specification library based on the nomenclature of the pin constraints, and performing timing analysis, wherein the timing analysis includes timing of the commonly routable via mesh specifications.

15. 1. A computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions comprising: generating a set of via mesh specifications for cells in an integrated circuit, each via mesh specification defining one or more straps in each layer above a first layer including one or more pins forming pin terminals, up to a top-most layer connecting the cell to a net for interconnecting the cell to one or more other cells, each via mesh specification also including one or more vias interconnecting adjacent ones of the layers; verifying whether each via mesh specification in the set of via mesh specifications is a commonly routable via mesh specification, wherein the commonly routable via mesh specification ensures that the cells interconnect with other cells through the nets while satisfying all design rules; including only those via mesh specifications from the set of via mesh specifications that are commonly routable via mesh specifications in a library of via mesh specifications, the library of via mesh specifications being used to define and fabricate the integrated circuit; 1. A computer program product executable by a processor to cause the processor to perform operations including:

16. 16. The computer program product of claim 15, further comprising grouping the cell with one or more other cells into a cell group based on statistics of the cell.

17. 17. The computer program product of claim 16, further comprising adding the commonly routable via mesh specifications obtained for the other cells of the cell group to the library of via mesh specifications.

18. 16. The computer program product of claim 15, wherein the verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of the via mesh complies with design requirements at each location within the cell.

19. 20. The computer program product of claim 18, wherein said verifying whether each via mesh specification is the commonly routable via mesh specification comprises checking whether routing of adjacent copies of the via mesh complies with the design requirements at each location.

20. 16. The computer program product of claim 15, further comprising: assigning a pin constraint to each pin terminal, wherein a nomenclature of the pin constraint indicates a cell property and a net property; selecting a net property, a source cell, and a sink cell to obtain a pin constraint that matches the net property and the source cell or the sink cell; obtaining a corresponding commonly routable via mesh specification from the via mesh specification library based on the nomenclature of the pin constraint; and performing timing analysis to optimize timing, wherein the timing analysis includes timing of the commonly routable via mesh specification.

Images