Dynamic detection and adjustment of subthreshold swing in memory cell sensing circuits.

Abstract

To provide a device, a system, and a method for determining an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page for non-volatile (NV) storage media such as NAND media written by a program and program verification operation.SOLUTION: A method performs program verify with a first word line (WL) select voltage for SSPC cell detection for a first write of a page to detect an expected number of SSPC cells. Based on the determined expected number of SSPC cells, the method sets a boost voltage to capture the expected number of SSPC cells during the program verify operation. The method performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present description relates generally to memory cells, and more particularly, the description relates to sub-threshold swing in memory cell sensing circuits. [Background technology]

[0002] To increase bit density in a memory or storage device, the array can be arranged as a three-dimensional (3D) memory array with bit cells in a vertical stack. Traditional arrays are planar, with bit cells arranged in a horizontal plane. 3D devices can include vertical stacks of horizontal planes. Vertical stacking allows cells to be formed around vertical channels rather than just around horizontal channels, thereby increasing the bit density per unit area of ​​an integrated circuit.

[0003] 3D NAND memory arrays program data into pages by applying a sequence of pulses that inject charge into memory cells. Typically, each program pulse is followed by a series of program verify pulses to check that each cell has captured the desired amount of charge. Once a cell passes the verify corresponding to the cell's desired programming level, the controller inhibits further charge injection with subsequent pulses.

[0004] Some cells may program faster than other cells on the string and therefore trap more charge. The additional charge puts the cells in a higher state of charge compared to the other cells, resulting in the cells charging faster with subsequent program pulses. Thus, the cells tend to trap more charge, widening the threshold voltage (Vt) distribution with each subsequent program.

[0005] Selective Slow Programming Convergence (SSPC) allows programming to adjust the bit line voltage to limit how much charge is injected into cells detected as close to the path. Limiting the charge effectively creates a weaker pulse for SSPC cells. The detection of a cell to be treated as an SSPC cell depends on the subthreshold slope (SS), which depends on the word line position in the string, the operating temperature, and the amount of program / erase stress the cell has previously experienced. [Brief explanation of the drawings]

[0006] The following description includes discussion of figures with illustrations given as examples of implementations. The figures should be understood as examples and not as limitations. As used herein, reference to one or more examples should be understood as describing particular features, structures, or characteristics included in at least one implementation of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention and do not necessarily all refer to the same implementation. However, they are also not necessarily mutually exclusive.

[0007] [Figure 1] FIG. 1 is a block diagram of an example memory that senses cells using sense circuitry that performs program verify based on SSPC detection.

[0008] [Figure 2] 1 is a graphical representation of Vt distribution illustrating SSPC detection.

[0009] [Figure 3] 1 is a representation of an example of SSPC detection with extended program verification.

[0010] [Figure 4] 10 is a representation of an example of SSPC detection with detection of non-SSPC cells.

[0011] [Figure 5A]1 is a diagrammatic representation of an example of cell transfer characteristics of an SSPC cell.

[0012] [Figure 5B] 10 is a diagrammatic representation of an example of selecting VBoost.

[0013] [Figure 6] 10 is a representation of an example of SSPC detection with different first pass and subsequent pass behavior.

[0014] [Figure 7A] 1 is a diagrammatic representation of an example of a binary search for detecting SSPC subthresholds.

[0015] [Figure 7B] 1 is a diagrammatic representation of an example of a linear search for detecting SSPC subthresholds.

[0016] [Figure 8] FIG. 1 is a flow diagram of an example process for program verification using SSPC detection.

[0017] [Figure 9A] FIG. 1 is a block diagram of an example system with a hardware diagram of a solid-state drive (SSD) having a non-volatile array with sense circuitry that performs SSPC detection.

[0018] [Figure 9B] FIG. 1 is a block diagram of an example logical view of a system having a solid-state drive (SSD) with a non-volatile array having sense circuits that perform SSPC detection.

[0019] [Figure 10] FIG. 1 is a block diagram of an example memory subsystem in which a non-volatile array having sense circuits that perform SSPC detection may be implemented.

[0020] [Figure 11]FIG. 1 is a block diagram of an example computing system in which a non-volatile array having sense circuits that perform SSPC detection may be implemented.

[0021] [Figure 12] FIG. 1 is a block diagram of an example mobile device in which a non-volatile array having sense circuits that perform SSPC detection may be implemented.

[0022] A description of specific details and implementations follows, including a non-limiting description of figures that may show some or all examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE INVENTION

[0023] As described herein, for nonvolatile (NV) storage media, such as NAND media, that are written by program and program verify operations, a system can determine the expected number of SSPC (Selective Slow Programming Convergence) cells in a page of cells for specific conditions of the page. The system can perform SSPC detection based on the subthreshold slope (SS) of the cells. In contrast to conventional approaches that add only temperature detection without being able to consider dependence on array position and cycles, SS depends on the word line position in the string, the operating temperature, and the amount of program / erase stress the cell has previously experienced. Therefore, detecting SSPC using SS can improve detection and allow easier adjustments to device operation compared to conventional approaches that use large trim spaces, a lot of tuning, and degraded write performance.

[0024] The system may perform a program verify for a first write of the page using a first word line (WL) select voltage for SSPC cell detection and detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system may set a boost voltage to capture the expected number of SSPC cells during the program verify operation. The system may perform a program verify for subsequent writes to the page using a higher WL select voltage, perform a program verify on the standard cells, and then perform an SSPC program verify using the boost voltage determined from the first write.

[0025] In one example, a boost circuit generates a boost voltage. Generating the boost voltage may include generating a sequence of SSPC boost voltages to determine an appropriate boost voltage to capture approximately the expected number of SSPC cells. Thus, the system can efficiently dynamically detect subthreshold swing and set a dependent trim to a value that detects the expected number of SSPC cells. Dynamic detection and setting the sense to capture the correct number of cells significantly improves level placement over the life of the NAND device. Improved level placement can result in better endurance, faster performance, or a combination of better endurance and faster performance in 3D NAND memory.

[0026] 1 is a block diagram of an example memory that senses cells using a sense circuit that performs program verification based on SSPC detection. System 100 includes a host 110 coupled to a solid-state drive (SSD) 120. Host 110 represents a computing system platform that stores data on SSD 120. SSD 120 represents a storage device for system 100. The computing system platform may be, for example, a laptop or other computer, a gaming system, a tablet or other handheld system, or other computing system.

[0027] Host 110 includes processor 112, which represents the host or primary processor for the computing devices of system 100. Processor 112 may be any type of processor that performs operations that trigger access to storage resources on SSD 120, such as a central processing unit (CPU), a system-on-chip (SOC), a graphics processing unit (GPU), or other processor or controller.

[0028] Host 110 includes interface 116, which represents an interface for accessing SSD 120. Interface 116 may include hardware, such as signal lines, drivers, receivers, or other hardware, for communicating with SSD 120. SSD 120 includes host interface 122 for communicating with host 110. In one example, interface 116 and host interface 122 may communicate via the Non-Volatile Memory Express (NVMe) standard. The NVMe standard defines a register-level interface for host software to communicate with an SSD over Peripheral Component Interconnect Express (PCIe), a high-speed serial computer expansion bus. The NVM Express standard is available at www.nvmexpress.org. The PCIe standard is available at pcisig.com.

[0029] In one example, host 110 includes storage controller 114, which represents a host-side controller for managing host access to SSD 120. Storage controller 114 may manage interface 116, which allows host 110 to communicate with SSD 120. Storage controller 114 receives requests from processor 112 or another component on host 110 for data stored on SSD 120. The requests may be read requests to access data at a particular location, or write or program requests to send data to SSD 120 for storage.

[0030] In one example, SSD 120 includes media controller 124, which represents a storage-side controller for managing host interface 122 and generating internal operations to respond to requests from host 110. Media controller 124 represents a controller for the SSD device itself and may control access to NVM (non-volatile memory) die 130.

[0031] In one example, the NVM die 130 represents a three-dimensional (3D) NAND memory, such as a 3D NAND flash device. The NVM die 130 is a non-volatile memory that maintains a deterministic state even when power to the memory device is interrupted.

[0032] The NVM die 130 includes an array 132 representing an array of cells 134. In one example, the SSD 120 includes multiple NVM dies 130. The array 132 includes word lines (WLs) and bit lines (BLs). In the case of a 3D storage device, the array 132 may include multiple layers of WLs in a 3D stack, with channels extending vertically through the stack. The cells 134 represent storage nodes or storage locations at the intersections of the BLs and WLs. The WLs may be charged in response to a row address, and the BLs may be charged in response to a column address. The cells 134 represent multiple cells at the intersections of the various WLs and BLs, which may be referred to as bit cells, storage cells, or memory cells.

[0033] The arrow below BL represents output line 136 to a sense circuit. When BL and WL are selected, charge from the cell is provided on output line 136 to sense circuit 144. Sense circuit 144 represents circuitry that determines the value stored in the cell, such as a 0 or 1 for a single-level cell (SLC), or a voltage level for a multi-level cell (e.g., a triple-level cell (TLC) or a quad-level cell (QLC)).

[0034] The programmable unit of array 132 is a page, which is accessible by selecting a word line. In one example, each cell 134 of array 132 has 2 n A QLC cell stores n bits of a binary digit by storing one of n voltage levels or levels of charge. For example, a QLC cell stores four bits per cell, requiring 16 distinct programming levels. Programming involves a series of programming pulses applied to a selected word line to inject electrons into the charge storage portion of the cell (e.g., charge trap or floating gate).

[0035] The program pulse is followed by a series of verify or program verify (PV) pulses, which effectively read the cell to detect whether it has reached its desired programming level. If the cell has not reached the desired programming level, it should remain selected for programming (to inject more charge) or it is inhibited for subsequent program pulses. Inhibiting a cell may involve deactivating the bit line for gate junction selection to inhibit further programming.

[0036] In one example, the media controller 124 includes an SSPC detector 126. The SSPC detector 126 can detect cells 134 that are close to the verify path and may widen the distribution of programming levels, which can cause interference by overlapping the voltage windows of adjacent programming levels. In response to detecting the SSPC cell, the media controller 124 can adjust the operation of the programming sequence to trigger the cell with the SSPC voltage, allowing the cell to reach the desired programming level and to be inhibited before completing programming on other cells for the same programming level. In one example, the media controller 124 controls the application of a boost voltage or controls the bit line voltage to limit the amount of charge injected in the next pulse. The SSPC cell can therefore be triggered at a lower voltage, resulting in a weaker injection of charge.

[0037] In one example, the media controller 124 uses the SSPC detector 126 to detect an ideal setup for the SSPC during the first pulse with cells passing the PV of the first level (PV_L1). In one example, the SSPC detector 126 performs a PV-like operation to detect cells located above (PV_L1-GS / 2), where PV_L1 refers to the first level program verify and GS refers to the gate step, voltage step, or voltage difference between subsequent PV pulses. Thus, in one example, cells with a Vt (voltage threshold) or voltage that triggers cell reading that is within half of the PV increment voltage (GS / 2) of PV_L1 (i.e., cells with a Vt between (PV_L1-GS / 2) and (PV_L1)) should ideally be detected as SSPC cells. The media controller 124 includes one or more counters for tracking the number of SSPC cells detected during the detection operation.

[0038] Following the detect operation, the media controller 124 may trigger a normal verify of PV_L1 and count or track the number of cells that pass in the normal verify operation. The number of cells that should be SSPC in the ideal case may be counted as the difference between the cells that pass PV_L1 and the cells that pass (PV_L1-GS / 2). In one example, the media controller 124 triggers the second strobe using the SSPC detect trim program verify. To distinguish the SSPC program verify from the program for the level, the SSPC PV may be referred to as a pre-program verify (PPV), which refers to performing a program verify on the SSPC cells before the program verify for the level. It is understood that the SSPC operation may be referred to by different designations.

[0039] In one example, the pulse or strobe for the SSPC PV or PPV represents a best estimate of the SSPC level, which may be temperature calibrated or adjusted for conservative changes. When the PPV is set to an ideal value, the number of cells identified in the detection is detected. If the initial PPV value is not ideal, resulting in a bit count higher or lower than the ideal setting, in one example, the media controller 124 may perform a calculation or a linear or binary search to calibrate the PPV. The search may include repeated strobes and counts. In one example, after determining the difference between the ideal SSPC count and the count obtained using the initial PPV setting, the media controller 124 may perform a summary adjustment or other calculation to set a new PPV value.

[0040] In one example, if the system 100 includes computational resources for computationally complex operations, the media controller 124 may calculate the ideal PPV based on the initial configuration and the detected number of SSPC cells. In one example, the ideal PPV may be analytically expressed as a function of sense trim and subthreshold slope, where the subthreshold slope (SS) depends on temperature and WL position, as well as changes with cycling. In one example, the media controller 124 may calculate SS from counts coming from the PV and PPV dual strobes. In one example, the calculation may be performed dynamically on the first pulse, or may be calculated and stored using an initial voltage (e.g., dynamic start voltage (DSV)).

[0041] In one example, NVM die 130 includes a boost circuit, boost 142, for sense circuit 144. The boost circuit may be or may include a boost capacitor. Boost 142 provides a charge to sense circuit 144 to bias the sense circuit. Voltage regulator 140 represents a circuit for providing a bias voltage or a charging voltage to boost 142. In one example, voltage regulator 140 charges boost 142, which may apply a boost voltage to sense circuit 144, where the boost voltage is specific to the SSPC cell level as determined by SSPC detector 126.

[0042] Therefore, system 100 may perform a verify pulse to perform detection of SSPC characteristics for the first program cycle. After determining the number of SSPC cells, the media controller may determine the ideal PPV to trigger the Vt of the expected number of SSPC cells. The detection and calculation may be considered dynamic detection that takes into account different system conditions. Therefore, system 100 may dynamically adjust program verification based on the system conditions.

[0043] While detecting the number of SSPC cells and calculating the PPV may incur a performance penalty, the performance penalty is small because it is performed only once at the beginning of the program sequence and the SSPC calculation is reused for subsequent program operations on a WL or group of WLs. Also, depending on the system design, the performance penalty for additional sensing (e.g., detection and PPV calculation) may improve the rest of the programming and reduce errors to a point where there is an overall performance improvement in the system. Whether or not there is a penalty, the reliability of SSD 120 is expected to improve.

[0044] 2 is a graphical representation of Vt distribution illustrating SSPC detection. Diagram 200 illustrates cell Vt in millivolts (mV) versus Vt distribution (σ). Diagram 200 may represent the Vt distribution of NVM cells in a system, according to an example of system 100.

[0045] Curve 210 represents the Vt distribution curve of cell Vt for level #1. Curve 210 may represent a portion of a graph mapping the distribution of all levels of programming for a multi-level cell. Ideal 240 represents cells within GS / 2 below the desired Vt (line 220) for that level of programming. Cells between line 230 and line 220 should be designated as SSPCs. Slowing down cells within ideal 240 can help narrow the width of states for a given GS or a given program level.

[0046] The second strobe for ideal PPV is illustrated by line 230 at (PV_Li-GS / 2), where i is an integer representing which level of programming is being performed. In one example, the ideal program voltage, set by regulation to a boost voltage, is approximately half a program step voltage lower than the WL program voltage. GS refers to the gate step, which is the program step voltage. PV_Li is represented by line 220, which is the program step voltage for level Li. Setting the PPV voltage to the value at line 230 captures SSPC cells with Vt within the voltage range (PV_Li-GS / 2) to (PV_Li).

[0047] 3 is a representation of an example of SSPC detection using extended program verify. Diagram 300 shows program verify voltage response curves for a standard cell and an SSPC cell according to example system 100. Curve 310 shows the voltage response over time for a selected WL node. Curve 320 shows the voltage response over time for the sense node. Curve 330 shows the voltage response over time for the boost node.

[0048] The top line of diagram 300 illustrates the verify time for level Li. Curve 310 represents the curve for a selected WL node. At 312, the WL node is raised to PV_SSPC_Li. A first pulse on the sense node and boost node occurs when the WL node is at PV_SSPC_Li for SSPC detection. In one example, the curve is raised to PV_Li at 314. A second pulse on the sense node and boost node occurs when the WL node is at PV_Li and the boost is set to SSPC verify for normal cell or non-SSPC cell verification.

[0049] Curve 320 represents the voltage response for the sense node. The sense node may be labeled as a "TC node," which may refer to a sense circuit architecture in which the sense node is the terminal of a temporary capacitor (TC). Curve 330 represents the voltage response for a boost node or boost circuit that boosts the sense node. In one example, the boost node starts at 0V. Curve 332 represents the boost voltage of VBoost.

[0050] In one example, for curve 320, the sense node is initially charged to Vcc. In response to VBoost on the boost node, the sense node is increased by VBoost to Vcc+VBoost, as can be seen from curve 322. In one example, the Vboost voltage when WL is PV_SSPC_Li is not enough voltage to cause non-SSPC cells to generate enough current to discharge sufficiently to reach the sense amplifier trip voltage, SA Vtrip.

[0051] After tsense, the system applies a reverse boost to bring the boost back to 0V, as seen by curve 332. During tsense, the sense node discharges. A standard cell or PV cell does not discharge with much current, as seen by the solid line of curve 322. The SSPC cell discharges with a current that provides ideal SSPC discharge, illustrated by the dashed line of curve 322. The dashed line discharges DV during tsense. In response to the reverse boost, the PV cell is still above the sense amplifier trip voltage.

[0052] As can be seen from the dashed line for the strobed SSPC at 326, the SSPC cells can be detected by the sense amplifier. The first pulse in curve 322 detects the SSPC cells but does not trip the PV cells. Thus, the media controller can count the number of tripped SSPC cells and determine the number of SSPC cells that should be detected by the SSPC boost.

[0053] Curve 322 shows the read for the SSPC, and curve 324 illustrates how far the system needs to push the SSPC cell when providing a read for a non-SSPC cell. Curve 334 on the boost node brings the boost node back up to VBoost, which is applied to the sense node at 324. The voltage on WL is higher by DVT_SSPC, which refers to the differential voltage threshold for the SSPC cell.

[0054] At the higher WL voltage, the sense node boost causes the PV cell to trip and discharge during tsense at the ideal current for discharge. The PV cell discharges DV. As can be seen from the dashed line, the SSPC cell has discharged DV_SSPC. In response to the reverse boost to bring the boost node back down to 0V, as can be seen at 328, the solid line indicates that the strobe PV trips the SA Vtrip.

[0055] It should be understood that the illustrated diagram 300 represents an ideal case, where the first verify pulse is used to determine the ideal SSPC verification. Essentially, diagram 300 illustrates doubling the number of verifications for every verification operation. For each level in any loop, an additional verification for the PV_SSPC is performed before the conventional verification operation. The performance penalty of doubling the number of verifications is not practical for system implementation.

[0056] 4 is a representation of an example of SSPC detection using non-SSPC cell detection. Diagram 400 shows program verify voltage response curves for a standard cell and an SSPC cell according to example system 100. Curve 410 shows the voltage response over time for a selected WL node. Curve 420 shows the voltage response over time for the sense node. Curve 430 shows the voltage response over time for the boost node.

[0057] The line at the top of graph 400 illustrates the verify time for level Li. Curve 410 represents the curve for a selected WL node. At 412, the WL node is raised to PV_Li. Curve 420 represents the voltage response for the sense node. The sense node is labeled as the TC node for the output temporary capacitor. Curve 430 represents the voltage response for a boost node or boost circuit that boosts the sense node. In one example, the boost node starts at 0V. Curve 432 represents the boost voltage of VBoost.

[0058] In one example, for curve 420, the sense node is initially charged to Vcc. In response to VBoost on the boost node, the sense node is increased by VBoost to Vcc+VBoost, as seen from curve 422. In one example, the Vboost voltage when WL is at PV_Li causes the PV cell to discharge DV during tsense. The discharge is ideal for a PV cell, as shown by the solid line. The SSPC cell has discharged DV_SSPC, as seen by the dashed line at 424.

[0059] As can be seen from 424, after tsense, the boost node may apply a negative boost, bringing the node back down to 0V, and the solid line indicates that strobe PV trips SA Vtrip. In one example, the boost node is returned to Vboost_SSPC at 434 of curve 430. As can be seen from strobe PV and strobe SSPC, in response to Vboost_SSPC, the sense node boosts the SSPC cell to at least the level of detection. Without detection, the amount of boost for Vboost_SSPC cannot be guaranteed to be ideal.

[0060] If chart 400 represents a traditional SSPC boosting scenario, the system has a fixed amount of Vboost_SSPC at 434. The fixed SSPC boost is set based on an average of conditions and factors. If chart 400 represents a verification operation after detecting the number of SSPC cells, a Vboost_SSPC specific to the number of SSPC cells in the system for a given condition is calculated. Vboost_SSPC can then be set condition-specific to detect a specific number of SSPC cells.

[0061] As can be seen from 422, the SSPC cell has a lower Vt, resulting in a higher string current, providing a DV_SSPC that is much larger than the sense time tsense. Graph 400 does not show the application of independent verification to SSPC detection as performed in graph 300. Applying independent verification to perform SSPC detection allows the system to dynamically adapt to changes in sub-threshold swing and know how much VBoost to bring the SSPC cell back up to the sense amplifier threshold.

[0062] 5A is a graphical representation of an example cell transfer characteristic for an SSPC cell. By adjusting the boost node voltage of the sense amplifier, the system can detect the cell as an SSPC cell with a Vt higher than PV_SSPC, rather than just PV. Diagram 502 illustrates the difference between a brand new SSPC cell and an EOL SSPC cell for an example cell in system 100.

[0063] In contrast to conventional approaches that set the PPV based on an intermediate case or a worst-case scenario, the media controller may dynamically detect the expected number of SSPC cells and set the PPV based on the detected number. A dynamic approach allows the system to adjust the PPV as system conditions change.

[0064] Consider diagram 502, which illustrates cell transfer characteristics for an SSPC cell. Diagram 502 illustrates a first curve for cell 520 and a second curve for cell 530. Cell 520 is an SSPC cell when new, or a brand new cell. Cell 530 is an SSPC cell when near end of life (EOL). The brand new cell has different characteristics than the EOL cell due to cycles and other conditions that change in the system over the life cycle of the cell.

[0065] For each level of programming of a multi-level cell, there are certain cells that should be treated as SSPC cells to avoid injecting too much charge into the cells. An ideal SSPC boost captures the cells that should be SSPC cells without capturing too many cells or too few cells. The cells that should be treated as SSPC cells can be considered part of an "SSPC bucket."

[0066] A conventional approach to setting PPV is to attempt to fix a valid PPV value for both cell 520 and cell 530. As can be seen from diagram 502, as the cycle count increases, cells degrade with shallower subthreshold swings. Cycling generally results in oxide scavenging and degradation, which results in shallower (i.e., larger SS) memory cell characteristics.

[0067] An SSPC bucket can be defined by the Vt voltage that captures the ideal number of SSPC cells. A shallower SS means that for an SSPC bucket defined by DVT_SSPC=GS / 2, cells on the lower Vt side of the SSPC bucket will exhibit significantly less cell current at end of life compared to start of life.

[0068] The ideal boundary of the SSPC bucket is a smaller current difference between the PV and PPV cells at end of life (as the SS has degraded) compared to the new condition. This indicates a smaller drop in Vboost_SSPC (PPV) voltage. In one example, the media controller provides an appropriate reduction in Vboost_SSPC (PPV) to achieve the best placement or window margin.

[0069] Isense_PV 510 represents the sense current for the PV cell. The Isense_PV line intersects the curve for cell 520 at point 514 and the curve for cell 530 at point 512. Isense_SSPC 522 represents the sense current for SSPC cell 520. Isense_SSPC 522 intersects the curve for cell 520 at point 524. The voltage difference between points 514 and 524 is DVT_SSPC. Point 534 on the curve for cell 530 is determined by starting at point 512 on the curve for cell 530 and then working back to DVT_SSPC.

[0070] In one example, Isense_SSPC 522 is four times larger than Isense_PV 510, indicating a four-fold difference when the memory array is new. In one example, Isense_SSPC 532 is only three times larger than Isense_PV 510, indicating that EOL cells should be treated differently than new cells. In one example, the media controller can dynamically adjust Vboost_SSPC to reflect differences in ideal SSPC sense currents.

[0071] 5B is a diagrammatic representation of an example of selecting VBoost. Diagram 504 provides an example of Vboost_SSPC versus window margin. Curve 540 represents the curve for example cell 520 of diagram 502. Curve 550 represents the curve for example cell 530 of diagram 502.

[0072] The peaks of curves 540 and 550 represent the ideal SSPC VBoost for the different cells. Line 542 represents the ideal Vboost_SSPC for the new cell. Line 552 represents the ideal Vboost_SSPC for the EOL cell.

[0073] Curve 540 intersects curve 550 at point 560. A conventional fixed Vboost_SSPC sets line 562 as the selected Vboost_SSPC. In contrast to a fixed compromise between the two curves, the media controller can adjust the SSPC boost to the ideal new 542 for new cells and to the ideal EOL 552 for cells near the end of life.

[0074] 6 is a representation of an example of SSPC detection with different first pass and subsequent pass operations. Diagram 600 shows voltage response curves for program verify for standard cells and SSPC cells according to example system 100. Diagram 600 illustrates SSPC detection according to example diagram 300. Diagram 600 illustrates SSPC boosting according to example diagram 400.

[0075] Diagram 600 enables a media controller to generate a PPV that matches the conditions in a computing system. Thus, the PPV in diagram 600 can rely on sub-threshold swing detection and adjustment, allowing the system to adjust the PPV based on where the block or page is located in the memory device, how many cycles have passed, temperature, and other conditions. Diagram 600 illustrates detection that is performed at the beginning of programming of any page without requiring an additional pulse for each program operation.

[0076] The line at the top of diagram 300 illustrates the verification time of level Li. Curve 310 represents a voltage response curve over time for a selected WL node. At 612, the WL node is raised to PV_SSPC_Li. A first pulse at the sense node and boost node occurs when the WL node is at PV_SSPC_Li for SSPC detection. In one example, the curve is raised to PV_Li at 614. PV_Li is illustrated as DVT_SSPC, which is higher than PV_SSPC_Li. A second pulse at the sense node and boost node occurs when the WL node is at PV_Li for normal or non-SSPC cell verification, and a series of boosts or sequences for SSPC cell verification.

[0077] Curve 620 represents the voltage response over time for the sense node. The sense node may be labeled as a "TC node," which may refer to a sense circuit architecture in which the sense node is the terminal of a temporary capacitor (TC). Curve 630 represents the voltage response over time for a boost node or boost circuit that boosts the sense node. In one example, the boost node starts at 0V. Curve 642 represents the boost voltage of VBoost.

[0078] In one example, the sense node is initially charged to Vcc for curve 620. In response to VBoost on the boost node, the sense node is increased by VBoost to Vcc+VBoost, as can be seen from curve 622. In one example, the Vboost voltage when WL is PV_SSPC_Li is not enough voltage to cause non-SSPC cells to generate enough current to discharge sufficiently to reach the sense amplifier trip voltage, SA Vtrip.

[0079] After tsense, the system applies a negative boost to return the boost node to 0V, as can be seen from curve 642. During tsense, the sense node discharges. A standard cell or PV cell does not discharge much current, as can be seen from the solid line of curve 622. The SSPC cell discharges with a current that provides an ideal SSPC discharge, illustrated by the dashed line of curve 622. The dashed line indicates the SSPC discharge of DV during tsense. In response to the reverse boost, the PV cell is still above the sense amplifier trip voltage, while the SSPC node is readable by the sense amplifier, as can be seen from the strobed SSPC at SA Vtrip in 626. Thus, the boost pulse reads the SSPC cells and does not read the non-SSPC cells, allowing the media controller to detect and count the ideal number of SSPC cells. The media controller can use the ideal number as the expected number of SSPC cells for subsequent operations.

[0080] Curve 622 shows SSPC detection, while curve 624 illustrates how the system applies SSPC boost to trigger the expected number of SSPC cells. Curve 644 on the boost node brings the boost node back up to VBoost, which is applied to the sense node at 624. The voltage on WL is higher by DVT_SSPC, which refers to the differential voltage threshold for the SSPC cell.

[0081] At the higher WL voltage, the sense node boost causes the PV cell to trip and discharge during tsense at the ideal current for discharge. The PV cell discharges DV. As can be seen from the dashed line, the SSPC cell has discharged DV_SSPC. In response to the reverse boost driving the boost node back to 0V, as can be seen from 628, the solid line shows that the strobed PV trips the SA Vtrip.

[0082] In one example, the media controller triggers a boost voltage on the boost node to bring the SSPC cell back up to the SA Vtrip level. It should be understood that while diagram 600 illustrates a binary search, other types of searches may also be used, or the system may perform complex calculations to determine the ideal VBoost to apply.

[0083] In one example, the boost node is raised by Vboost_SSPC1 at 646, followed by Vboost_SSPC2 at 648, followed by Vboost_SSPC3 at 650. Different numbers of SSPC boost voltages can be added to VBoost and Vboost_SSPC <n>It should be understood that each Vboost_SSPC can be used to push SSPC cells into / out of the SSPC bucket defined by <n>However, at strobe time after determining which SSPC boost provides the ideal bucket that captures cells between PV_Li and PV_Li-GS / 2, the media controller may read the number of SSPC cells.

[0084] In one example, in response to Vboost_SSPC1, curve 620 is ramped up to strobe SSPC1 at 630, which is still below SA Vtrip. In response to Vboost_SSPC2, curve 620 is ramped up to strobe SSPC2 at 632, thereby overshooting SA Vtrip. In response to Vboost_SSPC3, curve 620 is ramped up to strobe SSPC3 at 634, which represents the ideal Vboost_SSPC to achieve SA Vtrip.

[0085] According to the example of chart 600, the media controller can find the number of SSPC cells that should be in the ideal bucket with the first VBoost and discharge set for the SSPC cells. The media controller can obtain a count of cells that are expected to pass the PPV in the ideal case with the first boost.

[0086] In one example, the media controller may perform normal verification using the second strobe. In one example, the second strobe utilizes an initial guess or estimate of the PPV. Given that the ideal count SSPC is known from detection, the media controller may cause an appropriate increase or decrease to the PPV to trigger the ideal count SSPC cell. Diagram 600 represents an example of a binary search for calibrating the PPV. Vboost_SSPC1 represents an initial guess of the appropriate boost. For the binary search, Vboost_SSPC2 represents a delta (Δ) increase in VBoost. This represents the fact that Vboost_SSPC1 was too small, resulting in an SSPC count that is lower than the expected or ideal count. Vboost_SSPC3 represents a divided repeat strobe decrease, e.g., Δ / 2, representing the fact that Vboost_SSPC2 resulted in too high a boost. It should be understood that the searches in diagram 600 are simplified for illustrative purposes and that more complex searches may be necessary in a real system.

[0087] It should be understood that after a suitable Vboost_SSPC is found in 634, the media controller may reuse the same boost for subsequent programming of the same page or block, or other portions with the same characteristics. Subsequent program operations may thus continue as illustrated in diagram 400. A system that applies VBoost SSPC dynamic detection and dynamic setting to expected SSPC counts may therefore adapt to dynamic conditions in the media device. In one example, the system may adapt to temperature changes, or to different word line locations, or to cycle count changes, or to different changes, or a combination of change conditions.

[0088] 7A is a diagrammatic representation of an example of a binary search for detecting SSPC subthresholds. Graph 702 illustrates cell V in millivolts (mV) versus V variance (σ). Graph 702 may represent the V variance for a search for an ideal PPV for a system according to the example of system 100, or may set the ideal PPV for the variance according to the example of graph 200.

[0089] Curve 710 represents a Vt dispersion curve for cell Vt at level #1. Curve 710 may represent a portion of a graph mapping the dispersion of all levels of programming for a multi-level cell. PV 722 represents the PV voltage for level #1. PPV 724 may represent the ideal PPV for the SSPC cell at PV 722. The measured SSPC between PV 722 and PPV 724 represents the difference between PV 722 and the ideal placement of the SSPC PV due to the number of SSPC cells detected during the detection operation.

[0090] Based on the PV voltage level used for SSPC detection, the media controller may determine that line 732 should be the starting point for a binary search sequence to determine the ideal PPV. The media controller may iteratively perform program verify on the SSPC cells using a binary search operation to find the ideal SSPC level.

[0091] Thus, the media controller may perform a program verify with the PV set to the value of line 732. The media controller may determine whether the detected SSPC cell count is higher or lower than expected from the detection operation. Next, the media controller may perform a program verify with the PV set to the value of line 734, assuming that line 732 results in an SSPC count that is too high. If line 734 results in an SSPC count that is too low, the media controller may make a next program verify pass at the level of line 736. Line 736 is either identical to PPV 724 or within an acceptable range or tolerance of PPV 724. The media controller may then set line 736 as the value for subsequent SSPC PV operations that have the same conditions as the line to which curve 710 applies.

[0092] 7B is a diagrammatic representation of an example of a linear search for detecting SSPC subthresholds. Graph 704 illustrates cell V in millivolts (mV) versus V variance (σ). Graph 704 may represent the V variance for a search for an ideal PPV for a system according to the example of system 100, or may set the ideal PPV for the variance according to the example of graph 200.

[0093] Curve 710 represents a Vt dispersion curve for the cell Vt of level #1. Curve 710 may represent a portion of a graph mapping the dispersion of all levels of programming for a multi-level cell. PV742 represents the PV voltage for level #1. PPV744 may represent the ideal PPV for the SSPC cell of PV742. The measured SSPC between PV742 and PPV744 represents the difference between PV742 and the ideal placement of the SSPC PV due to the number of SSPC cells detected during the detection operation.

[0094] Based on the PV voltage level used for SSPC detection, the media controller may determine that line 752 should be the starting point for a linear search sequence to determine the ideal PPV. The media controller may iteratively perform program verify on the SSPC cells using the linear search operation to find the ideal SSPC level.

[0095] Thus, the media controller may perform a program verify with the PV set to the value of line 752. The media controller may determine whether the detected SSPC cell count is higher or lower than expected from the detection operation. The media controller may then perform a program verify with the PV set to the value of line 754, and assume that line 752 results in an SSPC count that is too high.

[0096] In one example, the media controller makes a predetermined number of passes (seven passes are shown in diagram 704) using a predetermined step or difference between linear search steps. Thus, the media controller may perform passes using the PV values ​​at line 754, line 756, line 758, line 760, line 762, and line 764. The controller may count the number of SSPC cells determined for each pass and select the line level that was closest to PPV 774. Line 758 is shown as being closest to PPV 744. Thus, the media controller selects line 758 as the SSPC PV value for subsequent SSPC PV operations that have the same conditions as the line to which curve 710 applies.

[0097] 8 is a flow diagram of an example process for program verification using SSPC detection. Process 800 represents a process for program verification that may be performed by a system according to example system 100. Process 800 may be performed by a media controller to perform detection and program verification according to example diagram 600.

[0098] In one example, the media controller determines whether the write is the first write for a page (802). A page is referenced, but it can be any segment of memory that has the same conditions that affect the subthreshold swing of the SSPC cells. If the write is not the first write (NO branch at 804), in one example, the media controller applies a standard WL select voltage to the word line at 814.

[0099] If the write is the first write (YES branch at 804), in one example, the media controller applies an SSPC select voltage to the word line at 806. The SSPC select voltage can be lower than the standard WL select voltage. In one example, the media controller performs SSPC detection at 808 to determine the number of SSPC cells for the program level.

[0100] In one example, after determining how many SSPC cells are present, the media controller may apply a standard word line select voltage at 810. In one example, the media controller performs a program verify using boosting at 812, which includes determining the SSPC boost to capture the expected number of SSPC cells. The determined Vboost_SSPC may then be provided for use in subsequent verify operations. The media controller may perform a standard program verify and an SSPC program verify at 816 using the determined SSPC boost for the page for other program verify operations.

[0101] 9A is a block diagram of an example system with a hardware diagram of a solid-state drive (SSD) having a non-volatile array with sense circuitry that performs SSPC detection. System 902 represents components of a non-volatile storage system that may implement SSPC boost detection according to example system 100 according to any example herein.

[0102] System 902 includes SSD 920 coupled to host 910. Host 910 represents a host hardware platform that connects to SSD 920. Host 910 includes a CPU (Central Processing Unit) 912 or other processor as a host processor or host processor device. CPU 912 represents any host processor that generates requests to access data stored on SSD 920, either to read data or to write data to storage. Such processors may include single or multi-core processors, a computing device's primary processor, graphics processor, peripheral processor, or supplemental or auxiliary processor, or a combination. CPU 912 may execute a host OS and other applications to operate system 902.

[0103] The host 910 includes a chipset 914, which represents hardware components that may be included in connecting between the CPU 912 and the SSD 920. For example, the chipset 914 may include interconnect circuitry and logic that allows access to the SSD 920. Thus, the host platform 910 may include a hardware platform drive interconnect for coupling the SSD 920 to the host 910. The host 910 includes hardware for interconnecting with the SSD. Similarly, the SSD 920 includes corresponding hardware for interconnecting with the host 910.

[0104] The host 910 includes a controller 916, which represents a host-side storage or memory controller that controls access to the SSD 920. In one example, the controller 916 is included in the chipset 914. In one example, the controller 916 is included in the CPU 912. The controller 916 can be referred to as an NV memory controller that allows the host 910 to schedule and manage commands to the SSD 920 to read and write data.

[0105] SSD 920 represents a solid-state drive or other storage system or module that includes non-volatile (NV) media 930 for storing data. SSD 920 includes a HW (hardware) interface 922, which represents a hardware component that interfaces with host 910. For example, HW interface 922 may interface with one or more buses to implement high-speed interface standards such as NVMe (Non-Volatile Memory Express) or PCIe (Peripheral Component Interconnect Express).

[0106] In one example, SSD 920 includes NV (non-volatile) media 930 as primary storage for SSD 920. In one example, NV media 930 is or includes block-addressable memory technology such as NAND or NOR. In one example, NV media 930 may include non-volatile, block-addressable media, non-volatile, byte-addressable media, or non-volatile media that may be byte-addressable or block-addressable. In one example, NV media 930 includes 3D NAND cells.

[0107] In one example, the NV media 930 is implemented as multiple dies, shown as N dies, dies[0:{N-1}]. N can be any number of devices and is often a binary number. The SSD 920 includes a controller 940 that controls access to the NV media 930. The controller 940 represents the hardware and control logic within the SSD 920 that exercises control over the media. The controller 940 is internal to the non-volatile storage device or module and is separate from the controller 916 of the host 910. The NV die of the NV media 930 includes an NV array 932. In one example, the NV array 932 is a 3D memory array.

[0108] In one example, the NV array 932 includes a sense circuit 934 for sensing values ​​stored in memory cells of the NV array. In one example, the controller 940 implements SSPC cell detection and SSPC boosting to enable the sense circuit 934 to properly read the expected number of SSPC cells according to that described above. The SSPC cell detection and application of a dynamic SSPC boost voltage based on the number of detected SSPC cells enables the system 902 to adapt to changing conditions in the NV array 932.

[0109] 9B is a block diagram of an example logical view of a system having a solid-state drive (SSD) with a non-volatile array having sense circuitry that performs SSPC detection. System 904 illustrates a system having a non-volatile memory array according to the example of system 902 of FIG.

[0110] System 904 illustrates the logical layers of the host and SSD of a hardware platform according to system 902. System 904 may represent the software and firmware components as well as the physical components of an example of system 902. In one example, host 950 provides an example of host 910. In one example, SSD 960 provides an example of SSD 920.

[0111] In one example, the host 950 includes a host OS 952, which represents a host operating system or software platform for the host. The host OS 952 may include a platform on which applications, services, agents, and / or other software execute and are executed by a processor. The file system 954 represents control logic that controls access to the NV media. The file system 954 may manage which addresses or memory locations are used to store which data. Many file systems are known, and the file system 954 may implement a known file system or other proprietary system. In one example, the file system 954 is part of the host OS 952.

[0112] Storage driver 956 represents one or more system-level modules that control the hardware of host 950. In one example, driver 956 includes a software application that controls the interface to SSD 960 and therefore the hardware of SSD 960. Storage driver 956 may provide a communication interface between the host and the SSD.

[0113] The controller 970 of the SSD 960 includes firmware 974, which represents the control software / firmware of the controller. In one example, the controller 970 includes a host interface 972, which represents an interface to the host 950. In one example, the controller 970 includes a media interface 976, which represents an interface to the NAND die 962. The NAND die 962 represents a specific instance of NV media and includes an associated 3D NAND array 964. The NAND array 964 includes an array of memory cells.

[0114] The media interface 976 represents control implemented in hardware of the controller 970. It will be understood that the controller 970 includes hardware that interfaces with the host 950, which may be considered to be controlled by the host interface software / firmware 974. Likewise, it will be understood that the controller 970 includes hardware that interfaces with the NAND die 962. In one example, the code for the host interface 972 may be part of the firmware 974. In one example, the code for the media interface 976 may be part of the firmware 974.

[0115] In one example, controller 970 includes error control 980 that handles corner cases related to data errors in accessed data and compatibility of signal transmission and communication interface connections. Error control 980 can include implementation in hardware or firmware, or a combination of hardware and software.

[0116] In one example, the NAND die 962 includes a sense circuit 966 for sensing values ​​stored in memory cells of the NAND array. In one example, the controller 970 implements SSPC cell detection and SSPC boosting to enable the sense circuit 966 to properly read the expected number of SSPC cells according to that described above. The SSPC cell detection and application of a dynamic SSPC boost voltage based on the number of detected SSPC cells enables the system 904 to adapt to changing conditions within the NAND array 964.

[0117] 10 is a block diagram of an example memory subsystem in which a non-volatile array having sense circuits that perform SSPC detection may be implemented. System 1000 includes a processor and elements of a memory subsystem in a computing device.

[0118] In one example, non-volatile storage 1060 includes sense circuitry 1062 for sensing values ​​stored in memory cells of the non-volatile storage array. In one example, controller 1050 implements SSPC cell detection and SSPC boosting to enable sense circuitry 1062 to properly read the expected number of SSPC cells according to that described above. SSPC cell detection and application of a dynamic SSPC boost voltage based on the number of detected SSPC cells enables system 1000 to adapt to changing conditions within non-volatile storage 1060.

[0119] Processor 1010 represents a processing unit of a computing platform that may run an operating system (OS) and applications; such processing units may collectively be referred to as memory hosts or users. The OS and applications perform operations that result in memory accesses. Processor 1010 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a multi-core processor, or a combination. A processing unit may be a primary processor, such as a central processing unit (CPU), a peripheral processor, such as a graphics processing unit (GPU), or a combination thereof. Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices may be integrated with or attached to the processor in some systems via a bus (e.g., PCI Express), or a combination thereof. System 1000 may be implemented as a system-on-chip (SOC) or with standalone components.

[0120] Reference to a memory device may apply to different memory types, including a non-volatile memory device whose state is deterministic even when power to the device is interrupted. In one example, the non-volatile memory device is a block-addressable memory device, such as NAND or NOR technology.

[0121] The memory controller 1020 represents one or more memory controller circuits or devices for the system 1000. The memory controller 1020 represents control logic that generates memory access commands in response to the execution of operations by the processor 1010. The memory controller 1020 accesses one or more memory devices 1040. The memory devices 1040 are coupled to the memory controller 1020. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or a combination thereof. Physical coupling may include direct contact. Electrical coupling includes an interface or interconnect that allows electricity to flow between components, or allows signaling between components, or both. Communicative coupling includes a connection, including wired or wireless, that allows components to exchange data.

[0122] The memory controller 1020 includes I / O interface logic 1022 that couples to a memory bus, such as the memory channel mentioned above. The I / O interface logic 1022 (and the I / O interface logic 1042 of the memory device 1040) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware that connects to the device, or a combination thereof. The I / O interface logic 1022 may include a hardware interface. As shown, the I / O interface logic 1022 includes at least drivers / transceivers for the signal lines. Generally, wires in an integrated circuit interface couple with pads, pins, or connectors to interface with signal lines or traces or other wires between devices. The I / O interface logic 1022 may include drivers, receivers, transceivers, terminations, or other circuits or combinations of circuits for exchanging signals on signal lines between devices. The exchange of signals includes at least one of sending or receiving. Although shown coupling I / O 1022 from memory controller 1020 to I / O 1042 of memory device 1040, it is understood that in implementations of system 1000 where groups of memory devices 1040 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 1020. In implementations of system 1000 that include one or more memory modules 1070, I / O 1042 may include interface hardware of the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 1020 include separate interfaces to other memory devices 1040.

[0123] The bus between the memory controller 1020 and the memory devices 1040 may be implemented as multiple signal lines coupling the memory controller 1020 to the memory devices 1040. The bus may typically include at least a clock (CLK) 1032, a command / address (CMD) 1034, and write data (DQ) and read data (DQ) 1036, as well as zero or more other signal lines 1038. In one example, the bus or connection between the memory controller 1020 and the memory may be referred to as a memory bus. The CMD signal line enables the memory controller 1020 to provide commands to the memory devices 1040. The DQ 1036 enables data exchange between devices and may be referred to as a "data bus." In one example, independent channels may be referred to as different clock signals, C / A buses, data buses, and other signal lines. Thus, the system 1000 may be considered to have multiple "buses," in the sense that independent interface paths may be considered separate buses. It is understood that in addition to the lines explicitly shown, the bus may include at least one of a strobe signaling line, an alert line, an auxiliary line, or other signal lines, or a combination thereof. It is also understood that serial bus technology may be used for connection between the memory controller 1020 and the memory devices 1040. Other signals 1038, such as a strobe line DQS, may accompany the bus or sub-bus.

[0124] In one example, the memory device 1040 is disposed directly on a motherboard of a computing device or a host system platform (e.g., a PCB (printed circuit board) on which the processor 1010 is disposed). In one example, the memory device 1040 may be organized into a memory module 1070. In one example, the memory module 1070 represents a dual in-line memory module (DIMM). In one example, the memory module 1070 represents another organization of multiple memory devices for sharing at least a portion of the access or control circuitry, which may be a separate circuit, a separate device, or a separate board from the host system platform. The memory module 1070 may include multiple memory devices 1040, and the memory modules may include support for multiple separate channels to the memory devices disposed therein. In another example, the memory device 1040 may be integrated into the same package as the memory controller 1020, for example, by a technology such as a multi-chip module (MCM), package-on-package, through-silicon via (TSV), or other technology or a combination thereof. Similarly, in one example, multiple memory devices 1040 may be incorporated into a memory module 1070, which may itself be incorporated into the same package as the memory controller 1020. It will be understood that in these and other implementations, the memory controller 1020 may be part of the host processor 1010.

[0125] The memory devices 1040 each include non-volatile storage 1060, which represents a separate array of memory or storage locations for data. Typically, the non-volatile storage 1060 is managed as rows of data accessed via word line (row) and bit line (individual bits within a row) control. The non-volatile storage 1060 may be organized as separate channels or ranks of memory. A channel refers to an independent control path to storage locations within the memory device 1040. A rank refers to a common location across multiple memory devices (e.g., the same row address in different devices).

[0126] In one example, memory device 1040 includes one or more registers 1044. Register 1044 represents one or more storage devices or locations that provide configurations or settings for operation of the memory device. In one example, register 1044 can provide storage locations in memory device 1040 for storing data accessed by memory controller 1020 as part of control or management operations. In one example, register 1044 includes one or more mode registers. In one example, register 1044 includes one or more general-purpose registers. Depending on the configuration of locations in register 1044, memory device 1040 can be configured to operate in different “modes.” Command information can trigger different operations in memory device 1040 based on the mode. Additionally or alternatively, different modes can also trigger different operations or other signal lines than address information, depending on the mode. The settings of register 1044 may indicate the configuration of an I / O setting (eg, timing, termination or ODT (on-die termination), driver configuration, or other I / O setting).

[0127] The memory device 1040 includes a controller 1050, which represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 1050 decodes commands sent by the memory controller 1020 and generates internal operations to execute or satisfy the commands. The controller 1050 may be referred to as an internal controller and is separate from the host's memory controller 1020. The controller 1050 may determine what mode is selected based on the register 1044 and configure internal execution of operations for accessing the non-volatile storage 1060 or other operations based on the selected mode. The controller 1050 generates control signals to control the routing of bits within the memory device 1040 to provide the appropriate interface for the selected mode and to send commands to the appropriate memory locations or addresses. The controller 1050 includes command logic 1052 that can decode command encodings received on the command and address signal lines. Thus, the command logic 1052 may be or include a command decoder. Command logic 1052 allows the memory device to identify commands and generate internal operations to carry out the requested command.

[0128] Referring back to the memory controller 1020, the memory controller 1020 includes command (CMD) logic 1024, which represents logic or circuitry for generating commands to be sent to the memory device 1040. Generating a command may refer to preparing a command before scheduling or a queued command for transmission. Generally, signaling within a memory subsystem includes address information within or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for the memory device 1040, the memory controller 1020 can issue a command via the I / O 1022 to cause the memory device 1040 to execute the command. In one example, the controller 1050 of the memory device 1040 receives and decodes the command and address information received from the memory controller 1020 via the I / O 1042. Based on the received command and address information, the controller 1050 can execute the command by controlling the timing of operation of logic and circuits within the memory device 1040. The controller 1050 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within the memory device 1040. The memory controller 1020 can implement compliance with standards or specifications by scheduling and controlling accesses.

[0129] The memory controller 1020 includes a scheduler 1026, which represents logic or circuitry for generating and ordering transactions to be sent to the memory device 1040. From one perspective, the primary function of the memory controller 1020 can be said to be scheduling memory accesses and other transactions to the memory device 1040. Such scheduling may include generating the transactions themselves to implement requests for data by the processor 1010 and to maintain data integrity (e.g., using refresh-related commands). A transaction may include one or more commands and thus may result in the transfer of commands, data, or both, in one or more timing cycles, such as a clock cycle or unit interval. A transaction may be for an access, such as a read or write or related command, or a combination thereof. Other transactions may include memory management commands for configuration, settings, data integrity, or other commands or a combination thereof.

[0130] The memory controller 1020 typically includes logic, such as a scheduler 1026, to enable transaction selection and ordering to improve performance of the system 1000. Thus, the memory controller 1020 can select which pending transactions to send to the memory device 1040 and in what order, which is typically achieved with logic much more complex than a simple first-in, first-out algorithm. The memory controller 1020 manages the transmission of transactions to the memory device 1040 and manages the timing associated with the transactions. In one example, transactions have deterministic timing. The timing can be managed by the memory controller 1020 and used in determining how to schedule transactions in the scheduler 1026.

[0131] 11 is a block diagram of an example computing system in which a non-volatile array having sense circuits that perform SSPC detection may be implemented. System 1100 represents a computing device according to any example herein and can be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device.

[0132] System 1100 provides an example of a system that may include an SSD or another storage device according to system 902 or system 904. In one example, system 1100 includes storage 1184 having NV array 1188. NV array 1188 may be, for example, a 3D NAND array. NV array 1188 includes sense 1190, which represents a sense circuit for sensing values ​​stored in memory cells of the non-volatile storage array. In one example, controller 1182 implements SSPC cell detection and SSPC boosting, enabling sense 1190 to properly read the expected number of SSPC cells according to that described above. SSPC cell detection and application of a dynamic SSPC boost voltage based on the number of detected SSPC cells allows system 1100 to adapt to changing conditions within NV array 1188.

[0133] System 1100 includes a processor 1110, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 1100. Processor 1110 may be a host processor device. Processor 1110 controls the overall operation of system 1100 and may be or include one or more programmable general-purpose or application-specific microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0134] System 1100 includes boot / config 1116, which represents storage for storing boot code (e.g., basic input / output system (BIOS)), configuration settings, security hardware (e.g., trusted platform module (TPM)), or other system-level hardware that operates outside of the host OS. Boot / config 1116 may include a non-volatile storage device such as read-only memory (ROM), flash memory, or other memory device.

[0135] In one example, system 1100 includes an interface 1112 coupled to processor 1110. Interface 1112 may represent a higher-speed or high-throughput interface for a system component requiring a higher-bandwidth connection, such as memory subsystem 1120 or graphics interface component 1140. Interface 1112 represents an interface circuit that may be a standalone component or may be integrated into a processor die. Interface 1112 may be integrated on the processor die as a circuit or may be integrated into a system-on-chip as a component. When present, graphics interface 1140 interfaces to a graphics component for providing a visual display to a user of system 1100. Graphics interface 1140 may be a standalone component or may be integrated into the processor die or system-on-chip. In one example, graphics interface 1140 can drive a high-definition (HD) or ultra-high-definition (UHD) display that provides output to a user. In one example, the display may include a touchscreen display. In one example, graphics interface 1140 generates a display based on data stored in memory 1130, or based on operations performed by processor 1110, or both.

[0136] Memory subsystem 1120 represents the main memory of system 1100, providing storage for data values ​​used in the execution of code or routines executed by processor 1110. Memory subsystem 1120 may include one or more various random access memories (RAMs), such as DRAM or other memory devices, or a combination of such devices. Memory 1130 stores and hosts, among other things, an operating system (OS) 1132 to provide a software platform for the execution of instructions within system 1100. Additionally, applications 1134 may execute on the OS 1132 software platform from memory 1130. Applications 1134 represent programs. Such programs have their own operating logic for performing one or more functions. Processes 1136 represent agents or routines that provide auxiliary functionality to OS 1132 or one or more applications 1134, or a combination thereof. OS 1132, applications 1134, and processes 1136 provide the software logic to provide functionality for system 1100. In one example, memory subsystem 1120 includes memory controller 1122, which is a memory controller that generates and issues commands to memory 1130. It is understood that memory controller 1122 may be a physical part of processor 1110 or a physical part of interface 1112. For example, memory controller 1122 may be an integrated memory controller that is integrated into circuitry with processor 1110, such as integrated into a processor die or system-on-chip.

[0137] Although not specifically shown, it is understood that system 1100 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or others. A bus or other signal line may communicatively or electrically couple components to each other, or may communicatively and electrically couple components. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit, or a combination thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport Architecture bus or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other bus, or a combination thereof.

[0138] In one example, system 1100 includes interface 1114, which may be coupled to interface 1112. Interface 1114 may be a slower interface than interface 1112. In one example, interface 1114 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface components and / or peripheral components are coupled to interface 1114. Network interface 1150 provides system 1100 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 1150 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB) or other wired or wireless standards-based or proprietary interface. Network interface 1150 can exchange data with remote devices. Such exchange may include transmitting data stored in memory or receiving data stored in memory.

[0139] In one example, system 1100 includes one or more input / output (I / O) interfaces 1160. I / O interface 1160 may include one or more interface components through which a user interacts with system 1100 (e.g., voice, alphanumeric, haptic / touch, or other interface modalities). Peripheral interface 1170 may include any hardware interface not specifically mentioned above. Peripheral generally refers to devices that connect dependently to system 1100. A dependent connection is one in which system 1100 provides a software or hardware platform on which operations run and with which a user interacts.

[0140] In one example, system 1100 includes a storage subsystem 1180 for storing data in a nonvolatile manner. In one example, in a particular system implementation, at least certain components of storage 1180 may overlap with components of memory subsystem 1120. Storage subsystem 1180 includes storage device 1184, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid-state, or optical-based disks, or a combination. Storage 1184 holds code or instructions and data 1186 in a persistent state (i.e., values ​​are retained even when power to system 1100 is interrupted). While storage 1184 may be generally considered to be “memory,” memory 1130 is typically an execution or operating memory for providing instructions to processor 1110. While storage 1184 is nonvolatile, memory 1130 may include volatile memory (i.e., the value or state of the data is indeterminate when power to system 1100 is interrupted). In one example, storage subsystem 1180 includes a controller 1182 for interfacing with storage 1184. In one example, controller 1182 may be a physical part of interface 1114 or processor 1110, or may include circuitry or logic in both processor 1110 and interface 1114.

[0141] The power source 1102 provides power to the components of the system 1100. More specifically, the power source 1102 typically interfaces with one or more power supplies 1104 in the system 1100 to provide power to the components of the system 1100. In one example, the power supply 1104 includes an AC-DC (alternating current-to-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy (e.g., solar-powered) power source 1102. In one example, the power source 1102 includes a DC power source, such as an external AC-DC converter. In one example, the power source 1102 or the power supply 1104 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 1102 can include an internal battery or fuel cell power source.

[0142] 12 is a block diagram of an example of a mobile device in which a non-volatile array having sense circuits for performing SSPC detection may be implemented. System 1200 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile or embedded computing device. It will be understood that certain components are shown throughout, and not all components of such a device are shown in system 1200.

[0143] System 1200 provides an example of a system that may include an SSD or another storage device according to system 902 or system 904. In one example, system 1200 includes memory 1262 having NV array 1266. NV array 1266 may be, for example, a 3D NAND array. NV array 1266 includes sense 1290, which represents a sense circuit for sensing values ​​stored in memory cells of the non-volatile storage array. In one example, controller 1264 implements SSPC cell detection and SSPC boosting, enabling sense 1290 to properly read the expected number of SSPC cells according to that described above. SSPC cell detection and application of a dynamic SSPC boost voltage based on the number of detected SSPC cells allows system 1200 to adapt to changing conditions within NV array 1266.

[0144] System 1200 includes a processor 1210 that performs the primary processing operations of system 1200. Processor 1210 can be a host processor device. Processor 1210 can include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 1210 include running an operating platform or operating system on which applications and device functions run. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting system 1200 to another device, or a combination thereof. The processing operations can also include operations related to audio I / O, display I / O, or other interface methods, or a combination thereof. Processor 1210 can execute data stored in memory. Processor 1210 can write or edit data stored in memory.

[0145] In one example, system 1200 includes one or more sensors 1212. Sensors 1212 represent built-in sensors or interfaces to external sensors, or a combination thereof. Sensors 1212 enable system 1200 to monitor or detect one or more conditions of the environment or device in which system 1200 is implemented. Sensors 1212 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. Sensors 1212 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user characteristics. Sensors 1212 should be understood broadly and not as a limitation on the many different types of sensors that may be implemented with system 1200. In one example, the one or more sensors 1212 couple to the processor 1210 via front-end circuitry integrated into the processor 1210. In one example, the one or more sensors 1212 couple to the processor 1210 via another component of the system 1200.

[0146] In one example, system 1200 includes an audio subsystem 1220 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components related to providing audio functionality to a computing device. Audio functionality may include speaker or headphone output and microphone input. Devices for such functionality may be integrated into or connected to system 1200. In one example, a user interacts with system 1200 by providing voice commands that are received and processed by processor 1210.

[0147] Display subsystem 1230 represents hardware (e.g., display device) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes a haptic component or touchscreen element through which a user interacts with the computing device. Display subsystem 1230 includes a display interface 1232 that includes a particular screen or hardware device used to provide a display to a user. In one example, display interface 1232 includes logic separate from processor 1210 (such as a graphics processor) for performing at least some processing related to the display. In one example, display subsystem 1230 includes a touchscreen device that provides both output and input to a user. In one example, display subsystem 1230 includes a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touchscreen display. In one example, the display subsystem 1230 generates display information based on data stored in memory, or based on operations performed by the processor 1210, or both.

[0148] I / O controller 1240 represents hardware devices and software components related to interaction with a user. I / O controller 1240 may operate to manage hardware that is part of audio subsystem 1220 or display subsystem 1230, or both. In addition, I / O controller 1240 represents connection points for additional devices that connect to system 1200 through which a user may interact with the system. For example, devices that may be attached to system 1200 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with specific applications, such as a card reader, or other devices.

[0149] As mentioned above, I / O controller 1240 can interact with audio subsystem 1220, display subsystem 1230, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of system 1200. Additionally, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem includes a touchscreen, the display device also functions as an input device that may be managed, at least in part, by I / O controller 1240. Additional buttons or switches may also be present on system 1200 to provide I / O functions managed by I / O controller 1240.

[0150] In one example, I / O controller 1240 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware or sensors 1212 that may be included in system 1200. The inputs may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other features).

[0151] In one example, system 1200 includes power management 1250, which manages battery power usage and functions related to battery charging and power-saving operation. Power management 1250 manages power from a power source 1252, which provides power to components of system 1200. In one example, power source 1252 includes an AC-DC (alternating current-to-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy source (e.g., solar power, motion-based power). In one example, power source 1252 includes only DC power, which can be provided by a DC power source such as an external AC-DC converter. In one example, power source 1252 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, power source 1252 can include an internal battery or a fuel cell power source.

[0152] Memory subsystem 1260 includes memory device 1262 for storing information in system 1200. Memory subsystem 1260 may include nonvolatile (state remains unchanged when power to the memory device is interrupted) or volatile (state becomes indeterminate when power to the memory device is interrupted) memory devices, or a combination thereof. Memory 1260 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of system 1200. In one example, memory subsystem 1260 includes memory controller 1264 (which may also be considered part of a control unit of system 1200 and potentially part of processor 1210). Memory controller 1264 includes a scheduler that generates and issues commands to control access to memory device 1262.

[0153] Connections 1270 include hardware devices (e.g., wireless or wired connectors and communications hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable system 1200 to communicate with external devices. External devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers, or other devices. In one example, system 1200 exchanges data with external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory for reading, writing, or editing data.

[0154] Connection 1270 may include multiple different types of connections. For generalization, system 1200 is shown with cellular connection 1272 and wireless connection 1274. Cellular connection 1272 generally refers to a cellular network connection provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or a variant or derivative thereof, or CDMA (Code Division Multiple Access) or a variant or derivative thereof, TDM (Time Division Multiplexing) or a variant or derivative thereof, LTE (Long Term Evolution, also referred to as "4G"), 5G, or other cellular service standards. Wireless connection 1274 refers to a non-cellular wireless connection and may include a personal area network (such as Bluetooth), a local area network (such as WiFi), or a wide area network (such as WiMAX), or other wireless communications, or a combination thereof. Wireless communications refers to the transfer of data through the use of modulated electromagnetic radiation over a non-solid medium. Wired communications occur via a solid communications medium.

[0155] Peripheral connections 1280 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It is understood that system 1200 may comprise peripheral devices that are peripheral to other computing devices (“out” 1282) and connected to system 1200 (“from” 1284). System 1200 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, syncing) content on system 1200. Additionally, the docking connector may enable system 1200 to connect to certain peripherals that allow system 1200 to control content output to, for example, an audiovisual system or other system.

[0156] In addition to proprietary docking connectors or other proprietary connection hardware, system 1200 may make peripheral connections 1280 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), MiniDisplayPort (MDP), DisplayPort including High-Definition Multimedia Interface (HDMI®), or other types.

[0157] In general, in relation to the description herein, in one example, an apparatus includes a non-volatile (NV) storage medium that is written by operations of programming cells and then performing a program verify of the cells, the NV storage medium being written as a page of cells, and a controller that, for a first write of the page of cells, performs a program verify using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection to detect an expected number of SSPC cells, and, for a subsequent write of the page of cells, performs a program verify using a second WL select voltage that is higher than the first WL select voltage to perform a program verify for the standard cells, and then performs an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells.

[0158] In one example of the device, in one example, the first WL select voltage comprises a voltage approximately half the program step voltage less than the WL program voltage. According to any of the above-mentioned device examples, in one example, the device includes a boost circuit for generating boost voltages, including generating a sequence of SSPC boost voltages and determining a boost voltage for capturing approximately the expected number of SSPC cells. According to any of the above-mentioned device examples, in one example, the sequence of SSPC boost voltages comprises a linear search sequence. According to any of the above-mentioned device examples, in one example, the sequence of SSPC boost voltages comprises a binary search sequence. According to any of the above-mentioned device examples, in one example, the controller calculates the boost voltage for capturing approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition of the NV storage medium. According to any of the above-mentioned device examples, in one example, the changed condition comprises a temperature change. According to any of the above-mentioned device examples, in one example, the changed condition comprises a different word line position. According to any of the above-mentioned device examples, in one example, the changed condition comprises a change in cycle count. According to any of the above examples of the device, in one example the cell comprises a 3D (three dimensional) NAND memory cell.

[0159] Generally, in relation to the description herein, in one example, a system includes a processor; a solid-state drive (SSD) coupled to the processor, the SSD including a non-volatile (NV) storage medium that is written by operations of programming cells and then performing a program verify of the cells, the NV storage medium being written as a page of cells; and a controller that performs a program verify using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection for a first write of the page of cells to detect an expected number of SSPC cells, performs a program verify using a second WL select voltage higher than the first WL select voltage for a subsequent write of the page of cells to perform a program verify for the standard cells, and then performs an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells.

[0160] In one example of the system, in one example, the first WL select voltage comprises a voltage approximately half the program step voltage less than the WL program voltage. According to any of the above-mentioned examples of the system, in one example, the system includes a boost circuit for generating the boost voltages, including generating a sequence of SSPC boost voltages and determining the boost voltages for capturing approximately the expected number of SSPC cells. According to any of the above-mentioned examples of the system, in one example, the sequence of SSPC boost voltages comprises a linear search sequence. According to any of the above-mentioned examples of the system, in one example, the sequence of SSPC boost voltages comprises a binary search sequence. According to any of the above-mentioned examples of the system, in one example, the controller calculates the boost voltages for capturing approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition of the NV storage medium. According to any of the above-mentioned examples of the system, in one example, the changed condition comprises a temperature change. According to any of the above-mentioned examples of the system, in one example, the changed condition comprises a different word line location. According to any of the above-mentioned examples of the system, in one example, the changed condition comprises a change in cycle count. According to any of the above-described examples of the system, in one example the cells include 3D (three-dimensional) NAND memory cells.

[0161] Generally, in relation to the description herein, in one example, a method for program verification of cells includes performing a program verify using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection for a first write of a page of cells of a non-volatile (NV) storage medium to detect an expected number of SSPC cells, performing a program verify using a second WL select voltage higher than the first WL select voltage for a subsequent write of the page of cells to perform a program verify for the standard cells, and then performing an SSPC program verify using a boost voltage determined from the first write to capture approximately the expected number of SSPC cells.

[0162] In one example of the method, in one example, the first WL select voltage comprises a voltage approximately half the program step voltage less than the WL program voltage. According to any of the above-mentioned examples of the method, in one example, the method includes generating a boost voltage, including generating a sequence of SSPC boost voltages and determining a boost voltage for capturing approximately the expected number of SSPC cells. According to any of the above-mentioned examples of the method, in one example, the sequence of SSPC boost voltages comprises a linear search sequence. According to any of the above-mentioned examples of the method, in one example, the sequence of SSPC boost voltages comprises a binary search sequence. According to any of the above-mentioned examples of the method, in one example, the method includes calculating a boost voltage for capturing approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition of the NV storage medium. According to any of the above-mentioned examples of the method, in one example, the changed condition comprises a temperature change. According to any of the above-mentioned examples of the method, in one example, the changed condition comprises a different word line location. According to any of the above-mentioned examples of the method, in one example, the changed condition comprises a change in cycle count. According to any of the above examples of the method, in one example the cell comprises a 3D (three dimensional) NAND memory cell.

[0163] The flow diagrams shown herein provide example sequences of various process actions. The flow diagrams may depict operations performed by software or firmware routines as well as physical operations. The flow diagrams may depict an example implementation of states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular sequence or order, unless otherwise noted, the order of actions can be changed. Therefore, the illustrated diagrams should be understood as examples only, and processes can be performed in different orders and some operational actions can be performed in parallel. Additionally, one or more actions can be omitted, and therefore, not all implementations perform all actions.

[0164] To the extent various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable" format), source code, or differential code ("delta" or "patch" code). The software content described herein may be provided via a product on which the content is stored or via a method of operating a communications interface to transmit data via the communications interface. A machine-readable storage medium can cause a machine to perform the described functions or operations and includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism for interfacing with a hardwired, wireless, optical, or other medium for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or sending signals to prepare the communications interface to provide data signals describing software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0165] The various components described herein can be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component can be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0166] In addition to what is described herein, various modifications can be made to the disclosed subject matter and implementations of the invention without departing from their scope. Accordingly, the descriptions and examples herein should be interpreted in an illustrative, rather than a limiting, sense. The scope of the invention should be determined solely by reference to the claims that follow. [Other possible items] (Item 1) 1. An apparatus comprising: a non-volatile (NV) storage medium that is written by programming cells and then performing a program verify of said cells, the NV storage medium being written as a page of cells; a controller for performing a program verify for a first write of the page of cells using a first word line (WL) select voltage to detect an expected number of SSPC (Selective Slow Programming Convergence) cells, and for a subsequent write of the page of cells using a second WL select voltage higher than the first WL select voltage to perform a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells; An apparatus comprising: (Item 2) Item 10. The device of item 1, wherein the first WL select voltage comprises a voltage that is approximately half a program step voltage lower than the WL program voltage. (Item 3) 2. The apparatus of claim 1, further comprising: a boost circuit for generating the boost voltages, the boost circuit generating a sequence of SSPC boost voltages and determining the boost voltages for capturing approximately the expected number of SSPC cells. (Item 4) Item 4. The apparatus of item 3, wherein the sequence of SSPC boost voltages includes a linear search sequence. (Item 5) Item 4. The apparatus of item 3, wherein the sequence of SSPC boost voltages includes a binary search sequence. (Item 6) Item 10. The apparatus of item 1, wherein the controller calculates the boost voltage for capturing approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition of the NV storage medium. (Item 7) 7. The apparatus according to item 6, wherein the altered conditions include a temperature change. (Item 8) Item 7. The apparatus of item 6, wherein the changed conditions include different word line positions. (Item 9) 7. The apparatus of item 6, wherein the changed conditions include a change in cycle count. (Item 10) Item 1, wherein the cell comprises a 3D (three-dimensional) NAND memory cell. (Item 11) 1. A system comprising: a processor; a solid-state drive (SSD) coupled to the processor, a non-volatile (NV) storage medium that is written by programming cells and then performing a program verify of said cells, the NV storage medium being written as a page of cells; a controller performing a program verify using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection for a first write of the page of cells to detect an expected number of SSPC cells, performing a program verify using a second WL select voltage higher than the first WL select voltage for a subsequent write of the page of cells to perform a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells; SSDs including A system comprising: (Item 12) Item 12. The system of item 11, wherein the first WL select voltage comprises a voltage that is approximately half a program step voltage less than a WL program voltage. (Item 13) Item 12. The system of item 11, wherein the SSD further includes a boost circuit for generating the boost voltages, including generating a sequence of SSPC boost voltages and determining the boost voltages for capturing approximately the expected number of SSPC cells. (Item 14) Item 14. The system of item 13, wherein the sequence of SSPC boost voltages includes a linear search sequence. (Item 15) Item 14. The system of item 13, wherein the sequence of SSPC boost voltages includes a binary search sequence. (Item 16) Item 12. The system of item 11, wherein the controller calculates the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for temperature changes, different word line positions, or changes in cycle count of the NV storage media. (Item 17) Item 12. The system of item 11, wherein the cells include 3D (three-dimensional) NAND memory cells. (Item 18) 1. A method for program verify of a cell, comprising: performing a program verify using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection for a first write of a page of cells of a non-volatile (NV) storage medium to detect an expected number of SSPC cells; performing a program verify for a subsequent write of the page of cells using a second WL select voltage higher than the first WL select voltage, performing a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write, capturing approximately the expected number of SSPC cells; A method for providing the above. (Item 19) 20. The method of claim 18, further comprising generating a sequence of SSPC boosted voltages, the step of determining the boosted voltages to capture approximately the expected number of SSPC cells. (Item 20) Item 19. The method of item 18, further comprising calculating the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for temperature changes, different word line positions, or changes in cycle count of the NV storage media. (Item 21) 21. The method of claim 20, wherein calculating the boost voltage comprises performing a linear search sequence or performing a binary search sequence.< / n> < / n>

Claims

1. 1. A device for storing data, comprising: a non-volatile (NV) storage medium that is written by programming cells and then performing a program verify of said cells, the NV storage medium being written as a page of cells; a controller for performing a program verify for a first write of the page of cells using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection to detect an expected number of SSPC cells, and for a subsequent write of the page of cells using a second WL select voltage higher than the first WL select voltage to perform a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the first WL select voltage comprises a WL program voltage less than approximately one-half a program step voltage.

3. 3. The apparatus of claim 1, further comprising: a boost circuit for generating the boosted voltages, the boost circuit generating a sequence of SSPC boosted voltages and determining the boosted voltages to capture approximately the expected number of SSPC cells.

4. The apparatus of claim 3 , wherein the sequence of SSPC boost voltages comprises a linear search sequence.

5. The apparatus of claim 3 , wherein the sequence of SSPC boosted voltages comprises a binary search sequence.

6. 6. The apparatus of claim 1, wherein the controller calculates the boost voltage for capturing approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition of the NV storage medium.

7. The apparatus of claim 6 , wherein the altered condition comprises a temperature change.

8. The apparatus of claim 6 , wherein the changed condition comprises a different word line location.

9. The apparatus of claim 6 , wherein the changed condition comprises a change in cycle count.

10. The device of claim 1 , wherein the cells comprise 3D (three dimensional) NAND memory cells.

11. 1. A system for program verification of storage, comprising: a processor; a solid-state drive (SSD) coupled to the processor, a non-volatile (NV) storage medium that is written by programming cells and then performing a program verify of said cells, the NV storage medium being written as a page of cells; a controller for performing a program verify for a first write of the page of cells using a first word line (WL) select voltage for SSPC (Selective Slow Programming Convergence) cell detection to detect an expected number of SSPC cells, and for a subsequent write of the page of cells using a second WL select voltage higher than the first WL select voltage to perform a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write to capture approximately the expected number of SSPC cells; and an SSD including A system comprising:

12. 12. The system of claim 11, wherein the first WL select voltage comprises a WL program voltage less than approximately one-half a program step voltage.

13. 13. The system of claim 11 or 12, wherein the SSD further includes a boost circuit for generating the boosted voltages, the boost circuit generating a sequence of SSPC boosted voltages and determining the boosted voltages to capture approximately the expected number of SSPC cells.

14. The system of claim 13 , wherein the sequence of SSPC boost voltages comprises a linear search sequence.

15. The system of claim 13 , wherein the sequence of SSPC boosted voltages comprises a binary search sequence.

16. 16. The system of claim 11, wherein the controller calculates the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for temperature changes, different word line positions, or changes in cycle count of the NV storage media.

17. 17. The system of claim 11, wherein the cells comprise 3D (three dimensional) NAND memory cells.

18. 1. A method for program verify of a cell, comprising: performing program verification using a first word line (WL) select voltage for selective slow programming convergence (SSPC) cell detection for a first write of a page of cells of a non-volatile (NV) storage medium to detect an expected number of SSPC cells; performing a program verify for a subsequent write of the page of cells using a second WL select voltage higher than the first WL select voltage, performing a program verify for standard cells, and then performing an SSPC program verify using a boosted voltage determined from the first write, capturing approximately the expected number of SSPC cells; A method for providing the above.

19. 20. The method of claim 18, further comprising generating the boosted voltages including generating a sequence of SSPC boosted voltages and determining the boosted voltages to capture approximately the expected number of SSPC cells.

20. 20. The method of claim 18 or 19, further comprising calculating the boosted voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for temperature changes, different word line locations, or changes in cycle count of the NV storage media.

21. 21. The method of claim 20, wherein calculating the boosted voltage comprises performing a linear search sequence or performing a binary search sequence.

22. Apparatus for program verification, comprising means for carrying out the method of any one of claims 18 to 21.

Images