Semiconductor device manufacturing method and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device in which on-resistance can be reduced.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment comprises: forming a mask material that has an opening on a surface of a silicon carbide layer; forming a trench on the silicon carbide layer using a mask material as a mask; performing first ion implantation to implant carbon (C) into a bottom surface of the trench using a mask material as a mask; forming a side wall material on a side surface of the trench; performing second ion implantation to implant p-type first impurity into the bottom surface of the trench using the side wall material as a mask; and performing heat-treatment at temperature more than or equal to 1600°C.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device manufacturing method and a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these physical properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) using silicon carbide are required to have reduced on-resistance. To reduce the on-resistance of MOSFETs, trench-gate vertical MOSFETs are used, in which the gate electrode is provided inside a trench. By miniaturizing trench-gate vertical MOSFETs, it is possible to further reduce the on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-195081 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the on-resistance. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to an embodiment includes forming a mask material having an opening on a surface of a silicon carbide layer, forming a trench in the silicon carbide layer using the mask material as a mask, performing a first ion implantation to implant carbon (C) into a bottom surface of the trench using the mask material as a mask, forming a sidewall material on a side surface of the trench, and performing a second ion implantation to implant a p-type first impurity into the bottom surface of the trench using the sidewall material as a mask; The mask material and the sidewall material are removed, and after the mask material and the sidewall material are removed, Heat treatment at 1600℃ or higher The dose of carbon (C) implanted in the first ion implantation is 10 times or more the dose of the first impurity implanted in the second ion implantation. . [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is a diagram showing the crystal structure of a silicon carbide semiconductor. [Figure 4] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a first comparative example. [Figure 12] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 13] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 15] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 17] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 20] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 21] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 22] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 23] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 24] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second comparative example. [Figure 26] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second comparative example. [Figure 27] FIG. 10 is a schematic plan view of a semiconductor device according to a second comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n ++ , n + , n, n - and p ++ , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. ++ is n + The n-type impurity concentration is relatively higher than that of +has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. ++ HAp + The p-type impurity concentration is relatively higher than that of p + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. ++ type, n + type, n - The type is simply n-type, p ++ type, p + type, p - The type is sometimes simply referred to as p-type.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The trench width, trench spacing, trench depth, insulating layer thickness, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0012] (First embodiment) The method for manufacturing a semiconductor device of the first embodiment includes forming a mask material having an opening on the surface of a silicon carbide layer, forming a trench in the silicon carbide layer using the mask material as a mask, performing a first ion implantation to implant carbon (C) into the bottom surface of the trench using the mask material as a mask, forming a sidewall material on the side surface of the trench, using the sidewall material as a mask, performing a second ion implantation to implant a first p-type impurity into the bottom surface of the trench, and performing a heat treatment at 1600°C or higher.

[0013] The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer and extending in the first direction in the first surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer and extending in the first direction in the first surface, the first distance in the second direction between the second trench and the second trench being 1.0 μm or less; a second gate electrode located in the silicon carbide layer; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; an n-type third silicon carbide region located in the silicon carbide layer, between the second silicon carbide region and the first surface; and a first p-type impurity region located in the silicon carbide layer, between the first silicon carbide region and the first trench, having a first p-type impurity concentration of 1×10 20 cm -3 a fourth silicon carbide region of higher p-type, located in the silicon carbide layer and between the first silicon carbide region and the second trench, the fourth silicon carbide region having a second p-type impurity concentration of 1×10 20 cm -3 The semiconductor device comprises a fifth silicon carbide region of a higher p-type, a first electrode located on the first surface side of the silicon carbide layer and electrically connected to the second silicon carbide region and the third silicon carbide region, and a second electrode located on the second surface side of the silicon carbide layer, wherein a second distance in a second direction between the fourth silicon carbide region and the fifth silicon carbide region is equal to or greater than half the first distance.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a trench-gate vertical MOSFET 100 made of silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0015] 2 is a schematic plan view of the semiconductor device of the first embodiment. FIG. 2 is a plan view of the first plane (F1 in FIG. 1) of FIG. 1. The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction. FIG. 1 is a cross section taken along line AA' of FIG. 2.

[0016] The MOSFET 100 includes a silicon carbide layer 10, a first trench 11a, a second trench 11b, a third trench 11c, a first gate electrode 12a, a second gate electrode 12b, a third gate electrode 12c, a first gate insulating layer 14a, a second gate insulating layer 14b, a third gate insulating layer 14c, a source electrode 16 (first electrode), a drain electrode 18 (second electrode), and an interlayer insulating layer 20.

[0017] Hereinafter, the first trench 11a, the second trench 11b, and the third trench 11c may be collectively referred to as trench 11. Hereinafter, the first gate electrode 12a, the second gate electrode 12b, and the third gate electrode 12c may be collectively referred to as gate electrode 12. Hereinafter, the first gate insulating layer 14a, the second gate insulating layer 14b, and the third gate insulating layer 14c may be collectively referred to as gate insulating layer 14.

[0018] In the silicon carbide layer 10, n + n-type drain region 22 - a p-type drift region 24 (first silicon carbide region), a p-type body region 26 (second silicon carbide region), an n + a source region 28 (third silicon carbide region), p + Type contact region 30, p + a first electric field relaxation region 32a (fourth silicon carbide region) of p + a second electric field relaxation region 32b (fifth silicon carbide region) of p + A third electric field relief region 32c of the type is provided.

[0019] Hereinafter, the first electric field relaxation region 32a, the second electric field relaxation region 32b, and the third electric field relaxation region 32c may be collectively referred to as the electric field relaxation region 32.

[0020] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0021] Silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). First surface F1 and second surface F2 face each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2, with first surface F1 as the reference.

[0022] 1 and 2, the first direction and the second direction are parallel to the first plane F1 and the second plane F2, and the third direction is perpendicular to the first plane F1 and the second plane F2.

[0023] Figure 3 shows the crystal structure of a silicon carbide semiconductor. A typical crystal structure of a silicon carbide semiconductor is a hexagonal system such as 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face and is expressed as the {0001} face. Silicon (Si) is arranged on the silicon face.

[0024] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface and is written as the {000-1} surface. Carbon (C) is arranged on the carbon surface.

[0025] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon (Si) and carbon (C) are arranged on the m-plane and a-plane.

[0026] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at an angle of 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0027] The (0001) plane is called the silicon plane, and the (000-1) plane is called the carbon plane.

[0028] The tilt direction of the first plane F1 and the second plane F2 is, for example, the <11-20> direction. The <11-20> direction is the a-axis direction. In FIG. 1, for example, the first direction shown in FIG. 2 is in the same plane as the a-axis direction.

[0029] The trench 11 exists in the silicon carbide layer 10. The trench 11 is a recess provided in the silicon carbide layer 10. The trench 11 extends in a first direction as shown in FIG.

[0030] The width of trench 11 in the second direction (w in FIG. 2) is, for example, equal to or less than the first distance (d1 in FIGS. 1 and 2) between two adjacent trenches 11.

[0031] The width of the trench 11 in the second direction (w in FIG. 2) is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0032] The first distance d1 between two adjacent trenches 11 is 1.0 μm or less. The first distance d1 between two adjacent trenches 11 is, for example, 0.2 μm or more and 1.0 μm or less. For example, the first distance d1 between the first trench 11a and the second trench 11b is 0.2 μm or more and 1.0 μm or less.

[0033] The trenches 11 are repeatedly arranged in the second direction. The repeat pitch of the trenches 11 in the second direction is, for example, not less than 0.4 μm and not more than 2.0 μm.

[0034] The depth of the trench 11 is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0035] The inclination angle of the side surface of trench 11 with respect to the m-plane or the a-plane is, for example, not less than 0 degrees and not more than 5 degrees.

[0036] The gate electrode 12 is provided in the trench 11. The first gate electrode 12a is provided in the first trench 11a. The second gate electrode 12b is provided in the second trench 11b. The third gate electrode 12c is provided in the third trench 11c.

[0037] The gate electrode 12 is provided between the source electrode 16 and the drain electrode 18. The gate electrode 12 extends in a first direction.

[0038] The gate insulating layer 14 is provided between the gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 14a is provided between the first gate electrode 12a and the silicon carbide layer 10. The second gate insulating layer 14b is provided between the second gate electrode 12b and the silicon carbide layer 10. The third gate insulating layer 14c is provided between the third gate electrode 12c and the silicon carbide layer 10.

[0039] The gate insulating layer 14 is provided between the gate electrode 12 and each of the source region 28 , the body region 26 , the drain region 22 , and the electric field reduction region 32 .

[0040] The gate electrode 12 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0041] The gate insulating layer 14 is, for example, a silicon oxide film. For example, a high-k insulating film (a high-dielectric-constant insulating film such as HfSiON, ZrSiON, or AlON) can be used as the gate insulating layer 14. Alternatively, for example, a stacked film of a silicon oxide film (SiO2) and a high-k insulating film can also be used as the gate insulating layer 14.

[0042] The interlayer insulating layer 20 is provided on the gate electrode 12. The interlayer insulating layer 20 is, for example, a silicon oxide film.

[0043] The source electrode 16 is provided on the front surface side of the silicon carbide layer 10. The source electrode 16 is provided on the front surface of the silicon carbide layer 10.

[0044] The source electrode 16 is electrically connected to the source region 28. The source electrode 16 contacts the source region 28.

[0045] The source electrode 16 is electrically connected to the contact region 30. The source electrode 16 is in contact with the contact region 30.

[0046] The source electrode 16 includes a metal. The metal forming the source electrode 16 has a laminated structure of titanium (Ti) and aluminum (Al), for example.

[0047] The drain electrode 18 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 18 is provided on the back surface of the silicon carbide layer 10. The drain electrode 18 is in contact with the drain region 22.

[0048] The drain electrode 18 is, for example, a metal or a metal-semiconductor compound, and includes a material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0049] n + The n-type drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0050] n -A metal-type drift region 24 is provided on the drain region 22. The drift region 24 is provided between the drain region 22 and the surface of the silicon carbide layer 10.

[0051] The drift region 24 functions as a current path when the MOSFET 100 is in an on-state, and also has the function of maintaining the breakdown voltage of the MOSFET 100 by forming a depletion layer in the drift region 24 when the MOSFET 100 is in an off-state.

[0052] The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is, for example, 4×10 14 cm -3 More than 1×10 18 cm -3 The thickness of the drift region 24 in the third direction is, for example, not less than 5 μm and not more than 150 μm.

[0053] The p-type body region 26 is provided between the drift region 24 and the surface of the silicon carbide layer 10. The body region 26 is provided between two adjacent trenches 11. The body region 26 is provided between the first trench 11a and the second trench 11b.

[0054] The body region 26 is in contact with the gate insulating layer 14. The body region 26 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in the region of the body region 26 in contact with the gate insulating layer 14.

[0055] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 26 is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The depth of the body region 26 is, for example, not less than 0.5 μm and not more than 1.0 μm.

[0056] n +The source region 28 is provided between the body region 26 and the surface of the silicon carbide layer 10. The source region 28 is in contact with the source electrode 16. The source region 28 is in contact with the trench 11. The source region 28 is the gate insulating layer 14.

[0057] The n-type impurity concentration of the source region 28 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The depth of the source region 28 is shallower than the depth of the body region 26. The depth of the source region 28 is, for example, not less than 0.1 μm and not more than 0.6 μm. The distance between the drift region 24 and the source region 28 is, for example, not less than 0.1 μm and not more than 0.6 μm.

[0058] p + The contact region 30 is provided between the body region 26 and the surface of the silicon carbide layer 10. The contact region 30 is in contact with the source electrode 16. The contact region 30 is adjacent to the source region 28. The contact region 30 is in contact with the source region 28.

[0059] The contact region 30 has the function of reducing the electrical resistance between the source electrode 16 and the body region 26 .

[0060] The contact region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 30 is, for example, higher than the p-type impurity concentration of the body region 26. The p-type impurity concentration of the contact region 30 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0061] p + The first electric field relaxation region 32a is provided between the drift region 24 and the first trench 11a. The first electric field relaxation region 32a is provided between the drift region 24 and the bottom surface of the first trench 11a. The first electric field relaxation region 32a contacts the bottom surface of the first trench 11a.

[0062] p + The second electric field relaxation region 32b is provided between the drift region 24 and the second trench 11b. The second electric field relaxation region 32b is provided between the drift region 24 and the bottom surface of the second trench. The second electric field relaxation region 32b contacts the bottom surface of the second trench.

[0063] p + The third electric field relaxation region 32c is provided between the drift region 24 and the third trench 11c. The third electric field relaxation region 32c is provided between the drift region 24 and the bottom surface of the third trench 11c. The third electric field relaxation region 32c contacts the bottom surface of the third trench 11c.

[0064] Between two adjacent electric field reduction regions 32, a drift region 24 is provided.

[0065] The electric field buffer region 32 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 32 is higher than the p-type impurity concentration of the body region 26. The p-type impurity concentration of the electric field buffer region 32 is, for example, 1×10 20 cm -3 The p-type impurity concentration of the electric field relaxation region 32 is, for example, 5×10 20 cm -3 5x10 or more 22 cm -3 The following is the result.

[0066] The electric field relaxation region 32 can be formed, for example, by forming a trench in the silicon carbide layer 10 and then ion-implanting aluminum (Al) into the silicon carbide layer 10 from the bottom surface of the trench.

[0067] The potential of the electric field relaxation region 32 is fixed to the potential of the source electrode 16 at a portion not shown. The potential of the electric field relaxation region 32 is fixed to the source potential. The electric field relaxation region 32 has the function of relaxing the electric field applied to the gate insulating layer 14 at the bottom of the trench 11.

[0068] The second distance (d2 in FIG. 1) between two adjacent electric field reduction regions 32 is, for example, half or more of the first distance (d1 in FIGS. 1 and 2) between two adjacent trenches 11.

[0069] A third distance (d3 in FIG. 1) in the third direction between the electric field relief region 32 and the body region 26 corresponds to the distance between the bottom surface of the trench 11 and the body region 26, for example.

[0070] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0071] 4, 5, 6, 7, 8, 9, and 10 are explanatory views of the method for manufacturing the semiconductor device of the first embodiment. Figures 4 to 10 are schematic cross-sectional views showing the semiconductor device in the middle of manufacturing. Figures 4 to 10 show cross sections corresponding to Figure 1.

[0072] First, a silicon carbide layer 10 is prepared, which has a first face F1 (front face) that is a silicon face and a second face F2 (back face) that is a carbon face (FIG. 4). + n-type drain region 22 - a p-type drift region 24, a p-type body region 26, and an n + type source region 28, and p + A mold contact region 30 is formed.

[0073] The drift region 24 is formed by, for example, epitaxial growth on the drain region 22. The body region 26, the source region 28, and the contact region 30 are formed in the surface of the drift region 24 by, for example, ion implantation.

[0074] Next, a mask material 40 having openings 40a is formed on the surface of the silicon carbide layer 10 (FIG. 5). The mask material 40 is, for example, an insulator. The mask material 40 is, for example, silicon oxide.

[0075] The mask material 40 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0076] Next, using the mask material 40 as an etching mask, trenches 11 are formed in the silicon carbide layer 10 (FIG. 6). The trenches 11 are formed by, for example, reactive ion etching (RIE).

[0077] Next, using mask material 40 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the bottom surface of trench 11 (FIG. 7). Carbon regions 42 are formed in silicon carbide layer 10 by the first ion implantation.

[0078] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0079] Next, a sidewall material 44 is formed on the side surface of the trench 11. The sidewall material 44 is, for example, an insulator. The sidewall material 44 is, for example, silicon oxide.

[0080] The bottom surface of the trench 11 is exposed at the bottom of the sidewall material 44. The sidewall material 44 is formed by, for example, depositing an insulating film and etching using the RIE method.

[0081] Next, using the mask material 40 and the sidewall material 44 as an ion implantation mask, a second ion implantation is performed to implant aluminum (Al) into the bottom surface of the trench 11 (FIG. 8). + A type electric field relaxation region 32 is formed. Aluminum (Al) implanted in the second ion implantation is an example of the first impurity.

[0082] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0083] The maximum concentration of carbon implanted in the silicon carbide layer 10 by the first ion implantation is higher than, for example, the maximum concentration of aluminum implanted in the silicon carbide layer 10 by the second ion implantation.

[0084] The carbon dose in the first ion implantation is, for example, 10 times or more the aluminum dose in the second ion implantation. In order to prevent diffusion of impurities to the region outside the electric field buffer region 32, the carbon dose in the first ion implantation implanted into the carbon region 56 is more than 10 times the carbon vacancy amount in the drift region 24, preferably 100 times or more, and more preferably 1000 times or more. The carbon vacancy amount in the drift region 24 formed by epitaxial growth is 1×10 14 cm -3 Therefore, the carbon dose of the first ion implantation is estimated to be 1×10 15 cm -3 That's 1 x 10 16 cm -3 More than 1×10 is preferable. 17 cm -3 The above is more preferable.

[0085] For example, the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment. For example, the distribution of aluminum (Al) implanted in silicon carbide layer 10 by the second ion implantation is included in carbon region 42, as shown in FIG.

[0086] Next, the mask material 40 and the sidewall material 44 are removed by etching using, for example, a wet etching method.

[0087] Next, a carbon film 46 is formed on the surface of the silicon carbide layer 10 .

[0088] Next, heat treatment is performed (FIG. 9). The heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0089] The heat treatment activates the aluminum ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0090] Carbon film 46 prevents silicon and carbon from being desorbed into the atmosphere from silicon carbide layer 10 during heat treatment. Carbon film 46 also absorbs excess interstitial carbon in silicon carbide layer 10 during heat treatment.

[0091] Next, the carbon film 46 is removed (FIG. 10). Thereafter, a gate insulating layer 14 and a gate electrode 12 are formed inside the trench 11 using a known process technology. Furthermore, an interlayer insulating layer 20 and a source electrode 16 are formed on the surface of the silicon carbide layer 10. Furthermore, a drain electrode 18 is formed on the back surface of the silicon carbide layer 10.

[0092] By the above manufacturing method, the MOSFET 100 shown in FIGS. 1 and 2 is manufactured.

[0093] Next, the operation and effects of the semiconductor device and the semiconductor device manufacturing method of the first embodiment will be described.

[0094] The MOSFET 100 of the first embodiment can achieve a reduced on-resistance and improved reliability, as will be described in detail below.

[0095] The MOSFET 100 employs a trench gate structure in which a gate electrode is provided in a trench. The trench gate structure increases the channel area per unit area, thereby reducing the on-resistance of the MOSFET 100. For example, by miniaturizing the MOSFET 100 by reducing the trench width or the trench repetition pitch, the on-resistance of the MOSFET 100 can be further reduced.

[0096] MOSFET 100 also has electric field relaxation region 32 at the bottom of trench 11. By providing electric field relaxation region 32, the electric field applied to gate insulating layer 14 at the bottom of trench 11 is relaxed when MOSFET 100 is in an off state, thereby improving the reliability of gate insulating layer 14.

[0097] 11 is a schematic cross-sectional view of a semiconductor device of Comparative Example 1. The semiconductor device of Comparative Example 1 is a trench-gate vertical MOSFET 901 using silicon carbide. MOSFET 901 is an n-channel MOSFET that uses electrons as carriers.

[0098] The MOSFET 901 of the first comparative example is a MOSFET manufactured by a manufacturing method different from that of the semiconductor device of the first embodiment. The MOSFET 901 of the first comparative example is manufactured without performing the first ion implantation included in the semiconductor manufacturing method of the first embodiment. The first ion implantation implants carbon (C) into the bottom surface of the trench.

[0099] In the MOSFET 901 of the first comparative example, the distance in the second direction between adjacent electric field relaxation regions 32 (d2 in FIG. 11) is smaller than that in the MOSFET 100 of the first embodiment. Also, in the MOSFET 901 of the first comparative example, the third distance in the third direction between the electric field relaxation regions 32 and the body region 26 (d3 in FIG. 11) is smaller than that in the MOSFET 100 of the first embodiment.

[0100] When the distance d2 between adjacent electric field buffer regions 32 in the second direction becomes small, the current path through the drift region 24 is narrowed during the on-state of the MOSFET. Furthermore, when the third distance d3 between the electric field buffer regions 32 and the body region 26 in the third direction becomes small, the current path through the drift region 24 is narrowed during the on-state of the MOSFET. Therefore, the on-resistance of the MOSFET increases. Furthermore, if Al in the electric field buffer regions 32 diffuses and reaches the body region 26, that is, if the third distance d3 becomes zero, the operation of the MOSFET becomes difficult.

[0101] Furthermore, if the third distance d3 in the third direction between the electric field reduction region 32 and the body region 26 becomes small, the threshold voltage of the MOSFET may fluctuate due to fluctuations in the third distance d3.

[0102] For example, if the diffusion of aluminum in the electric field relaxation region 32 can be suppressed, the distance d2 in the second direction between adjacent electric field relaxation regions 32 and the third distance d3 in the third direction between the electric field relaxation region 32 and the body region 26 can be increased, thereby reducing the on-resistance of the MOSFET.

[0103] In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted. This method reduces the carbon vacancy density in the silicon carbide layer 10, and can suppress diffusion of the impurities ion-implanted into the silicon carbide layer 10 due to heat treatment.

[0104] The diffusion of impurities in the silicon carbide layer 10 is promoted by carbon vacancies in the silicon carbide layer 10. In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 42 are formed by carbon ion implantation, thereby reducing the carbon vacancy density in the silicon carbide layer 10. This suppresses the diffusion of impurities, and also the diffusion of aluminum in the electric field relaxation region 32.

[0105] In particular, in the method for manufacturing a semiconductor device according to the first embodiment, carbon is ion-implanted into the bottom surface of trench 11 by a first ion implantation to form carbon region 42, and then aluminum is ion-implanted into the bottom surface of trench 11 by a second ion implantation using sidewall material 44 as a mask. As a result, the distribution of aluminum is covered by carbon region 42 at least in the second direction.

[0106] In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 42 are formed in regions where lateral diffusion of aluminum is expected before the heat treatment for diffusing aluminum, thereby effectively suppressing the lateral diffusion of aluminum.

[0107] Therefore, the method for manufacturing a semiconductor device according to the first embodiment can manufacture a MOSFET 100 having a larger second distance d2 in the second direction between adjacent electric field relaxation regions 32 and a larger third distance d3 in the third direction between the electric field relaxation regions 32 and the body region 26 than the MOSFET 901 of the first comparative example. This makes it possible to manufacture a MOSFET 100 that can reduce on-resistance. Furthermore, the larger third distance d3 in the third direction between the electric field relaxation regions 32 and the body region 26 suppresses fluctuations in the threshold voltage of the MOSFET 100.

[0108] Furthermore, since the diffusion of aluminum in the electric field relaxation region 32 can be suppressed, the p-type impurity concentration in the electric field relaxation region 32 can be increased. This reduces the electrical resistance of the electric field relaxation region 32. Therefore, for example, when the MOSFET 100 is turned off, the discharge of holes from the electric field relaxation region 32 is promoted. This reduces the switching loss of the MOSFET 100. The electric field relaxation region 32 is connected to the source electrode 16 at some position in the first direction, but since the p-type impurity concentration in the electric field relaxation region 32 can be increased, a wider distance can be provided before the connection of the source electrode 16.

[0109] Furthermore, by increasing the p-type impurity concentration in the electric field relaxation region 32, the electric field applied to the gate insulating layer 14 at the bottom of the trench 11 is further relaxed during the off operation of the MOSFET 100. This further improves the reliability of the gate insulating layer 14 of the MOSFET 100.

[0110] The first ion implantation for implanting carbon is preferably performed at a temperature of 1000° C. or higher. By introducing carbon into silicon carbide layer 10 at a temperature of 1000° C. or higher, interstitial carbon enters carbon vacancies during ion implantation, thereby reducing the carbon vacancy density. Therefore, for example, diffusion of impurities can be suppressed when subsequent ion implantation of impurities is performed at a high temperature.

[0111] Furthermore, by implanting carbon ions at a temperature of 1000° C. or higher, damage caused by the carbon ion implantation can be reduced, thereby improving the characteristics of the MOSFET 100.

[0112] The second ion implantation of aluminum (Al) is preferably performed at a temperature of 1000°C or higher. By implanting impurity ions at a temperature of 1000°C or higher, damage caused by the ion implantation of impurities can be reduced. This can suppress amorphization of the silicon carbide layer 10 due to damage, and maintain high crystallinity, thereby increasing the activation efficiency after activation annealing. Since the higher the ion implantation temperature, the higher the crystallinity of the silicon carbide layer 10 can be maintained, the more preferable ion implantation temperature is 1100°C or higher.

[0113] From the viewpoint of suppressing thermal deterioration of the mask material 40 and the sidewall material 44, the temperature of the first ion implantation and the second ion implantation is preferably 1300°C or less, and more preferably 1200°C.

[0114] It should be noted that prior to the second ion implantation of aluminum, the carbon region 42 is formed by the first ion implantation of carbon, so that diffusion of impurities due to high-temperature ion implantation can be suppressed.

[0115] From the viewpoint of suppressing aluminum diffusion, it is preferable that the maximum concentration of carbon implanted in silicon carbide layer 10 by the first ion implantation be higher than the maximum concentration of aluminum implanted in silicon carbide layer 10 by the second ion implantation.

[0116] From the viewpoint of suppressing aluminum diffusion, the carbon dose in the first ion implantation is preferably 10 times or more, and more preferably 100 times or more, the aluminum dose in the second ion implantation.

[0117] From the viewpoint of suppressing the diffusion of aluminum, it is preferable that the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment.

[0118] The temperature of the heat treatment is preferably 1850°C or higher. By performing the heat treatment at 1850°C or higher, the activation rate of the impurities is improved. Note that, because the carbon region 42 is formed by the first ion implantation of carbon prior to the second ion implantation of aluminum, the diffusion of aluminum can be suppressed even when the heat treatment is performed at 1850°C or higher.

[0119] In the MOSFET 100 of the first embodiment, the first distance (d1 in FIGS. 1 and 2) between two adjacent trenches 11 is 1.0 μm or less, and the second distance (d2 in FIG. 1) between two adjacent electric field relaxation regions 32 is at least half the first distance (d1 in FIGS. 1 and 2) between two adjacent trenches 11.

[0120] Although the first distance d1 between two adjacent trenches 11 is as small as 1.0 μm or less, the distance d2 between two adjacent electric field relaxation regions 32 is large, and the current path is not narrowed. This reduces the on-resistance of the MOSFET 100. In the MOSFET 901 of the first comparative example, it is difficult to make the first distance d1 1.0 μm or less.

[0121] Furthermore, in the MOSFET 100 of the first embodiment, the p-type impurity concentration of the electric field relaxation region 32 is 1×10 20 cm -3 This reduces the switching loss of the MOSFET 100. Furthermore, the reliability of the gate insulating layer 14 is improved.

[0122] Furthermore, the third distance (d3 in FIG. 1) in the third direction between the electric field relaxation region 32 and the body region 26 is wider than the third distance (d3 in FIG. 11) of the MOSFET 901 of the first comparative example. Therefore, the current path is not narrowed, and the on-resistance of the MOSFET 100 can be reduced. Furthermore, the threshold voltage of the MOSFET 100 due to the variation in the third distance d3 is suppressed.

[0123] From the viewpoint of reducing the on-resistance of MOSFET 100, the first distance d1 between two adjacent trenches 11 is preferably equal to or less than 0.8 μm, and more preferably equal to or less than 0.6 μm.

[0124] From the viewpoint of reducing the on-resistance of the MOSFET 100, the second distance d2 between two adjacent electric field relaxation regions 32 is preferably at least two-thirds of the first distance d1 between two adjacent trenches 11, more preferably at least four-fifths of the first distance d1, and even more preferably at least the first distance d1.

[0125] From the viewpoint of reducing the switching loss of the MOSFET 100 and improving the reliability of the gate insulating layer 14, the p-type impurity concentration of the electric field relaxation region 32 is set to 5×10 20 cm -3 It is preferable that the concentration is 1×10 or more. 21 cm -3 More preferably, it is equal to or greater than this.

[0126] (Variation) The manufacturing method of the semiconductor device according to the modified example of the first embodiment differs from the manufacturing method of the semiconductor device according to the first embodiment in that after forming the sidewall material, and before heat treatment, a third ion implantation is performed to implant carbon (C) into the bottom surface of the trench using the sidewall material as a mask.

[0127] In the manufacturing method of the modified semiconductor device, for example, before performing a second ion implantation to implant aluminum (Al) into the bottom surface of the trench 11 using the mask material 40 and the sidewall material 44 as an ion implantation mask, a third ion implantation to implant carbon (C) into the bottom surface of the trench 11 using the mask material 40 and the sidewall material 44 as an ion implantation mask is performed.

[0128] The dose of carbon (C) implanted in the third ion implantation is, for example, 1 This is higher than the dose of carbon (C) implanted by ion implantation.

[0129] In the manufacturing method of the semiconductor device of the modified example, the diffusion of aluminum in the electric field relaxation region 32 can be further suppressed by performing a third ion implantation in which carbon (C) is implanted.

[0130] As described above, according to the semiconductor device manufacturing method and semiconductor device of the first embodiment and the modified example, it is possible to achieve a reduction in on-resistance.

[0131] (Second embodiment) A method for manufacturing a semiconductor device according to a second embodiment includes forming a first mask material having an opening on the surface of a silicon carbide layer, forming a trench in the silicon carbide layer using the first mask material as a mask, the trench having a first side and a second side and extending in a first direction parallel to the surface, performing a first ion implantation using the first mask material as a mask to implant carbon (C) into the second side of the trench, using the first mask material as a mask to perform a second ion implantation using the first mask material as a mask to implant a first p-type impurity into the second side of the trench, using the first mask material as a mask to perform a third ion implantation using the first mask material as a mask to implant carbon (C) into the bottom of the trench, forming a sidewall material on the first and second side of the trench, using the sidewall material as a mask to perform a fourth ion implantation using the sidewall material as a mask to implant a second p-type impurity into the bottom of the trench, and performing a heat treatment at 1600°C or higher. The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that a first ion implantation is performed to implant carbon (C) into the second side surface of the trench using a first mask material as a mask, and a second ion implantation is performed to implant a first p-type impurity into the second side surface of the trench using the first mask material as a mask. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0132] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it further includes a plurality of p-type sixth silicon carbide regions located in the silicon carbide layer, in contact with the fourth silicon carbide region, between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the third silicon carbide region and the first trench, and repeatedly arranged in the first direction. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0133] 12 and 13 are schematic cross-sectional views of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 made of silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0134] Fig. 14 is a schematic plan view of the semiconductor device of the second embodiment. Fig. 14 is a plan view of the first plane (F1 in Figs. 12 and 13) of Figs. 12 and 13. The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction. Fig. 12 is a BB' cross section of Fig. 14. Fig. 13 is a CC' cross section of Fig. 14.

[0135] The MOSFET 200 includes a silicon carbide layer 10, a first trench 11a, a second trench 11b, a third trench 11c, a first gate electrode 12a, a second gate electrode 12b, a third gate electrode 12c, a first gate insulating layer 14a, a second gate insulating layer 14b, a third gate insulating layer 14c, a source electrode 16 (first electrode), a drain electrode 18 (second electrode), and an interlayer insulating layer 20.

[0136] Hereinafter, the first trench 11a, the second trench 11b, and the third trench 11c may be collectively referred to as trench 11. Hereinafter, the first gate electrode 12a, the second gate electrode 12b, and the third gate electrode 12c may be collectively referred to as gate electrode 12. Hereinafter, the first gate insulating layer 14a, the second gate insulating layer 14b, and the third gate insulating layer 14c may be collectively referred to as gate insulating layer 14.

[0137] In the silicon carbide layer 10, n + n-type drain region 22 - a p-type drift region 24 (first silicon carbide region), a p-type body region 26 (second silicon carbide region), an n + a source region 28 (third silicon carbide region), p + a first electric field relaxation region 32a (fourth silicon carbide region) of p + a second electric field relaxation region 32b (fifth silicon carbide region) of silicon carbide type, and + A mold connection region 34 (sixth silicon carbide region) is provided.

[0138] Hereinafter, the first electric field relaxation region 32a, the second electric field relaxation region 32b, and the third electric field relaxation region 32c may be collectively referred to as the electric field relaxation region 32.

[0139] The width of trench 11 in the second direction (w in FIG. 14) is, for example, equal to or less than the first distance between two adjacent trenches 11 (d1 in FIGS. 13 and 14).

[0140] The width of the trench 11 in the second direction (w in FIG. 14) is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0141] The first distance d1 between two adjacent trenches 11 is 1.0 μm or less. The first distance d1 between two adjacent trenches 11 is, for example, 0.2 μm or more and 1.0 μm or less. For example, the first distance d1 between the first trench 11a and the second trench 11b is 0.2 μm or more and 1.0 μm or less. Since the diffusion of aluminum from the electric field relaxation region 32 can be suppressed, the first distance d1 between two adjacent trenches 11 can be reduced.

[0142] The trenches 11 are repeatedly arranged in the second direction. The repeat pitch of the trenches 11 in the second direction is, for example, not less than 0.4 μm and not more than 2.0 μm.

[0143] The depth of the trench 11 is, for example, not less than 0.5 μm and not more than 2 μm. Since the diffusion of aluminum in the electric field buffer region 32 can be suppressed, the third distance d3 can be made small, and the depth of the trench 11 can be made shallow.

[0144] The inclination angle of the side surface of trench 11 with respect to the m-plane or the a-plane is, for example, not less than 0 degrees and not more than 5 degrees.

[0145] p +A connection region 34 of the type contacts the electric field relief region 32. The connection region 34 is provided between the drift region 24 and the trench 11. The connection region 34 is provided between the body region 26 and the trench 11. The connection region 34 is provided between the source region 28 and the trench 11.

[0146] p + The connection region 34 of the transistor contacts the first electric field relief region 32a. The connection region 34 is provided between the drift region 24 and the first trench 11a. The connection region 34 is provided between the body region 26 and the first trench 11a. The connection region 34 is provided between the source region 28 and the first trench 11a.

[0147] The connection region 34 contacts the side surface of the trench 11. The connection region 34 contacts, for example, the bottom surface of the trench 11. The connection region 34 contacts, for example, the first face F1.

[0148] The connection region 34 contacts the side surface of the first trench 11a. The connection region 34 contacts, for example, the bottom surface of the first trench 11a.

[0149] The connection region 34 contacts the gate insulating layer 14. The connection region 34 contacts the source electrode 16 on the first face F1, for example.

[0150] 14, the multiple connection regions 34 are repeatedly arranged in a first direction. The interval between two connection regions 34 adjacent to each other in the first direction is a first interval (s1 in FIG. 14).

[0151] The connection region 34 serves to electrically connect the electric field relaxation region 32 and the source electrode 16. The connection region 34 fixes the electric field relaxation region 32 to the potential of the source electrode 16. The connection region 34 fixes the electric field relaxation region 32 to the source potential.

[0152] The connection region 34 also serves to reduce the electrical resistance between the source electrode 16 and the body region 26 .

[0153] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described.

[0154] 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24 are explanatory views of a method for manufacturing a semiconductor device according to the second embodiment. 15 to 24 are schematic cross-sectional views showing a semiconductor device in the process of being manufactured. 15 to 18 and 20 to 24 show cross sections corresponding to FIG. 12. 19 shows a cross section corresponding to FIG. 13.

[0155] First, a silicon carbide layer 10 is prepared, which has a first face F1 (front face) that is a silicon face and a second face F2 (back face) that is a carbon face (FIG. 15). + n-type drain region 22 - a p-type drift region 24, a p-type body region 26, and an n + A source region 28 is formed.

[0156] The drift region 24 is formed, for example, by epitaxial growth on the drain region 22. The body region 26 and the source region 28 are formed in the surface of the drift region 24 by, for example, ion implantation.

[0157] Next, a first mask material 50 having an opening 50a is formed on the surface of the silicon carbide layer 10 (FIG. 16). The first mask material 50 is, for example, an insulator. The first mask material 50 is, for example, silicon oxide.

[0158] The first mask material 50 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0159] Next, using the first mask material 50 as an etching mask, trenches 11 are formed in the silicon carbide layer 10 (FIG. 17). The trenches 11 are formed by, for example, an RIE method. The trenches 11 have a first side surface 11x and a second side surface 11y.

[0160] Next, using the first mask material 50 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the second side surface 11y of the trench 11 (FIG. 18). A first carbon region 52 is formed in the silicon carbide layer 10 by the first ion implantation.

[0161] The first ion implantation is performed by, for example, oblique ion implantation.

[0162] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0163] Next, a second mask material 54 is formed to cover a part of the trench 11 (FIG. 19). The second mask material 54 is formed so as to cover the area where the connection region 34 will not be formed eventually. The second mask material 54 is formed so as to open only the area where the connection region 34 will be formed eventually.

[0164] The second mask material 54 is, for example, an insulator, and is, for example, silicon oxide.

[0165] The second mask material 54 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0166] Next, using the first mask material 50 and the second mask material 54 as an ion implantation mask, a second ion implantation is performed to implant aluminum (Al) into the second side surface 11y of the trench 11 (FIG. 20). + A mold connection region 34 is formed. Aluminum (Al) implanted in the second ion implantation is an example of the first impurity.

[0167] The second ion implantation is performed by, for example, oblique ion implantation.

[0168] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0169] The maximum concentration of carbon implanted in the silicon carbide layer 10 by the first ion implantation is higher than, for example, the maximum concentration of aluminum implanted in the silicon carbide layer 10 by the second ion implantation.

[0170] The carbon dose in the first ion implantation is, for example, 10 times or more the aluminum dose in the second ion implantation.

[0171] For example, the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment. For example, the distribution of aluminum (Al) implanted in silicon carbide layer 10 by the second ion implantation is included in first carbon region 52, as shown in FIG.

[0172] Next, the second mask material 54 is removed by etching using, for example, a wet etching method.

[0173] Next, using the first mask material 50 as an ion implantation mask, a third ion implantation is performed to implant carbon (C) into the bottom surface of the trench 11 (FIG. 21). A second carbon region 56 is formed in the silicon carbide layer 10 by the third ion implantation.

[0174] The third ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The third ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0175] Next, a sidewall material 44 is formed on the side surface of the trench 11. The sidewall material 44 is, for example, an insulator. The sidewall material 44 is, for example, silicon oxide.

[0176] The bottom surface of the trench 11 is exposed at the bottom of the sidewall material 44. The sidewall material 44 is formed by, for example, depositing an insulating film and etching using the RIE method.

[0177] Next, using the first mask material 50 and the sidewall material 44 as an ion implantation mask, a fourth ion implantation is performed to implant aluminum (Al) into the bottom surface of the trench 11 (FIG. 22). + A type electric field relaxation region 32 is formed. Aluminum (Al) implanted in the fourth ion implantation is an example of the second impurity.

[0178] The fourth ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The fourth ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0179] The maximum concentration of carbon implanted in silicon carbide layer 10 by the third ion implantation is higher than, for example, the maximum concentration of aluminum implanted in silicon carbide layer 10 by the fourth ion implantation.

[0180] The carbon dose in the third ion implantation is, for example, 10 times or more the aluminum dose in the fourth ion implantation.

[0181] For example, the distribution of carbon implanted into silicon carbide layer 10 by the third ion implantation in silicon carbide layer 10 before the heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the fourth ion implantation in silicon carbide layer 10 before the heat treatment. For example, the distribution of aluminum (Al) implanted in silicon carbide layer 10 by the fourth ion implantation is included in second carbon region 56, as shown in FIG.

[0182] Next, the first mask material 50 and the sidewall material 44 are removed. The first mask material 50 and the sidewall material 44 are removed by etching using, for example, a wet etching method.

[0183] Next, a carbon film 46 is formed on the surface of the silicon carbide layer 10 .

[0184] Next, heat treatment is performed (FIG. 23). The heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0185] The heat treatment activates the aluminum ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0186] Carbon film 46 prevents silicon and carbon from being desorbed into the atmosphere from silicon carbide layer 10 during heat treatment. Carbon film 46 also absorbs excess interstitial carbon in silicon carbide layer 10 during heat treatment.

[0187] Next, the carbon film 46 is removed (FIG. 24). Thereafter, a gate insulating layer 14 and a gate electrode 12 are formed inside the trench 11 using a known process technology. Furthermore, an interlayer insulating layer 20 and a source electrode 16 are formed on the surface of the silicon carbide layer 10. Furthermore, a drain electrode 18 is formed on the back surface of the silicon carbide layer 10.

[0188] By the above manufacturing method, the MOSFET 200 shown in FIGS. 12, 13 and 14 is manufactured.

[0189] Next, the operation and effects of the semiconductor device and the semiconductor device manufacturing method of the second embodiment will be described.

[0190] The MOSFET 200 of the second embodiment can achieve a reduced on-resistance and improved reliability, as will be described in detail below.

[0191] The MOSFET 200 employs a trench gate structure in which a gate electrode is provided in a trench. The trench gate structure increases the channel area per unit area, thereby reducing the on-resistance of the MOSFET 200. For example, by miniaturizing the MOSFET 200 by reducing the trench width or the trench repetition pitch, the on-resistance of the MOSFET 200 can be further reduced.

[0192] Furthermore, MOSFET 200 has electric field relaxation region 32 at the bottom of trench 11. By providing electric field relaxation region 32, the electric field applied to gate insulating layer 14 at the bottom of trench 11 is relaxed when MOSFET 200 is in an off state, thereby improving the reliability of gate insulating layer 14.

[0193] Furthermore, the MOSFET 200 has a connection region 34 that electrically connects the electric field relaxation region 32 and the source electrode 16. This facilitates the discharge of holes from the electric field relaxation region 32 during the turn-off operation of the MOSFET 200, thereby reducing the switching loss of the MOSFET 200.

[0194] Furthermore, the MOSFET 200 has the connection region 34, and thus has a p-type MOSFET on the first face F1, as in the MOSFET 100. + Therefore, for example, the first distance d1 between two adjacent trenches can be reduced, and the on-resistance of the MOSFET 200 can be reduced.

[0195] 25 and 26 are schematic cross-sectional views of the semiconductor device of the second comparative example, and Fig. 27 is a schematic plan view of the semiconductor device of the second comparative example.

[0196] Fig. 25 is a diagram corresponding to Fig. 12. Fig. 26 is a diagram corresponding to Fig. 13. Fig. 27 is a diagram corresponding to Fig. 14.

[0197] The semiconductor device of the second comparative example is a trench-gate vertical MOSFET 902 using silicon carbide. The MOSFET 902 is an n-channel MOSFET that uses electrons as carriers.

[0198] The MOSFET 902 of the second comparative example is a MOSFET manufactured by a manufacturing method different from that of the semiconductor device of the second embodiment. The MOSFET 902 of the second comparative example is manufactured without performing the first ion implantation and the third ion implantation that are included in the semiconductor manufacturing method of the second embodiment. The first ion implantation implants carbon (C) into the second side surface 11y of the trench. The third ion implantation implants carbon (C) into the bottom surface of the trench.

[0199] In the MOSFET 902 of the second comparative example, the second distance in the second direction between adjacent electric field relaxation regions 32 (d2 in FIG. 26) is smaller than that in the MOSFET 200 of the second embodiment. Furthermore, in the MOSFET 902 of the second comparative example, the third distance in the third direction between the electric field relaxation regions 32 and the body region 26 (d3 in FIG. 26) is smaller than that in the MOSFET 200 of the second embodiment. Furthermore, in the MOSFET 902 of the second comparative example, the fourth distance between the connection region 34 and the trench 11 (d4 in FIGS. 25 and 27) is smaller than that in the MOSFET 200 of the second embodiment.

[0200] Furthermore, in the MOSFET 902 of the second comparative example, the first distance in the first direction between two adjacent connection regions 34 (s1 in FIG. 27) is smaller than the first distance in the first direction between two adjacent connection regions 34 of the MOSFET 200 of the second embodiment (s1 in FIG. 14).

[0201] When the second distance d2 in the second direction between adjacent electric field buffer regions 32 becomes smaller, the current path through drift region 24 is narrowed when the MOSFET is in on-state. Also, when the third distance d3 in the third direction between electric field buffer regions 32 and body region 26 becomes smaller, the current path through drift region 24 is narrowed when the MOSFET is in on-state. Therefore, the on-resistance of the MOSFET increases.

[0202] Furthermore, if the third distance d3 in the third direction between the electric field relaxation region 32 and the body region 26 becomes small, the threshold voltage of the MOSFET may fluctuate due to the fluctuation of the third distance d3. Furthermore, if the fourth distance d4 between the connection region 34 and the trench 11 becomes small, the threshold voltage of the MOSFET may fluctuate.

[0203] Furthermore, when the first distance s1 in the first direction between two adjacent connection regions 34 is reduced, the channel area per unit area is reduced, and the on-resistance of the MOSFET is reduced.

[0204] For example, if the diffusion of aluminum in the electric field relaxation region 32 can be suppressed, the second distance d2 in the second direction between adjacent electric field relaxation regions 32 and the third distance d3 in the third direction between the electric field relaxation region 32 and the body region 26 can be increased, thereby reducing the on-resistance of the MOSFET.

[0205] For example, if the diffusion of aluminum in the connection region 34 can be suppressed, the fourth distance d4 between the connection region 34 and the trench 11 becomes large, and fluctuations in the threshold voltage of the MOSFET can be suppressed.

[0206] For example, if the diffusion of aluminum in the connection regions 34 can be suppressed, the first distance s1 in the first direction between two connection regions 34 adjacent in the first direction can be increased, and the on-resistance of the MOSFET can be reduced.

[0207] In the method for manufacturing a semiconductor device according to the second embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted. This method reduces the carbon vacancy density in the silicon carbide layer, and can suppress the diffusion of the implanted impurities into the silicon carbide layer due to heat treatment.

[0208] The diffusion of impurities in the silicon carbide layer 10 is promoted by carbon vacancies in the silicon carbide layer 10. In the method for manufacturing a semiconductor device according to the second embodiment, a carbon region is formed by carbon ion implantation, thereby reducing the carbon vacancy density in the silicon carbide layer 10. This suppresses the diffusion of impurities, and also the diffusion of aluminum in the connection region 34 and the electric field relaxation region 32.

[0209] In the method for manufacturing a semiconductor device according to the second embodiment, carbon is ion-implanted into the side surface of trench 11 by a first ion implantation to form first carbon region 52, and then aluminum is ion-implanted into the side surface of trench 11 by a second ion implantation. As a result, the distribution of aluminum overlaps with first carbon region 52.

[0210] In the method for manufacturing a semiconductor device according to the second embodiment, after carbon is ion-implanted into the bottom surface of trench 11 by a third ion implantation to form second carbon region 56, a fourth ion implantation is performed using sidewall material 44 as a mask to ion-implant aluminum into the bottom surface of trench 11. As a result, the distribution of aluminum is covered by second carbon region 56 at least in the second direction.

[0211] In the semiconductor device manufacturing method of the second embodiment, carbon regions are formed in the regions where lateral diffusion of aluminum is expected before the heat treatment that diffuses aluminum, thereby effectively suppressing the lateral diffusion of aluminum.

[0212] Therefore, according to the method for manufacturing a semiconductor device of the second embodiment, it is possible to manufacture a MOSFET 200 in which the second distance d2 in the second direction between adjacent electric field relaxation regions 32 and the third distance d3 in the third direction between the electric field relaxation regions 32 and the body region 26 are greater than those of the MOSFET 902 of the second comparative example. Therefore, it is possible to manufacture a MOSFET 200 in which the on-resistance can be reduced.

[0213] Furthermore, in the MOSFET 200, the fluctuation of the threshold voltage is suppressed by increasing the third distance d3 in the third direction between the electric field relaxation region 32 and the body region 26. Furthermore, in the MOSFET 200, the fluctuation of the threshold voltage is suppressed by increasing the fourth distance d4 between the connection region 34 and the trench 11.

[0214] Furthermore, in the MOSFET 200, the first distance s1 in the first direction between two adjacent connection regions 34 is increased, and the on-resistance of the MOSFET 200 can be reduced.

[0215] Furthermore, suppressing the diffusion of aluminum in the electric field relaxation region 32 allows for a high p-type impurity concentration in the electric field relaxation region 32. Furthermore, suppressing the diffusion of aluminum in the connection region 34 allows for a high p-type impurity concentration in the connection region 34.

[0216] This reduces the electrical resistance of the electric field relaxation region 32 and the connection region 34. Therefore, for example, when the MOSFET 200 is turned off, the discharge of holes from the electric field relaxation region 32 and the connection region 34 is promoted. This reduces the switching loss of the MOSFET 200. Furthermore, the electrical resistance of the electric field relaxation region 32 and the connection region 34 is reduced. This makes it possible to increase the first distance s1 in the first direction between two connection regions 34 adjacent to each other in the first direction, thereby further reducing the on-resistance of the MOSFET 200.

[0217] Furthermore, by increasing the p-type impurity concentration in the electric field relaxation region 32, the electric field applied to the gate insulating layer 14 at the bottom of the trench 11 is further relaxed during the off operation of the MOSFET 200. This improves the reliability of the gate insulating layer 14 of the MOSFET 200.

[0218] In the method for manufacturing a semiconductor device according to the second embodiment, the first and third ion implantations for implanting carbon are preferably performed at a temperature of 1000° C. or higher. By introducing carbon into the silicon carbide layer 10 at a temperature of 1000° C. or higher, interstitial carbon enters carbon vacancies during ion implantation, thereby reducing the carbon vacancy density. Therefore, for example, diffusion of impurities can be suppressed when subsequent ion implantation of impurities is performed at a high temperature.

[0219] Furthermore, by implanting carbon ions at a temperature of 1000° C. or higher, damage caused by the carbon ion implantation can be reduced, thereby improving the characteristics of the MOSFET 200.

[0220] The second ion implantation and the fourth ion implantation for implanting aluminum (Al) are preferably performed at a temperature of 1000°C or higher. By implanting impurity ions at a temperature of 1000°C or higher, damage caused by the ion implantation of the impurity can be reduced. Amorphization of the silicon carbide layer 10 due to damage can be suppressed, and high crystallinity can be maintained, thereby increasing the activation efficiency after activation annealing. Since the higher the ion implantation temperature, the higher the crystallinity of the silicon carbide layer 10 can be maintained, the ion implantation temperature is more preferably 1100°C or higher.

[0221] From the viewpoint of suppressing thermal deterioration of the mask material 40 and the sidewall material 44, the temperatures of the first ion implantation, the second ion implantation, the third ion implantation, and the fourth ion implantation are preferably 1300°C or less, and more preferably 1200°C.

[0222] Prior to the second ion implantation of aluminum, the first carbon region 52 is formed by the first ion implantation of carbon, which makes it possible to suppress the diffusion of impurities caused by ion implantation at high temperatures.

[0223] From the viewpoint of suppressing aluminum diffusion, it is preferable that the maximum concentration of carbon implanted in silicon carbide layer 10 by the first ion implantation be higher than the maximum concentration of aluminum implanted in silicon carbide layer 10 by the second ion implantation.

[0224] From the viewpoint of suppressing aluminum diffusion, the carbon dose in the first ion implantation is preferably 10 times or more, and more preferably 100 times or more, the aluminum dose in the second ion implantation.

[0225] From the viewpoint of suppressing the diffusion of aluminum, it is preferable that the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment.

[0226] Prior to the fourth ion implantation of aluminum, the second carbon region 56 is formed by the third ion implantation of carbon, so that diffusion of impurities due to high-temperature ion implantation can be suppressed.

[0227] From the viewpoint of suppressing aluminum diffusion, it is preferable that the maximum concentration of carbon implanted in silicon carbide layer 10 by the third ion implantation be higher than the maximum concentration of aluminum implanted in silicon carbide layer 10 by the fourth ion implantation.

[0228] From the viewpoint of suppressing aluminum diffusion, the dose of carbon in the third ion implantation is preferably 10 times or more, and more preferably 100 times or more, the dose of aluminum in the fourth ion implantation.

[0229] From the viewpoint of suppressing the diffusion of aluminum, it is preferable that the distribution of carbon implanted into silicon carbide layer 10 by the third ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the fourth ion implantation in silicon carbide layer 10 before heat treatment.

[0230] The heat treatment temperature is preferably 1850°C or higher. By performing the heat treatment at 1850°C or higher, the activation rate of the impurities is improved. Note that, since a carbon region is formed by carbon ion implantation prior to the aluminum ion implantation, aluminum diffusion can be suppressed even when the heat treatment is performed at 1850°C or higher.

[0231] In the MOSFET 200 of the second embodiment, the first distance (d1 in FIGS. 13 and 14) between two adjacent trenches 11 is 1.0 μm or less, and the second distance (d2 in FIG. 13) between two adjacent electric field relaxation regions 32 is at least half the first distance (d1 in FIGS. 13 and 14) between two adjacent trenches 11.

[0232] Although the first distance d1 between two adjacent trenches 11 is as small as 1.0 μm or less, the distance d2 between two adjacent electric field relaxation regions 32 is not narrowed. Therefore, the on-resistance of the MOSFET 200 can be reduced.

[0233] Furthermore, in the MOSFET 200 of the second embodiment, the p-type impurity concentration of the electric field relaxation region 32 is 1×10 20 cm -3 Therefore, the switching loss of the MOSFET 200 is reduced, and the reliability of the gate insulating layer 14 is improved.

[0234] From the viewpoint of reducing the on-resistance of the MOSFET 200, the first distance d1 between two adjacent trenches 11 is preferably equal to or less than 0.8 μm, and more preferably equal to or less than 0.6 μm.

[0235] From the viewpoint of reducing the on-resistance of the MOSFET 200, the second distance d2 between two adjacent electric field relaxation regions 32 is preferably at least two-thirds of the first distance d1 between two adjacent trenches 11, more preferably at least four-fifths of the first distance d1, and even more preferably at least the first distance d1.

[0236] From the viewpoint of reducing the switching loss of the MOSFET 200 and improving the reliability of the gate insulating layer 14, the p-type impurity concentration of the electric field relaxation region 32 is set to 5×10 20 cm -3 It is preferable that the concentration is 1×10 or more. 21 cm -3 More preferably, it is equal to or greater than this.

[0237] As described above, according to the semiconductor device manufacturing method and the semiconductor device of the second embodiment, it is possible to achieve a reduction in on-resistance.

[0238] In the above, in the first and second embodiments, aluminum (Al) has been used as an example of a p-type impurity, but boron (B) can also be used as a p-type impurity.

[0239] In the first and second embodiments, the first ion implantation is performed before the second ion implantation, but the first ion implantation can also be performed after the second ion implantation. Also, in the second embodiment, the third ion implantation is performed before the fourth ion implantation, but the third ion implantation can also be performed after the fourth ion implantation.

[0240] In the above, the first and second embodiments have been described using an example in which the silicon carbide has a crystal structure of 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0241] In the first and second embodiments, a MOSFET is used as an example of a semiconductor device, but the present invention can also be applied to an insulated gate bipolar transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 22 of the MOSFET 100 from n-type to p-type.

[0242] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0243] 10 Silicon carbide layer 11 Trench 11a First Trench 11b Second trench 11x First Aspect 11y Second Aspect 12a First gate electrode 12b Second gate electrode 14a First gate insulating layer 14b Second gate insulating layer 16 Source electrode (first electrode) 18 Drain electrode (second electrode) 24 drift region (first silicon carbide region) 26 Body region (second silicon carbide region) 28 source region (third silicon carbide region) 32a First electric field relaxation region (fourth silicon carbide region) 32b Second electric field relaxation region (fifth silicon carbide region) 40 Masking material 40a opening 44 Sidewall material 50 First mask material 50a opening 54 Second mask material 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) F1 First Side F2 Second side d1 First distance d2 Second distance d3 Third distance

Claims

1. forming a mask material having an opening on the surface of the silicon carbide layer; forming a trench in the silicon carbide layer using the mask material as a mask; performing a first ion implantation to implant carbon (C) into the bottom surface of the trench using the mask material as a mask; forming a sidewall material on a side surface of the trench; performing a second ion implantation using the sidewall material as a mask to implant a p-type first impurity into the bottom surface of the trench; removing the mask material and the sidewall material; After removing the mask material and the sidewall material, a heat treatment is performed at 1600° C. or more. A method for manufacturing a semiconductor device, wherein the dose of carbon (C) implanted in the first ion implantation is 10 times or more the dose of the first impurity implanted in the second ion implantation.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first ion implantation is carried out at a temperature of 1000[deg.] C. or higher.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said second ion implantation is carried out at a temperature of 1000[deg.] C. or higher.

4. A mask material having an opening is formed on the surface of a silicon carbide layer, forming a trench in the silicon carbide layer using the mask material as a mask; performing a first ion implantation to implant carbon (C) into the bottom surface of the trench using the mask material as a mask; forming a sidewall material on a side surface of the trench; performing a second ion implantation using the sidewall material as a mask to implant a p-type first impurity into the bottom surface of the trench; removing the mask material and the sidewall material; After removing the mask material and the sidewall material, a heat treatment is performed at 1600° C. or more. a third ion implantation step of implanting carbon (C) into the bottom surface of the trench using the sidewall material as a mask after forming the sidewall material and before the heat treatment;

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a dose of carbon (C) implanted in said third ion implantation is higher than a dose of carbon (C) implanted in said first ion implantation.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first impurity is aluminum (Al).

7. forming a first mask material having an opening on a surface of a silicon carbide layer; forming a trench in the silicon carbide layer using the first mask material as a mask, the trench having a first side surface and a second side surface and extending in a first direction parallel to the surface; performing a first ion implantation to implant carbon (C) into the second side surface of the trench using the first mask material as a mask; performing a second ion implantation using the first mask material as a mask to implant a p-type first impurity into the second side surface of the trench; performing a third ion implantation to implant carbon (C) into the bottom surface of the trench using the first mask material as a mask; forming a sidewall material on the first side surface and the second side surface of the trench; performing a fourth ion implantation using the sidewall material as a mask to implant a p-type second impurity into the bottom surface of the trench; removing the first mask material and the sidewall material; A method for manufacturing a semiconductor device, comprising the steps of: removing the first mask material and the sidewall material; and performing a heat treatment at 1600° C. or higher.

8. 8. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming a second mask material covering a part of said trench after said first ion implantation and before said second ion implantation.

9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein said first ion implantation is performed by oblique ion implantation.

10. 8. The method for manufacturing a semiconductor device according to claim 7, wherein said second ion implantation is performed by oblique ion implantation.

11. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a dose of carbon (C) implanted in the first ion implantation is 10 times or more a dose of the first impurity implanted in the second ion implantation.

12. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a distribution of carbon (C) implanted into said silicon carbide layer by said first ion implantation, in said silicon carbide layer before said heat treatment, covers a distribution of said first impurity implanted into said silicon carbide layer by said second ion implantation, in said silicon carbide layer before said heat treatment.

13. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first impurity and the second impurity are aluminum (Al).

14. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench in the silicon carbide layer, the first trench extending in the first direction at the first surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench present in the silicon carbide layer, extending in the first direction on the first surface, the first distance in the second direction between the second trench and the first trench being 1.0 μm or less; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; an n-type third silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; a first p-type impurity region having a first p-type impurity concentration of 1×10 ２０ cm －３ a fourth region of higher p-type silicon carbide; and a second p-type impurity region located in the silicon carbide layer between the first silicon carbide region and the second trench, the second p-type impurity region having a concentration of 1×10 ２０ cm －３ a fifth region of higher p-type silicon carbide; and a first electrode located on the first surface side of the silicon carbide layer and electrically connected to the second silicon carbide region and the third silicon carbide region; a second electrode located on the second surface side of the silicon carbide layer; Equipped with a second distance in the second direction between the fourth silicon carbide region and the fifth silicon carbide region is equal to or greater than half of the first distance; The semiconductor device, wherein the first p-type impurity concentration and the second p-type impurity concentration are 1×10 21 cm −3 or more.

15. 15. The semiconductor device according to claim 14, wherein the first distance is equal to or less than 0.8 [mu]m.

16. 15. The semiconductor device according to claim 14, wherein the second distance is equal to or greater than the first distance.

17. 15. The semiconductor device according to claim 14, further comprising: a plurality of p-type sixth silicon carbide regions located in the silicon carbide layer, in contact with the fourth silicon carbide region, between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the third silicon carbide region and the first trench, and repeatedly arranged in the first direction.

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