Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that is increased in carrier lifetime.SOLUTION: A semiconductor device is provided, comprising: a first conductivity-type first semiconductor layer including first conductivity-type impurities; a first conductivity-type second semiconductor layer that is provided on the first semiconductor layer and contains first conductivity-type impurity having concentration lower than that of the first semiconductor layer; and a third semiconductor layer that is provided within the first semiconductor layer and contains hydrogen having a concentration of 5×1017atoms / cm3 or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are used for power conversion and other applications. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-009148 [Patent Document 2] Patent No. 6662393 [Patent Document 3] International Publication No. 2013 / 080417 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device having an increased carrier lifetime. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a first semiconductor layer of a first conductivity type containing a first conductivity type impurity, a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower concentration of the first conductivity type impurity than the first semiconductor layer, and a second semiconductor layer of a first conductivity type provided in the first semiconductor layer and having a hydrogen concentration of 5×10 17 atoms / cm 3 and a third semiconductor layer having the above structure. The hydrogen concentration in the third semiconductor layer is 500 times or more higher than the concentration of the first conductivity type carriers in the third semiconductor layer. . [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another aspect of the first embodiment. [Figure 3] 4 is a graph showing impurity concentrations in the semiconductor device of the first embodiment. [Figure 4] 4 is a graph showing carrier concentrations in the semiconductor device of the first embodiment. [Figure 5] 4 is a graph showing the hydrogen concentration and the n-type carrier concentration before and after hydrogen plasma treatment in the semiconductor device of the first embodiment. [Figure 6] 10 shows DLTS spectrum waveforms before and after hydrogen plasma treatment in the semiconductor device of the first embodiment. [Figure 7] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 3 is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device of the first embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components will be denoted by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0009] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type.

[0010] In the following description, n + , n, n - and p+ , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0011] (First embodiment) The semiconductor device of this embodiment includes a first semiconductor layer of a first conductivity type containing a first conductivity type impurity, a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower concentration of the first conductivity type impurity than the first semiconductor layer, and a second semiconductor layer of a first conductivity type provided in the first semiconductor layer and having a hydrogen concentration of 5×10 17 atoms / cm 3 and a third semiconductor layer as described above.

[0012] The semiconductor device of this embodiment further includes a first semiconductor region of a second conductivity type provided on the second semiconductor layer, a second semiconductor region of the first conductivity type provided on the first semiconductor region, a first electrode provided in a trench extending from above the second semiconductor region to the second semiconductor layer via a first insulating film in the first semiconductor region, a second insulating film provided on the first electrode, a second electrode provided on the second semiconductor region and the second insulating film, a fourth semiconductor layer provided below the first semiconductor layer, and a third electrode provided below the fourth semiconductor layer and electrically connected to the fourth semiconductor layer.

[0013] Alternatively, the semiconductor device of this embodiment further includes a first semiconductor region of a second conductivity type provided on the second semiconductor layer, a second semiconductor region of the first conductivity type provided in the first semiconductor region, a first electrode provided on the first semiconductor region, a first insulating film provided between the first semiconductor region and the first electrode, a second insulating film provided on the first electrode, a second electrode provided on the second semiconductor region and the second insulating film, a fourth semiconductor layer provided below the first semiconductor layer, and a third electrode provided below the fourth semiconductor layer and electrically connected to the fourth semiconductor layer.

[0014] 1 is a schematic cross-sectional view of a semiconductor device 100a according to this embodiment. The semiconductor device 100a is a vertical trench IGBT.

[0015] The semiconductor device 100a includes a semiconductor substrate 2, a collector electrode 4, a collector layer 6, a first buffer layer 8, a drift layer 10, a second buffer layer 12, an emitter electrode 20, a trench 30, a gate insulating film 40, a gate electrode 42, an emitter region 44, a contact region 46, an interlayer insulating film 48, and a base region 50.

[0016] The first buffer layer 8 is an example of a first semiconductor layer. The drift layer 10 is an example of a second semiconductor layer. The second buffer layer 12 is an example of a third semiconductor layer. The base region 50 is an example of a first semiconductor region. The emitter region 44 is an example of a second semiconductor region. The gate insulating film 40 is an example of a first insulating film. The gate electrode 42 is an example of a first electrode. The interlayer insulating film 48 is an example of a second insulating film. The emitter electrode 20 is an example of a second electrode. The collector layer 6 is an example of a fourth semiconductor layer. The collector electrode 4 is an example of a third electrode.

[0017] The semiconductor substrate 2 is, for example, a silicon (Si) substrate. However, the semiconductor substrate 2 may be a substrate containing other semiconductor materials, such as a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. The semiconductor substrate 2 has a first surface 2a and a second surface 2b provided on the first surface 2a and facing the first surface 2a.

[0018] Here, when the semiconductor substrate 2 is a Si substrate, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be preferably used as the n-type impurity. When the semiconductor substrate 2 is a Si substrate, for example, boron (B) can be used as the p-type impurity. In this specification, hydrogen (H) is not included in either "n-type impurity" or "p-type impurity."

[0019] Also, here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X and Y directions are defined. The first surface 2a and the second surface 2b are planes parallel to the XY plane. The "depth direction" of the semiconductor device 100a, which will be described later, is a direction parallel to the Z direction. Figure 1 is a schematic cross-sectional view of the semiconductor device 100a in the YZ plane.

[0020] The first buffer layer 8 is provided in the semiconductor substrate 2. The first buffer layer 8 is provided, for example, parallel to the XY plane. The first buffer layer 8 is provided, for example, to suppress the extension of a depletion layer during switching of the IGBT. The first buffer layer 8 is, for example, n + The first buffer layer 8 contains an n-type semiconductor material. 14 atoms / cm 3 More than 1×10 17 atoms / cm 3 The first buffer layer 8 contains hydrogen at a concentration of, for example, 1×10 14 atoms / cm 3 5x10 or more 17 atoms / cm 3 Includes the following:

[0021] The drift layer 10 is provided in the semiconductor substrate 2. The drift layer 10 is provided, for example, on the first buffer layer 8 and parallel to the XY plane. The drift layer 10 has, for example, an n - The drift layer 10 contains an n-type semiconductor material. 12 atoms / cm 3 More than 1×10 15atoms / cm 3 Includes the following:

[0022] The collector layer 6 is provided in the semiconductor substrate 2. The collector layer 6 is provided, for example, under the first buffer layer 8 and parallel to the XY plane. The collector layer 6 is, for example, p + The collector layer 6 contains a p-type semiconductor material. 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Includes the following:

[0023] The collector electrode 4 is provided below the first surface 2a of the semiconductor substrate 2. The collector electrode 4 is provided below the collector layer 6. The collector electrode 4 is electrically connected to the collector layer 6.

[0024] The second buffer layer 12 has a hydrogen (H) concentration of 5×10 17 atoms / cm 3 As will be described later, the second buffer layer 12 is formed by proton irradiation from the first surface 2a side, subsequent hydrogen plasma treatment of the first surface 2a, and subsequent annealing of the semiconductor substrate 2. The second buffer layer 12 is formed, for example, by reducing the V ce This is provided to suppress oscillation of the emitter-collector voltage.

[0025] The position where the second buffer layer 12 is provided varies depending on the manufacturing process, which includes the proton irradiation from the first surface 2a side, the subsequent hydrogen plasma treatment of the first surface 2a, and the subsequent annealing of the semiconductor substrate 2. For example, the second buffer layer 12 may be provided in the first buffer layer 8, as illustrated as second buffer layer 12c in FIG. 1 . The second buffer layer 12 may also be provided across the collector layer 6 and the first buffer layer 8, as illustrated as second buffer layer 12b in FIG. 1 . The second buffer layer 12 may also be provided across the collector layer 6, the first buffer layer 8, and the drift layer 10, as illustrated as second buffer layer 12a in FIG. 1 . For example, the second buffer layer 12 may also be provided in the collector layer 6. For example, the second buffer layer 12 may also be provided in the drift layer 10. For example, the second buffer layer 12 may also be provided across the first buffer layer 8 and the drift layer 10. When the second buffer layer 12 is provided in the first buffer layer 8, the second buffer layer 12 is provided on the collector layer 6.

[0026] The base region 50 is provided in the semiconductor substrate 2. The base region 50 is provided on the drift layer 10. The base region 50 includes, for example, a p-type semiconductor material. The base region 50 is doped with a p-type impurity at a concentration of, for example, 1×10 16 atoms / cm 3 More than 1×10 18 atoms / cm 3 1 shows base region 50a, base region 50b, base region 50c, and base region 50d.

[0027] The emitter region 44 is provided in the semiconductor substrate 2. The emitter region 44 is provided on the base region 50. The emitter region 44 is, for example, an n + The emitter region 44 includes an n-type semiconductor material. 18 atoms / cm 3 More than 1×10 21 atoms / cm 31, emitter region 44a, emitter region 44b, emitter region 44c, emitter region 44d, emitter region 44e, and emitter region 44f are shown.

[0028] The contact region 46 is provided in the semiconductor substrate 2. The contact region 46 is provided on the base region 50. The contact region 46 is, for example, p + The contact region 46 contains a p-type semiconductor material. 18 atoms / cm 3 More than 1×10 21 atoms / cm 3 1, contact region 46a, contact region 46b, contact region 46c, and contact region 46d are provided. Contact region 46a is provided in contact with emitter region 44a. Contact region 46b is provided between emitter region 44b and emitter region 44c. Contact region 46c is provided between emitter region 44d and emitter region 44e. Contact region 46d is provided in contact with emitter region 44f.

[0029] The gate electrode 42 is provided in the trench 30 extending from above the emitter region 44 to the drift layer 10, with the base region 50 and the gate insulating film 40 interposed therebetween. The gate electrode 42 is provided in the trench 30 extending from above the emitter region 44 to the drift layer 10, with the base region 50 interposed therebetween, with the gate insulating film 40 interposed therebetween. FIG. 1 illustrates gate electrodes 42a, 42b, and 42c. FIG. 1 also illustrates trenches 30a, 30b, and 30c. FIG. 1 also illustrates gate insulating films 40a, 40b, and 40c. The gate electrode 42a is provided in the trench 30a, facing the base region 50a and the base region 50b with the gate insulating film 40a interposed therebetween. The gate electrode 42b is provided in the trench 30b, facing the base region 50b and the base region 50c with the gate insulating film 40b interposed therebetween. The gate electrode 42c is provided in the trench 30c so as to face the base region 50c and the base region 50d via the gate insulating film 40c.

[0030] The emitter electrode 20 is disposed on the emitter region 44 and the contact region 46 .

[0031] The interlayer insulating film 48 is provided between the gate electrode 42 and the emitter electrode 20. The interlayer insulating film 48 insulates the gate electrode 42 and the emitter electrode 20 from each other. FIG. 1 shows interlayer insulating films 48a, 48b, and 48c. The interlayer insulating film 48a is provided between the gate electrode 42a and the emitter electrode 20. The interlayer insulating film 48b is provided between the gate electrode 42b and the emitter electrode 20. The interlayer insulating film 48c is provided between the gate electrode 42c and the emitter electrode 20.

[0032] The gate insulating film 40 and the interlayer insulating film 48 include an insulating material such as silicon oxide.

[0033] The collector electrode 4 and the emitter electrode 20 include a conductive material such as Al (aluminum).

[0034] The gate electrode 42 includes a conductive material such as, for example, conductive polysilicon containing impurities.

[0035] 2 is a schematic cross-sectional view of a semiconductor device 100b according to another aspect of this embodiment. The semiconductor device 100b is a vertical planar IGBT.

[0036] In FIG. 2, base region 50a and base region 50b are shown.

[0037] The emitter region 44 is provided in the base region 50. The emitter region 44a and the emitter region 44b are shown in Figure 2. The emitter region 44a is provided in the base region 50a. The emitter region 44b is provided in the base region 50b.

[0038] The gate electrode 42 is provided on the base region 50 .

[0039] The gate insulating film 40 is provided between the gate electrode 42 and the base region 50 .

[0040] The emitter electrode 20 is provided on the emitter region 44 and the gate electrode 42. The emitter electrode 20 is electrically connected to the emitter region 44.

[0041] The interlayer insulating film 48 is provided between the gate electrode 42 and the emitter electrode 20 .

[0042] The semiconductor device 100a shown in FIG. 1 and the semiconductor device 100b shown in FIG. 2 are both preferred aspects of the semiconductor device 100 of this embodiment.

[0043] Fig. 3 is a graph showing the impurity concentration in the semiconductor device 100 of this embodiment. The horizontal axis of Fig. 3 represents the distance from the collector electrode 4 in a direction parallel to the Z direction. The longer the distance from the collector electrode 4, the closer the semiconductor device is to the second surface 2b.

[0044] Also, in Figure 3, boron (11 B), phosphorus ( 31 P), and hydrogen ( 1 H) impurity concentrations are shown.

[0045] 3, the hydrogen concentration in the second buffer layer 12 is 5×10 17 atoms / cm 3 3, the second buffer layer 12 is provided across the collector layer 6 and the first buffer layer 8. In the example shown in FIG.

[0046] The hydrogen concentration increases from 2×10 18 atoms / cm 3 The hydrogen concentration increases to about 2×10 18 atoms / cm 3 The distance between the collector electrode 4 (or the first surface 2a) and the increased area corresponds to the projected range (Rp) of the protons. As the distance from the collector electrode 4 increases further, the hydrogen concentration increases by 2×10 17 atoms / cm 3 Thereafter, the hydrogen concentration decreases relatively slowly with increasing distance from the collector electrode 4.

[0047] It should be noted that the change in hydrogen concentration with the distance from the collector electrode 4 is not limited to that shown in FIG.

[0048] FIG. 4 is a graph showing the carrier concentration in the semiconductor device 100 of this embodiment. The horizontal axis of FIG. 4 represents the distance from the collector electrode 4 in a direction parallel to the Z direction. 11 B) carrier concentration of holes generated from phosphorus ( 31 P) and hydrogen ( 1 H) resulting from the carrier concentration of electrons "N - " is shown.

[0049] The dependency of the carrier concentration of holes generated from boron on the distance from the collector electrode 4 is approximately the same as the dependency of the impurity concentration of boron on the distance from the collector electrode 4 .

[0050] The dependency of the carrier concentration of electrons generated from phosphorus on the distance from the collector electrode 4 is approximately the same as the dependency of the impurity concentration of phosphorus on the distance from the collector electrode 4 .

[0051] The activation rate of hydrogen is lower than that of boron and phosphorus. The activation rate of hydrogen is about 1%. Therefore, the carrier concentration of electrons generated from hydrogen (N - ) is lower than the concentration of hydrogen.

[0052] The hydrogen concentration is 2×10 at a distance equivalent to the proton's projected range. 18 atoms / cm 3 However, the carrier concentration of electrons originating from hydrogen does not show the same sharp increase as seen in the hydrogen concentration at a distance equivalent to the proton projected range.

[0053] The carrier concentration of electrons originating from hydrogen (N - ) increases with increasing distance from the collector electrode by 1×10 15 / cm 3 The carrier concentration of electrons originating from hydrogen decreases gradually with increasing distance from the collector electrode.

[0054] 5 is a graph showing the hydrogen concentration and n-type carrier concentration before and after hydrogen plasma treatment in the semiconductor device 100 of this embodiment. The n-type carrier concentration is almost the same before and after the hydrogen plasma treatment. On the other hand, the hydrogen concentration after the hydrogen plasma treatment is 2×10 18 atoms / cm 3The concentration of hydrogen in the second buffer layer 12 increases sharply up to a distance corresponding to the projected range of protons. In other words, the semiconductor device 100 of this embodiment has a second buffer layer 12 in which hydrogen, which has a low donor contribution rate, is highly concentrated near a distance corresponding to the projected range of protons. Here, the concentration of hydrogen in the second buffer layer 12 is preferably 500 times or more higher than the n-type carrier concentration (concentration of carriers of the first conductivity type) of the second buffer layer 12.

[0055] The impurity concentration in the semiconductor device 100 can be measured by, for example, secondary ion mass spectroscopy (SIMS).

[0056] The carrier concentration in the semiconductor device 100 can be measured by, for example, spreading resistance analysis (SRA).

[0057] 6 shows DLTS (Deep Level Transient Spectroscopy) spectrum waveforms before and after hydrogen plasma treatment in the semiconductor device 100 of this embodiment. Peaks due to the first complex defect, the second complex defect, the third complex defect, and the fourth complex defect are observed.

[0058] Here, the measured temperature of the second complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the first complex defect measured by deep level transient spectroscopy. The measured temperature of the third complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the second complex defect measured by deep level transient spectroscopy. The measured temperature of the fourth complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the third complex defect measured by deep level transient spectroscopy.

[0059] The absolute values ​​of the signal intensity of the first complex defects before and after the hydrogen plasma treatment are shown in FIG.

[0060] The first complex defect is a defect containing O (oxygen) and C (carbon). The second complex defect is a defect containing O (oxygen), C (carbon), and H (hydrogen). The third complex defect contains any of O, C, H, Si, and V (vacancy), and is a defect different from the first complex defect and the second complex defect. The fourth complex defect contains any of O, C, H, Si, and V (vacancy), and is a defect different from the first complex defect, the second complex defect, and the third complex defect.

[0061] The absolute values ​​of the signal intensities of the third complex defects and the fourth complex defects after the hydrogen plasma treatment are smaller than the absolute values ​​of the signal intensities of the third complex defects and the fourth complex defects before the hydrogen plasma treatment, which indicates that the amount of the third complex defects and the fourth complex defects has decreased by the hydrogen plasma treatment.

[0062] Here, it is preferable that the absolute value of the signal intensity of the first complex defect measured by deep level transient spectroscopy is four or more times higher than the sum of the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy and the absolute value of the signal intensity of the fourth complex defect measured by deep level transient spectroscopy.

[0063] Furthermore, it is preferable that the absolute value of the signal intensity of the second complex defect measured by deep level transient spectroscopy is three or more times higher than the sum of the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy and the absolute value of the signal intensity of the fourth complex defect measured by deep level transient spectroscopy.

[0064] In addition, the carrier lifetime was measured using the μ-PCD (Microwave Photo Conductivity Decay) method. The carrier lifetime before hydrogen plasma treatment was 239.1 μsec, but after hydrogen plasma treatment it increased to 338.1 μsec. It is thought that the increase in carrier lifetime was due to the reduction in the amounts of third and fourth complex defects caused by hydrogen plasma treatment.

[0065] FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment.

[0066] The method for manufacturing a semiconductor device according to the present embodiment includes the steps of: implanting a first conductivity type impurity into a semiconductor substrate having a first surface and a second surface disposed on the first surface and facing the first surface, from the first surface side, thereby forming a first semiconductor layer of the first conductivity type; irradiating the first surface side with protons; performing hydrogen plasma treatment on the first surface side; and annealing the semiconductor substrate, thereby forming a first semiconductor layer of the first conductivity type, the first semiconductor layer being provided with hydrogen at a concentration of 5×10 17 atoms / cm 3 The third semiconductor layer is formed as described above.

[0067] First, a semiconductor substrate 2 is prepared. Here, the semiconductor substrate 2 is, for example, an n-type silicon substrate containing phosphorus. Next, an IGBT element structure is formed on the second surface 2b side of the semiconductor substrate 2. That is, a base region 50, an emitter region 44, a contact region 46, a trench 30, a gate electrode 42, an interlayer insulating film 48, and an emitter electrode 20 are formed on the second surface 2b side of the semiconductor substrate 2 (S2).

[0068] Next, the first surface 2a of the semiconductor substrate 2 is ground to make the semiconductor substrate 2 have a desired thickness (S4).

[0069] Next, for example, phosphorus is implanted by ion implantation from the first surface 2a side of the ground semiconductor substrate 2 to form an n-type first buffer layer 8 on the first surface 2a side. Furthermore, for example, boron is implanted by ion implantation from the first surface 2a side of the ground semiconductor substrate 2 to a position shallower than the first buffer layer 8 (on the first surface 2a side) to form a collector layer 6 below the first buffer layer 8 (S6). The semiconductor substrate 2 between the first buffer layer 8 and the IGBT element structure is used as a drift layer 10.

[0070] Next, protons are irradiated from the first surface 2a side of the ground semiconductor substrate 2 (S8). Here, the proton irradiation is performed by, for example, a method using a cyclotron accelerator. The acceleration energy of the protons is, for example, about 4 MeV. The dose of protons injected is, for example, 1.5×10 14 / cm 2 The proton irradiation may be performed by ion implantation.

[0071] Next, a hydrogen plasma treatment is performed on the first surface 2a side of the ground semiconductor substrate 2 (S10). Here, the hydrogen plasma treatment is performed in an atmosphere at 400° C. for 5 minutes, for example.

[0072] Next, the semiconductor substrate 2 that has been subjected to the hydrogen plasma treatment is annealed in, for example, N2 gas (nitrogen gas) (S12). Here, the annealing is performed at, for example, 400° C. for 120 minutes.

[0073] As a result, the second buffer layer 12 is formed.

[0074] Next, a collector electrode 4 is formed on the first surface 2a side of the ground semiconductor substrate (S14), thereby obtaining the semiconductor device 100 of this embodiment.

[0075] Next, the effects of the semiconductor device 100 of this embodiment will be described.

[0076] During the IGBT switching process, V ce This has led to vibration and oscillation. Therefore, it has been desired to suppress such oscillation. Here, it is believed that such oscillation occurs, for example, when the depletion layer expands from the base region 50 to the drift layer 10 at the time of turning off the IGBT, because the number of accumulated carriers decreases.

[0077] Therefore, the semiconductor device of this embodiment includes a first semiconductor layer of a first conductivity type containing a first conductivity type impurity, a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower concentration of the first conductivity type impurity than the first semiconductor layer, and a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a hydrogen concentration of 5×10 17 atoms / cm 3 and a third semiconductor layer as described above.

[0078] FIG. 8 is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device of this embodiment.

[0079] 8(a) is a diagram showing the hydrogen concentration in the depth direction in a semiconductor device that is a comparative example of this embodiment, in which the semiconductor substrate 2 is irradiated with protons from the first surface 2a side and then annealed without being treated with hydrogen plasma.

[0080] By irradiating protons, it is possible to form an n-type semiconductor layer closer (deeper) to the second surface 2b than when using phosphorus, for example. This increases the number of carriers. However, crystal defects are formed in a concentrated manner at a depth corresponding to the proton projected range. These crystal defects cause the problem of shortening the carrier lifetime. Furthermore, even if annealing is performed to reduce the crystal defects, the crystal defects remain.

[0081] 8(b) is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device 100 of this embodiment. Here, in the semiconductor device 100 of this embodiment, after proton irradiation from the first surface 2a side of the semiconductor substrate 2, hydrogen plasma processing is performed, and then annealing is performed.

[0082] In the semiconductor device 100 of this embodiment, hydrogen is trapped near the depth corresponding to the proton projected range by the hydrogen plasma treatment and subsequent annealing, forming the second buffer layer 12. It is believed that the crystal defects formed by the proton irradiation are then hydrogen-terminated by hydrogen. The hydrogen concentration in the second buffer layer 12 is 5×10 17 atoms / cm 3 This is very high. Therefore, hydrogen termination is sufficiently performed. This significantly reduces carrier traps, making it possible to increase the carrier lifetime. Therefore, V ce It is possible to suppress the oscillation.

[0083] On the other hand, as explained with reference to Fig. 5, hydrogen-terminated hydrogen has a low donor contribution rate and is thought to contribute little to the n-type carrier concentration. The hydrogen concentration of the second buffer layer 12 is preferably 500 times or more higher than the n-type carrier concentration of the second buffer layer 12. This is because, in this case, the hydrogen concentration is sufficiently high, so that crystal defects are suitably terminated with hydrogen, and the carrier lifetime is thought to increase.

[0084] Furthermore, it is believed that the amount of the third complex defects and the fourth complex defects was reduced by the hydrogen termination of the crystal defects.

[0085] It is preferable to reduce the amount of the third complex defect and the amount of the fourth complex defect so that the absolute value of the signal intensity measured by deep level transient spectroscopy of the first complex defect is four or more times higher than the sum of the absolute value of the signal intensity measured by deep level transient spectroscopy of the third complex defect and the absolute value of the signal intensity measured by deep level transient spectroscopy of the fourth complex defect, because this sufficiently increases the carrier lifetime.

[0086] It is preferable to reduce the amount of the third complex defect and the amount of the fourth complex defect so that the absolute value of the signal intensity measured by deep level transient spectroscopy of the second complex defect is three or more times higher than the sum of the absolute value of the signal intensity measured by deep level transient spectroscopy of the third complex defect and the absolute value of the signal intensity measured by deep level transient spectroscopy of the fourth complex defect, because this sufficiently increases the carrier lifetime.

[0087] According to the semiconductor device of this embodiment, it is possible to provide a semiconductor device with an increased carrier lifetime.

[0088] (Second embodiment) In the semiconductor device of this embodiment, the third electrode of the semiconductor device of the first embodiment is replaced with a fifth electrode. Also, in the semiconductor device of this embodiment, the fourth semiconductor layer of the semiconductor device of the first embodiment is replaced with a sixth semiconductor layer. Also, in the semiconductor device of this embodiment, the second electrode of the first embodiment is replaced with a fourth electrode. Also, the semiconductor device of this embodiment does not include the first semiconductor region, second semiconductor region, first electrode, second electrode, first insulating film, and second insulating film of the semiconductor device of the first embodiment. The semiconductor device of this embodiment includes a fifth semiconductor layer. Here, description of content that overlaps with the first embodiment will be omitted.

[0089] 9 is a schematic cross-sectional view of a semiconductor device 200 of this embodiment. The semiconductor device 200 of this embodiment is a PIN type diode.

[0090] The semiconductor device 200 includes a semiconductor substrate 2, a cathode electrode 54, a cathode layer 56, a first buffer layer 8, a drift layer 10, a second buffer layer 12, an anode layer 62, and an anode electrode 70.

[0091] The anode layer 62 is an example of a fifth semiconductor layer. The anode electrode 70 is an example of a fourth electrode. The cathode layer 56 is an example of a sixth semiconductor layer. The cathode electrode 54 is an example of a fifth electrode.

[0092] The anode layer 62 is provided in the semiconductor substrate 2. The anode layer 62 is provided on the drift layer 10. The anode layer 62 includes, for example, a p-type semiconductor material. The anode layer 62 is doped with a p-type impurity at a concentration of, for example, 1×10 16 atoms / cm 3 More than 1×10 21 atoms / cm 3 Includes the following:

[0093] The anode electrode 70 is provided on the anode layer 62. The anode electrode 70 is electrically connected to the anode layer 62.

[0094] The cathode layer 56 is provided in the semiconductor substrate 2. For example, the cathode layer 56 is provided below the first buffer layer 8 and parallel to the XY plane. The cathode layer 56 includes, for example, an n-type semiconductor material. The cathode layer 56 is doped with an n-type impurity at a concentration of, for example, 1×10 19 atoms / cm 3 More than 1×10 21 atoms / cm 3 Includes the following:

[0095] The cathode electrode 54 is provided below the semiconductor substrate 2. The cathode electrode 54 is provided below the cathode layer 56. The cathode electrode 54 is electrically connected to the cathode layer 56.

[0096] The position where the second buffer layer 12 is provided varies depending on the manufacturing processes, which include the proton irradiation from the first surface 2a side, the subsequent hydrogen plasma treatment of the first surface 2a, and the subsequent annealing of the semiconductor substrate 2. For example, the second buffer layer 12 may be provided in the first buffer layer 8, as illustrated as second buffer layer 12c in FIG. 9 . The second buffer layer 12 may also be provided across the cathode layer 56 and the first buffer layer 8, as illustrated as second buffer layer 12b in FIG. 9 . The second buffer layer 12 may also be provided across the cathode layer 56, the first buffer layer 8, and the drift layer 10, as illustrated as second buffer layer 12a in FIG. 9 . For example, the second buffer layer 12 may be provided in the cathode layer 56. For example, the second buffer layer 12 may be provided in the drift layer 10. For example, the second buffer layer 12 may also be provided across the first buffer layer 8 and the drift layer 10. When the second buffer layer 12 is provided within the first buffer layer 8, the second buffer layer 12 is provided on the cathode layer 56.

[0097] The anode electrode 70 and the cathode electrode 54 include a conductive material such as Al (aluminum).

[0098] The semiconductor device of this embodiment also makes it possible to provide a semiconductor device with an increased carrier lifetime.

[0099] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0100] 2: Semiconductor substrate 2a: 1st page 2b: 2nd side 4: Collector electrode (third electrode) 6: Collector layer (fourth semiconductor layer) 8: First buffer layer (first semiconductor layer) 10: Drift layer (second semiconductor layer) 12: Second buffer layer (third semiconductor layer) 20: Emitter electrode (second electrode) 30: Trench 40: Gate insulating film (first insulating film) 42: Gate electrode (first electrode) 44: Emitter region (second semiconductor region) 46: Contact area 48: Interlayer insulating film (second insulating film) 50: Base region (first semiconductor region) 54: Cathode electrode (fifth electrode) 56: Cathode layer (sixth semiconductor layer) 62: Anode layer (fifth semiconductor layer) 70: Anode electrode (fourth electrode) 100: Semiconductor device 100a: semiconductor device 100b: semiconductor device 200: Semiconductor device

Claims

1. a first semiconductor layer of a first conductivity type containing first conductivity type impurities; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower concentration of first conductivity type impurities than the first semiconductor layer; The first semiconductor layer has a hydrogen concentration of 5×10 １７ atoms / cm ３ the third semiconductor layer; Equipped with The concentration of hydrogen in the third semiconductor layer is 500 times or more higher than the concentration of first conductivity type carriers in the third semiconductor layer. Semiconductor device.

2. A first semiconductor layer of a first conductivity type containing a first conductivity type impurity; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower concentration of first conductivity type impurities than the first semiconductor layer; a third semiconductor layer provided in the first semiconductor layer and having a hydrogen concentration of 5×10 17 atoms / cm 3 or more; Equipped with The third semiconductor layer is a first complex defect; a second complex defect having a lower measurement temperature measured by deep level transient spectroscopy than the measurement temperature of the first complex defect measured by deep level transient spectroscopy; a third complex defect having a lower measurement temperature measured by deep level transient spectroscopy than the measurement temperature of the second complex defect measured by deep level transient spectroscopy; a fourth complex defect having a measurement temperature by deep level transient spectroscopy lower than the measurement temperature of the third complex defect measured by deep level transient spectroscopy; Including, The absolute value of the signal intensity of the first complex defect measured by deep level transient spectroscopy is four times or more higher than the sum of the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy and the absolute value of the signal intensity of the fourth complex defect measured by deep level transient spectroscopy; Semiconductor device.

3. A first semiconductor layer of a first conductivity type containing a first conductivity type impurity; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower concentration of first conductivity type impurities than the first semiconductor layer; a third semiconductor layer provided in the first semiconductor layer and having a hydrogen concentration of 5×10 17 atoms / cm 3 or more; Equipped with The third semiconductor layer is a first complex defect; a second complex defect having a lower measurement temperature measured by deep level transient spectroscopy than the measurement temperature of the first complex defect measured by deep level transient spectroscopy; a third complex defect having a lower measurement temperature measured by deep level transient spectroscopy than the measurement temperature of the second complex defect measured by deep level transient spectroscopy; a fourth complex defect having a measurement temperature measured by deep level transient spectroscopy lower than the measurement temperature of the third complex defect measured by deep level transient spectroscopy; Including, The absolute value of the signal intensity of the second complex defect measured by deep level transient spectroscopy is three times or more higher than the sum of the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy and the absolute value of the signal intensity of the fourth complex defect measured by deep level transient spectroscopy. Semiconductor device.

4. a first semiconductor region of a second conductivity type provided on the second semiconductor layer; a second semiconductor region of a first conductivity type provided on the first semiconductor region; a first electrode provided in a trench extending from above the second semiconductor region to the second semiconductor layer, the first electrode being provided in the first semiconductor region via a first insulating film; a second insulating film provided on the first electrode; a second electrode provided on the second semiconductor region and the second insulating film; a fourth semiconductor layer provided below the first semiconductor layer; a third electrode provided under the fourth semiconductor layer and electrically connected to the fourth semiconductor layer; The semiconductor device according to claim 1 , further comprising:

5. a first semiconductor region of a second conductivity type provided on the second semiconductor layer; a second semiconductor region of a first conductivity type provided within the first semiconductor region; a first electrode provided on the first semiconductor region; a first insulating film provided between the first semiconductor region and the first electrode; a second insulating film provided on the first electrode; a second electrode provided on the second semiconductor region and the second insulating film; a fourth semiconductor layer provided below the first semiconductor layer; a third electrode provided under the fourth semiconductor layer and electrically connected to the fourth semiconductor layer; The semiconductor device according to claim 1 , further comprising:

6. the third semiconductor layer is provided across the first semiconductor layer and the fourth semiconductor layer; 6. The semiconductor device according to claim 4.

7. a fifth semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth electrode provided on the fifth semiconductor layer and electrically connected to the fifth semiconductor layer; a sixth semiconductor layer provided below the first semiconductor layer; a fifth electrode provided under the sixth semiconductor layer and electrically connected to the sixth semiconductor layer; The semiconductor device according to claim 1 , further comprising:

8. the third semiconductor layer is provided across the first semiconductor layer and the sixth semiconductor layer; 8. The semiconductor device according to claim 7.

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