High density condenser for focal plane arrays.

Abstract

The photodetector structure includes a readout integrated circuit (ROIC) substrate and a dielectric layer overlying the IC substrate. The dielectric layer defines a plurality of recesses formed in an upper surface of the dielectric layer, each recess having at least one sidewall extending from the upper surface of the dielectric layer to a bottom of each respective recess. A capacitor structure forms part of the photodetector structure and includes a first electrode formed over the upper surface of the dielectric layer and across at least one sidewall of each of the plurality of recesses. A capacitor dielectric layer is formed on either side of the first electrode, and a second electrode is formed on either side of the capacitor dielectric layer. A detector overlies the capacitor structure.

Description

[Technical Field]

[0001]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 051,028, filed July 13, 2020, and U.S. Patent Application No. 17 / 244,679, filed April 29, 2021, the disclosures of which are incorporated herein by reference. [Background technology]

[0002]

[0002] As photodetector technology continues to develop, new designs can provide significantly improved resolution compared to past technologies. The resolution of a photodetector is determined, at least in part, by the number of pixels in the detector array. Generally, the more pixels in a detector array, the more detail can be provided during an imaging operation. Improvements in technology have allowed manufacturing operations to produce pixels of much smaller size in order to incorporate more pixels and improve resolution while maintaining the overall shape of the detector array.

[0003] Despite advances in detector arrays, there remains a need in the art for improved methods and systems related to detector arrays. Summary of the Invention

[0004]

[0004] The present technology relates to photodetection devices and processes, and more particularly to photodetector structures that include high density integrated capacitors.

[0005] In some embodiments, the photodetector includes a semiconductor layer having one or more integrated electrical components and a top metal layer. An electrically insulating layer overlies the semiconductor layer and defines a plurality of recesses formed in a first surface of the electrically insulating layer, each recess of the plurality of recesses including at least one sidewall extending from the first surface to a bottom of the respective recess. A capacitor structure is coupled to the one or more integrated electrical components and includes a first electrode formed across the first surface of the electrically insulating layer and along at least one sidewall of each recess of the plurality of recesses, a capacitor dielectric layer formed on the first electrode, and a second electrode formed on the capacitor dielectric layer. The detector overlies the capacitor structure.

[0006] In some embodiments, the electrical isolation layer includes a passivation layer formed on the semiconductor layer as part of the integrated circuit substrate. In various embodiments, the electrical isolation layer includes a dielectric layer disposed between the semiconductor layer and the detector. In some embodiments, a first portion of the electrical isolation layer is disposed between the capacitor structure and the detector, and a second portion of the electrical isolation layer is disposed between the capacitor structure and the semiconductor layer. In some embodiments, the plurality of recesses includes partial vias. In various embodiments, the plurality of recesses includes trenches. In some embodiments, the capacitor structure includes a first capacitor structure, and a second capacitor structure is formed in the dielectric layer and disposed between the first capacitor structure and the detector.

[0007] In some embodiments, the photodetector structure includes a semiconductor layer including an outer metal layer, and an electrically insulating layer overlying the semiconductor layer and defining a plurality of recesses formed in a top surface of the electrically insulating layer. The capacitor structure includes a first electrode formed in the plurality of recesses over a top surface of the electrically insulating layer. A capacitor dielectric layer is formed on either side of the first electrode, and a second electrode is formed on either side of the capacitor dielectric layer. A detector overlies the capacitor structure.

[0008] In some embodiments, the electrical insulating layer includes a passivation layer formed on the semiconductor layer. In various embodiments, the electrical insulating layer includes a dielectric layer disposed between the semiconductor layer and the detector. In some embodiments, a first portion of the electrical insulating layer is disposed between the capacitor structure and the detector, and a second portion of the electrical insulating layer is disposed between the capacitor structure and the semiconductor layer. In various embodiments, the plurality of recesses includes partial vias. In some embodiments, the plurality of recesses includes trenches.

[0009] In some embodiments, the capacitor structure includes a first capacitor structure, and a second capacitor structure is formed in the dielectric layer and disposed between the first capacitor structure and the detector. In various embodiments, the second capacitor structure includes a planar capacitor.

[0010] In some embodiments, a capacitor is formed in a focal plane array unit cell, the capacitor including an electrically insulating layer defining a plurality of recesses formed in a first surface of the electrically insulating layer, the electrically insulating layer being formed above an upper metal layer of a semiconductor substrate. A first electrode is formed in the plurality of recesses across the first surface of the electrically insulating layer. Capacitor dielectric layers are formed on either side of the first electrode, and a second electrode is formed on either side of the capacitor dielectric layer.

[0011] In some embodiments, the electrically insulating layer comprises a passivation portion of the integrated circuit substrate. In various embodiments, the electrically insulating layer comprises a dielectric layer disposed between the readout integrated circuit device and the detector. In some embodiments, the plurality of recesses comprises partial vias. In various embodiments, the plurality of recesses comprises trenches.

[0012]

[0012] The present invention achieves many benefits over conventional approaches. For example, embodiments of the present invention provide the ability to increase the capacitor surface area, thereby increasing the capacitance density per unit cell area. Increased capacitance density allows for smaller focal plane arrays and allows for greater operating flexibility in temperature and flux, known in the art as the "dynamic range" of both the focal plane array and the readout integrated circuit. Increased capacitance density also allows for the addition of more decoupling capacitance internal to the focal plane array, thereby easing the weight and size constraints of the focal plane dewar.

[0013] These and other embodiments of the present invention, along with its many advantages and features, are described in more detail in conjunction with the following text and accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a simplified cross-sectional view of a photodetector structure having a high density capacitor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a simplified isometric view of a portion of the high-density capacitor structure shown in FIG. 1. [Figure 3] FIG. 1 is a simplified plan view of one embodiment of a focal plane array unit cell, in accordance with an embodiment of the present disclosure. [Figure 4] 1 is a cross-sectional view of a recess according to an embodiment of the present disclosure. [Figure 5] FIG. 1 is a simplified electrical diagram of a focal plane array unit cell according to an embodiment of the present disclosure. [Figure 6] FIG. 1 is a simplified cross-sectional view of a multi-condenser focal plane array unit cell according to one embodiment of the present disclosure. [Figure 7] 1 is a simplified cross-sectional view of a photodetector structure having a double-layer high-density capacitor according to an embodiment of the present disclosure. [Figure 8] 1 is a simplified cross-sectional view of a photodetector structure having a planar capacitor structure and a high-density capacitor structure according to an embodiment of the present disclosure. [Figure 9]1 is a method of forming a high density condenser focal plane array unit cell according to an embodiment of the present disclosure. [Figure 10] 1 is a simplified cross-sectional view of a photodetector structure having a high density capacitor according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0024] In the accompanying figures, similar parts and / or features may be labeled with the same reference label. Furthermore, various parts of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar parts and / or features. When only the first reference label is used herein, the description applies to any of the similar parts and / or features that have the same first reference label, regardless of the letter. The figures are not drawn to scale.

[0016]

[0025] The present disclosure generally describes approaches related to photodetector devices that use focal plane arrays. More specifically, the approaches disclosed herein relate to high-density capacitors integrated into an interlayer structure located between a readout integrated circuit ("ROIC") and a detector structure within a focal plane array unit cell. As described herein, as pixel sizes shrink, there is less room to integrate capacitors that provide integration capacitance, which can directly relate to detector array performance. Embodiments of the present invention increase the capacitance density within each pixel unit cell to provide the necessary integration capacitance. Various embodiments of the present invention, including methods, processes, systems, devices, and the like, are described herein.

[0017]

[0026] For example, in some embodiments, a plurality of recesses are formed in a dielectric layer within the focal plane array. The capacitor structure includes two electrodes that follow the topography of the recesses and are insulated by the dielectric layer. The corrugated capacitor structure can increase the surface area of ​​the capacitor compared to a planar capacitor structure that fits within the same planar area.

[0018]

[0027] In another example, additional layers of capacitor structures can be formed in the focal plane array, and the capacitor structures can be dense, planar, or a mix of the two types. In some embodiments, the capacitor structures can be used independently or in combination with an internal integration capacitor, and in other embodiments, one or more of the capacitor structures can be used for other purposes, such as a decoupling capacitor or a bypass capacitor.

[0019]

[0028] To better understand the features and aspects of the high density capacitor structure for a focal plane array according to the present disclosure, the following section provides further context for the disclosure by discussing one particular implementation of a high density capacitor structure for a focal plane array unit cell according to embodiments of the present disclosure. These embodiments, for example, are merely examples, and other embodiments may be used in other focal plane array configurations.

[0020]

[0029] 1 shows a simplified cross-section of a focal plane array unit cell 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the unit cell 100 has three main layers, including a bottom IC substrate 102, a middle dielectric layer 104, and a top photodetector layer 106. A detector 164 is formed in the photodetector layer 106, and in response to the detector detecting infrared light, the semiconductor layer 110 of the IC substrate 102 generates and transfers a corresponding signal to one or more outputs for readout by appropriate system electronics.

[0021]

[0030] More specifically, the semiconductor layer 110, in conjunction with first and second high-density capacitors 116, 118, respectively, disposed between the semiconductor layer and the photodetector layer 106, generates a corresponding signal using integrated active and passive electrical components formed within the semiconductor layer. In the embodiment shown in FIG. 1 , the first and second high-density capacitors 116, 118 are each formed using a plurality of recesses 128 located within the passivation portion 108 of the IC substrate 102 and a capacitor structure 120 that follows the contours of the plurality of recesses. In one embodiment, the plurality of recesses 128 may be in the form of partial vias (also known as blind vias) that form an array of conical topographies, although other topographies may be used in other embodiments, as will be understood by those skilled in the art having the benefit of this disclosure. The wavy geometry of the capacitor structure 120 results in an increased area of ​​the capacitor structure and the associated capacitance of each of the first and second high-density capacitors 116, 118 compared to a planar capacitor structure formed within the same planar region (e.g., a capacitor structure that is planar and does not follow the contours of the plurality of recesses).

[0022]

[0031] The first and second high-density capacitors 116, 118 may be coupled to one or more electrical components in the semiconductor layer 110 using any combination of connectors 138a-138e, vias 142a-142e, 143a-143d, and inter-layer connectors 158a-158c. In the embodiment shown in FIG. 1, the first and second high-density capacitors 116, 118 are each coupled in parallel with the integrating capacitor 112. More specifically, the integrating capacitor 112 has a first electrode coupled to the connectors 138a-138e and a second electrode coupled to the connectors 138b-138d. In one embodiment, the connectors 138a-138e are formed from the top metal layer of the semiconductor layer 110. That is, the semiconductor layer may include a layer of semiconductor material (e.g., silicon) and may also include one or more metal layers (commonly referred to as metal 1, metal 2, etc. by those skilled in the art) insulated by dielectric layers formed as part of the semiconductor layer. As defined herein, the top or outer metal layer is furthest from the silicon material. Connector 138a is coupled to top electrode layer 126 of first high-density capacitor 116 through via 143a, interlayer connector 158a, and via 142a, which is coupled to conductor layer 160. In some embodiments, conductor layer 160 may be a relatively thick conductive layer formed in dielectric layer 104. Conductor layer 160 may be coupled to via 142b, which is coupled to top electrode layer 126 of first capacitor 116. In some embodiments, conductor layer 160 may be coupled to top electrode layer 126 at multiple locations to lower a potential across the top electrode and / or electrically couple separate portions of first capacitor 116 to one another.

[0023]

[0032] Similarly, connector 138e is coupled to the top electrode layer 126 of the second capacitor 118 through via 143d, interlayer connector 158c, and via 142e, which is coupled to conductor layer 160. Conductor layer 160 may be coupled to via 142d, which is coupled to the top electrode layer 126 of the second high density capacitor 118. In some embodiments, conductor layer 160 may be coupled to multiple portions of the top electrode of the high density capacitor to lower a potential across the top electrode and / or electrically couple separate portions of the second capacitor to one another.

[0024]

[0033] The connector 138b is connected to the lower electrode layer 122 of the first capacitor 116 through a via 143b, and the connector 138d is connected to the lower electrode layer 122 of the second capacitor 118 through a via 143c.

[0025]

[0034] Although the first and second capacitors 116, 118 are shown in FIG. 1 as being coupled in parallel with the integrating capacitor 112, the first and second high-density capacitors may be coupled to any other electrical components within the semiconductor layer 110 in any other suitable configuration. For example, in another embodiment, the first high-density capacitor 116 may be coupled in parallel with the integrating capacitor 112, and the second high-density capacitor 118 may be configured for use as a decoupling capacitor. In further embodiments, more than one high-density capacitor layer may be used, including two, three, four, or more separate high-density capacitor layers. The example of two high-density capacitors represented by 116 and 118 is an example of one embodiment of the present invention. Any suitable number of high-density capacitors may be formed and coupled to electrical components within the IC substrate 102 in any suitable manner.

[0026]

[0035] In some embodiments, the use of one or more high-density capacitors 116, 118 within the unit cell 100 can increase the storage capacity for a given unit cell area, allow for reduced size, and / or provide greater temperature and flux manipulation flexibility for both the focal plane array and the IC substrate 102, compared to unit cells that use only capacitors formed within the semiconductor layer 110. In further embodiments, the use of one or more high-density capacitors 116, 118 also improves the ability to add decoupling capacitance internal to the unit cell 100, easing weight and size constraints on focal plane array design. Those skilled in the art, having the benefit of this disclosure, will recognize many variations, modifications, and alternatives. These and other advantages of integrated high-density capacitors are described in more detail below. In particular, unit cell design features, including substrate-related discussion, are provided below.

[0027]

[0036] In some embodiments, the semiconductor layer 110 of the IC substrate 102 is formed from a semiconductor material such as, for example, silicon, silicon germanium, glass, oxides of elements from Group 14 or 15 of the periodic table, gallium arsenide, alloys of various imperfect metals and non-metals including silicon and germanium, or other substrates that can be micro-machined.

[0028]

[0037] Above the semiconductor layer 110 is a passivation portion 108, which can be any type of dielectric material. In some embodiments, the passivation portion can be formed from silicon oxide, silicon nitride, oxides and / or nitrides of elements from Group 14 or 15 of the periodic table, oxides or nitrides of alloys of various impoverished metals and non-metals including gallium arsenide, silicon and geranium, or other substrates amenable to microfabrication. In some embodiments, the passivation portion 108 can be between 1 Angstrom and 3 microns in thickness, and the thickness of the passivation portion can depend on the design of the first and second high-density capacitors 116, 118 and other components described herein.

[0029]

[0038] In some embodiments, at least a portion of the high-density capacitors 116, 118 can be formed in the passivation portion 108. As shown in FIG. 1 , the wave-like structure of the first and second high-density capacitors 116, 118 is created by a plurality of recesses 128 formed in the passivation portion 108, respectively; however, other embodiments may utilize recesses formed in other portions of the unit cell 100, as described in more detail below. More specifically, in some embodiments, at least a portion of the high-density capacitors 116, 118 can be formed in the dielectric layer 104 (see, e.g., FIGS. 6-8 ), and in other embodiments, the entire high-density capacitor can be formed in the dielectric layer. As defined herein, the electrical insulation layer 157 includes any type of passivation layer 108 that can be formed as part of the semiconductor layer 110 and / or any type of dielectric layer 104 that can be formed on the IC substrate 102. In some embodiments, at least a portion of the high-density capacitors 116, 118 can be formed in the electrical insulation layer 157.

[0030]

[0039] In one embodiment, each of the plurality of recesses 128 includes a first sidewall 130 coupled to a flat segment 136 coupled to a second sidewall 132. In some embodiments, each sidewall 130, 132 can be sloped, thereby increasing the area of ​​the capacitor structure 120. In some embodiments, the plurality of recesses 128 can resemble a continuous trench, while in other embodiments, they can resemble an array of vias or a "cone-like structure," and in yet other embodiments, they can be rectangular in shape similar to a trench. In some embodiments, the width and / or diameter of each recess 128 can be between 0.1 microns and 1.0 microns, and in other embodiments, between 0.01 microns and 10.0 microns. One of ordinary skill in the art with the benefit of this disclosure will recognize many variations, modifications, and alternatives.

[0031]

[0040] In some embodiments, the sidewalls 130, 132 may be created by chemical etching, ion beam milling, deep reactive ion etching (DRIE), or other suitable techniques. The angle of each sidewall 130, 132 of the recess 128 may vary depending on the desired density of the capacitor structure and / or manufacturing considerations. In some embodiments, each sidewall of the recess 128 may have the same and / or different slope angle relative to the recess structure on its right and / or left side.

[0032]

[0041] Generally, the angle of inclination, as measured from the top surface of the IC substrate 102, can vary between nearly vertical (e.g., about 90 degrees) and 10 degrees or less. In some embodiments, the cross-sectional profile of the recess 128 can resemble the letter U, V, or W in appearance. Each sidewall 130, 132 can vary in length depending on the design of the capacitor structure 120. In some embodiments, the first sidewall 130 can be the same length as the second sidewall 132 of the recess 128, while in other embodiments, the first sidewall can be a different length than the second sidewall to accommodate different recess structure configurations.

[0033]

[0042] Generally, each sidewall 130, 132 includes an upper portion joined to a flat portion 134 and a lower portion joined to a flat segment 136 between each sidewall. In some embodiments, the sidewalls 130, 132 can be formed with a uniform or smooth slope, as each sidewall slopes upward or downward at a consistent increasing or decreasing rate. This sidewall structure can create a contoured appearance and may aid in creating a uniform distribution of each layer of the capacitor structure 120. In other embodiments, the sidewalls 130, 132 can be formed with a series of steps as each sidewall slopes downward or upward. This series of steps can create the appearance of a set of stairs as each sidewall extends from its respective flat portion 134 to its respective flat segment 136. In some embodiments, each step in the series of steps can be uniform in size with respect to the width and height of each step. In other embodiments, each step in the series of steps can vary in width, height, and / or shape. In some embodiments, each sidewall 130, 132 may be formed using a single etching technique, while in other embodiments, each sidewall may be formed using a combination of different etching techniques.

[0034]

[0043] In some embodiments, the capacitor structure 120 includes a bottom electrode layer 122, a dielectric material 124, and a top electrode layer 126, with each layer of the capacitor structure vertically stacked on top of each other. More specifically, the dielectric material 124 is formed on top of the bottom electrode layer 122, and the top electrode layer 126 is formed on top of the dielectric material 124. Each electrode layer 122, 126 may include one or more materials including a transition metal, such as titanium, or a transition metal nitride, such as titanium nitride. In further embodiments, the electrode layers 122, 126 may include a conductive material that may include a metal, alloy, or other material that may include silver, nickel, copper, platinum, tungsten, iridium, ruthenium, tantalum, chromium, iron, niobium, manganese, aluminum, gallium indium tin, or the like, or some combination of one or more of these or other conductive materials.

[0035]

[0044] In some embodiments, the electrode layers 122, 126 can be formed as thin film coatings deposited using thin film sputtering, evaporation, or other techniques to form uniform layers that can be used as electrodes for capacitors. The thickness of each electrode layer 122, 126 can vary depending on the type of material used and the design of the high-density capacitors 116, 118. In one embodiment, the equivalent series resistance design parameters of the first and second high-density capacitors 116, 118 are used to select appropriate materials and thicknesses for the electrode layers 122, 126. In some embodiments, the thickness of each electrode layer 122, 126 can vary from 1 angstrom to 1 micron, while in other embodiments, each electrode layer can be of a different thickness. In one embodiment, each electrode layer 122, 126 is 50-4000 angstroms thick, while in other embodiments, each electrode layer is 75-3000 angstroms thick, and in one embodiment, each electrode layer is 100-2000 angstroms thick.

[0036]

[0045] In some embodiments, the electrode layers 122, 126 can include a combination of materials and can include multiple layers of materials. For example, in one embodiment, each electrode layer 122, 126 can be composed of at least two layers of material. The layers of material can be the same or different from one another, and in one embodiment, can include both metal and metal nitride layers. As an illustrative example, the bottom electrode layer 122 can include a first layer of material, which can be made from a transition metal, such as titanium. A second layer of material, which can be made from a transition metal nitride, such as titanium nitride, can be layered on top of this first layer of material. The top electrode layer 126 can be formed in a similar manner to the bottom electrode layer 122 or in a different manner. For example, in some embodiments, bottom electrode layer 122 may include a first layer such as bismuth, tin, nickel titanium, aluminum, or tungsten, and a second layer such as bismuth oxide, tin oxide, nickel oxide, titanium nitride, aluminum nitride, or tungsten oxide, while top electrode layer 126 may include an inverted structure including a first layer of bismuth oxide, tin oxide, nickel oxide, titanium nitride, aluminum nitride, or tungsten oxide and a second layer of bismuth, tin, nickel, titanium, aluminum, or tungsten overlying the first layer. One of ordinary skill in the art, having the benefit of this disclosure, will recognize many variations, modifications, and alternatives.

[0037]

[0046] In some embodiments, the dielectric material 124 can include an oxide of a transition metal, or a poor transition metal or post-transition metal. For example, the dielectric material 124 can include titanium, zirconium, hafnium, tantalum, lanthanum, aluminum, gallium, indium, silicon, and other metals that provide suitable permittivity, leakage blocking, or some combination of these or other dielectric properties. Some embodiments can include multiple layers of dielectric material, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 20, etc., or more layers of dielectric material. The layers of dielectric material can be included in alternating layers of two or more dielectrics. For example, the dielectric material 124 can include a three-layer material with bismuth oxide, hafnium oxide, tin oxide, aluminum oxide, and / or zirconium oxide between the electrode layers 122, 126. Alternatively, alternating layers of two materials can be used. Those skilled in the art, having the benefit of this disclosure, will recognize many variations, modifications, and alternatives. In some embodiments, the thickness of the dielectric material 124 may be the same as the thickness of each electrode layer 122, 126. In other embodiments, the dielectric material 124 may be thinner or thicker than each electrode layer 122, 126. The thickness of the dielectric material 124 may vary depending on the design of the first and second high density capacitors 116, 118. In some embodiments, the dielectric material 124 may be deposited using atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), plasma-assisted deposition, or any other suitable process.

[0038]

[0047] In some embodiments, the capacitor structure 120 can follow the topography of the plurality of recesses 128 formed in the passivation portion 108, while in other embodiments, the capacitor structure 120 can follow the topography of a portion of the dielectric layer 104, as described in more detail below. In further embodiments, there can be multiple layers of the capacitor structure 120, some of which can follow a non-planar topography and some of which can follow a planar topography, as described in more detail below. The particular topography of the capacitor structure 120 will vary for each capacitor structure and can be based on other design requirements, such as, but not limited to, the desired capacitance level and / or equivalent series resistance (ESR).

[0039]

[0048] In some embodiments, the first high density capacitor 116 can have a different capacitance and / or performance than the second high density capacitor 118 based on the needs of the particular unit cell 100. More specifically, in some embodiments, the first high density capacitor 116 can have a relatively high density recess 128 used to maximize the capacitance coupled in parallel with the integrating capacitor 112, and the second high density capacitor 118 can have a relatively low density recess 128 and can be used as a decoupling capacitor for the unit cell 100. Those skilled in the art with the benefit of this disclosure will recognize many variations, modifications, and alternatives.

[0040]

[0049] The dielectric layer 104 may be disposed between the IC substrate 102 and the photodetector layer 106 and may form part of the first and second high-density capacitors 116, 118. More specifically, in some embodiments, the dielectric layer 104 may be deposited after the capacitor structure 120, such that the dielectric layer 104 insulates the top and bottom electrodes 122, 126, respectively, and further insulates the photodetector layer 106 from other portions of the unit cell 100. In some embodiments, the dielectric layer 104 may be an oxide, nitride, polymer, or any other material that provides suitable electrical insulation within the unit cell 100. In one embodiment, the dielectric layer 104 may be, for example, silicon dioxide. In some embodiments, multiple layers of the capacitive structure 120 may be formed within an interlayer dielectric, as described in more detail below.

[0041]

[0050] In some embodiments, the dielectric layer 104 can include a conductor layer 160 that is insulated from the photodetector layer 106 and the capacitor structure 120. The conductor layer 160 can be formed using a thin film or thick film process, and in one embodiment, is formed using an electrode plating process to deposit a metallic material. The metallic material can be deposited directly onto predetermined segments using a mask, or the entire top surface of the dielectric layer 104 can be covered with the metallic material, and individual segments can be etched to form the desired features of the conductor layer 160.

[0042]

[0051] In some embodiments, the conductor layer 160 can be configured to uniformly generate an electrical potential across the electrode layers 122, 126 of the capacitor structure 120. In various embodiments, the conductor layer 160 can have a lower electrical resistance than the electrode layers 122, 126 and can be configured to reduce the electrical potential that may form across the electrode layers 122, 126. The thickness of the conductor layer 160 can vary depending on the acceptable electrical potential and / or other performance of the electrodes and manufacturing considerations of the respective first and second high-density capacitors 116, 118. In some embodiments, the conductor layer 160 can be 0.3 to 30 microns thick, in other embodiments, 0.7 to 2 microns thick, and in one embodiment, approximately 1 micron thick. In some embodiments, the conductor layer 160 can be 10 to 10,000 times thicker than the electrode layers 122, 126.

[0043]

[0052] The photodetector layer 106 may be formed on the dielectric layer 104 and may include a reflector layer 162 disposed adjacent to the interlayer dielectric. The reflector layer 162 may be formed from any transition or non-transition metal, such as titanium or aluminum, or any other metal that provides a reflective coating. The reflector layer 162 may allow a signal incident on the detector 164 to pass through the detector multiple times to increase the likelihood of detection. The reflector layer 162 may also provide an electrical connection that allows access to the top electrode.

[0044]

[0053] The detector layer 166 can be disposed above and adjacent to the reflector layer 162. The detector layer 166 can be any type of photodetector material, including a photodiode. In alternative embodiments, the detector layer 166 can be a p-on-n photodiode, an n-on-p photodiode, a PIN photodiode, a bolometer, or the like. The detector layer 166 can be operated at various bias regimes, including a high reverse bias to generate avalanche breakdown. The detector layer 166 can be formed from a variety of materials that can be utilized alone or in combination to generate a resulting bandgap as needed in various situations. The materials can include one or more of silicon, germanium, indium, gallium, vanadium, vanadium oxide, arsenic, mercury, cadmium, tellurium, lead, sulfur, and the like. In one embodiment, an exemplary combination of materials is mercury cadmium telluride ("HgCdTe" or "MCT"), which can be used in various amounts to generate a resulting bandgap of about 0 to about 1.5 eV.

[0045]

[0054] Although the high-density capacitor embodiments described herein are illustrated as being formed as part of a photodetector, the high-density capacitor structure can be formed on any type of substrate. In particular, the capacitor structure can be formed as a discrete capacitive device or can be integrated with a different type of electrical component, such as a microprocessor, a power converter, a logic device, or any other type of integrated circuit-based component. More specifically, in one embodiment, an electrical insulating layer 157 can be formed on a substrate (e.g., a semiconductor substrate layer 110, an organic substrate, a ceramic substrate, or any other material), and the capacitive structure 120 can be formed within the electrical insulating layer to form a discrete capacitor device without integrated circuit functionality. In another embodiment, the semiconductor layer 110 can be part of a microprocessor, the electrical insulating layer 157 can be formed on a semiconductor layer of the microprocessor, and the capacitive structure 120 can be formed within the electrical insulating layer. Those skilled in the art, given the benefit of this disclosure, will recognize other ways to use the capacitor structure 120 described herein.

[0046]

[0055] FIG. 2 illustrates an isometric view of a portion of the capacitive structure 120 of the first high-density capacitor 116 shown in FIG. 1. As shown in FIG. 2, the capacitive structure 120 conforms to a wavy topography formed by a plurality of recesses 128 (see FIG. 1), resulting in increased capacitance compared to a planar structure. More specifically, the wavy topography illustrated in FIG. 2 demonstrates a visible increase in the surface area of ​​the capacitive structure 120 due to interleaved conical formations 205. As described above, the capacitive structure 120 includes a top electrode layer 126, a dielectric 124, and a bottom electrode layer 122, all of which conform to the topography illustrated in FIG. 2. As described herein, in other embodiments, the capacitive structure 120 may have other configurations, geometries, and contours.

[0047]

[0056] FIG. 3 shows a simplified transparent plan view of the focal plane array unit cell 100 shown in FIG. 1. As shown in FIG. 3, the photodetector layer 106 is transparent, and a plurality of recesses 128 are arranged in an array format and distributed across a majority of the unit cell 100. In one embodiment, using 18-20 recesses 128 per unit cell 100 provides a 1.8-2.0 times increase in capacitor density compared to an equivalent planar capacitor formed in the same area. As described herein, in some embodiments, two or more high-density capacitors can be formed such that a portion of the recesses 128 can be used for a first high-density capacitor 116 (see FIG. 1) and the remaining portion of the recesses can be used for a second high-density capacitor 118.

[0048]

[0057] Figure 4 illustrates a partial cross-sectional view of a recess 405 formed in a passivation portion 410 of an IC substrate 415. As shown in Figure 4, recess 405 is a partial via with sloped sidewalls 420 and a relatively flat bottom surface 425. In this particular embodiment, recess 405 is approximately 0.958 microns deep and formed in passivation portion 410 that is approximately 1.075 microns thick.

[0049]

[0058] FIG. 5 shows a simplified electrical diagram 500 of the unit cell 100 shown in FIG. 1 . As shown in FIG. 5 , the first and second high-density capacitors 116, 118 are connected in parallel with the integrating capacitor 112. The integrating capacitor 112 may be coupled to the detector 164. In other embodiments, the first and / or second high-density capacitors 116, 118 may be coupled in series with the integrating capacitor 112 or may be coupled to other portions of the unit cell circuit 100. While the detector 164 is shown with n-on-p polarity, the detector may be, for example, a p-on-n photodiode or a PIN photodiode. In still other embodiments, different circuit designs may be used to interface with other types of photodetectors, such as microbolometers.

[0050]

[0059] 6 shows a simplified cross-sectional view of a focal plane array unit cell 600 having a multi-layer capacitor according to an embodiment of the present disclosure. As shown in FIG. 6, unit cell 600 is similar to unit cell 100, except that unit cell 600 includes a double-layer capacitor structure stacked on top of one another, which can increase capacitor density. More specifically, unit cell 600 shows four capacitors, with capacitors 630 and 632 having a planar structure and capacitors 614 and 618 having a non-planar high-density structure.

[0051]

[0060] The high-density capacitor structures 614, 618 can include a first bottom electrode 620 and a dielectric layer 622 formed on the first bottom electrode 620. A first top electrode 624 can be formed on the first dielectric layer 622. A portion of the dielectric layer 604 can be formed on the first top electrode 624, with the dielectric layer acting as an electrical insulator between the high-density capacitor structures 614, 618 and the planar capacitor structures 630, 632. In some embodiments, the planar capacitor structure 632 includes similar layers and materials as the high-density capacitor structures 614, 618. More specifically, the planar capacitor structure 632 includes a second bottom electrode 634 and a second dielectric material 636 formed on the second bottom electrode. A second top electrode 638 is formed on the second dielectric material 636. In some embodiments, the high-density capacitor structures 614, 618 and the planar capacitor structures 630, 632 can be electrically coupled to each other to function as a single capacitor. In further embodiments, planar capacitor structures 630, 632 may be formed below the high density capacitors 614, 618. A dielectric layer 604 may be formed over the semiconductor substrate 602.

[0052]

[0061] Those skilled in the art having the benefit of this disclosure will understand that in other embodiments, dielectric layer 604 can include any number of layers of a capacitor structure, and in one embodiment can have 3, 4, 5, 6, 7, 8, or more layers of a capacitor structure.

[0053]

[0062] FIG. 7 illustrates a cross-sectional view of a multi-capacitor structure of a focal plane array unit cell 700 according to an embodiment of the present disclosure. As shown in FIG. 7, the unit cell 700 is similar to the unit cell 600 illustrated in FIG. 6, except that the unit cell 700 includes a two-layer high-density capacitor structure, which can increase capacitor density. Specifically, the unit cell 700 includes four capacitors in two high-density layers. A passivation portion 708 of the ROIC 702 includes first and second high-density capacitors 716 and 718, respectively, and a dielectric layer 704 includes third and fourth high-density capacitors 720 and 724, respectively. More specifically, in one embodiment, the passivation portion 708 can be a passivation layer applied over a semiconductor substrate 703, which includes a layer of semiconductor material and one or more metal layers formed as part of the ROIC. In one embodiment, the passivation portion is silicon nitride, which is formed as the final dielectric layer in a semiconductor fabrication process. Each high density capacitor 716, 718, 720, 724 is similar to the high density capacitor structures previously described and may be formed using any of the techniques previously disclosed.

[0054]

[0063] As shown, first and second high density capacitors 716, 718, respectively, are formed in a passivation portion 708 of an IC substrate 702. Both the first and second high density capacitors 716, 718 include a capacitor structure similar to those previously disclosed, with an upper electrode 730 formed on a dielectric material 728 formed on a lower electrode 726. The capacitor structure follows the topography created by a plurality of first recesses 755 formed in the passivation portion 708.

[0055]

[0064] The third and fourth high density capacitors 720, 724 are similarly formed of similar or different materials as the first and second high density capacitors 716, 718, respectively. A top electrode 733 is formed on a dielectric material 729 formed on the bottom electrode 727. The capacitor structure follows the topography created by a plurality of second recesses 756 formed in the dielectric layer 704. In some embodiments, the bottom electrodes 727 of the third and fourth high density capacitors 720, 724, respectively, are coupled to the top electrodes 730 of the first and second high density capacitors 716, 718, respectively, through one or more vias 736. The capacitor integration structure can provide multiple capacitors per pixel with any suitable number of capacitors.

[0056]

[0065] FIG. 8 shows a simplified cross-sectional view of a focal plane array unit cell 800 according to an embodiment of the present disclosure. As shown in FIG. 8, unit cell 800 is similar to unit cell 600 of FIG. 6 in that the unit cell includes both a planar capacitor 805 and a high-density capacitor 810; however, in FIG. 8, the high-density capacitor overlies and is in electrical contact with the lower planar capacitor. More specifically, in unit cell 800, the upper electrode 815 of planar capacitor 805 is adjacent to and in electrical contact with the lower electrode 820 of high-density capacitor 810. In one embodiment, the lower electrode 820 contacts the upper electrode 815 at the bottom 825 of each recess 830. Those skilled in the art, having the benefit of this disclosure, will recognize many variations, modifications, and alternatives.

[0057]

[0066] FIG. 9 illustrates an exemplary process 900 by which a capacitor structure can be formed on or over an IC substrate, as shown in FIG. 10. Process 900 can be referred to as a fabrication process. A cross-sectional view of a focal plane array unit cell 1000 is formed on an IC substrate 1002 according to the method of FIG. 9, as shown in FIG. 10. More specifically, in this particular embodiment, a high density capacitor structure 1020 is formed in a dielectric layer 1004 formed on top of the IC substrate 1002, although in other embodiments, as disclosed herein, a high density capacitor structure can be formed using a portion of a passivation layer that is on top of the IC substrate.

[0058]

[0067] As shown, in step 902, an IC substrate 1002 is provided on which a high density capacitor structure 1016 can be formed. The IC substrate can include pre-processed silicon, silicon dioxide, silicon-on-insulator, germanium, gallium arsenide, or other III-V or II-VI materials.

[0059]

[0068] In step 904, covering the IC substrate 1002 is a first portion of a dielectric layer 1004 deposited thereon. As previously described, the dielectric layer 1004 is disposed between the IC substrate 1002 and the photodetector layer 1006 and may form a portion of the first and second high density capacitors 1016, 1018. More specifically, in some embodiments, a portion of the dielectric layer 1004 may be deposited before, during, or after the capacitor structure 1020, such that the dielectric layer 1004 insulates the electrode layers of the high density capacitor structure 1020 from the photodetector layer 1006 and / or other portions of the unit cell 1000. In some embodiments, the dielectric layer 1004 may be an oxide, nitride, polymer, or any other material that provides suitable electrical insulation within the unit cell 1000. In one embodiment, the dielectric layer 1004 may be, for example, silicon dioxide. In some embodiments, additional layers of the capacitor structure 1016 may be formed within the interlayer dielectric, as described in more detail below.

[0060]

[0069] In step 906, prior to depositing additional layers to form a high-density capacitor, a plurality of interconnected recessed structures 1034 may be etched into the dielectric layer 1004, as shown in FIG. 10 . As previously described, each capacitor structure 1016 is formed into a wavy and / or corrugated structure, with a planar portion bonded to a first sidewall that extends downward into a planar segment that is bonded to a second sidewall portion that extends upward toward a second planar portion. To form the desired capacitor structures, this process of etching recessed structures 1034 into the dielectric layer is repeated until the desired capacitor topography is formed. In some embodiments, via structures or any other geometric shapes may be formed in the dielectric layer 1004.

[0061]

[0070] In step 908, a first electrode layer 1022 can be deposited on the first portion of the dielectric layer 1004. The material for the first electrode 1022 can be deposited using a variety of fabrication techniques, including chemical vapor deposition, physical vapor deposition or sputtering, plasma-enhanced chemical vapor deposition including high-density plasma deposition, low-pressure or sub-atmospheric pressure chemical vapor deposition, epitaxial growth, or atomic layer deposition. The electrode material can include transition metals or poor metals including metal nitrides, or other combinations. For example, as shown in FIG. 10, a first electrode layer 1022 can be deposited comprising titanium grown or deposited within the dielectric layer 1004. The layer height can be less than or about 1 μm. Alternatively, the layer height can be 1 μm, 0.1 μm, 500 nm, 400 nm, 375 nm, 350 nm, 325 nm, 300 nm, 250 nm, 200 nm, 175 nm, 150 nm, 125 nm, 100 nm, 75 nm, 50 nm, 25 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm, 7 Angstroms, 5 Angstroms, etc., or less.

[0062]

[0071] In some embodiments, a second material layer is deposited on the first material layer. This second material layer can include a metal similar to or alternative to the first material layer, and can include any of the materials described above. For example, the second material layer is deposited on the first material layer of the first electrode 1022, which includes titanium nitride. Like the first material layer of the first electrode 1022, the height of the second material layer can be approximately 5 μm or less. Alternatively, the height of the layer can be 1 μm, 0.1 μm, 500 nm, 400 nm, 375 nm, 350 nm, 325 nm, 300 nm, 250 nm, 200 nm, 175 nm, 150 nm, 125 nm, 100 nm, 75 nm, 50 nm, 25 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm, 7 Angstroms, etc., or less. In an alternative embodiment, an additional layer of material may be deposited over the first and second material layers of the first electrode 1022 .

[0063]

[0072] One or more layers of material can be deposited at a thickness and patterned to maximize current density so that the material can fracture during operation. For example, as shown in Figure 10, the first material layer of any of the first electrodes 1022 can be deposited at a thickness such that a voltage above a certain threshold melts or fractures the electrode material, effectively isolating the detector associated with a negative voltage. This feature can serve as a fusing mechanism for isolating a malfunctioning detector pixel and can be applied to any of the embodiments disclosed herein.

[0064]

[0073] After one or more layers of the first electrode material are deposited or grown in step 910, the first electrode structure can be etched. Etching can be performed using a wet or dry etching process that selectively removes portions of the first electrode layer. A resist layer can first be deposited on the substrate so that the electrode material is removed in some areas but substantially preserved in other areas. As shown in FIG. 10 , material from the dielectric layer 1004 can be removed over areas including over the connector 1028 for the top electrode contact, the connectors 1030a and 1030b for the bottom electrode contact, and the connector 1032 for the detector contact. Following removal of the dielectric layer material, post-processing steps can be performed, including removal of the resist material.

[0065]

[0074] In step 912, a capacitor dielectric material 1024 can be deposited over the first electrode material. The dielectric can include metal oxides, metal nitrides, metal oxynitrides, metal carbides, or other known dielectric materials. Metals utilized can include oxides or other compositions containing silicon, aluminum, titanium, zirconium, hafnium, molybdenum, or chromium, for example. Alternative dielectric structures can include multiple layers of materials to provide a combination of dielectric properties. For example, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 17, 20, 23, 25, etc., or more layers of material can be included. The layers can include multiple materials stacked in various ways, such as alternating layers, stacking two or more materials, or reversing and re-stacking sequentially stacked materials to form a complete structure. As shown in FIG. 10, the dielectric material 1024 is deposited in one or more layers over the first electrode 1022 layer. The layers of dielectric material can be less than or about 1 μm in height. Alternatively, the layer heights can be 1 μm, 0.11 μm, 500 nm, 400 nm, 375 nm, 350 nm, 325 nm, 300 nm, 250 nm, 200 nm, 175 nm, 150 nm, 125 nm, 100 nm, 75 nm, 50 nm, 25 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm, 7 Angstroms, etc., or less. In alternative embodiments, each inner layer of dielectric material can be less than or about any of the listed heights. The overall height of the layers of dielectric material can be varied based on the requirements of a particular application to preferentially minimize leakage current, maximize breakdown voltage, or maximize capacitance density.

[0066]

[0075] After one or more layers of dielectric material are deposited or grown in step 914, the dielectric structure can be etched. The dielectric material can be etched down to the level of the first electrode material, and the etching can be performed using a wet or dry etching process that selectively removes the dielectric material relative to the first electrode material. Initially, a resist layer can be deposited such that the dielectric material is removed in certain areas on the substrate while being substantially maintained in other areas. As shown in FIG. 10 , material from the dielectric layer 1004 can be removed over areas including over the connector 1028 for the top electrode contact, the connectors 1030a and 1030b for the bottom electrode contact, and the connector 1032 for the detector contact. Following removal of the dielectric layer material, post-processing steps can be performed, including removal of the resist material.

[0067]

[0076] In process step 916, a material for the second electrode 1026 can be deposited on the capacitor structure 1016, covering the first electrode 1022 and the dielectric material 1024. The material for the second electrode 1026 can be deposited by any of the methods listed above and can be formed by a similar or different method than the first or bottom electrode. Furthermore, the material for the second electrode 1026 can include any one or any combination of the aforementioned materials. The second electrode 1026 can be formed similarly to the first electrode and can include one or more layers of electrode material. Alternatively, a different electrode material structure can be formed with the second electrode. Like the first electrode material, each of the second electrode material layers, or the combination of materials forming the second electrode material, can have a thickness of less than about 5 μm in height. Alternatively, the layer height can be 3 μm, 1 μm, 500 nm, 400 nm, 375 nm, 350 nm, 325 nm, 300 nm, 250 nm, 200 nm, 175 nm, 150 nm, 125 nm, 100 nm, 75 nm, 50 nm, 25 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm, 7 Angstroms, etc., or less.

[0068]

[0077] After one or more layers of material are deposited for the second electrode 1022 in step 918, the second electrode 1022 can be etched. A resist layer can first be deposited on the substrate to remove the electrode material in some areas while substantially maintaining it in other areas. As shown in FIG. 10 , the material of the dielectric layer 1004 can be removed over areas including the connector 1028 for the top electrode contact, the connector 1030 for the bottom electrode contact, and the connector 1030 for the detector contact. Following the removal of the dielectric layer material, a post-processing step can be performed that includes removing the resist material. Any etching process or combination of processes can be used to remove material previously deposited over the dielectric layer 1004. As shown in FIG. 10 , the structures over the individual connectors 1028, 1030a, 1030b, and 1032 are insulated from one another. An additional etching process can be performed to remove the second electrode material over the connector 1032. This additional etching process can further enhance the isolation between the detector landing connections and the capacitor structures. In some embodiments, more or fewer etches may be performed. In one embodiment, multiple layers may be etched simultaneously using one etching process.

[0069]

[0078] In step 920, a second portion of the dielectric layer 1004 may be deposited. In some embodiments, the second portion of the dielectric layer 1004 comprises the same dielectric material as that deposited in step 904. As previously disclosed, the dielectric layer 1004 may be an insulating material such as silicon dioxide or any other insulating material previously described, or may be used to insulate an IC substrate or structure above the capacitor structure 1020 formed in another portion of the dielectric layer 1004. The dielectric layer 1004 may be deposited by any of the methods previously described, and in one example, may be deposited by plasma-enhanced chemical vapor deposition. As shown in FIG. 10, the dielectric layer 1004 is deposited to completely insulate the areas below and above the capacitor structure 1020. In some embodiments, multiple deposition and / or etching steps can be performed to ensure adequate step coverage of the capacitor structure 1020, and material of the dielectric layer 1004 can be removed over areas including over the connector 1028 for the upper electrode contact, the connectors 1030a, 1030b for the lower electrode contact, and the connector 1032 for the detector contact.

[0070]

[0079] In step 922, a conductor layer 1014 is deposited and in step 924, etched to provide a uniform potential across the electrode layers of the underlying capacitor structures while adequately insulating the structures from one another. The conductor layer 1014 is formed and etched according to the information previously disclosed. A resist pattern can be deposited prior to etching to ensure adequate removal areas. Any of the etching methods previously described can be performed to selectively remove the conductive layer material while substantially preserving the underlying structures.

[0071]

[0080] In step 926, another portion of the material of the dielectric layer 1004 can be deposited on the conductor layer 1014. The dielectric layer 1004 can provide a barrier to the underlying capacitor structure and conductive layers while maintaining adequate insulation of the structures from each other. Any of the etching methods previously described can be performed.

[0072]

[0081] After the formation of the capacitor structure on the IC substrate has been performed, further processing steps may be performed. In step 928, a detector layer 1006 may optionally be formed on the capacitor structure. The detector layer 1006 may be grown or formed directly on the reflector material, or alternatively may be formed separately and then connected to the reflector and capacitor structure. Post-processing including via etching may also be performed to enhance photodiode functionality. An additional insulating layer may or may not be formed on regions of the reflector material to further prevent electrical connection from being formed between the detector contact regions and the capacitor regions.

[0073]

[0082] Any of the aforementioned processing steps, as well as any additional polishing, annealing, or curing, can be performed at temperatures of about 800°C or less to protect the underlying preformed ROIC structure. Alternatively, the process can be performed at temperatures of about 700°C, 600°C, 500°C, 450°C, 400°C, 350°C, 300°C, 200°C, 150°C, 100°C, etc., or lower. The material layer deposited on the ROIC, with or without the detector material, can have a total height of about 30 μm or less. Alternatively, the deposited material layer can have a thickness of about 7 μm, 5 μm, 3 μm, 2 μm, 1 μm, 800 nm, 750 nm, 600 nm, 500 nm, 450 nm, 400 nm, 350 nm, 300 nm, 250 nm, 200 nm, 150 nm, 100 nm, 50 nm, etc., or less.

[0074]

[0083] It will be understood that process 900 is illustrative and that variations and modifications are possible: steps described as sequential may be performed in parallel, the order of steps may be changed, and steps may be modified, combined, added, or omitted.

[0075]

[0084] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0076]

[0085] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosed embodiments. Moreover, in order to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the invention.

[0077]

[0086] It should be noted that individual embodiments may be described as a process, which is depicted as a flowchart, flow diagram, or block diagram. While a flowchart may describe the method as a sequential process, many of the operations may be performed in parallel or concurrently. Furthermore, the order of operations may be rearranged. A process may terminate when its operations are completed, but there may be additional steps not discussed or included in the figures. Furthermore, not all operations of a specifically described process occur in all embodiments. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0078]

[0087] Where a range of values ​​is given, unless the context clearly indicates otherwise, each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also understood to be specifically disclosed. Each smaller range between any stated or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded, and each range in which either limit, neither limit, or both limits are included in the smaller range is also included within the disclosure, subject to the specifically excluded limit in the stated range. When a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0079]

[0088] As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a dielectric material" includes a plurality of such materials, reference to "the present application" includes a reference to one or more applications and equivalents thereof known to those skilled in the art, and so forth.

[0080]

[0089] Furthermore, the words "comprise," "comprising," "contains," "containing," "include," "including," and "includes," when used in this specification and the claims that follow, specify the presence of stated features, integers, components, or steps, but they do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A photodetector comprising: a semiconductor layer having one or more integrated electrical components; an electrically insulating layer overlying the semiconductor layer and defining a plurality of partial vias formed in a first surface of the electrically insulating layer, each partial via of the plurality of partial vias including at least one sidewall extending from the first surface to a bottom of the respective partial via; an intermediate layer connector extending through the electrical insulating layer to the semiconductor layer, wherein a first portion of the plurality of partial vias is disposed on a first side of the intermediate layer connector and another portion of the plurality of partial vias is disposed on a second side of the intermediate layer connector; a capacitor structure coupled to one or more of the integrated electrical components by the interlayer connector, a first electrode formed across the first surface of the electrically insulating layer, positioned a first distance from the semiconductor layer, and formed along the at least one sidewall of each partial via of the plurality of partial vias; a capacitor dielectric layer formed over the first electrode; a second electrode formed above the capacitor dielectric layer; a capacitor structure including: a top metal layer disposed a second distance from the semiconductor layer, the second distance being greater than the first distance; and a plurality of vias extending through the electrically insulating layer and positioned between the top metal layer and the capacitor structure, the plurality of vias electrically connecting the top metal layer to the second electrode; a detector above the capacitor structure; A photodetector comprising:

2. The photodetector of claim 1 , wherein the electrically insulating layer comprises a passivation layer formed over the semiconductor layer as part of an integrated circuit substrate.

3. The photodetector of claim 1 , wherein the electrically insulating layer comprises a dielectric layer disposed between the semiconductor layer and the detector.

4. 2. The photodetector of claim 1, wherein a first portion of the electrically insulating layer is disposed between the capacitor structure and the detector, and a second portion of the electrically insulating layer is disposed between the capacitor structure and the semiconductor layer.

5. 1. A photodetector structure comprising: a semiconductor layer; an electrically insulating layer overlying the semiconductor layer and defining a plurality of partial vias formed in an upper surface of the electrically insulating layer; an intermediate layer connector extending through the electrical insulating layer to the semiconductor layer, wherein a first portion of the plurality of partial vias is disposed on a first side of the intermediate layer connector and another portion of the plurality of partial vias is disposed on a second side of the intermediate layer connector; a capacitor structure disposed a first distance from the semiconductor layer, a first electrode formed within the plurality of partial vias across the top surface of the electrically insulating layer; a capacitor dielectric layer formed over the first electrode; a second electrode formed over the capacitor dielectric layer; and a capacitor structure including: an outer metal layer disposed a second distance from the semiconductor layer, the second distance being greater than the first distance; a plurality of vias extending through the electrically insulating layer and positioned between the outer metal layer and the capacitor structure, the plurality of vias electrically connecting the outer metal layer to the second electrode; a detector above the capacitor structure; A photodetector structure comprising:

6. 6. The photodetector structure of claim 5, wherein the electrically insulating layer comprises a passivation layer formed on the semiconductor layer.

7. 6. The photodetector structure of claim 5, wherein the electrically insulating layer comprises a dielectric layer disposed between the semiconductor layer and the detector.

8. 6. The photodetector structure of claim 5, wherein a first portion of the electrically insulating layer is disposed between the capacitor structure and the detector, and a second portion of the electrically insulating layer is disposed between the capacitor structure and the semiconductor layer.

9. a capacitor formed within a focal plane array unit cell, an electrically insulating layer defining a first plurality of vias formed in a first surface of the electrically insulating layer, the electrically insulating layer being formed a first distance above the semiconductor substrate; an interlayer connector extending through the electrically insulating layer to the semiconductor substrate, a first portion of the first plurality of vias being disposed on a first side of the interlayer connector and another portion of the first plurality of vias being disposed on a second side of the interlayer connector; a first electrode formed in the first plurality of vias across the first surface of the electrically insulating layer; a capacitor dielectric layer formed over the first electrode; a second electrode formed over the capacitor dielectric layer; a second plurality of vias extending through the electrically insulating layer and positioned between a top metal layer formed above the semiconductor substrate at a second distance greater than the first distance and the second electrode, the second plurality of vias electrically connecting the top metal layer to the second electrode; A capacitor comprising:

10. The capacitor of claim 9 wherein the electrically insulating layer comprises a passivation portion of an integrated circuit substrate.

11. 10. The capacitor of claim 9, wherein the electrically insulating layer comprises a dielectric layer disposed between a readout integrated circuit device and a detector.

12. The capacitor of claim 9 , wherein the first plurality of vias comprises partial vias.

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